/* frv vliw model.
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/* frv vliw model.
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Copyright (C) 1999, 2000, 2001, 2003, 2007, 2008
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Copyright (C) 1999, 2000, 2001, 2003, 2007, 2008
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Free Software Foundation, Inc.
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Free Software Foundation, Inc.
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Contributed by Red Hat.
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Contributed by Red Hat.
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This file is part of the GNU simulators.
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This file is part of the GNU simulators.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#define WANT_CPU frvbf
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#define WANT_CPU frvbf
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#define WANT_CPU_FRVBF
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#define WANT_CPU_FRVBF
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#include "sim-main.h"
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#include "sim-main.h"
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/* Simulator specific vliw related functions. Additional vliw related
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/* Simulator specific vliw related functions. Additional vliw related
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code used by both the simulator and the assembler is in frv.opc. */
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code used by both the simulator and the assembler is in frv.opc. */
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int insns_in_slot[UNIT_NUM_UNITS] = {0};
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int insns_in_slot[UNIT_NUM_UNITS] = {0};
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void
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void
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frv_vliw_setup_insn (SIM_CPU *current_cpu, const CGEN_INSN *insn)
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frv_vliw_setup_insn (SIM_CPU *current_cpu, const CGEN_INSN *insn)
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{
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{
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FRV_VLIW *vliw;
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FRV_VLIW *vliw;
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int index;
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int index;
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/* Always clear the NE index which indicates the target register
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/* Always clear the NE index which indicates the target register
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of a non excepting insn. This will be reset by the insn if
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of a non excepting insn. This will be reset by the insn if
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necessary. */
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necessary. */
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frv_interrupt_state.ne_index = NE_NOFLAG;
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frv_interrupt_state.ne_index = NE_NOFLAG;
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vliw = CPU_VLIW (current_cpu);
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vliw = CPU_VLIW (current_cpu);
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index = vliw->next_slot - 1;
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index = vliw->next_slot - 1;
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if (frv_is_float_insn (insn))
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if (frv_is_float_insn (insn))
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{
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{
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/* If the insn is to be added and is a floating point insn and
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/* If the insn is to be added and is a floating point insn and
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it is the first floating point insn in the vliw, then clear
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it is the first floating point insn in the vliw, then clear
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FSR0.FTT. */
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FSR0.FTT. */
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int i;
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int i;
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for (i = 0; i < index; ++i)
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for (i = 0; i < index; ++i)
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if (frv_is_float_major (vliw->major[i], vliw->mach))
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if (frv_is_float_major (vliw->major[i], vliw->mach))
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break; /* found float insn. */
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break; /* found float insn. */
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if (i >= index)
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if (i >= index)
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{
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{
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SI fsr0 = GET_FSR (0);
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SI fsr0 = GET_FSR (0);
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SET_FSR_FTT (fsr0, FTT_NONE);
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SET_FSR_FTT (fsr0, FTT_NONE);
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SET_FSR (0, fsr0);
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SET_FSR (0, fsr0);
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}
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}
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}
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}
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else if (frv_is_media_insn (insn))
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else if (frv_is_media_insn (insn))
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{
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{
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/* Clear the appropriate MSR fields depending on which slot
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/* Clear the appropriate MSR fields depending on which slot
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this insn is in. */
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this insn is in. */
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CGEN_ATTR_VALUE_ENUM_TYPE preserve_ovf;
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CGEN_ATTR_VALUE_ENUM_TYPE preserve_ovf;
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SI msr0 = GET_MSR (0);
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SI msr0 = GET_MSR (0);
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preserve_ovf = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_PRESERVE_OVF);
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preserve_ovf = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_PRESERVE_OVF);
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if ((*vliw->current_vliw)[index] == UNIT_FM0)
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if ((*vliw->current_vliw)[index] == UNIT_FM0)
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{
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{
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if (! preserve_ovf)
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if (! preserve_ovf)
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{
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{
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/* Clear MSR0.OVF and MSR0.SIE. */
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/* Clear MSR0.OVF and MSR0.SIE. */
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CLEAR_MSR_SIE (msr0);
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CLEAR_MSR_SIE (msr0);
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CLEAR_MSR_OVF (msr0);
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CLEAR_MSR_OVF (msr0);
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}
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}
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}
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}
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else
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else
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{
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{
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if (! preserve_ovf)
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if (! preserve_ovf)
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{
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{
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/* Clear MSR1.OVF and MSR1.SIE. */
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/* Clear MSR1.OVF and MSR1.SIE. */
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SI msr1 = GET_MSR (1);
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SI msr1 = GET_MSR (1);
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CLEAR_MSR_SIE (msr1);
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CLEAR_MSR_SIE (msr1);
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CLEAR_MSR_OVF (msr1);
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CLEAR_MSR_OVF (msr1);
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SET_MSR (1, msr1);
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SET_MSR (1, msr1);
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}
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}
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}
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}
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SET_MSR (0, msr0);
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SET_MSR (0, msr0);
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} /* Insn is a media insns. */
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} /* Insn is a media insns. */
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COUNT_INSNS_IN_SLOT ((*vliw->current_vliw)[index]);
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COUNT_INSNS_IN_SLOT ((*vliw->current_vliw)[index]);
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}
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}
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