/* IQ2000 simulator support code
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/* IQ2000 simulator support code
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Copyright (C) 2000, 2004, 2007, 2008 Free Software Foundation, Inc.
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Copyright (C) 2000, 2004, 2007, 2008 Free Software Foundation, Inc.
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Contributed by Cygnus Support.
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Contributed by Cygnus Support.
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This file is part of the GNU simulators.
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This file is part of the GNU simulators.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#define WANT_CPU
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#define WANT_CPU
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#define WANT_CPU_IQ2000BF
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#define WANT_CPU_IQ2000BF
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#include "sim-main.h"
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#include "sim-main.h"
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#include "cgen-mem.h"
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#include "cgen-mem.h"
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#include "cgen-ops.h"
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#include "cgen-ops.h"
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enum
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enum
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{
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{
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GPR0_REGNUM = 0,
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GPR0_REGNUM = 0,
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NR_GPR = 32,
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NR_GPR = 32,
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PC_REGNUM = 32
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PC_REGNUM = 32
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};
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};
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enum libgloss_syscall
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enum libgloss_syscall
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{
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{
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SYS_exit = 1,
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SYS_exit = 1,
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SYS_open = 2,
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SYS_open = 2,
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SYS_close = 3,
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SYS_close = 3,
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SYS_read = 4,
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SYS_read = 4,
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SYS_write = 5,
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SYS_write = 5,
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SYS_lseek = 6,
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SYS_lseek = 6,
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SYS_unlink = 7,
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SYS_unlink = 7,
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SYS_getpid = 8,
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SYS_getpid = 8,
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SYS_kill = 9,
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SYS_kill = 9,
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SYS_fstat = 10,
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SYS_fstat = 10,
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SYS_argvlen = 12,
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SYS_argvlen = 12,
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SYS_argv = 13,
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SYS_argv = 13,
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SYS_chdir = 14,
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SYS_chdir = 14,
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SYS_stat = 15,
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SYS_stat = 15,
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SYS_chmod = 16,
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SYS_chmod = 16,
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SYS_utime = 17,
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SYS_utime = 17,
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SYS_time = 18,
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SYS_time = 18,
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SYS_gettimeofday = 19,
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SYS_gettimeofday = 19,
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SYS_times = 20
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SYS_times = 20
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};
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};
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/* Read a null terminated string from memory, return in a buffer */
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/* Read a null terminated string from memory, return in a buffer */
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static char *
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static char *
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fetch_str (current_cpu, pc, addr)
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fetch_str (current_cpu, pc, addr)
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SIM_CPU *current_cpu;
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SIM_CPU *current_cpu;
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PCADDR pc;
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PCADDR pc;
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DI addr;
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DI addr;
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{
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{
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char *buf;
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char *buf;
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int nr = 0;
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int nr = 0;
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while (sim_core_read_1 (current_cpu,
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while (sim_core_read_1 (current_cpu,
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pc, read_map, CPU2DATA(addr + nr)) != 0)
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pc, read_map, CPU2DATA(addr + nr)) != 0)
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nr++;
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nr++;
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buf = NZALLOC (char, nr + 1);
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buf = NZALLOC (char, nr + 1);
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sim_read (CPU_STATE (current_cpu), CPU2DATA(addr), buf, nr);
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sim_read (CPU_STATE (current_cpu), CPU2DATA(addr), buf, nr);
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return buf;
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return buf;
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}
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}
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void
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void
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do_syscall (SIM_CPU *current_cpu, PCADDR pc)
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do_syscall (SIM_CPU *current_cpu, PCADDR pc)
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{
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{
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#if 0
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#if 0
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int syscall = H2T_4 (iq2000bf_h_gr_get (current_cpu, 11));
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int syscall = H2T_4 (iq2000bf_h_gr_get (current_cpu, 11));
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#endif
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#endif
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int syscall_function = iq2000bf_h_gr_get (current_cpu, 4);
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int syscall_function = iq2000bf_h_gr_get (current_cpu, 4);
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int i;
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int i;
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char *buf;
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char *buf;
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int PARM1 = iq2000bf_h_gr_get (current_cpu, 5);
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int PARM1 = iq2000bf_h_gr_get (current_cpu, 5);
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int PARM2 = iq2000bf_h_gr_get (current_cpu, 6);
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int PARM2 = iq2000bf_h_gr_get (current_cpu, 6);
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int PARM3 = iq2000bf_h_gr_get (current_cpu, 7);
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int PARM3 = iq2000bf_h_gr_get (current_cpu, 7);
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const int ret_reg = 2;
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const int ret_reg = 2;
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switch (syscall_function)
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switch (syscall_function)
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{
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{
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case 0:
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case 0:
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switch (H2T_4 (iq2000bf_h_gr_get (current_cpu, 11)))
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switch (H2T_4 (iq2000bf_h_gr_get (current_cpu, 11)))
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{
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{
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case 0:
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case 0:
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/* Pass. */
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/* Pass. */
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puts ("pass");
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puts ("pass");
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exit (0);
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exit (0);
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case 1:
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case 1:
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/* Fail. */
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/* Fail. */
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puts ("fail");
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puts ("fail");
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exit (1);
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exit (1);
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}
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}
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case SYS_write:
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case SYS_write:
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buf = zalloc (PARM3);
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buf = zalloc (PARM3);
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sim_read (CPU_STATE (current_cpu), CPU2DATA(PARM2), buf, PARM3);
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sim_read (CPU_STATE (current_cpu), CPU2DATA(PARM2), buf, PARM3);
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SET_H_GR (ret_reg,
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SET_H_GR (ret_reg,
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sim_io_write (CPU_STATE (current_cpu),
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sim_io_write (CPU_STATE (current_cpu),
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PARM1, buf, PARM3));
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PARM1, buf, PARM3));
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zfree (buf);
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zfree (buf);
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break;
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break;
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case SYS_lseek:
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case SYS_lseek:
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SET_H_GR (ret_reg,
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SET_H_GR (ret_reg,
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sim_io_lseek (CPU_STATE (current_cpu),
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sim_io_lseek (CPU_STATE (current_cpu),
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PARM1, PARM2, PARM3));
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PARM1, PARM2, PARM3));
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break;
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break;
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case SYS_exit:
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case SYS_exit:
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sim_engine_halt (CPU_STATE (current_cpu), current_cpu,
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sim_engine_halt (CPU_STATE (current_cpu), current_cpu,
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NULL, pc, sim_exited, PARM1);
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NULL, pc, sim_exited, PARM1);
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break;
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break;
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case SYS_read:
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case SYS_read:
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buf = zalloc (PARM3);
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buf = zalloc (PARM3);
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SET_H_GR (ret_reg,
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SET_H_GR (ret_reg,
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sim_io_read (CPU_STATE (current_cpu),
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sim_io_read (CPU_STATE (current_cpu),
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PARM1, buf, PARM3));
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PARM1, buf, PARM3));
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sim_write (CPU_STATE (current_cpu), CPU2DATA(PARM2), buf, PARM3);
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sim_write (CPU_STATE (current_cpu), CPU2DATA(PARM2), buf, PARM3);
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zfree (buf);
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zfree (buf);
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break;
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break;
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case SYS_open:
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case SYS_open:
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buf = fetch_str (current_cpu, pc, PARM1);
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buf = fetch_str (current_cpu, pc, PARM1);
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SET_H_GR (ret_reg,
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SET_H_GR (ret_reg,
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sim_io_open (CPU_STATE (current_cpu),
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sim_io_open (CPU_STATE (current_cpu),
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buf, PARM2));
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buf, PARM2));
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zfree (buf);
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zfree (buf);
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break;
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break;
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case SYS_close:
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case SYS_close:
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SET_H_GR (ret_reg,
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SET_H_GR (ret_reg,
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sim_io_close (CPU_STATE (current_cpu), PARM1));
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sim_io_close (CPU_STATE (current_cpu), PARM1));
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break;
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break;
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case SYS_time:
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case SYS_time:
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SET_H_GR (ret_reg, time (0));
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SET_H_GR (ret_reg, time (0));
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break;
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break;
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default:
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default:
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SET_H_GR (ret_reg, -1);
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SET_H_GR (ret_reg, -1);
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}
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}
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}
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}
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void
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void
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do_break (SIM_CPU *current_cpu, PCADDR pc)
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do_break (SIM_CPU *current_cpu, PCADDR pc)
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{
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{
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SIM_DESC sd = CPU_STATE (current_cpu);
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SIM_DESC sd = CPU_STATE (current_cpu);
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sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
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sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
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}
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}
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/* The semantic code invokes this for invalid (unrecognized) instructions. */
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/* The semantic code invokes this for invalid (unrecognized) instructions. */
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SEM_PC
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SEM_PC
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sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC vpc)
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sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC vpc)
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{
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{
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SIM_DESC sd = CPU_STATE (current_cpu);
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SIM_DESC sd = CPU_STATE (current_cpu);
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sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL);
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sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL);
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return vpc;
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return vpc;
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}
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}
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/* Process an address exception. */
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/* Process an address exception. */
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void
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void
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iq2000_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia,
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iq2000_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia,
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unsigned int map, int nr_bytes, address_word addr,
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unsigned int map, int nr_bytes, address_word addr,
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transfer_type transfer, sim_core_signals sig)
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transfer_type transfer, sim_core_signals sig)
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{
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{
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sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr,
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sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr,
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transfer, sig);
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transfer, sig);
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}
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}
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/* Initialize cycle counting for an insn.
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/* Initialize cycle counting for an insn.
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FIRST_P is non-zero if this is the first insn in a set of parallel
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FIRST_P is non-zero if this is the first insn in a set of parallel
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insns. */
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insns. */
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void
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void
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iq2000bf_model_insn_before (SIM_CPU *cpu, int first_p)
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iq2000bf_model_insn_before (SIM_CPU *cpu, int first_p)
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{
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{
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/* Do nothing. */
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/* Do nothing. */
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}
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}
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/* Record the cycles computed for an insn.
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/* Record the cycles computed for an insn.
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LAST_P is non-zero if this is the last insn in a set of parallel insns,
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LAST_P is non-zero if this is the last insn in a set of parallel insns,
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and we update the total cycle count.
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and we update the total cycle count.
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CYCLES is the cycle count of the insn. */
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CYCLES is the cycle count of the insn. */
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void
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void
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iq2000bf_model_insn_after(SIM_CPU *cpu, int last_p, int cycles)
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iq2000bf_model_insn_after(SIM_CPU *cpu, int last_p, int cycles)
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{
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{
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/* Do nothing. */
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/* Do nothing. */
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}
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}
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int
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int
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iq2000bf_model_iq2000_u_exec (SIM_CPU *cpu, const IDESC *idesc,
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iq2000bf_model_iq2000_u_exec (SIM_CPU *cpu, const IDESC *idesc,
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int unit_num, int referenced)
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int unit_num, int referenced)
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{
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{
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return idesc->timing->units[unit_num].done;
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return idesc->timing->units[unit_num].done;
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}
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}
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PCADDR
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PCADDR
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get_h_pc (SIM_CPU *cpu)
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get_h_pc (SIM_CPU *cpu)
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{
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{
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return CPU_CGEN_HW(cpu)->h_pc;
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return CPU_CGEN_HW(cpu)->h_pc;
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}
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}
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void
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void
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set_h_pc (SIM_CPU *cpu, PCADDR addr)
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set_h_pc (SIM_CPU *cpu, PCADDR addr)
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{
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{
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CPU_CGEN_HW(cpu)->h_pc = addr | IQ2000_INSN_MASK;
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CPU_CGEN_HW(cpu)->h_pc = addr | IQ2000_INSN_MASK;
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}
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}
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int
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int
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iq2000bf_fetch_register (SIM_CPU *cpu, int nr, unsigned char *buf, int len)
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iq2000bf_fetch_register (SIM_CPU *cpu, int nr, unsigned char *buf, int len)
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{
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{
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if (nr >= GPR0_REGNUM
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if (nr >= GPR0_REGNUM
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&& nr < (GPR0_REGNUM + NR_GPR)
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&& nr < (GPR0_REGNUM + NR_GPR)
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&& len == 4)
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&& len == 4)
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{
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{
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*((unsigned32*)buf) =
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*((unsigned32*)buf) =
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H2T_4 (iq2000bf_h_gr_get (cpu, nr - GPR0_REGNUM));
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H2T_4 (iq2000bf_h_gr_get (cpu, nr - GPR0_REGNUM));
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return 4;
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return 4;
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}
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}
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else if (nr == PC_REGNUM
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else if (nr == PC_REGNUM
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&& len == 4)
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&& len == 4)
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{
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{
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*((unsigned32*)buf) = H2T_4 (get_h_pc (cpu));
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*((unsigned32*)buf) = H2T_4 (get_h_pc (cpu));
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return 4;
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return 4;
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}
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}
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else
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else
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return 0;
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return 0;
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}
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}
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int
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int
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iq2000bf_store_register (SIM_CPU *cpu, int nr, unsigned char *buf, int len)
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iq2000bf_store_register (SIM_CPU *cpu, int nr, unsigned char *buf, int len)
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{
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{
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if (nr >= GPR0_REGNUM
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if (nr >= GPR0_REGNUM
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&& nr < (GPR0_REGNUM + NR_GPR)
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&& nr < (GPR0_REGNUM + NR_GPR)
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&& len == 4)
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&& len == 4)
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{
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{
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iq2000bf_h_gr_set (cpu, nr - GPR0_REGNUM, T2H_4 (*((unsigned32*)buf)));
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iq2000bf_h_gr_set (cpu, nr - GPR0_REGNUM, T2H_4 (*((unsigned32*)buf)));
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return 4;
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return 4;
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}
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}
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else if (nr == PC_REGNUM
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else if (nr == PC_REGNUM
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&& len == 4)
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&& len == 4)
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{
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{
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set_h_pc (cpu, T2H_4 (*((unsigned32*)buf)));
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set_h_pc (cpu, T2H_4 (*((unsigned32*)buf)));
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return 4;
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return 4;
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}
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}
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else
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else
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return 0;
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return 0;
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}
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}
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