OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [iq2000/] [sim-main.h] - Diff between revs 24 and 157

Go to most recent revision | Only display areas with differences | Details | Blame | View Log

Rev 24 Rev 157
 
 
/* Main header for the Vitesse IQ2000.  */
/* Main header for the Vitesse IQ2000.  */
 
 
#ifndef SIM_MAIN_H
#ifndef SIM_MAIN_H
#define SIM_MAIN_H
#define SIM_MAIN_H
 
 
#define USING_SIM_BASE_H /* FIXME: quick hack */
#define USING_SIM_BASE_H /* FIXME: quick hack */
 
 
struct _sim_cpu; /* FIXME: should be in sim-basics.h */
struct _sim_cpu; /* FIXME: should be in sim-basics.h */
typedef struct _sim_cpu SIM_CPU;
typedef struct _sim_cpu SIM_CPU;
 
 
/* sim-basics.h includes config.h but cgen-types.h must be included before
/* sim-basics.h includes config.h but cgen-types.h must be included before
   sim-basics.h and cgen-types.h needs config.h.  */
   sim-basics.h and cgen-types.h needs config.h.  */
#include "config.h"
#include "config.h"
 
 
#include "symcat.h"
#include "symcat.h"
#include "sim-basics.h"
#include "sim-basics.h"
#include "cgen-types.h"
#include "cgen-types.h"
#include "iq2000-desc.h"
#include "iq2000-desc.h"
#include "iq2000-opc.h"
#include "iq2000-opc.h"
#include "arch.h"
#include "arch.h"
 
 
/* Pull in IQ2000_{DATA,INSN}_{MASK,VALUE}.  */
/* Pull in IQ2000_{DATA,INSN}_{MASK,VALUE}.  */
#include "elf/iq2000.h"
#include "elf/iq2000.h"
 
 
/* These must be defined before sim-base.h.  */
/* These must be defined before sim-base.h.  */
typedef USI sim_cia;
typedef USI sim_cia;
 
 
#define CIA_GET(cpu)     CPU_PC_GET (cpu)
#define CIA_GET(cpu)     CPU_PC_GET (cpu)
#define CIA_SET(cpu,val) CPU_PC_SET ((cpu), (val))
#define CIA_SET(cpu,val) CPU_PC_SET ((cpu), (val))
 
 
#include "sim-base.h"
#include "sim-base.h"
#include "cgen-sim.h"
#include "cgen-sim.h"
#include "iq2000-sim.h"
#include "iq2000-sim.h"


/* The _sim_cpu struct.  */
/* The _sim_cpu struct.  */
 
 
struct _sim_cpu {
struct _sim_cpu {
  /* sim/common cpu base.  */
  /* sim/common cpu base.  */
  sim_cpu_base base;
  sim_cpu_base base;
 
 
  /* Static parts of cgen.  */
  /* Static parts of cgen.  */
  CGEN_CPU cgen_cpu;
  CGEN_CPU cgen_cpu;
 
 
  /* CPU specific parts go here.
  /* CPU specific parts go here.
     Note that in files that don't need to access these pieces WANT_CPU_FOO
     Note that in files that don't need to access these pieces WANT_CPU_FOO
     won't be defined and thus these parts won't appear.  This is ok in the
     won't be defined and thus these parts won't appear.  This is ok in the
     sense that things work.  It is a source of bugs though.
     sense that things work.  It is a source of bugs though.
     One has to of course be careful to not take the size of this
     One has to of course be careful to not take the size of this
     struct and no structure members accessed in non-cpu specific files can
     struct and no structure members accessed in non-cpu specific files can
     go after here.  Oh for a better language.  */
     go after here.  Oh for a better language.  */
#if defined (WANT_CPU_IQ2000BF)
#if defined (WANT_CPU_IQ2000BF)
  IQ2000BF_CPU_DATA cpu_data;
  IQ2000BF_CPU_DATA cpu_data;
#endif
#endif
};
};


/* The sim_state struct.  */
/* The sim_state struct.  */
 
 
struct sim_state {
struct sim_state {
  sim_cpu *cpu;
  sim_cpu *cpu;
#define STATE_CPU(sd, n) (/*&*/ (sd)->cpu)
#define STATE_CPU(sd, n) (/*&*/ (sd)->cpu)
 
 
  CGEN_STATE cgen_state;
  CGEN_STATE cgen_state;
 
 
  sim_state_base base;
  sim_state_base base;
};
};


/* Misc.  */
/* Misc.  */
 
 
/* Catch address exceptions.  */
/* Catch address exceptions.  */
extern SIM_CORE_SIGNAL_FN iq2000_core_signal;
extern SIM_CORE_SIGNAL_FN iq2000_core_signal;
#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
iq2000_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
iq2000_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
                  (TRANSFER), (ERROR))
                  (TRANSFER), (ERROR))
 
 
/* Convert between CPU-internal addresses and sim_core addresses.  */
/* Convert between CPU-internal addresses and sim_core addresses.  */
#define CPU2DATA(addr) (IQ2000_DATA_VALUE + (addr))
#define CPU2DATA(addr) (IQ2000_DATA_VALUE + (addr))
#define DATA2CPU(addr) ((addr) - IQ2000_DATA_VALUE)
#define DATA2CPU(addr) ((addr) - IQ2000_DATA_VALUE)
#define CPU2INSN(addr) (IQ2000_INSN_VALUE + ((addr) & ~IQ2000_INSN_MASK))
#define CPU2INSN(addr) (IQ2000_INSN_VALUE + ((addr) & ~IQ2000_INSN_MASK))
#define INSN2CPU(addr) ((addr) - IQ2000_INSN_VALUE)
#define INSN2CPU(addr) ((addr) - IQ2000_INSN_VALUE)
#define IQ2000_INSN_MEM_SIZE (CPU2INSN(0x800000) - CPU2INSN(0x0000))
#define IQ2000_INSN_MEM_SIZE (CPU2INSN(0x800000) - CPU2INSN(0x0000))
#define IQ2000_DATA_MEM_SIZE (CPU2DATA(0x800000) - CPU2DATA(0x0000))
#define IQ2000_DATA_MEM_SIZE (CPU2DATA(0x800000) - CPU2DATA(0x0000))
 
 
#endif /* SIM_MAIN_H */
#endif /* SIM_MAIN_H */
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.