/* This file is part of the program psim.
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/* This file is part of the program psim.
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Copyright (C) 1994-1996, Andrew Cagney <cagney@highland.com.au>
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Copyright (C) 1994-1996, Andrew Cagney <cagney@highland.com.au>
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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*/
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#ifndef _CORE_H_
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#ifndef _CORE_H_
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#define _CORE_H_
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#define _CORE_H_
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/* Introduction:
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/* Introduction:
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The core device, positioned at the top of the device tree that
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The core device, positioned at the top of the device tree that
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models the architecure being simulated, acts as an interface
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models the architecure being simulated, acts as an interface
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between the processor engines and the modeled devices.
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between the processor engines and the modeled devices.
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On the one side the processor engines issue read and write requests
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On the one side the processor engines issue read and write requests
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to the core (each request further catagorised as being for an
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to the core (each request further catagorised as being for an
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instruction or data subunit) while on the other side, the core is
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instruction or data subunit) while on the other side, the core is
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receiving address configuration and DMA requests from child
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receiving address configuration and DMA requests from child
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devices.
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devices.
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In the below a synopsis of the core object and device in PSIM is
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In the below a synopsis of the core object and device in PSIM is
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given, details of the object can be found in the files
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given, details of the object can be found in the files
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<<corefile.h>> and <<corefile.c>>.
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<<corefile.h>> and <<corefile.c>>.
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*/
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*/
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/* Core::
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/* Core::
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At the heart of the interface between devices and processor engines
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At the heart of the interface between devices and processor engines
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is a single core object. This object, in turn, has two children:
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is a single core object. This object, in turn, has two children:
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o a core device which exists in the device tree and provides
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o a core device which exists in the device tree and provides
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an interface to the core object to child devices.
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an interface to the core object to child devices.
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o a set of access maps which provide an efficient
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o a set of access maps which provide an efficient
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interface to the core object for the processor engines.
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interface to the core object for the processor engines.
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*/
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*/
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/* basic types */
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/* basic types */
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typedef struct _core core;
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typedef struct _core core;
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typedef struct _core_map core_map;
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typedef struct _core_map core_map;
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/* constructor */
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/* constructor */
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INLINE_CORE\
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INLINE_CORE\
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(core *) core_create
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(core *) core_create
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(void);
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(void);
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INLINE_CORE\
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INLINE_CORE\
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(core *) core_from_device
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(core *) core_from_device
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(device *root);
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(device *root);
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INLINE_CORE\
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INLINE_CORE\
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(void) core_init
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(void) core_init
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(core *memory);
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(core *memory);
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/* Core map management:::
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/* Core map management:::
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The core ojbect manages two different types of address maps:
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The core ojbect manages two different types of address maps:
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o raw-memory - the address range can be implemented using
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o raw-memory - the address range can be implemented using
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a simple byte array. No device needs to be notifed of
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a simple byte array. No device needs to be notifed of
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any accesses to the specified memory range.
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any accesses to the specified memory range.
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o callback - Any access to the specified address range
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o callback - Any access to the specified address range
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should be passed on to the associated device. That device
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should be passed on to the associated device. That device
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can in turn resolve the access - handling or aborting or
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can in turn resolve the access - handling or aborting or
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restarting it.
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restarting it.
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For callback maps it is possible to further order them by
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For callback maps it is possible to further order them by
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specifiying specifying a callback level (eg callback + 1).
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specifiying specifying a callback level (eg callback + 1).
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When the core is resolving an access it searches each of the maps
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When the core is resolving an access it searches each of the maps
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in order. First raw-memory and then callback maps (in assending
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in order. First raw-memory and then callback maps (in assending
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order of level). This search order makes it possible for latter
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order of level). This search order makes it possible for latter
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maps to overlap earlier ones. For instance, a device that wants to
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maps to overlap earlier ones. For instance, a device that wants to
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be notified of all accesses that are not covered by raw-memory maps
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be notified of all accesses that are not covered by raw-memory maps
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could attach its self with an address range of the entire address
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could attach its self with an address range of the entire address
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space.
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space.
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In addition, each attached address map as an associated set of
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In addition, each attached address map as an associated set of
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access attributes (readable, writeable, executable) which are
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access attributes (readable, writeable, executable) which are
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verified as part of resolving each access.
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verified as part of resolving each access.
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*/
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*/
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INLINE_CORE\
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INLINE_CORE\
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(void) core_attach
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(void) core_attach
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(core *map,
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(core *map,
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attach_type attach,
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attach_type attach,
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int address_space,
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int address_space,
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access_type access,
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access_type access,
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unsigned_word addr,
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unsigned_word addr,
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unsigned nr_bytes, /* host limited */
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unsigned nr_bytes, /* host limited */
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device *device); /*callback/default*/
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device *device); /*callback/default*/
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/* Bugs:::
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/* Bugs:::
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At present there is no method for removing address maps. That will
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At present there is no method for removing address maps. That will
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be implemented in a future release.
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be implemented in a future release.
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The operation of mapping between an address and its destination
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The operation of mapping between an address and its destination
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device or memory array is currently implemented using a simple
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device or memory array is currently implemented using a simple
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linked list. The posibility of replacing this list with a more
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linked list. The posibility of replacing this list with a more
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powerfull data structure exists.
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powerfull data structure exists.
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*/
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*/
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/* Device::
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/* Device::
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The device that corresponds to the core object is described
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The device that corresponds to the core object is described
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separatly in the devices section.
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separatly in the devices section.
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*/
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*/
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/* Access maps::
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/* Access maps::
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Providing an interface between the processor engines and the core
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Providing an interface between the processor engines and the core
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object are the access maps (core_map). Three access maps are
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object are the access maps (core_map). Three access maps are
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provided, one for each of the possible access requests that can be
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provided, one for each of the possible access requests that can be
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generated by a processor.
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generated by a processor.
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o read
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o read
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o write
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o write
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o execute
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o execute
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A processor being able to request a read (or write) or write
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A processor being able to request a read (or write) or write
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operation to any of the maps. Those operations can either be
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operation to any of the maps. Those operations can either be
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highly efficient (by specifying a specific transfer size) or
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highly efficient (by specifying a specific transfer size) or
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generic (specifying a parameterized number of bytes).
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generic (specifying a parameterized number of bytes).
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Internally the core object takes the request, determines the
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Internally the core object takes the request, determines the
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approperiate attached address space that it should handle it passes
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approperiate attached address space that it should handle it passes
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it on.
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it on.
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*/
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*/
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INLINE_CORE\
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INLINE_CORE\
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(core_map *) core_readable
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(core_map *) core_readable
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(core *memory);
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(core *memory);
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INLINE_CORE\
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INLINE_CORE\
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(core_map *) core_writeable
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(core_map *) core_writeable
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(core *memory);
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(core *memory);
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INLINE_CORE\
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INLINE_CORE\
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(core_map *) core_executable
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(core_map *) core_executable
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(core *memory);
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(core *memory);
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/* Variable sized read/write
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/* Variable sized read/write
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Transfer (zero) a variable size block of data between the host and
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Transfer (zero) a variable size block of data between the host and
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target (possibly byte swapping it). Should any problems occure,
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target (possibly byte swapping it). Should any problems occure,
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the number of bytes actually transfered is returned. */
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the number of bytes actually transfered is returned. */
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INLINE_CORE\
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INLINE_CORE\
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(unsigned) core_map_read_buffer
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(unsigned) core_map_read_buffer
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(core_map *map,
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(core_map *map,
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void *buffer,
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void *buffer,
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unsigned_word addr,
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unsigned_word addr,
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unsigned nr_bytes);
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unsigned nr_bytes);
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INLINE_CORE\
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INLINE_CORE\
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(unsigned) core_map_write_buffer
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(unsigned) core_map_write_buffer
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(core_map *map,
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(core_map *map,
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const void *buffer,
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const void *buffer,
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unsigned_word addr,
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unsigned_word addr,
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unsigned nr_bytes);
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unsigned nr_bytes);
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/* Fixed sized read/write
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/* Fixed sized read/write
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Transfer a fixed amout of memory between the host and target. The
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Transfer a fixed amout of memory between the host and target. The
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memory always being translated and the operation always aborting
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memory always being translated and the operation always aborting
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should a problem occure */
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should a problem occure */
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#define DECLARE_CORE_WRITE_N(N) \
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#define DECLARE_CORE_WRITE_N(N) \
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INLINE_CORE\
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INLINE_CORE\
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(void) core_map_write_##N \
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(void) core_map_write_##N \
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(core_map *map, \
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(core_map *map, \
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unsigned_word addr, \
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unsigned_word addr, \
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unsigned_##N val, \
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unsigned_##N val, \
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cpu *processor, \
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cpu *processor, \
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unsigned_word cia);
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unsigned_word cia);
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DECLARE_CORE_WRITE_N(1)
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DECLARE_CORE_WRITE_N(1)
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DECLARE_CORE_WRITE_N(2)
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DECLARE_CORE_WRITE_N(2)
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DECLARE_CORE_WRITE_N(4)
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DECLARE_CORE_WRITE_N(4)
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DECLARE_CORE_WRITE_N(8)
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DECLARE_CORE_WRITE_N(8)
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DECLARE_CORE_WRITE_N(word)
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DECLARE_CORE_WRITE_N(word)
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#define DECLARE_CORE_READ_N(N) \
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#define DECLARE_CORE_READ_N(N) \
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INLINE_CORE\
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INLINE_CORE\
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(unsigned_##N) core_map_read_##N \
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(unsigned_##N) core_map_read_##N \
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(core_map *map, \
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(core_map *map, \
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unsigned_word addr, \
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unsigned_word addr, \
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cpu *processor, \
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cpu *processor, \
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unsigned_word cia);
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unsigned_word cia);
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DECLARE_CORE_READ_N(1)
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DECLARE_CORE_READ_N(1)
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DECLARE_CORE_READ_N(2)
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DECLARE_CORE_READ_N(2)
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DECLARE_CORE_READ_N(4)
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DECLARE_CORE_READ_N(4)
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DECLARE_CORE_READ_N(8)
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DECLARE_CORE_READ_N(8)
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DECLARE_CORE_READ_N(word)
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DECLARE_CORE_READ_N(word)
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#endif
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#endif
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