URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [cris/] [asm/] [nopv32t3.ms] - Diff between revs 24 and 157

Rev 24	Rev 157
`#mach: crisv10 crisv32`	`#mach: crisv10 crisv32`
`#output: Schedulable clock cycles, total @: 5\n`	`#output: Schedulable clock cycles, total @: 5\n`
`#output: Memory source stall cycles: 0\n`	`#output: Memory source stall cycles: 0\n`
`#output: Memory read-after-write stall cycles: 0\n`	`#output: Memory read-after-write stall cycles: 0\n`
`#output: Movem source stall cycles: 0\n`	`#output: Movem source stall cycles: 0\n`
`#output: Movem destination stall cycles: 0\n`	`#output: Movem destination stall cycles: 0\n`
`#output: Movem address stall cycles: 0\n`	`#output: Movem address stall cycles: 0\n`
`#output: Multiplication source stall cycles: 0\n`	`#output: Multiplication source stall cycles: 0\n`
`#output: Jump source stall cycles: 0\n`	`#output: Jump source stall cycles: 0\n`
`#output: Branch misprediction stall cycles: 0\n`	`#output: Branch misprediction stall cycles: 0\n`
`#output: Jump target stall cycles: 0\n`	`#output: Jump target stall cycles: 0\n`
`#sim: --cris-cycles=schedulable`	`#sim: --cris-cycles=schedulable`
`.include "nopv32t.ms"`	`.include "nopv32t.ms"`