URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [cris/] [asm/] [raw5.ms] - Diff between revs 24 and 157

Rev 24	Rev 157
`; Checking read-after-write: write-then-nop-read 2 cycles.`	`; Checking read-after-write: write-then-nop-read 2 cycles.`
`#mach: crisv32`	`#mach: crisv32`
`#output: Basic clock cycles, total @: 5\n`	`#output: Basic clock cycles, total @: 5\n`
`#output: Memory source stall cycles: 0\n`	`#output: Memory source stall cycles: 0\n`
`#output: Memory read-after-write stall cycles: 2\n`	`#output: Memory read-after-write stall cycles: 2\n`
`#output: Movem source stall cycles: 0\n`	`#output: Movem source stall cycles: 0\n`
`#output: Movem destination stall cycles: 0\n`	`#output: Movem destination stall cycles: 0\n`
`#output: Movem address stall cycles: 0\n`	`#output: Movem address stall cycles: 0\n`
`#output: Multiplication source stall cycles: 0\n`	`#output: Multiplication source stall cycles: 0\n`
`#output: Jump source stall cycles: 0\n`	`#output: Jump source stall cycles: 0\n`
`#output: Branch misprediction stall cycles: 0\n`	`#output: Branch misprediction stall cycles: 0\n`
`#output: Jump target stall cycles: 0\n`	`#output: Jump target stall cycles: 0\n`
`#sim: --cris-cycles=basic`	`#sim: --cris-cycles=basic`
`.include "testutils.inc"`	`.include "testutils.inc"`
`startnostack`	`startnostack`
`.lcomm x,4`	`.lcomm x,4`
`.lcomm y,4`	`.lcomm y,4`
`move.d x,$r0`	`move.d x,$r0`
`move.d y,$r1`	`move.d y,$r1`
`move.d $r1,[$r0]`	`move.d $r1,[$r0]`
`nop`	`nop`
`move.d [$r1],$r2`	`move.d [$r1],$r2`
`break 15`	`break 15`