# fr30 testcase for asr $Rj,$Ri, asr $u4,$Rj
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# fr30 testcase for asr $Rj,$Ri, asr $u4,$Rj
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# mach(): fr30
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# mach(): fr30
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.include "testutils.inc"
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.include "testutils.inc"
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START
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START
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.text
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.text
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.global asr
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.global asr
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asr:
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asr:
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; Test asr $Rj,$Ri
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; Test asr $Rj,$Ri
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mvi_h_gr 0xdeadbee0,r7 ; Shift by 0
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mvi_h_gr 0xdeadbee0,r7 ; Shift by 0
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mvi_h_gr 0x80000000,r8
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mvi_h_gr 0x80000000,r8
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set_cc 0x05 ; Set mask opposite of expected
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set_cc 0x05 ; Set mask opposite of expected
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asr r7,r8
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asr r7,r8
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test_cc 1 0 0 0
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test_cc 1 0 0 0
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test_h_gr 0x80000000,r8
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test_h_gr 0x80000000,r8
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mvi_h_gr 0xdeadbee1,r7 ; Shift by 1
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mvi_h_gr 0xdeadbee1,r7 ; Shift by 1
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mvi_h_gr 0x80000000,r8
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mvi_h_gr 0x80000000,r8
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set_cc 0x07 ; Set mask opposite of expected
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set_cc 0x07 ; Set mask opposite of expected
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asr r7,r8
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asr r7,r8
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test_cc 1 0 1 0
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test_cc 1 0 1 0
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test_h_gr 0xc0000000,r8
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test_h_gr 0xc0000000,r8
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mvi_h_gr 0xdeadbeff,r7 ; Shift by 31
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mvi_h_gr 0xdeadbeff,r7 ; Shift by 31
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mvi_h_gr 0x80000000,r8
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mvi_h_gr 0x80000000,r8
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set_cc 0x07 ; Set mask opposite of expected
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set_cc 0x07 ; Set mask opposite of expected
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asr r7,r8
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asr r7,r8
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test_cc 1 0 1 0
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test_cc 1 0 1 0
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test_h_gr -1,r8
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test_h_gr -1,r8
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mvi_h_gr 0xdeadbeff,r7 ; clear register
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mvi_h_gr 0xdeadbeff,r7 ; clear register
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mvi_h_gr 0x40000000,r8
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mvi_h_gr 0x40000000,r8
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set_cc 0x0a ; Set mask opposite of expected
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set_cc 0x0a ; Set mask opposite of expected
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asr r7,r8
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asr r7,r8
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test_cc 0 1 1 1
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test_cc 0 1 1 1
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test_h_gr 0x00000000,r8
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test_h_gr 0x00000000,r8
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; Test asr $u4Ri
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; Test asr $u4Ri
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mvi_h_gr 0x80000000,r8
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mvi_h_gr 0x80000000,r8
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set_cc 0x05 ; Set mask opposite of expected
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set_cc 0x05 ; Set mask opposite of expected
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asr 0,r8
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asr 0,r8
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test_cc 1 0 0 0
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test_cc 1 0 0 0
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test_h_gr 0x80000000,r8
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test_h_gr 0x80000000,r8
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mvi_h_gr 0x80000000,r8
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mvi_h_gr 0x80000000,r8
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set_cc 0x07 ; Set mask opposite of expected
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set_cc 0x07 ; Set mask opposite of expected
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asr 1,r8
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asr 1,r8
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test_cc 1 0 1 0
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test_cc 1 0 1 0
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test_h_gr 0xc0000000,r8
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test_h_gr 0xc0000000,r8
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mvi_h_gr 0x80000000,r8
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mvi_h_gr 0x80000000,r8
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set_cc 0x07 ; Set mask opposite of expected
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set_cc 0x07 ; Set mask opposite of expected
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asr 15,r8
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asr 15,r8
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test_cc 1 0 1 0
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test_cc 1 0 1 0
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test_h_gr 0xffff0000,r8
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test_h_gr 0xffff0000,r8
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mvi_h_gr 0x00004000,r8
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mvi_h_gr 0x00004000,r8
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set_cc 0x0a ; Set mask opposite of expected
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set_cc 0x0a ; Set mask opposite of expected
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asr 15,r8
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asr 15,r8
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test_cc 0 1 1 1
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test_cc 0 1 1 1
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test_h_gr 0x00000000,r8
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test_h_gr 0x00000000,r8
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pass
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pass
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