URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [fr30/] [div0u.cgs] - Diff between revs 24 and 157

Rev 24	Rev 157
`# fr30 testcase for div0u $Ri`	`# fr30 testcase for div0u $Ri`
`# mach(): fr30`	`# mach(): fr30`

`.include "testutils.inc"`	`.include "testutils.inc"`

`START`	`START`

`.text`	`.text`
`.global div0u`	`.global div0u`
`div0u:`	`div0u:`
`; Test div0u $Rj,$Ri`	`; Test div0u $Rj,$Ri`
`; operand register has no effect`	`; operand register has no effect`
`mvi_h_gr 0xdeadbeef,r2`	`mvi_h_gr 0xdeadbeef,r2`
`mvi_h_dr 0xdeadbeef,mdh`	`mvi_h_dr 0xdeadbeef,mdh`
`mvi_h_dr 0x0ffffff0,mdl`	`mvi_h_dr 0x0ffffff0,mdl`
`set_dbits 0x3 ; Set opposite of expected`	`set_dbits 0x3 ; Set opposite of expected`
`set_cc 0x0f ; Condition codes should not change`	`set_cc 0x0f ; Condition codes should not change`
`div0u r2`	`div0u r2`
`test_cc 1 1 1 1`	`test_cc 1 1 1 1`
`test_h_gr 0xdeadbeef,r2`	`test_h_gr 0xdeadbeef,r2`
`test_h_dr 0x00000000,mdh`	`test_h_dr 0x00000000,mdh`
`test_h_dr 0x0ffffff0,mdl`	`test_h_dr 0x0ffffff0,mdl`
`test_dbits 0x0`	`test_dbits 0x0`

`pass`	`pass`