OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [fbu.cgs] - Diff between revs 24 and 157

Only display areas with differences | Details | Blame | View Log

Rev 24 Rev 157
# frv testcase for fbu $FCCi,$hint,$label16
# frv testcase for fbu $FCCi,$hint,$label16
# mach: all
# mach: all
        .include "testutils.inc"
        .include "testutils.inc"
        start
        start
        .global fbu
        .global fbu
fbu:
fbu:
        set_fcc         0x0 0
        set_fcc         0x0 0
        fbu             fcc0,0,bad
        fbu             fcc0,0,bad
        set_fcc         0x1 1
        set_fcc         0x1 1
        fbu             fcc1,1,ok2
        fbu             fcc1,1,ok2
        fail
        fail
ok2:
ok2:
        set_fcc         0x2 2
        set_fcc         0x2 2
        fbu             fcc2,2,bad
        fbu             fcc2,2,bad
        set_fcc         0x3 3
        set_fcc         0x3 3
        fbu             fcc3,3,ok4
        fbu             fcc3,3,ok4
        fail
        fail
ok4:
ok4:
        set_fcc         0x4 0
        set_fcc         0x4 0
        fbu             fcc0,0,bad
        fbu             fcc0,0,bad
        set_fcc         0x5 1
        set_fcc         0x5 1
        fbu             fcc1,1,ok6
        fbu             fcc1,1,ok6
        fail
        fail
ok6:
ok6:
        set_fcc         0x6 2
        set_fcc         0x6 2
        fbu             fcc2,2,bad
        fbu             fcc2,2,bad
        set_fcc         0x7 3
        set_fcc         0x7 3
        fbu             fcc3,3,ok8
        fbu             fcc3,3,ok8
        fail
        fail
ok8:
ok8:
        set_fcc         0x8 0
        set_fcc         0x8 0
        fbu             fcc0,0,bad
        fbu             fcc0,0,bad
        set_fcc         0x9 1
        set_fcc         0x9 1
        fbu             fcc1,1,oka
        fbu             fcc1,1,oka
        fail
        fail
oka:
oka:
        set_fcc         0xa 2
        set_fcc         0xa 2
        fbu             fcc2,2,bad
        fbu             fcc2,2,bad
        set_fcc         0xb 3
        set_fcc         0xb 3
        fbu             fcc3,3,okc
        fbu             fcc3,3,okc
        fail
        fail
okc:
okc:
        set_fcc         0xc 0
        set_fcc         0xc 0
        fbu             fcc0,0,bad
        fbu             fcc0,0,bad
        set_fcc         0xd 1
        set_fcc         0xd 1
        fbu             fcc1,1,oke
        fbu             fcc1,1,oke
        fail
        fail
oke:
oke:
        set_fcc         0xe 2
        set_fcc         0xe 2
        fbu             fcc2,2,bad
        fbu             fcc2,2,bad
        set_fcc         0xf 3
        set_fcc         0xf 3
        fbu             fcc3,3,okg
        fbu             fcc3,3,okg
        fail
        fail
okg:
okg:
        pass
        pass
bad:
bad:
        fail
        fail
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.