URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [interrupts/] [Ipipe-fr500.cgs] - Diff between revs 24 and 157

Rev 24	Rev 157
`# frv testcase`	`# frv testcase`
`# mach: fr500`	`# mach: fr500`

`.include "testutils.inc"`	`.include "testutils.inc"`

`start`	`start`

`.global Ipipe`	`.global Ipipe`
`Ipipe:`	`Ipipe:`
`; Clear the packing bit of the insn at 'pack:'. We can't`	`; Clear the packing bit of the insn at 'pack:'. We can't`
`; simply use '.p' because the assembler will catch the error.`	`; simply use '.p' because the assembler will catch the error.`
`set_gr_mem pack,gr10`	`set_gr_mem pack,gr10`
`and_gr_immed 0x7fffffff,gr10`	`and_gr_immed 0x7fffffff,gr10`
`set_mem_gr gr10,pack`	`set_mem_gr gr10,pack`
`set_gr_addr pack,gr10`	`set_gr_addr pack,gr10`
`flush_data_cache gr10`	`flush_data_cache gr10`

`and_spr_immed -4081,tbr ; clear tbr.tt`	`and_spr_immed -4081,tbr ; clear tbr.tt`
`set_gr_spr tbr,gr7`	`set_gr_spr tbr,gr7`
`inc_gr_immed 0x070,gr7 ; address of exception handler`	`inc_gr_immed 0x070,gr7 ; address of exception handler`
`set_bctrlr_0_0 gr7`	`set_bctrlr_0_0 gr7`
`set_spr_immed 128,lcr`	`set_spr_immed 128,lcr`
`set_spr_addr ok0,lr`	`set_spr_addr ok0,lr`
`set_psr_et 1`	`set_psr_et 1`

`add.p gr1,gr1,gr1`	`add.p gr1,gr1,gr1`
`pack: add gr2,gr2,gr2`	`pack: add gr2,gr2,gr2`
`bad: add gr3,gr3,gr3`	`bad: add gr3,gr3,gr3`
`fail`	`fail`
`ok0:`	`ok0:`
`test_spr_immed 1,esfr1`	`test_spr_immed 1,esfr1`
`test_spr_bits 0x3f,0,0xb,esr0`	`test_spr_bits 0x3f,0,0xb,esr0`
`test_spr_addr bad,epcr0`	`test_spr_addr bad,epcr0`

`pass`	`pass`