# frv testcase to generate interrupt for st $GRk,@($GRi,$GRj)
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# frv testcase to generate interrupt for st $GRk,@($GRi,$GRj)
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# mach: fr550
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# mach: fr550
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.include "testutils.inc"
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.include "testutils.inc"
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start
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start
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.global align
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.global align
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align:
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align:
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and_spr_immed -4081,tbr ; clear tbr.tt
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and_spr_immed -4081,tbr ; clear tbr.tt
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set_gr_spr tbr,gr17
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set_gr_spr tbr,gr17
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inc_gr_immed 0x100,gr17 ; address of exception handler
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inc_gr_immed 0x100,gr17 ; address of exception handler
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set_bctrlr_0_0 gr17
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set_bctrlr_0_0 gr17
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set_spr_immed 128,lcr
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set_spr_immed 128,lcr
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set_psr_et 1
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set_psr_et 1
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set_gr_immed 0xdeadbeef,gr17
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set_gr_immed 0xdeadbeef,gr17
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set_gr_immed 0,gr15
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set_gr_immed 0,gr15
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inc_gr_immed 2,sp ; out of alignment
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inc_gr_immed 2,sp ; out of alignment
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test_spr_bits 1,0,0,isr ; ISR.EMAM always clear (not used)
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test_spr_bits 1,0,0,isr ; ISR.EMAM always clear (not used)
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sti gr17,@(sp,0) ; no exception
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sti gr17,@(sp,0) ; no exception
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sti gr17,@(sp,4) ; no exception
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sti gr17,@(sp,4) ; no exception
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ldi @(sp,0),gr18 ; stored at unaligned address
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ldi @(sp,0),gr18 ; stored at unaligned address
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test_gr_immed 0xdeadbeef,gr18
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test_gr_immed 0xdeadbeef,gr18
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ldi @(sp,0),gr19 ; no exception
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ldi @(sp,0),gr19 ; no exception
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test_gr_immed 0xdeadbeef,gr19
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test_gr_immed 0xdeadbeef,gr19
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and_spr_immed 0xfffffffe,isr ; turn off ISR.EMAM
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and_spr_immed 0xfffffffe,isr ; turn off ISR.EMAM
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sti gr17,@(sp,0) ; misaligned -- no exception
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sti gr17,@(sp,0) ; misaligned -- no exception
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test_gr_immed 0,gr15
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test_gr_immed 0,gr15
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set_gr_gr sp,gr20
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set_gr_gr sp,gr20
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set_gr_immed 1,gr21
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set_gr_immed 1,gr21
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set_gr_immed 0x10101010,gr10
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set_gr_immed 0x10101010,gr10
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nop.p
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nop.p
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ldu @(sp,gr21),gr10 ; misaligned read no exception
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ldu @(sp,gr21),gr10 ; misaligned read no exception
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test_gr_immed 0,gr15 ; handler was not called
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test_gr_immed 0,gr15 ; handler was not called
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test_gr_immed 0xadbeefde,gr10 ; gr10 updated
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test_gr_immed 0xadbeefde,gr10 ; gr10 updated
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test_gr_immed 1,gr21 ; gr21 not updated
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test_gr_immed 1,gr21 ; gr21 not updated
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inc_gr_immed 1,gr20
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inc_gr_immed 1,gr20
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test_gr_gr gr20,sp ; sp updated
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test_gr_gr gr20,sp ; sp updated
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pass
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pass
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