# frv testcase to generate insn_access_error interrupt
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# frv testcase to generate insn_access_error interrupt
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# mach: fr550
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# mach: fr550
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# sim: --memory-region 0xfe800000,0x7f0500 --memory-region 0xfeff0540,0xfb00
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# sim: --memory-region 0xfe800000,0x7f0500 --memory-region 0xfeff0540,0xfb00
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.include "testutils.inc"
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.include "testutils.inc"
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start
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start
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.global dsr
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.global dsr
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dsr:
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dsr:
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and_spr_immed -4081,tbr ; clear tbr.tt
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and_spr_immed -4081,tbr ; clear tbr.tt
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set_gr_spr tbr,gr17
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set_gr_spr tbr,gr17
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inc_gr_immed 0x020,gr17 ; address of exception handler
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inc_gr_immed 0x020,gr17 ; address of exception handler
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set_bctrlr_0_0 gr17
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set_bctrlr_0_0 gr17
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set_spr_immed 128,lcr
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set_spr_immed 128,lcr
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set_psr_et 1
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set_psr_et 1
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set_spr_addr handler,lr
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set_spr_addr handler,lr
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set_gr_immed 0,gr16
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set_gr_immed 0,gr16
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set_gr_addr ok0,gr8
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set_gr_addr ok0,gr8
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set_gr_addr 0xfe800000,gr17
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set_gr_addr 0xfe800000,gr17
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jmpl @(gr17,gr0) ; cause interrupt
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jmpl @(gr17,gr0) ; cause interrupt
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ok0:
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ok0:
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test_gr_immed 1,gr16
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test_gr_immed 1,gr16
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set_gr_addr ok1,gr8
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set_gr_addr ok1,gr8
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set_gr_addr 0xfefffffc,gr17
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set_gr_addr 0xfefffffc,gr17
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jmpl @(gr17,gr0) ; cause interrupt
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jmpl @(gr17,gr0) ; cause interrupt
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ok1:
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ok1:
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test_gr_immed 2,gr16
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test_gr_immed 2,gr16
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pass
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pass
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handler:
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handler:
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; check interrupts
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; check interrupts
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test_spr_immed 0x1,esfr1 ; esr0 is active
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test_spr_immed 0x1,esfr1 ; esr0 is active
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; test_spr_gr epcr0,gr17 ; epcr0 is not used
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; test_spr_gr epcr0,gr17 ; epcr0 is not used
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test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid
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test_spr_bits 0x0001,0,0x1,esr0 ; esr0 is valid
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test_spr_bits 0x003e,1,0x2,esr0 ; esr0.ec is set
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test_spr_bits 0x003e,1,0x2,esr0 ; esr0.ec is set
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test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is not set
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test_spr_bits 0x0800,11,0x0,esr0 ; esr0.eav is not set
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addi gr16,1,gr16
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addi gr16,1,gr16
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movgs gr8,pcsr
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movgs gr8,pcsr
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rett 0
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rett 0
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fail
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fail
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