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| Rev 24 |
Rev 157 |
# sh testcase for ldrc, strc
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# sh testcase for ldrc, strc
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# mach: shdsp
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# mach: shdsp
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# as(shdsp): -defsym sim_cpu=1 -dsp
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# as(shdsp): -defsym sim_cpu=1 -dsp
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.include "testutils.inc"
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.include "testutils.inc"
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start
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start
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setrc_imm:
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setrc_imm:
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set_grs_a5a5
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set_grs_a5a5
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# Test setrc
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# Test setrc
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#
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#
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ldrs lstart
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ldrs lstart
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ldre lend
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ldre lend
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setrc #0xff
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setrc #0xff
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get_sr r1
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get_sr r1
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shlr16 r1
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shlr16 r1
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set_greg 0xfff, r0
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set_greg 0xfff, r0
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and r0, r1
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and r0, r1
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assertreg 0xff, r1
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assertreg 0xff, r1
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stc rs, r0 ! rs unchanged
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stc rs, r0 ! rs unchanged
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assertreg0 lstart
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assertreg0 lstart
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stc re, r0 ! re unchanged
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stc re, r0 ! re unchanged
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assertreg0 lend
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assertreg0 lend
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set_greg 0xa5a5a5a5, r0
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set_greg 0xa5a5a5a5, r0
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set_greg 0xa5a5a5a5, r1
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set_greg 0xa5a5a5a5, r1
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test_grs_a5a5
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test_grs_a5a5
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setrc_reg:
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setrc_reg:
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set_grs_a5a5
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set_grs_a5a5
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# Test setrc
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# Test setrc
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#
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#
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ldrs lstart
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ldrs lstart
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ldre lend
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ldre lend
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set_greg 0xfff, r0
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set_greg 0xfff, r0
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setrc r0
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setrc r0
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get_sr r1
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get_sr r1
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shlr16 r1
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shlr16 r1
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set_greg 0xfff, r0
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set_greg 0xfff, r0
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and r0, r1
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and r0, r1
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assertreg 0xfff, r1
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assertreg 0xfff, r1
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stc rs, r0 ! rs unchanged
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stc rs, r0 ! rs unchanged
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assertreg0 lstart
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assertreg0 lstart
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stc re, r0 ! re unchanged
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stc re, r0 ! re unchanged
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assertreg0 lend
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assertreg0 lend
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set_greg 0xa5a5a5a5, r0
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set_greg 0xa5a5a5a5, r0
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set_greg 0xa5a5a5a5, r1
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set_greg 0xa5a5a5a5, r1
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test_grs_a5a5
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test_grs_a5a5
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bra ldrc_imm
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bra ldrc_imm
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.global lstart
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.global lstart
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.align 2
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.align 2
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lstart: nop
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lstart: nop
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nop
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nop
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nop
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nop
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nop
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nop
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.global lend
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.global lend
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.align 2
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.align 2
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lend: nop
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lend: nop
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nop
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nop
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nop
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nop
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nop
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nop
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ldrc_imm:
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ldrc_imm:
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set_grs_a5a5
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set_grs_a5a5
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# Test ldrc
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# Test ldrc
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setrc #0x0 ! zero rc
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setrc #0x0 ! zero rc
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ldrc #0xa5
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ldrc #0xa5
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get_sr r1
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get_sr r1
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shlr16 r1
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shlr16 r1
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set_greg 0xfff, r0
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set_greg 0xfff, r0
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and r0, r1
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and r0, r1
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assertreg 0xa5, r1
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assertreg 0xa5, r1
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stc rs, r0 ! rs unchanged
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stc rs, r0 ! rs unchanged
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assertreg0 lstart
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assertreg0 lstart
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stc re, r0
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stc re, r0
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assertreg0 lend+1 ! bit 0 set in re
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assertreg0 lend+1 ! bit 0 set in re
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# fix up re for next test
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# fix up re for next test
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dt r0 ! Ugh! No DEC insn!
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dt r0 ! Ugh! No DEC insn!
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ldc r0, re
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ldc r0, re
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set_greg 0xa5a5a5a5, r0
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set_greg 0xa5a5a5a5, r0
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set_greg 0xa5a5a5a5, r1
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set_greg 0xa5a5a5a5, r1
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test_grs_a5a5
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test_grs_a5a5
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ldrc_reg:
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ldrc_reg:
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set_grs_a5a5
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set_grs_a5a5
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# Test ldrc
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# Test ldrc
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setrc #0x0 ! zero rc
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setrc #0x0 ! zero rc
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set_greg 0xa5a, r0
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set_greg 0xa5a, r0
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ldrc r0
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ldrc r0
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get_sr r1
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get_sr r1
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shlr16 r1
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shlr16 r1
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set_greg 0xfff, r0
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set_greg 0xfff, r0
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and r0, r1
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and r0, r1
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assertreg 0xa5a, r1
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assertreg 0xa5a, r1
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stc rs, r0 ! rs unchanged
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stc rs, r0 ! rs unchanged
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assertreg0 lstart
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assertreg0 lstart
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stc re, r0
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stc re, r0
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assertreg0 lend+1 ! bit 0 set in re
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assertreg0 lend+1 ! bit 0 set in re
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set_greg 0xa5a5a5a5, r0
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set_greg 0xa5a5a5a5, r0
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set_greg 0xa5a5a5a5, r1
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set_greg 0xa5a5a5a5, r1
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test_grs_a5a5
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test_grs_a5a5
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pass
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pass
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exit 0
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exit 0
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