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https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
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Rev 157 |
# sh testcase for mac.l
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# sh testcase for mac.l
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# mach: all
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# mach: all
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# as(sh): -defsym sim_cpu=0
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# as(sh): -defsym sim_cpu=0
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# as(shdsp): -defsym sim_cpu=1 -dsp
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# as(shdsp): -defsym sim_cpu=1 -dsp
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.include "testutils.inc"
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.include "testutils.inc"
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start
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start
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# force S-bit clear
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# force S-bit clear
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clrs
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clrs
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init:
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init:
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# Prime {MACL, MACH} to #1.
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# Prime {MACL, MACH} to #1.
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mov #1, r0
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mov #1, r0
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dmulu.l r0, r0
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dmulu.l r0, r0
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# Set up addresses.
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# Set up addresses.
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mov.l pfour00, r0 ! 85
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mov.l pfour00, r0 ! 85
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mov.l pfour12, r1 ! 17
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mov.l pfour12, r1 ! 17
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test:
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test:
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mac.l @r0+, @r1+
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mac.l @r0+, @r1+
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check:
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check:
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# Check result.
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# Check result.
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assert_sreg 0, mach
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assert_sreg 0, mach
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assert_sreg 85*17+1, macl
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assert_sreg 85*17+1, macl
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# Ensure post-increment occurred.
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# Ensure post-increment occurred.
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assertreg0 four00+4
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assertreg0 four00+4
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assertreg four12+4, r1
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assertreg four12+4, r1
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doubleinc:
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doubleinc:
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mov.l pfour00, r0
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mov.l pfour00, r0
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mac.l @r0+, @r0+
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mac.l @r0+, @r0+
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assertreg0 four00+8
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assertreg0 four00+8
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pass
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pass
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exit 0
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exit 0
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.align 1
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.align 1
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four00:
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four00:
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.long 85
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.long 85
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.long 2
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.long 2
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four12:
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four12:
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.long 17
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.long 17
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.long 3
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.long 3
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.align 2
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.align 2
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pfour00:
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pfour00:
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.long four00
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.long four00
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pfour12:
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pfour12:
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.long four12
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.long four12
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