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https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
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| Rev 24 |
Rev 157 |
# sh testcase for paddc
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# sh testcase for paddc
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# mach: shdsp
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# mach: shdsp
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# as(shdsp): -defsym sim_cpu=1 -dsp
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# as(shdsp): -defsym sim_cpu=1 -dsp
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.include "testutils.inc"
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.include "testutils.inc"
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start
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start
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set_grs_a5a5
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set_grs_a5a5
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lds r0, a0
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lds r0, a0
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pcopy a0, a1
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pcopy a0, a1
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lds r0, x0
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lds r0, x0
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lds r0, x1
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lds r0, x1
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lds r0, y0
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lds r0, y0
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lds r0, y1
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lds r0, y1
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pcopy x0, m0
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pcopy x0, m0
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pcopy y1, m1
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pcopy y1, m1
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# 2 + 2 = 4
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# 2 + 2 = 4
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set_dcfalse
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set_dcfalse
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mov #2, r0
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mov #2, r0
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lds r0, x0
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lds r0, x0
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lds r0, y0
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lds r0, y0
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paddc x0, y0, a0
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paddc x0, y0, a0
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assert_sreg 4, a0
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assert_sreg 4, a0
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# 2 + 2 + carry = 5
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# 2 + 2 + carry = 5
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set_dctrue
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set_dctrue
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paddc x0, y0, a1
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paddc x0, y0, a1
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assert_sreg2 5, a1
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assert_sreg2 5, a1
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set_greg 0xa5a5a5a5, r0
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set_greg 0xa5a5a5a5, r0
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test_grs_a5a5
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test_grs_a5a5
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assert_sreg 0xa5a5a5a5, x1
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assert_sreg 0xa5a5a5a5, x1
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assert_sreg 0xa5a5a5a5, y1
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assert_sreg 0xa5a5a5a5, y1
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assert_sreg2 0xa5a5a5a5, m0
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assert_sreg2 0xa5a5a5a5, m0
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assert_sreg2 0xa5a5a5a5, m1
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assert_sreg2 0xa5a5a5a5, m1
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pass
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pass
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exit 0
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exit 0
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