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https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
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Rev 157 |
# sh testcase for prnd
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# sh testcase for prnd
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# mach: shdsp
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# mach: shdsp
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# as(shdsp): -defsym sim_cpu=1 -dsp
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# as(shdsp): -defsym sim_cpu=1 -dsp
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# FIXME: opcode table ambiguity in ignored bits 4-7.
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# FIXME: opcode table ambiguity in ignored bits 4-7.
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.include "testutils.inc"
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.include "testutils.inc"
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start
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start
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set_grs_a5a5
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set_grs_a5a5
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lds r0, a0
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lds r0, a0
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pcopy a0, a1
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pcopy a0, a1
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lds r0, x0
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lds r0, x0
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lds r0, x1
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lds r0, x1
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lds r0, y0
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lds r0, y0
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lds r0, y1
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lds r0, y1
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pcopy x0, m0
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pcopy x0, m0
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pcopy y1, m1
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pcopy y1, m1
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# prnd(0xa5a5a5a5) = 0xa5a60000
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# prnd(0xa5a5a5a5) = 0xa5a60000
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prnd x0, x0
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prnd x0, x0
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prnd y0, y0
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prnd y0, y0
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assert_sreg 0xa5a60000, x0
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assert_sreg 0xa5a60000, x0
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assert_sreg 0xa5a60000, y0
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assert_sreg 0xa5a60000, y0
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# prnd(1) = 1
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# prnd(1) = 1
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mov #1, r0
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mov #1, r0
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shll16 r0
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shll16 r0
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lds r0, x0
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lds r0, x0
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pcopy x0, y0
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pcopy x0, y0
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prnd x0, x0
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prnd x0, x0
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prnd y0, y0
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prnd y0, y0
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assert_sreg 0x10000, x0
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assert_sreg 0x10000, x0
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assert_sreg 0x10000, y0
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assert_sreg 0x10000, y0
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# prnd(1.4999999) = 1
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# prnd(1.4999999) = 1
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mov #1, r0
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mov #1, r0
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shll8 r0
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shll8 r0
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or #0x7f, r0
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or #0x7f, r0
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shll8 r0
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shll8 r0
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or #0xff, r0
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or #0xff, r0
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lds r0, x0
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lds r0, x0
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pcopy x0, y0
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pcopy x0, y0
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prnd x0, x0
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prnd x0, x0
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prnd y0, y0
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prnd y0, y0
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assert_sreg 0x10000, x0
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assert_sreg 0x10000, x0
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assert_sreg 0x10000, y0
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assert_sreg 0x10000, y0
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# prnd(1.5) = 2
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# prnd(1.5) = 2
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mov #1, r0
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mov #1, r0
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shll8 r0
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shll8 r0
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or #0x80, r0
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or #0x80, r0
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shll8 r0
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shll8 r0
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lds r0, x0
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lds r0, x0
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pcopy x0, y0
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pcopy x0, y0
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prnd x0, x0
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prnd x0, x0
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prnd y0, y0
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prnd y0, y0
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assert_sreg 0x20000, x0
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assert_sreg 0x20000, x0
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assert_sreg 0x20000, y0
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assert_sreg 0x20000, y0
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# dct prnd
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# dct prnd
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set_dcfalse
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set_dcfalse
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dct prnd x0, x1
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dct prnd x0, x1
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dct prnd y0, y1
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dct prnd y0, y1
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assert_sreg2 0xa5a5a5a5, x1
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assert_sreg2 0xa5a5a5a5, x1
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assert_sreg2 0xa5a5a5a5, y1
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assert_sreg2 0xa5a5a5a5, y1
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set_dctrue
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set_dctrue
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dct prnd x0, x1
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dct prnd x0, x1
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dct prnd y0, y1
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dct prnd y0, y1
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assert_sreg2 0x20000, x1
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assert_sreg2 0x20000, x1
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assert_sreg2 0x20000, y1
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assert_sreg2 0x20000, y1
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# dcf prnd
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# dcf prnd
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set_dctrue
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set_dctrue
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dcf prnd x0, m0
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dcf prnd x0, m0
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dcf prnd y0, m1
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dcf prnd y0, m1
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assert_sreg2 0xa5a5a5a5, m0
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assert_sreg2 0xa5a5a5a5, m0
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assert_sreg2 0xa5a5a5a5, m1
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assert_sreg2 0xa5a5a5a5, m1
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set_dcfalse
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set_dcfalse
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dcf prnd x0, m0
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dcf prnd x0, m0
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dcf prnd y0, m1
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dcf prnd y0, m1
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assert_sreg2 0x20000, m0
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assert_sreg2 0x20000, m0
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assert_sreg2 0x20000, m1
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assert_sreg2 0x20000, m1
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set_greg 0xa5a5a5a5, r0
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set_greg 0xa5a5a5a5, r0
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test_grs_a5a5
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test_grs_a5a5
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assert_sreg 0xa5a5a5a5, a0
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assert_sreg 0xa5a5a5a5, a0
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assert_sreg2 0xa5a5a5a5, a1
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assert_sreg2 0xa5a5a5a5, a1
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pass
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pass
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exit 0
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exit 0
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