URL
https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
Only display areas with differences |
Details |
Blame |
View Log
Rev 24 |
Rev 157 |
# sh testcase for shlr16
|
# sh testcase for shlr16
|
# mach: all
|
# mach: all
|
# as(sh): -defsym sim_cpu=0
|
# as(sh): -defsym sim_cpu=0
|
# as(shdsp): -defsym sim_cpu=1 -dsp
|
# as(shdsp): -defsym sim_cpu=1 -dsp
|
|
|
.include "testutils.inc"
|
.include "testutils.inc"
|
|
|
start
|
start
|
|
|
shrl16:
|
shrl16:
|
set_grs_a5a5
|
set_grs_a5a5
|
shlr16 r0
|
shlr16 r0
|
assertreg0 0xa5a5
|
assertreg0 0xa5a5
|
shlr16 r0
|
shlr16 r0
|
assertreg0 0
|
assertreg0 0
|
|
|
set_greg 0xa5a5a5a5, r0
|
set_greg 0xa5a5a5a5, r0
|
test_grs_a5a5
|
test_grs_a5a5
|
pass
|
pass
|
exit 0
|
exit 0
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.