OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [sh64/] [media/] [addil.cgs] - Diff between revs 24 and 157

Only display areas with differences | Details | Blame | View Log

Rev 24 Rev 157
# sh testcase for addi.l $rm, $disp10, $rd -*- Asm -*-
# sh testcase for addi.l $rm, $disp10, $rd -*- Asm -*-
# mach: all
# mach: all
# as: -isa=shmedia
# as: -isa=shmedia
# ld: -m shelf64
# ld: -m shelf64
        .include "media/testutils.inc"
        .include "media/testutils.inc"
        start
        start
init:
init:
        pta wrong, tr0
        pta wrong, tr0
addil0:
addil0:
        movi 1, r63
        movi 1, r63
        addi.l r63, 0, r1
        addi.l r63, 0, r1
        bnei r1, 0, tr0
        bnei r1, 0, tr0
addil1:
addil1:
        movi 10, r0
        movi 10, r0
        addi.l r0, 0, r3
        addi.l r0, 0, r3
        bnei r3, 10, tr0
        bnei r3, 10, tr0
addil2:
addil2:
        movi 0, r0
        movi 0, r0
        addi.l r0, 10, r2
        addi.l r0, 10, r2
        bnei r2, 10, tr0
        bnei r2, 10, tr0
addil3:
addil3:
        addi.l r63, 10, r1
        addi.l r63, 10, r1
        bnei r1, 10, tr0
        bnei r1, 10, tr0
addil4:
addil4:
        movi 10, r0
        movi 10, r0
        addi.l r0, 0, r1
        addi.l r0, 0, r1
        bnei r1, 10, tr0
        bnei r1, 10, tr0
addil5:
addil5:
        # Ensure top 32-bits are discarded when adding.
        # Ensure top 32-bits are discarded when adding.
        movi 10, r0
        movi 10, r0
        shlli r0, 32, r0
        shlli r0, 32, r0
        addi r0, 10, r0
        addi r0, 10, r0
        addi.l r0, 10, r2
        addi.l r0, 10, r2
        bnei r2, 20, tr0
        bnei r2, 20, tr0
okay:
okay:
        pass
        pass
wrong:
wrong:
        fail
        fail
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.