/* crt0.S. C Runtime startup file.
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/* crt0.S. C Runtime startup file.
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|
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Copyright (C) 2004, Jacob Bower
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Copyright (C) 2004, Jacob Bower
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Copyright (C) 2010, Embecosm Limited
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Copyright (C) 2010, Embecosm Limited
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Contributor Jeremy Bennett
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Contributor Jeremy Bennett
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This file is part of Newlib.
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This file is part of Newlib.
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The original work by Jacob Bower is provided as-is without any kind of
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The original work by Jacob Bower is provided as-is without any kind of
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warranty. Use it at your own risk!
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warranty. Use it at your own risk!
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All subsequent work is bound by version 3 of the GPL as follows.
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All subsequent work is bound by version 3 of the GPL as follows.
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This program is free software; you can redistribute it and/or modify it
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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any later version.
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|
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This program is distributed in the hope that it will be useful, but WITHOUT
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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more details.
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You should have received a copy of the GNU General Public License along
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You should have received a copy of the GNU General Public License along
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with this program. If not, see . */
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with this program. If not, see . */
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/* -------------------------------------------------------------------------- */
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/* -------------------------------------------------------------------------- */
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/* This program is commented throughout in a fashion suitable for processing
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/* This program is commented throughout in a fashion suitable for processing
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with Doxygen. */
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with Doxygen. */
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/* -------------------------------------------------------------------------- */
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/* -------------------------------------------------------------------------- */
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#include "spr-defs.h"
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#include "spr-defs.h"
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#include "or1ksim-board.h"
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#include "or1ksim-board.h"
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|
|
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/* -------------------------------------------------------------------------- */
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/* -------------------------------------------------------------------------- */
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/*!Macro for expressions which do not have their own handler.
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/*!Macro for expressions which do not have their own handler.
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|
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Construct the arguments for a call to printf, then exit. Being varargs, the
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Construct the arguments for a call to printf, then exit. Being varargs, the
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arguments to printf must be on the stack, which we update using the
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arguments to printf must be on the stack, which we update using the
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standard prologue.
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standard prologue.
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|
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@param[in] str Label for a string describing the macro, suitable for
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@param[in] str Label for a string describing the macro, suitable for
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printf. */
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printf. */
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/* -------------------------------------------------------------------------- */
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/* -------------------------------------------------------------------------- */
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#define UNHANDLED_EXCEPTION(str) \
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#define UNHANDLED_EXCEPTION(str) \
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l.addi r1,r1,-20 /* Standard prologue */ ;\
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l.addi r1,r1,-20 /* Standard prologue */ ;\
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l.sw 16(r1),r2 ;\
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l.sw 16(r1),r2 ;\
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l.addi r2,r1,20 ;\
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l.addi r2,r1,20 ;\
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l.sw 12(r1),r9 ;\
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l.sw 12(r1),r9 ;\
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;\
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;\
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l.movhi r3,hi(.Lfmt) /* printf format string */ ;\
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l.movhi r3,hi(.Lfmt) /* printf format string */ ;\
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l.ori r3,r3,lo(.Lfmt) ;\
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l.ori r3,r3,lo(.Lfmt) ;\
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l.sw 0(r1),r3 ;\
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l.sw 0(r1),r3 ;\
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l.movhi r4,hi(str) /* Name of exception */ ;\
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l.movhi r4,hi(str) /* Name of exception */ ;\
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l.ori r4,r4,lo(str) ;\
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l.ori r4,r4,lo(str) ;\
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l.sw 4(r1),r4 ;\
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l.sw 4(r1),r4 ;\
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l.mfspr r5,r0,SPR_EPCR_BASE /* Source of the interrupt */ ;\
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l.mfspr r5,r0,SPR_EPCR_BASE /* Source of the interrupt */ ;\
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l.jal _printf ;\
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l.jal _printf ;\
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l.sw 8(r1),r5 ;\
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l.sw 8(r1),r5 ;\
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;\
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;\
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l.ori r3,r0,0xffff /* Failure RC */ ;\
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l.ori r3,r0,0xffff /* Failure RC */ ;\
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l.jal _exit ;\
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l.jal _exit ;\
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l.nop ;\
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l.nop ;\
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;\
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;\
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l.rfe /* Never executed we hope */
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l.rfe /* Never executed we hope */
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/* -------------------------------------------------------------------------- */
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/* -------------------------------------------------------------------------- */
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/*!Text strings for the different exceptions */
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/*!Text strings for the different exceptions */
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/* -------------------------------------------------------------------------- */
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/* -------------------------------------------------------------------------- */
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.section .rodata
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.section .rodata
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.Lfmt: .string "Unhandled %s exception at address %08p\n"
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.Lfmt: .string "Unhandled %s exception at address %08p\n"
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.L200: .string "bus error"
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.L200: .string "bus error"
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.L300: .string "data page fault"
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.L300: .string "data page fault"
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.L400: .string "instruction page fault"
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.L400: .string "instruction page fault"
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.L500: .string "timer"
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.L500: .string "timer"
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.L600: .string "alignment"
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.L600: .string "alignment"
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.L700: .string "illegal instruction"
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.L700: .string "illegal instruction"
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.L800: .string "external interrupt"
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.L800: .string "external interrupt"
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.L900: .string "data TLB"
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.L900: .string "data TLB"
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.La00: .string "instruction TLB"
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.La00: .string "instruction TLB"
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.Lb00: .string "range"
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.Lb00: .string "range"
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.Lc00: .string "syscall"
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.Lc00: .string "syscall"
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.Ld00: .string "floating point"
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.Ld00: .string "floating point"
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.Le00: .string "trap"
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.Le00: .string "trap"
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.Lf00: .string "undefined 0xf00"
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.Lf00: .string "undefined 0xf00"
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.L1000: .string "undefined 0x1000"
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.L1000: .string "undefined 0x1000"
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.L1100: .string "undefined 0x1100"
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.L1100: .string "undefined 0x1100"
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.L1200: .string "undefined 0x1200"
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.L1200: .string "undefined 0x1200"
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.L1300: .string "undefined 0x1300"
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.L1300: .string "undefined 0x1300"
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.L1400: .string "undefined 0x1400"
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.L1400: .string "undefined 0x1400"
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.L1500: .string "undefined 0x1500"
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.L1500: .string "undefined 0x1500"
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.L1600: .string "undefined 0x1600"
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.L1600: .string "undefined 0x1600"
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.L1700: .string "undefined 0x1700"
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.L1700: .string "undefined 0x1700"
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.L1800: .string "undefined 0x1800"
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.L1800: .string "undefined 0x1800"
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.L1900: .string "undefined 0x1900"
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.L1900: .string "undefined 0x1900"
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.L1a00: .string "undefined 0x1a00"
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.L1a00: .string "undefined 0x1a00"
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.L1b00: .string "undefined 0x1b00"
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.L1b00: .string "undefined 0x1b00"
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.L1c00: .string "undefined 0x1c00"
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.L1c00: .string "undefined 0x1c00"
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.L1d00: .string "undefined 0x1d00"
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.L1d00: .string "undefined 0x1d00"
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.L1e00: .string "undefined 0x1e00"
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.L1e00: .string "undefined 0x1e00"
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.L1f00: .string "undefined 0x1f00"
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.L1f00: .string "undefined 0x1f00"
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|
|
|
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/* -------------------------------------------------------------------------- */
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/* -------------------------------------------------------------------------- */
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/*!Exception vectors */
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/*!Exception vectors */
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/* -------------------------------------------------------------------------- */
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/* -------------------------------------------------------------------------- */
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.section .vectors,"ax"
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.section .vectors,"ax"
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|
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/* 0x100: RESET exception */
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/* 0x100: RESET exception */
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.org 0x100
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.org 0x100
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_reset:
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_reset:
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/* Jump to program initialisation code */
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/* Jump to program initialisation code */
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l.j _start
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l.j _start
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l.nop
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l.nop
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|
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/* 0x200: BUS exception is special, because during startup we use it
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/* 0x200: BUS exception is special, because during startup we use it
|
to detect where the stack should go. So we need some special code
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to detect where the stack should go. So we need some special code
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before we return, which wel will later overwrite with l.nop.
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before we return, which wel will later overwrite with l.nop.
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|
|
We use registers we know will not interfere in this case. */
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We use registers we know will not interfere in this case. */
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.org 0x200
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.org 0x200
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_buserr:
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_buserr:
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l.mfspr r24,r0,SPR_EPCR_BASE
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l.mfspr r24,r0,SPR_EPCR_BASE
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l.addi r24,r24,4 /* Return one instruction on */
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l.addi r24,r24,4 /* Return one instruction on */
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l.mtspr r0,r24,SPR_EPCR_BASE
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l.mtspr r0,r24,SPR_EPCR_BASE
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l.rfe
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l.rfe
|
|
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_buserr_std:
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_buserr_std:
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UNHANDLED_EXCEPTION (.L200)
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UNHANDLED_EXCEPTION (.L200)
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|
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/* 0x300: Data Page Fault exception */
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/* 0x300: Data Page Fault exception */
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.org 0x300
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.org 0x300
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UNHANDLED_EXCEPTION (.L300)
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UNHANDLED_EXCEPTION (.L300)
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|
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/* 0x400: Insn Page Fault exception */
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/* 0x400: Insn Page Fault exception */
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.org 0x400
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.org 0x400
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UNHANDLED_EXCEPTION (.L400)
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UNHANDLED_EXCEPTION (.L400)
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|
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/* 0x500: Timer exception */
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/* 0x500: Timer exception */
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.org 0x500
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.org 0x500
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UNHANDLED_EXCEPTION (.L500)
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UNHANDLED_EXCEPTION (.L500)
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|
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/* 0x600: Aligment exception */
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/* 0x600: Aligment exception */
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.org 0x600
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.org 0x600
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UNHANDLED_EXCEPTION (.L600)
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UNHANDLED_EXCEPTION (.L600)
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|
|
/* 0x700: Illegal insn exception */
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/* 0x700: Illegal insn exception */
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.org 0x700
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.org 0x700
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UNHANDLED_EXCEPTION (.L700)
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UNHANDLED_EXCEPTION (.L700)
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|
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/* 0x800: External interrupt exception */
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/* 0x800: External interrupt exception */
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.org 0x800
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.org 0x800
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UNHANDLED_EXCEPTION (.L800)
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UNHANDLED_EXCEPTION (.L800)
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|
|
/* 0x900: DTLB miss exception */
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/* 0x900: DTLB miss exception */
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.org 0x900
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.org 0x900
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UNHANDLED_EXCEPTION (.L900)
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UNHANDLED_EXCEPTION (.L900)
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|
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/* 0xa00: ITLB miss exception */
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/* 0xa00: ITLB miss exception */
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.org 0xa00
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.org 0xa00
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UNHANDLED_EXCEPTION (.La00)
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UNHANDLED_EXCEPTION (.La00)
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|
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/* 0xb00: Range exception */
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/* 0xb00: Range exception */
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.org 0xb00
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.org 0xb00
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UNHANDLED_EXCEPTION (.Lb00)
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UNHANDLED_EXCEPTION (.Lb00)
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|
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/* 0xc00: Syscall exception */
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/* 0xc00: Syscall exception */
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.org 0xc00
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.org 0xc00
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UNHANDLED_EXCEPTION (.Lc00)
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UNHANDLED_EXCEPTION (.Lc00)
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|
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/* 0xd00: floating point exception */
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/* 0xd00: floating point exception */
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.org 0xd00
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.org 0xd00
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UNHANDLED_EXCEPTION (.Ld00)
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UNHANDLED_EXCEPTION (.Ld00)
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|
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/* 0xe00: Trap exception */
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/* 0xe00: Trap exception */
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.org 0xe00
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.org 0xe00
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UNHANDLED_EXCEPTION (.Le00)
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UNHANDLED_EXCEPTION (.Le00)
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|
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/* 0xf00: Reserved exceptions */
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/* 0xf00: Reserved exceptions */
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.org 0xf00
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.org 0xf00
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UNHANDLED_EXCEPTION (.Lf00)
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UNHANDLED_EXCEPTION (.Lf00)
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|
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.org 0x1000
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.org 0x1000
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UNHANDLED_EXCEPTION (.L1000)
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UNHANDLED_EXCEPTION (.L1000)
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|
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.org 0x1100
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.org 0x1100
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UNHANDLED_EXCEPTION (.L1100)
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UNHANDLED_EXCEPTION (.L1100)
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|
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.org 0x1200
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.org 0x1200
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UNHANDLED_EXCEPTION (.L1200)
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UNHANDLED_EXCEPTION (.L1200)
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|
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.org 0x1300
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.org 0x1300
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UNHANDLED_EXCEPTION (.L1300)
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UNHANDLED_EXCEPTION (.L1300)
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|
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.org 0x1400
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.org 0x1400
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UNHANDLED_EXCEPTION (.L1400)
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UNHANDLED_EXCEPTION (.L1400)
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|
|
.org 0x1500
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.org 0x1500
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UNHANDLED_EXCEPTION (.L1500)
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UNHANDLED_EXCEPTION (.L1500)
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|
|
.org 0x1600
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.org 0x1600
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UNHANDLED_EXCEPTION (.L1600)
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UNHANDLED_EXCEPTION (.L1600)
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|
|
.org 0x1700
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.org 0x1700
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UNHANDLED_EXCEPTION (.L1700)
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UNHANDLED_EXCEPTION (.L1700)
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|
|
.org 0x1800
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.org 0x1800
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UNHANDLED_EXCEPTION (.L1800)
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UNHANDLED_EXCEPTION (.L1800)
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|
|
.org 0x1900
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.org 0x1900
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UNHANDLED_EXCEPTION (.L1900)
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UNHANDLED_EXCEPTION (.L1900)
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|
|
.org 0x1a00
|
.org 0x1a00
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UNHANDLED_EXCEPTION (.L1a00)
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UNHANDLED_EXCEPTION (.L1a00)
|
|
|
.org 0x1b00
|
.org 0x1b00
|
UNHANDLED_EXCEPTION (.L1b00)
|
UNHANDLED_EXCEPTION (.L1b00)
|
|
|
.org 0x1c00
|
.org 0x1c00
|
UNHANDLED_EXCEPTION (.L1c00)
|
UNHANDLED_EXCEPTION (.L1c00)
|
|
|
.org 0x1d00
|
.org 0x1d00
|
UNHANDLED_EXCEPTION (.L1d00)
|
UNHANDLED_EXCEPTION (.L1d00)
|
|
|
.org 0x1e00
|
.org 0x1e00
|
UNHANDLED_EXCEPTION (.L1e00)
|
UNHANDLED_EXCEPTION (.L1e00)
|
|
|
.org 0x1f00
|
.org 0x1f00
|
UNHANDLED_EXCEPTION (.L1f00)
|
UNHANDLED_EXCEPTION (.L1f00)
|
|
|
/* Pad to the end */
|
/* Pad to the end */
|
.org 0x1ffc
|
.org 0x1ffc
|
l.nop
|
l.nop
|
|
|
/* -------------------------------------------------------------------------- */
|
/* -------------------------------------------------------------------------- */
|
/*!Main entry point
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/*!Main entry point
|
|
|
We initialise the stack and frame pointer first, before we set up the
|
We initialise the stack and frame pointer first, before we set up the
|
caches, since otherwise we'll need to disable the instruction cache when
|
caches, since otherwise we'll need to disable the instruction cache when
|
patching the bus error vector code.
|
patching the bus error vector code.
|
|
|
The remaining tasks are then:
|
The remaining tasks are then:
|
- optionally set up instruction and/or data caches
|
- optionally set up instruction and/or data caches
|
- clear BSS
|
- clear BSS
|
- call global and static constructors
|
- call global and static constructors
|
- set up destructors to be called from exit
|
- set up destructors to be called from exit
|
- initialize the UART (may be dummy, if no UART supported)
|
- initialize the UART (may be dummy, if no UART supported)
|
- jump to the main function
|
- jump to the main function
|
- call exit if the main function ever returns.
|
- call exit if the main function ever returns.
|
- loop forever (should never get here) */
|
- loop forever (should never get here) */
|
/* -------------------------------------------------------------------------- */
|
/* -------------------------------------------------------------------------- */
|
/* The stack grows down from the top of writable memory. */
|
/* The stack grows down from the top of writable memory. */
|
.section .data
|
.section .data
|
.global _stack
|
.global _stack
|
_stack: .space 4,0
|
_stack: .space 4,0
|
|
|
.section .text
|
.section .text
|
.global _start
|
.global _start
|
.type _start,@function
|
.type _start,@function
|
|
|
_start:
|
_start:
|
/* Determine where the stack should end. Must be somewhere above the
|
/* Determine where the stack should end. Must be somewhere above the
|
end of loaded memory. We look in blocks of 64KB. */
|
end of loaded memory. We look in blocks of 64KB. */
|
l.movhi r30,hi(end)
|
l.movhi r30,hi(end)
|
l.ori r30,r30,lo(end)
|
l.ori r30,r30,lo(end)
|
l.srli r30,r30,16 /* Round down to 64KB boundary */
|
l.srli r30,r30,16 /* Round down to 64KB boundary */
|
l.slli r30,r30,16
|
l.slli r30,r30,16
|
|
|
l.addi r28,r0,1 /* Constant 64KB in register */
|
l.addi r28,r0,1 /* Constant 64KB in register */
|
l.slli r28,r28,16
|
l.slli r28,r28,16
|
|
|
l.add r30,r30,r28
|
l.add r30,r30,r28
|
l.addi r30,r30,-4 /* SP one word inside next 64KB? */
|
l.addi r30,r30,-4 /* SP one word inside next 64KB? */
|
|
|
l.movhi r26,0xaaaa /* Test pattern to store in memory */
|
l.movhi r26,0xaaaa /* Test pattern to store in memory */
|
l.ori r26,r26,0xaaaa
|
l.ori r26,r26,0xaaaa
|
|
|
/* Is this a writeable location? */
|
/* Is this a writeable location? */
|
.L3:
|
.L3:
|
l.sw 0(r30),r26
|
l.sw 0(r30),r26
|
l.lwz r24,0(r30)
|
l.lwz r24,0(r30)
|
l.sfeq r24,r26
|
l.sfeq r24,r26
|
l.bnf .L4
|
l.bnf .L4
|
l.nop
|
l.nop
|
|
|
l.j .L3
|
l.j .L3
|
l.add r30,r30,r28 /* Try 64KB higher */
|
l.add r30,r30,r28 /* Try 64KB higher */
|
|
|
.L4:
|
.L4:
|
l.sub r30,r30,r28 /* Previous value was wanted */
|
l.sub r30,r30,r28 /* Previous value was wanted */
|
l.movhi r26,hi(_stack)
|
l.movhi r26,hi(_stack)
|
l.ori r26,r26,lo(_stack)
|
l.ori r26,r26,lo(_stack)
|
l.sw 0(r26),r30
|
l.sw 0(r26),r30
|
|
|
/* Initialise stack and frame pointer (set to same value) */
|
/* Initialise stack and frame pointer (set to same value) */
|
l.add r1,r30,r0
|
l.add r1,r30,r0
|
l.add r2,r30,r0
|
l.add r2,r30,r0
|
|
|
/* Clear out the bus error vector special code. */
|
/* Clear out the bus error vector special code. */
|
l.movhi r30,hi(_buserr)
|
l.movhi r30,hi(_buserr)
|
l.ori r30,r30,lo(_buserr)
|
l.ori r30,r30,lo(_buserr)
|
l.movhi r28,hi(_buserr_std)
|
l.movhi r28,hi(_buserr_std)
|
l.ori r28,r28,lo(_buserr_std)
|
l.ori r28,r28,lo(_buserr_std)
|
l.movhi r26,0x1500 /* l.nop 0 */
|
l.movhi r26,0x1500 /* l.nop 0 */
|
l.ori r26,r26,0x0000
|
l.ori r26,r26,0x0000
|
|
|
.L5:
|
.L5:
|
l.sfeq r28,r30
|
l.sfeq r28,r30
|
l.bf .L6
|
l.bf .L6
|
l.nop
|
l.nop
|
|
|
l.sw 0(r30),r26 /* Patch the instruction */
|
l.sw 0(r30),r26 /* Patch the instruction */
|
l.j .L5
|
l.j .L5
|
l.addi r30,r30,4 /* Delay slot: next instruction */
|
l.addi r30,r30,4 /* Delay slot: next instruction */
|
|
|
.L6:
|
.L6:
|
/* Cache initialisation. Enable IC and/or DC */
|
/* Instruction cache enable */
|
.if IC_ENABLE || DC_ENABLE
|
/* Check if IC present and skip enabling otherwise */
|
l.mfspr r10,r0,SPR_SR
|
l.mfspr r24,r0,SPR_UPR
|
.if IC_ENABLE
|
l.andi r26,r24,SPR_UPR_ICP
|
l.ori r10,r10,SPR_SR_ICE
|
l.sfeq r26,r0
|
.endif
|
l.bf .L8
|
.if DC_ENABLE
|
l.nop
|
l.ori r10,r10,SPR_SR_DCE
|
|
.endif
|
/* Disable IC */
|
l.mtspr r0,r10,SPR_SR
|
l.mfspr r6,r0,SPR_SR
|
l.nop /* Flush the pipeline. */
|
l.addi r5,r0,-1
|
|
l.xori r5,r5,SPR_SR_ICE
|
|
l.and r5,r6,r5
|
|
l.mtspr r0,r5,SPR_SR
|
|
|
|
/* Establish cache block size
|
|
If BS=0, 16;
|
|
If BS=1, 32;
|
|
r14 contain block size
|
|
*/
|
|
l.mfspr r24,r0,SPR_ICCFGR
|
|
l.andi r26,r24,SPR_ICCFGR_CBS
|
|
l.srli r28,r26,7
|
|
l.ori r30,r0,16
|
|
l.sll r14,r30,r28
|
|
|
|
/* Establish number of cache sets
|
|
r16 contains number of cache sets
|
|
r28 contains log(# of cache sets)
|
|
*/
|
|
l.andi r26,r24,SPR_ICCFGR_NCS
|
|
l.srli r28,r26,3
|
|
l.ori r30,r0,1
|
|
l.sll r16,r30,r28
|
|
|
|
/* Invalidate IC */
|
|
l.addi r6,r0,0
|
|
l.sll r5,r14,r28
|
|
|
|
.L7:
|
|
l.mtspr r0,r6,SPR_ICBIR
|
|
l.sfne r6,r5
|
|
l.bf .L7
|
|
l.add r6,r6,r14
|
|
|
|
/* Enable IC */
|
|
l.mfspr r6,r0,SPR_SR
|
|
l.ori r6,r6,SPR_SR_ICE
|
|
l.mtspr r0,r6,SPR_SR
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
l.nop
|
.endif
|
l.nop
|
|
l.nop
|
|
l.nop
|
|
l.nop
|
|
|
|
.L8:
|
|
/* Data cache enable */
|
|
/* Check if DC present and skip enabling otherwise */
|
|
l.mfspr r24,r0,SPR_UPR
|
|
l.andi r26,r24,SPR_UPR_DCP
|
|
l.sfeq r26,r0
|
|
l.bf .L10
|
|
l.nop
|
|
/* Disable DC */
|
|
l.mfspr r6,r0,SPR_SR
|
|
l.addi r5,r0,-1
|
|
l.xori r5,r5,SPR_SR_DCE
|
|
l.and r5,r6,r5
|
|
l.mtspr r0,r5,SPR_SR
|
|
/* Establish cache block size
|
|
If BS=0, 16;
|
|
If BS=1, 32;
|
|
r14 contain block size
|
|
*/
|
|
l.mfspr r24,r0,SPR_DCCFGR
|
|
l.andi r26,r24,SPR_DCCFGR_CBS
|
|
l.srli r28,r26,7
|
|
l.ori r30,r0,16
|
|
l.sll r14,r30,r28
|
|
/* Establish number of cache sets
|
|
r16 contains number of cache sets
|
|
r28 contains log(# of cache sets)
|
|
*/
|
|
l.andi r26,r24,SPR_DCCFGR_NCS
|
|
l.srli r28,r26,3
|
|
l.ori r30,r0,1
|
|
l.sll r16,r30,r28
|
|
/* Invalidate DC */
|
|
l.addi r6,r0,0
|
|
l.sll r5,r14,r28
|
|
.L9:
|
|
l.mtspr r0,r6,SPR_DCBIR
|
|
l.sfne r6,r5
|
|
l.bf .L9
|
|
l.add r6,r6,r14
|
|
/* Enable DC */
|
|
l.mfspr r6,r0,SPR_SR
|
|
l.ori r6,r6,SPR_SR_DCE
|
|
l.mtspr r0,r6,SPR_SR
|
|
|
|
.L10:
|
/* Clear BSS */
|
/* Clear BSS */
|
l.movhi r28,hi(__bss_start)
|
l.movhi r28,hi(__bss_start)
|
l.ori r28,r28,lo(__bss_start)
|
l.ori r28,r28,lo(__bss_start)
|
l.movhi r30,hi(end)
|
l.movhi r30,hi(end)
|
l.ori r30,r30,lo(end)
|
l.ori r30,r30,lo(end)
|
|
|
.L1:
|
.L1:
|
l.sw (0)(r28),r0
|
l.sw (0)(r28),r0
|
l.sfltu r28,r30
|
l.sfltu r28,r30
|
l.bf .L1
|
l.bf .L1
|
l.addi r28,r28,4 /* Delay slot */
|
l.addi r28,r28,4 /* Delay slot */
|
|
|
/* Call global and static constructors */
|
/* Call global and static constructors */
|
l.jal init
|
l.jal init
|
l.nop
|
l.nop
|
|
|
/* Set up destructors to be called from exit if main never returns */
|
/* Set up destructors to be called from exit if main never returns */
|
l.movhi r3,hi(fini)
|
l.movhi r3,hi(fini)
|
l.jal _atexit
|
l.jal _atexit
|
l.ori r3,r3,lo(fini) /* Delay slot */
|
l.ori r3,r3,lo(fini) /* Delay slot */
|
|
|
/* Initialise UART in a C function. If the UART isn't present, we'll */
|
/* Initialise UART in a C function. If the UART isn't present, we'll */
|
/* link against a dummy function. */
|
/* link against a dummy function. */
|
l.jal __uart_init
|
l.jal __uart_init
|
l.nop
|
l.nop
|
|
|
/* Jump to main program entry point (argc = argv = envp = 0) */
|
/* Jump to main program entry point (argc = argv = envp = 0) */
|
l.or r3,r0,r0
|
l.or r3,r0,r0
|
l.or r4,r0,r0
|
l.or r4,r0,r0
|
l.jal _main
|
l.jal _main
|
l.or r5,r0,r0 /* Delay slot */
|
l.or r5,r0,r0 /* Delay slot */
|
|
|
/* If program exits, call exit routine */
|
/* If program exits, call exit routine */
|
l.jal _exit
|
l.jal _exit
|
l.addi r3,r11,0 /* Delay slot */
|
l.addi r3,r11,0 /* Delay slot */
|
|
|
/* Loop forever */
|
/* Loop forever */
|
.L2:
|
.L2:
|
l.j .L2
|
l.j .L2
|
l.nop
|
l.nop
|
|
|
.size _start, .-_start
|
.size _start, .-_start
|
|
|
