URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [binutils-2.20.1/] [gas/] [testsuite/] [gas/] [arm/] [arch5tej.d] - Diff between revs 816 and 818

Rev 816	Rev 818
`#objdump: -dr --prefix-addresses --show-raw-insn`	`#objdump: -dr --prefix-addresses --show-raw-insn`
`#name: ARM Architecture v5TEJ instructions`	`#name: ARM Architecture v5TEJ instructions`
`#as: -march=armv5tej`	`#as: -march=armv5tej`

`# Test the ARM Architecture v5TEJ instructions`	`# Test the ARM Architecture v5TEJ instructions`

`.: +file format .arm.*`	`.: +file format .arm.*`

`Disassembly of section .text:`	`Disassembly of section .text:`
`0+00 <[^>]*> e12fff20 ? bxj r0`	`0+00 <[^>]*> e12fff20 ? bxj r0`
`0+04 <[^>]*> e12fff21 ? bxj r1`	`0+04 <[^>]*> e12fff21 ? bxj r1`
`0+08 <[^>]*> e12fff2e ? bxj lr`	`0+08 <[^>]*> e12fff2e ? bxj lr`
`0+0c <[^>]*> 012fff20 ? bxjeq r0`	`0+0c <[^>]*> 012fff20 ? bxjeq r0`
`0+10 <[^>]*> 412fff20 ? bxjmi r0`	`0+10 <[^>]*> 412fff20 ? bxjmi r0`
`0+14 <[^>]*> 512fff27 ? bxjpl r7`	`0+14 <[^>]*> 512fff27 ? bxjpl r7`
`0+18 <[^>]*> e1200070 ? bkpt 0x0000`	`0+18 <[^>]*> e1200070 ? bkpt 0x0000`
`0+1c <[^>]*> e120007a ? bkpt 0x000a`	`0+1c <[^>]*> e120007a ? bkpt 0x000a`