#name: ARM V6 instructions
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#name: ARM V6 instructions
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#as: -march=armv6zk
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#as: -march=armv6zk
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#objdump: -dr --prefix-addresses --show-raw-insn
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#objdump: -dr --prefix-addresses --show-raw-insn
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.*: +file format .*arm.*
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.*: +file format .*arm.*
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Disassembly of section .text:
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Disassembly of section .text:
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0+000 <[^>]*> f57ff01f ? clrex
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0+000 <[^>]*> f57ff01f ? clrex
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0+004 <[^>]*> e1dc4f9f ? ldrexb r4, \[ip\]
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0+004 <[^>]*> e1dc4f9f ? ldrexb r4, \[ip\]
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0+008 <[^>]*> 11d4cf9f ? ldrexbne ip, \[r4\]
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0+008 <[^>]*> 11d4cf9f ? ldrexbne ip, \[r4\]
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0+00c <[^>]*> e1bc4f9f ? ldrexd r4, \[ip\]
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0+00c <[^>]*> e1bc4f9f ? ldrexd r4, \[ip\]
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0+010 <[^>]*> 11b4cf9f ? ldrexdne ip, \[r4\]
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0+010 <[^>]*> 11b4cf9f ? ldrexdne ip, \[r4\]
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0+014 <[^>]*> e1fc4f9f ? ldrexh r4, \[ip\]
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0+014 <[^>]*> e1fc4f9f ? ldrexh r4, \[ip\]
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0+018 <[^>]*> 11f4cf9f ? ldrexhne ip, \[r4\]
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0+018 <[^>]*> 11f4cf9f ? ldrexhne ip, \[r4\]
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0+01c <[^>]*> e320f080 ? nop \{128\}.*
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0+01c <[^>]*> e320f080 ? nop \{128\}.*
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0+020 <[^>]*> 1320f07f ? nopne \{127\}.*
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0+020 <[^>]*> 1320f07f ? nopne \{127\}.*
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0+024 <[^>]*> e320f004 ? sev
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0+024 <[^>]*> e320f004 ? sev
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0+028 <[^>]*> e1c74f9c ? strexb r4, ip, \[r7\]
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0+028 <[^>]*> e1c74f9c ? strexb r4, ip, \[r7\]
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0+02c <[^>]*> 11c8cf94 ? strexbne ip, r4, \[r8\]
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0+02c <[^>]*> 11c8cf94 ? strexbne ip, r4, \[r8\]
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0+030 <[^>]*> e1a74f9c ? strexd r4, ip, \[r7\]
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0+030 <[^>]*> e1a74f9c ? strexd r4, ip, \[r7\]
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0+034 <[^>]*> 11a8cf94 ? strexdne ip, r4, \[r8\]
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0+034 <[^>]*> 11a8cf94 ? strexdne ip, r4, \[r8\]
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0+038 <[^>]*> e1e74f9c ? strexh r4, ip, \[r7\]
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0+038 <[^>]*> e1e74f9c ? strexh r4, ip, \[r7\]
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0+03c <[^>]*> 11e8cf94 ? strexhne ip, r4, \[r8\]
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0+03c <[^>]*> 11e8cf94 ? strexhne ip, r4, \[r8\]
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0+040 <[^>]*> e320f002 ? wfe
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0+040 <[^>]*> e320f002 ? wfe
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0+044 <[^>]*> e320f003 ? wfi
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0+044 <[^>]*> e320f003 ? wfi
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0+048 <[^>]*> e320f001 ? yield
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0+048 <[^>]*> e320f001 ? yield
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0+04c <[^>]*> e16ec371 ? smc 60465.*
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0+04c <[^>]*> e16ec371 ? smc 60465.*
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0+050 <[^>]*> 11613c7e ? smcne 5070.*
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0+050 <[^>]*> 11613c7e ? smcne 5070.*
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#...
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#...
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