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Rev 818 |
.arch armv7-r
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.arch armv7-r
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.syntax unified
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.syntax unified
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.text
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.text
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.thumb
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.thumb
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.global foo
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.global foo
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foo:
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foo:
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@ Section A6.1.3 "Use of 0b1101 as a register specifier".
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@ Section A6.1.3 "Use of 0b1101 as a register specifier".
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@ R13 as the source or destination register of a mov instruction.
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@ R13 as the source or destination register of a mov instruction.
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@ only register to register transfers without shifts are supported,
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@ only register to register transfers without shifts are supported,
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@ with no flag setting
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@ with no flag setting
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mov sp,r0
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mov sp,r0
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mov r0,sp
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mov r0,sp
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@ Using the following instructions to adjust r13 up or down by a
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@ Using the following instructions to adjust r13 up or down by a
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@ multiple of 4:
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@ multiple of 4:
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add sp,sp,#0
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add sp,sp,#0
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addw sp,sp,#0
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addw sp,sp,#0
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sub sp,sp,#0
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sub sp,sp,#0
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subw sp,sp,#0
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subw sp,sp,#0
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add sp,sp,r0
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add sp,sp,r0
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add sp,sp,r0,lsl #1
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add sp,sp,r0,lsl #1
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sub sp,sp,r0
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sub sp,sp,r0
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sub sp,sp,r0,lsl #1
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sub sp,sp,r0,lsl #1
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@ R13 as a base register <Rn> of any load/store instruction.
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@ R13 as a base register <Rn> of any load/store instruction.
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ldr r0, [sp]
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ldr r0, [sp]
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ldr r0, [pc]
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ldr r0, [pc]
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ldr pc, [r0]
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ldr pc, [r0]
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ldr sp, [r0]
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ldr sp, [r0]
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ldr pc, [pc]
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ldr pc, [pc]
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ldr sp, [sp]
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ldr sp, [sp]
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ldr pc, [sp]
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ldr pc, [sp]
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ldr sp, [pc]
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ldr sp, [pc]
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ldr sp, [r0, +pc]
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ldr sp, [r0, +pc]
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str r0, [sp]
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str r0, [sp]
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str r0, [pc]
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str r0, [pc]
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str pc, [r0]
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str pc, [r0]
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str sp, [r0]
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str sp, [r0]
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str pc, [pc]
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str pc, [pc]
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str sp, [sp]
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str sp, [sp]
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str pc, [sp]
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str pc, [sp]
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str sp, [pc]
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str sp, [pc]
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str sp, [r0, +pc]
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str sp, [r0, +pc]
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@ R13 as the first operand <Rn> in any add{s}, cmn, cmp, or sub{s} instruction.
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@ R13 as the first operand <Rn> in any add{s}, cmn, cmp, or sub{s} instruction.
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add r0, sp, r0
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add r0, sp, r0
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adds r0, sp, r0
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adds r0, sp, r0
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add r0, sp, r0, lsl #1
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add r0, sp, r0, lsl #1
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adds r0, sp, r0, lsl #1
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adds r0, sp, r0, lsl #1
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cmn sp, #0
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cmn sp, #0
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cmn sp, r0
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cmn sp, r0
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cmn sp, r0, lsl #1
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cmn sp, r0, lsl #1
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cmp sp, #0
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cmp sp, #0
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cmp sp, r0
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cmp sp, r0
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cmp sp, r0, lsl #1
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cmp sp, r0, lsl #1
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sub sp, #0
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sub sp, #0
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subs sp, #0
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subs sp, #0
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sub r0, sp, #0
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sub r0, sp, #0
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subs r0, sp, #0
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subs r0, sp, #0
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@ ADD (sp plus immediate).
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@ ADD (sp plus immediate).
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add sp, #4
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add sp, #4
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add r0, sp, #4
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add r0, sp, #4
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adds sp, #4
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adds sp, #4
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adds r0, sp, #4
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adds r0, sp, #4
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addw r0, sp, #4
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addw r0, sp, #4
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add sp, sp, #4
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add sp, sp, #4
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adds sp, sp, #4
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adds sp, sp, #4
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addw sp, sp, #4
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addw sp, sp, #4
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@ ADD (sp plus register).
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@ ADD (sp plus register).
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add sp, r0
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add sp, r0
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add r0, sp, r0
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add r0, sp, r0
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add r0, sp, r0, lsl #1
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add r0, sp, r0, lsl #1
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adds sp, r0
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adds sp, r0
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adds r0, sp, r0
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adds r0, sp, r0
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adds r0, sp, r0, lsl #1
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adds r0, sp, r0, lsl #1
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add sp, sp, r0
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add sp, sp, r0
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add sp, sp, r0, lsl #1
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add sp, sp, r0, lsl #1
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adds sp, sp, r0
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adds sp, sp, r0
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adds sp, sp, r0, lsl #1
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adds sp, sp, r0, lsl #1
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add sp, sp, sp
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add sp, sp, sp
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@ SUB (sp minus immediate).
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@ SUB (sp minus immediate).
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sub r0, sp , #0
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sub r0, sp , #0
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subs r0, sp , #0
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subs r0, sp , #0
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subw r0, sp , #0
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subw r0, sp , #0
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sub sp, sp , #0
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sub sp, sp , #0
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subs sp, sp , #0
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subs sp, sp , #0
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subw sp, sp , #0
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subw sp, sp , #0
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@ SUB (sp minus register).
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@ SUB (sp minus register).
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sub sp, #0
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sub sp, #0
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subs sp, #0
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subs sp, #0
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sub r0, sp, r0, lsl #1
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sub r0, sp, r0, lsl #1
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subs r0, sp, r0, lsl #1
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subs r0, sp, r0, lsl #1
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sub sp, sp, r0, lsl #1
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sub sp, sp, r0, lsl #1
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subs sp, sp, r0, lsl #1
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subs sp, sp, r0, lsl #1
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@ PC-related insns (equivalent to adr).
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@ PC-related insns (equivalent to adr).
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add r0, pc, #4
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add r0, pc, #4
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sub r0, pc, #4
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sub r0, pc, #4
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adds r0, pc, #4
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adds r0, pc, #4
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subs r0, pc, #4
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subs r0, pc, #4
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addw r0, pc, #4
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addw r0, pc, #4
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subw r0, pc, #4
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subw r0, pc, #4
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@ nops to pad the section out to an alignment boundary.
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@ nops to pad the section out to an alignment boundary.
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nop
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nop
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nop
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nop
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nop
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nop
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