@ VFP with Neon-style syntax
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@ VFP with Neon-style syntax
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.syntax unified
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.syntax unified
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.include "itblock.s"
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.include "itblock.s"
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func:
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func:
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.macro testvmov cond="" f32=".f32" f64=".f64"
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.macro testvmov cond="" f32=".f32" f64=".f64"
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itblock 4 \cond
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itblock 4 \cond
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vmov\cond\f32 s0,s1
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vmov\cond\f32 s0,s1
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vmov\cond\f64 d0,d1
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vmov\cond\f64 d0,d1
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vmov\cond\f32 s0,#0.25
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vmov\cond\f32 s0,#0.25
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vmov\cond\f64 d0,#1.0
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vmov\cond\f64 d0,#1.0
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itblock 4 \cond
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itblock 4 \cond
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vmov\cond r0,s1
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vmov\cond r0,s1
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vmov\cond s0,r1
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vmov\cond s0,r1
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vmov\cond r0,r1,s2,s3
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vmov\cond r0,r1,s2,s3
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vmov\cond s0,s1,r2,r4
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vmov\cond s0,s1,r2,r4
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.endm
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.endm
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@ Test VFP vmov variants. These can all be conditional.
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@ Test VFP vmov variants. These can all be conditional.
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testvmov
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testvmov
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testvmov eq
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testvmov eq
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.macro monadic op cond="" f32=".f32" f64=".f64"
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.macro monadic op cond="" f32=".f32" f64=".f64"
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itblock 2 \cond
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itblock 2 \cond
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\op\cond\f32 s0,s1
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\op\cond\f32 s0,s1
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\op\cond\f64 d0,d1
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\op\cond\f64 d0,d1
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.endm
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.endm
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.macro monadic_c op
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.macro monadic_c op
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monadic \op
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monadic \op
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monadic \op eq
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monadic \op eq
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.endm
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.endm
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.macro dyadic op cond="" f32=".f32" f64=".f64"
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.macro dyadic op cond="" f32=".f32" f64=".f64"
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itblock 2 \cond
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itblock 2 \cond
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\op\cond\f32 s0,s1,s2
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\op\cond\f32 s0,s1,s2
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\op\cond\f64 d0,d1,d2
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\op\cond\f64 d0,d1,d2
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.endm
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.endm
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.macro dyadic_c op
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.macro dyadic_c op
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dyadic \op
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dyadic \op
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dyadic \op eq
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dyadic \op eq
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.endm
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.endm
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.macro dyadicz op cond="" f32=".f32" f64=".f64"
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.macro dyadicz op cond="" f32=".f32" f64=".f64"
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itblock 2 \cond
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itblock 2 \cond
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\op\cond\f32 s0,#0
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\op\cond\f32 s0,#0
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\op\cond\f64 d0,#0
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\op\cond\f64 d0,#0
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.endm
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.endm
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.macro dyadicz_c op
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.macro dyadicz_c op
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dyadicz \op
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dyadicz \op
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dyadicz \op eq
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dyadicz \op eq
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.endm
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.endm
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monadic_c vsqrt
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monadic_c vsqrt
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monadic_c vabs
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monadic_c vabs
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monadic_c vneg
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monadic_c vneg
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monadic_c vcmp
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monadic_c vcmp
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monadic_c vcmpe
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monadic_c vcmpe
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dyadic_c vnmul
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dyadic_c vnmul
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dyadic_c vnmla
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dyadic_c vnmla
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dyadic_c vnmls
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dyadic_c vnmls
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dyadic_c vmul
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dyadic_c vmul
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dyadic_c vmla
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dyadic_c vmla
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dyadic_c vmls
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dyadic_c vmls
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dyadic_c vadd
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dyadic_c vadd
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dyadic_c vsub
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dyadic_c vsub
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dyadic_c vdiv
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dyadic_c vdiv
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dyadicz_c vcmp
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dyadicz_c vcmp
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dyadicz_c vcmpe
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dyadicz_c vcmpe
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.macro cvtz cond="" s32=".s32" u32=".u32" f32=".f32" f64=".f64"
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.macro cvtz cond="" s32=".s32" u32=".u32" f32=".f32" f64=".f64"
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itblock 4 \cond
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itblock 4 \cond
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vcvtz\cond\s32\f32 s0,s1
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vcvtz\cond\s32\f32 s0,s1
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vcvtz\cond\u32\f32 s0,s1
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vcvtz\cond\u32\f32 s0,s1
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vcvtz\cond\s32\f64 s0,d1
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vcvtz\cond\s32\f64 s0,d1
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vcvtz\cond\u32\f64 s0,d1
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vcvtz\cond\u32\f64 s0,d1
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.endm
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.endm
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cvtz
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cvtz
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cvtz eq
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cvtz eq
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.macro cvt cond="" s32=".s32" u32=".u32" f32=".f32" f64=".f64"
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.macro cvt cond="" s32=".s32" u32=".u32" f32=".f32" f64=".f64"
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itblock 4 \cond
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itblock 4 \cond
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vcvt\cond\s32\f32 s0,s1
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vcvt\cond\s32\f32 s0,s1
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vcvt\cond\u32\f32 s0,s1
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vcvt\cond\u32\f32 s0,s1
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vcvt\cond\f32\s32 s0,s1
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vcvt\cond\f32\s32 s0,s1
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vcvt\cond\f32\u32 s0,s1
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vcvt\cond\f32\u32 s0,s1
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itblock 4 \cond
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itblock 4 \cond
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vcvt\cond\f32\f64 s0,d1
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vcvt\cond\f32\f64 s0,d1
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vcvt\cond\f64\f32 d0,s1
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vcvt\cond\f64\f32 d0,s1
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vcvt\cond\s32\f64 s0,d1
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vcvt\cond\s32\f64 s0,d1
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vcvt\cond\u32\f64 s0,d1
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vcvt\cond\u32\f64 s0,d1
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itblock 2 \cond
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itblock 2 \cond
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vcvt\cond\f64\s32 d0,s1
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vcvt\cond\f64\s32 d0,s1
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vcvt\cond\f64\u32 d0,s1
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vcvt\cond\f64\u32 d0,s1
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.endm
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.endm
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cvt
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cvt
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cvt eq
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cvt eq
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.macro cvti cond="" s32=".s32" u32=".u32" f32=".f32" f64=".f64" s16=".s16" u16=".u16"
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.macro cvti cond="" s32=".s32" u32=".u32" f32=".f32" f64=".f64" s16=".s16" u16=".u16"
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itblock 4 \cond
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itblock 4 \cond
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vcvt\cond\s32\f32 s0,s0,#1
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vcvt\cond\s32\f32 s0,s0,#1
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vcvt\cond\u32\f32 s0,s0,#1
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vcvt\cond\u32\f32 s0,s0,#1
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vcvt\cond\f32\s32 s0,s0,#1
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vcvt\cond\f32\s32 s0,s0,#1
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vcvt\cond\f32\u32 s0,s0,#1
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vcvt\cond\f32\u32 s0,s0,#1
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itblock 4 \cond
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itblock 4 \cond
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vcvt\cond\s32\f64 d0,d0,#1
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vcvt\cond\s32\f64 d0,d0,#1
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vcvt\cond\u32\f64 d0,d0,#1
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vcvt\cond\u32\f64 d0,d0,#1
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vcvt\cond\f64\s32 d0,d0,#1
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vcvt\cond\f64\s32 d0,d0,#1
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vcvt\cond\f64\u32 d0,d0,#1
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vcvt\cond\f64\u32 d0,d0,#1
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itblock 4 \cond
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itblock 4 \cond
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vcvt\cond\f32\s16 s0,s0,#1
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vcvt\cond\f32\s16 s0,s0,#1
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vcvt\cond\f32\u16 s0,s0,#1
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vcvt\cond\f32\u16 s0,s0,#1
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vcvt\cond\f64\s16 d0,d0,#1
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vcvt\cond\f64\s16 d0,d0,#1
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vcvt\cond\f64\u16 d0,d0,#1
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vcvt\cond\f64\u16 d0,d0,#1
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itblock 4 \cond
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itblock 4 \cond
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vcvt\cond\s16\f32 s0,s0,#1
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vcvt\cond\s16\f32 s0,s0,#1
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vcvt\cond\u16\f32 s0,s0,#1
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vcvt\cond\u16\f32 s0,s0,#1
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vcvt\cond\s16\f64 d0,d0,#1
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vcvt\cond\s16\f64 d0,d0,#1
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vcvt\cond\u16\f64 d0,d0,#1
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vcvt\cond\u16\f64 d0,d0,#1
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.endm
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.endm
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cvti
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cvti
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cvti eq
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cvti eq
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.macro multi op cond="" n="" ia="ia" db="db"
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.macro multi op cond="" n="" ia="ia" db="db"
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itblock 4 \cond
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itblock 4 \cond
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\op\n\cond r0,{s3-s6}
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\op\n\cond r0,{s3-s6}
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\op\ia\cond r0,{s3-s6}
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\op\ia\cond r0,{s3-s6}
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\op\ia\cond r0!,{s3-s6}
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\op\ia\cond r0!,{s3-s6}
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\op\db\cond r0!,{s3-s6}
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\op\db\cond r0!,{s3-s6}
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itblock 4 \cond
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itblock 4 \cond
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\op\n\cond r0,{d3-d6}
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\op\n\cond r0,{d3-d6}
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\op\ia\cond r0,{d3-d6}
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\op\ia\cond r0,{d3-d6}
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\op\ia\cond r0!,{d3-d6}
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\op\ia\cond r0!,{d3-d6}
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\op\db\cond r0!,{d3-d6}
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\op\db\cond r0!,{d3-d6}
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.endm
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.endm
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multi vldm
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multi vldm
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multi vldm eq
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multi vldm eq
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multi vstm
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multi vstm
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multi vstm eq
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multi vstm eq
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.macro single op cond=""
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.macro single op cond=""
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itblock 2 \cond
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itblock 2 \cond
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\op\cond s0,[r0,#4]
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\op\cond s0,[r0,#4]
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\op\cond d0,[r0,#4]
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\op\cond d0,[r0,#4]
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.endm
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.endm
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single vldr
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single vldr
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single vldr eq
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single vldr eq
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single vstr
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single vstr
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single vstr eq
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single vstr eq
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