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Rev 816 |
Rev 818 |
#as:
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#as:
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#objdump: -dr
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#objdump: -dr
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#name: tbit_test
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#name: tbit_test
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.*: +file format .*
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.*: +file format .*
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Disassembly of section .text:
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Disassembly of section .text:
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00000000 :
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00000000 :
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0: 00 06 tbit \$0x0:s,r0
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0: 00 06 tbit \$0x0:s,r0
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2: 11 06 tbit \$0x1:s,r1
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2: 11 06 tbit \$0x1:s,r1
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4: 22 06 tbit \$0x2:s,r2
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4: 22 06 tbit \$0x2:s,r2
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6: 33 06 tbit \$0x3:s,r3
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6: 33 06 tbit \$0x3:s,r3
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8: 44 06 tbit \$0x4:s,r4
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8: 44 06 tbit \$0x4:s,r4
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a: 55 06 tbit \$0x5:s,r5
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a: 55 06 tbit \$0x5:s,r5
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c: 66 06 tbit \$0x6:s,r6
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c: 66 06 tbit \$0x6:s,r6
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e: 77 06 tbit \$0x7:s,r7
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e: 77 06 tbit \$0x7:s,r7
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10: 88 06 tbit \$0x8:s,r8
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10: 88 06 tbit \$0x8:s,r8
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12: 99 06 tbit \$0x9:s,r9
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12: 99 06 tbit \$0x9:s,r9
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14: aa 06 tbit \$0xa:s,r10
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14: aa 06 tbit \$0xa:s,r10
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16: bb 06 tbit \$0xb:s,r11
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16: bb 06 tbit \$0xb:s,r11
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18: cc 06 tbit \$0xc:s,r12
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18: cc 06 tbit \$0xc:s,r12
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1a: dd 06 tbit \$0xd:s,r13
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1a: dd 06 tbit \$0xd:s,r13
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1c: 00 07 tbit r0,r0
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1c: 00 07 tbit r0,r0
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1e: 11 07 tbit r1,r1
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1e: 11 07 tbit r1,r1
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20: 22 07 tbit r2,r2
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20: 22 07 tbit r2,r2
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22: 33 07 tbit r3,r3
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22: 33 07 tbit r3,r3
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24: 44 07 tbit r4,r4
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24: 44 07 tbit r4,r4
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26: 55 07 tbit r5,r5
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26: 55 07 tbit r5,r5
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28: 66 07 tbit r6,r6
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28: 66 07 tbit r6,r6
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2a: 77 07 tbit r7,r7
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2a: 77 07 tbit r7,r7
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2c: 88 07 tbit r8,r8
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2c: 88 07 tbit r8,r8
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2e: 99 07 tbit r9,r9
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2e: 99 07 tbit r9,r9
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30: aa 07 tbit r10,r10
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30: aa 07 tbit r10,r10
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32: bb 07 tbit r11,r11
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32: bb 07 tbit r11,r11
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34: cc 07 tbit r12,r12
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34: cc 07 tbit r12,r12
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36: dd 07 tbit r13,r13
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36: dd 07 tbit r13,r13
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