URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [gnu-stable/] [binutils-2.20.1/] [ld/] [testsuite/] [ld-arm/] [arm-static-app.d] - Diff between revs 816 and 818

Rev 816	Rev 818

`tmpdir/arm-static-app: file format elf32-(little\|big)arm`	`tmpdir/arm-static-app: file format elf32-(little\|big)arm`
`architecture: arm, flags 0x00000112:`	`architecture: arm, flags 0x00000112:`
`EXEC_P, HAS_SYMS, D_PAGED`	`EXEC_P, HAS_SYMS, D_PAGED`
`start address 0x.*`	`start address 0x.*`

`Disassembly of section .text:`	`Disassembly of section .text:`

`.* <_start>:`	`.* <_start>:`
`.*: e1a0c00d mov ip, sp`	`.*: e1a0c00d mov ip, sp`
`.*: e92dd800 push {fp, ip, lr, pc}`	`.*: e92dd800 push {fp, ip, lr, pc}`
`.: eb000001 bl .`	`.: eb000001 bl .`
`.*: e89d6800 ldm sp, {fp, sp, lr}`	`.*: e89d6800 ldm sp, {fp, sp, lr}`
`.*: e12fff1e bx lr`	`.*: e12fff1e bx lr`

`.* :`	`.* :`
`.*: e1a0c00d mov ip, sp`	`.*: e1a0c00d mov ip, sp`
`.*: e92dd800 push {fp, ip, lr, pc}`	`.*: e92dd800 push {fp, ip, lr, pc}`
`.: eb000001 bl .`	`.: eb000001 bl .`
`.*: e89d6800 ldm sp, {fp, sp, lr}`	`.*: e89d6800 ldm sp, {fp, sp, lr}`
`.*: e12fff1e bx lr`	`.*: e12fff1e bx lr`

`.* :`	`.* :`
`.*: e12fff1e bx lr`	`.*: e12fff1e bx lr`