/* Instruction building/extraction support for m32r. -*- C -*-
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/* Instruction building/extraction support for m32r. -*- C -*-
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THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
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THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
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- the resultant file is machine generated, cgen-ibld.in isn't
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- the resultant file is machine generated, cgen-ibld.in isn't
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Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2006, 2007,
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Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2006, 2007,
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2008 Free Software Foundation, Inc.
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2008 Free Software Foundation, Inc.
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This file is part of libopcodes.
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This file is part of libopcodes.
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This library is free software; you can redistribute it and/or modify
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software Foundation, Inc.,
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along with this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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/* ??? Eventually more and more of this stuff can go to cpu-independent files.
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/* ??? Eventually more and more of this stuff can go to cpu-independent files.
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Keep that in mind. */
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Keep that in mind. */
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#include "sysdep.h"
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#include "sysdep.h"
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#include <stdio.h>
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#include <stdio.h>
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#include "ansidecl.h"
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#include "ansidecl.h"
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#include "dis-asm.h"
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#include "dis-asm.h"
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#include "bfd.h"
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#include "bfd.h"
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#include "symcat.h"
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#include "symcat.h"
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#include "m32r-desc.h"
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#include "m32r-desc.h"
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#include "m32r-opc.h"
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#include "m32r-opc.h"
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#include "opintl.h"
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#include "opintl.h"
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#include "safe-ctype.h"
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#include "safe-ctype.h"
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#undef min
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#undef min
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#define min(a,b) ((a) < (b) ? (a) : (b))
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#define min(a,b) ((a) < (b) ? (a) : (b))
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#undef max
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#undef max
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#define max(a,b) ((a) > (b) ? (a) : (b))
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#define max(a,b) ((a) > (b) ? (a) : (b))
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|
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/* Used by the ifield rtx function. */
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/* Used by the ifield rtx function. */
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#define FLD(f) (fields->f)
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#define FLD(f) (fields->f)
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static const char * insert_normal
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static const char * insert_normal
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(CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
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(CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
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unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR);
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unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR);
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static const char * insert_insn_normal
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static const char * insert_insn_normal
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(CGEN_CPU_DESC, const CGEN_INSN *,
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(CGEN_CPU_DESC, const CGEN_INSN *,
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CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
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CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
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static int extract_normal
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static int extract_normal
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(CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
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(CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
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unsigned int, unsigned int, unsigned int, unsigned int,
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unsigned int, unsigned int, unsigned int, unsigned int,
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unsigned int, unsigned int, bfd_vma, long *);
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unsigned int, unsigned int, bfd_vma, long *);
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static int extract_insn_normal
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static int extract_insn_normal
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(CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
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(CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
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CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
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CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
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#if CGEN_INT_INSN_P
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#if CGEN_INT_INSN_P
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static void put_insn_int_value
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static void put_insn_int_value
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(CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT);
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(CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT);
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#endif
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#endif
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#if ! CGEN_INT_INSN_P
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#if ! CGEN_INT_INSN_P
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static CGEN_INLINE void insert_1
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static CGEN_INLINE void insert_1
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(CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *);
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(CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *);
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static CGEN_INLINE int fill_cache
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static CGEN_INLINE int fill_cache
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(CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma);
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(CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma);
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static CGEN_INLINE long extract_1
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static CGEN_INLINE long extract_1
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(CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma);
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(CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma);
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#endif
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#endif
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/* Operand insertion. */
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/* Operand insertion. */
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#if ! CGEN_INT_INSN_P
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#if ! CGEN_INT_INSN_P
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/* Subroutine of insert_normal. */
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/* Subroutine of insert_normal. */
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static CGEN_INLINE void
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static CGEN_INLINE void
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insert_1 (CGEN_CPU_DESC cd,
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insert_1 (CGEN_CPU_DESC cd,
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unsigned long value,
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unsigned long value,
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int start,
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int start,
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int length,
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int length,
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int word_length,
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int word_length,
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unsigned char *bufp)
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unsigned char *bufp)
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{
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{
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unsigned long x,mask;
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unsigned long x,mask;
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int shift;
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int shift;
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x = cgen_get_insn_value (cd, bufp, word_length);
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x = cgen_get_insn_value (cd, bufp, word_length);
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/* Written this way to avoid undefined behaviour. */
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/* Written this way to avoid undefined behaviour. */
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mask = (((1L << (length - 1)) - 1) << 1) | 1;
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mask = (((1L << (length - 1)) - 1) << 1) | 1;
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if (CGEN_INSN_LSB0_P)
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if (CGEN_INSN_LSB0_P)
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shift = (start + 1) - length;
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shift = (start + 1) - length;
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else
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else
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shift = (word_length - (start + length));
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shift = (word_length - (start + length));
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x = (x & ~(mask << shift)) | ((value & mask) << shift);
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x = (x & ~(mask << shift)) | ((value & mask) << shift);
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cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
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cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
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}
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}
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#endif /* ! CGEN_INT_INSN_P */
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#endif /* ! CGEN_INT_INSN_P */
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/* Default insertion routine.
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/* Default insertion routine.
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ATTRS is a mask of the boolean attributes.
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ATTRS is a mask of the boolean attributes.
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WORD_OFFSET is the offset in bits from the start of the insn of the value.
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WORD_OFFSET is the offset in bits from the start of the insn of the value.
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WORD_LENGTH is the length of the word in bits in which the value resides.
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WORD_LENGTH is the length of the word in bits in which the value resides.
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START is the starting bit number in the word, architecture origin.
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START is the starting bit number in the word, architecture origin.
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LENGTH is the length of VALUE in bits.
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LENGTH is the length of VALUE in bits.
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TOTAL_LENGTH is the total length of the insn in bits.
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TOTAL_LENGTH is the total length of the insn in bits.
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The result is an error message or NULL if success. */
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The result is an error message or NULL if success. */
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/* ??? This duplicates functionality with bfd's howto table and
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/* ??? This duplicates functionality with bfd's howto table and
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bfd_install_relocation. */
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bfd_install_relocation. */
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/* ??? This doesn't handle bfd_vma's. Create another function when
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/* ??? This doesn't handle bfd_vma's. Create another function when
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necessary. */
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necessary. */
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static const char *
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static const char *
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insert_normal (CGEN_CPU_DESC cd,
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insert_normal (CGEN_CPU_DESC cd,
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long value,
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long value,
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unsigned int attrs,
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unsigned int attrs,
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unsigned int word_offset,
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unsigned int word_offset,
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unsigned int start,
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unsigned int start,
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unsigned int length,
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unsigned int length,
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unsigned int word_length,
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unsigned int word_length,
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unsigned int total_length,
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unsigned int total_length,
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CGEN_INSN_BYTES_PTR buffer)
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CGEN_INSN_BYTES_PTR buffer)
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{
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{
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static char errbuf[100];
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static char errbuf[100];
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/* Written this way to avoid undefined behaviour. */
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/* Written this way to avoid undefined behaviour. */
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unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1;
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unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1;
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|
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/* If LENGTH is zero, this operand doesn't contribute to the value. */
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/* If LENGTH is zero, this operand doesn't contribute to the value. */
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if (length == 0)
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if (length == 0)
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return NULL;
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return NULL;
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if (word_length > 32)
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if (word_length > 32)
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abort ();
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abort ();
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/* For architectures with insns smaller than the base-insn-bitsize,
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/* For architectures with insns smaller than the base-insn-bitsize,
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word_length may be too big. */
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word_length may be too big. */
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if (cd->min_insn_bitsize < cd->base_insn_bitsize)
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if (cd->min_insn_bitsize < cd->base_insn_bitsize)
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{
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{
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if (word_offset == 0
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if (word_offset == 0
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&& word_length > total_length)
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&& word_length > total_length)
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word_length = total_length;
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word_length = total_length;
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}
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}
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|
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/* Ensure VALUE will fit. */
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/* Ensure VALUE will fit. */
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if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT))
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if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT))
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{
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{
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long minval = - (1L << (length - 1));
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long minval = - (1L << (length - 1));
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unsigned long maxval = mask;
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unsigned long maxval = mask;
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|
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if ((value > 0 && (unsigned long) value > maxval)
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if ((value > 0 && (unsigned long) value > maxval)
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|| value < minval)
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|| value < minval)
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{
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{
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/* xgettext:c-format */
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/* xgettext:c-format */
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sprintf (errbuf,
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sprintf (errbuf,
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_("operand out of range (%ld not between %ld and %lu)"),
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_("operand out of range (%ld not between %ld and %lu)"),
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value, minval, maxval);
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value, minval, maxval);
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return errbuf;
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return errbuf;
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}
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}
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}
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}
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else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED))
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else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED))
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{
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{
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unsigned long maxval = mask;
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unsigned long maxval = mask;
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unsigned long val = (unsigned long) value;
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unsigned long val = (unsigned long) value;
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|
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/* For hosts with a word size > 32 check to see if value has been sign
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/* For hosts with a word size > 32 check to see if value has been sign
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extended beyond 32 bits. If so then ignore these higher sign bits
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extended beyond 32 bits. If so then ignore these higher sign bits
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as the user is attempting to store a 32-bit signed value into an
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as the user is attempting to store a 32-bit signed value into an
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unsigned 32-bit field which is allowed. */
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unsigned 32-bit field which is allowed. */
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if (sizeof (unsigned long) > 4 && ((value >> 32) == -1))
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if (sizeof (unsigned long) > 4 && ((value >> 32) == -1))
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val &= 0xFFFFFFFF;
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val &= 0xFFFFFFFF;
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|
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if (val > maxval)
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if (val > maxval)
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{
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{
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/* xgettext:c-format */
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/* xgettext:c-format */
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sprintf (errbuf,
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sprintf (errbuf,
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_("operand out of range (0x%lx not between 0 and 0x%lx)"),
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_("operand out of range (0x%lx not between 0 and 0x%lx)"),
|
val, maxval);
|
val, maxval);
|
return errbuf;
|
return errbuf;
|
}
|
}
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}
|
}
|
else
|
else
|
{
|
{
|
if (! cgen_signed_overflow_ok_p (cd))
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if (! cgen_signed_overflow_ok_p (cd))
|
{
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{
|
long minval = - (1L << (length - 1));
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long minval = - (1L << (length - 1));
|
long maxval = (1L << (length - 1)) - 1;
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long maxval = (1L << (length - 1)) - 1;
|
|
|
if (value < minval || value > maxval)
|
if (value < minval || value > maxval)
|
{
|
{
|
sprintf
|
sprintf
|
/* xgettext:c-format */
|
/* xgettext:c-format */
|
(errbuf, _("operand out of range (%ld not between %ld and %ld)"),
|
(errbuf, _("operand out of range (%ld not between %ld and %ld)"),
|
value, minval, maxval);
|
value, minval, maxval);
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return errbuf;
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return errbuf;
|
}
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}
|
}
|
}
|
}
|
}
|
|
|
#if CGEN_INT_INSN_P
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#if CGEN_INT_INSN_P
|
|
|
{
|
{
|
int shift;
|
int shift;
|
|
|
if (CGEN_INSN_LSB0_P)
|
if (CGEN_INSN_LSB0_P)
|
shift = (word_offset + start + 1) - length;
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shift = (word_offset + start + 1) - length;
|
else
|
else
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shift = total_length - (word_offset + start + length);
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shift = total_length - (word_offset + start + length);
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*buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
|
*buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
|
}
|
}
|
|
|
#else /* ! CGEN_INT_INSN_P */
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#else /* ! CGEN_INT_INSN_P */
|
|
|
{
|
{
|
unsigned char *bufp = (unsigned char *) buffer + word_offset / 8;
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unsigned char *bufp = (unsigned char *) buffer + word_offset / 8;
|
|
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insert_1 (cd, value, start, length, word_length, bufp);
|
insert_1 (cd, value, start, length, word_length, bufp);
|
}
|
}
|
|
|
#endif /* ! CGEN_INT_INSN_P */
|
#endif /* ! CGEN_INT_INSN_P */
|
|
|
return NULL;
|
return NULL;
|
}
|
}
|
|
|
/* Default insn builder (insert handler).
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/* Default insn builder (insert handler).
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The instruction is recorded in CGEN_INT_INSN_P byte order (meaning
|
The instruction is recorded in CGEN_INT_INSN_P byte order (meaning
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that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is
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that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is
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recorded in host byte order, otherwise BUFFER is an array of bytes
|
recorded in host byte order, otherwise BUFFER is an array of bytes
|
and the value is recorded in target byte order).
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and the value is recorded in target byte order).
|
The result is an error message or NULL if success. */
|
The result is an error message or NULL if success. */
|
|
|
static const char *
|
static const char *
|
insert_insn_normal (CGEN_CPU_DESC cd,
|
insert_insn_normal (CGEN_CPU_DESC cd,
|
const CGEN_INSN * insn,
|
const CGEN_INSN * insn,
|
CGEN_FIELDS * fields,
|
CGEN_FIELDS * fields,
|
CGEN_INSN_BYTES_PTR buffer,
|
CGEN_INSN_BYTES_PTR buffer,
|
bfd_vma pc)
|
bfd_vma pc)
|
{
|
{
|
const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
|
const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
|
unsigned long value;
|
unsigned long value;
|
const CGEN_SYNTAX_CHAR_TYPE * syn;
|
const CGEN_SYNTAX_CHAR_TYPE * syn;
|
|
|
CGEN_INIT_INSERT (cd);
|
CGEN_INIT_INSERT (cd);
|
value = CGEN_INSN_BASE_VALUE (insn);
|
value = CGEN_INSN_BASE_VALUE (insn);
|
|
|
/* If we're recording insns as numbers (rather than a string of bytes),
|
/* If we're recording insns as numbers (rather than a string of bytes),
|
target byte order handling is deferred until later. */
|
target byte order handling is deferred until later. */
|
|
|
#if CGEN_INT_INSN_P
|
#if CGEN_INT_INSN_P
|
|
|
put_insn_int_value (cd, buffer, cd->base_insn_bitsize,
|
put_insn_int_value (cd, buffer, cd->base_insn_bitsize,
|
CGEN_FIELDS_BITSIZE (fields), value);
|
CGEN_FIELDS_BITSIZE (fields), value);
|
|
|
#else
|
#else
|
|
|
cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
|
cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
|
(unsigned) CGEN_FIELDS_BITSIZE (fields)),
|
(unsigned) CGEN_FIELDS_BITSIZE (fields)),
|
value);
|
value);
|
|
|
#endif /* ! CGEN_INT_INSN_P */
|
#endif /* ! CGEN_INT_INSN_P */
|
|
|
/* ??? It would be better to scan the format's fields.
|
/* ??? It would be better to scan the format's fields.
|
Still need to be able to insert a value based on the operand though;
|
Still need to be able to insert a value based on the operand though;
|
e.g. storing a branch displacement that got resolved later.
|
e.g. storing a branch displacement that got resolved later.
|
Needs more thought first. */
|
Needs more thought first. */
|
|
|
for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn)
|
for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn)
|
{
|
{
|
const char *errmsg;
|
const char *errmsg;
|
|
|
if (CGEN_SYNTAX_CHAR_P (* syn))
|
if (CGEN_SYNTAX_CHAR_P (* syn))
|
continue;
|
continue;
|
|
|
errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
|
errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
|
fields, buffer, pc);
|
fields, buffer, pc);
|
if (errmsg)
|
if (errmsg)
|
return errmsg;
|
return errmsg;
|
}
|
}
|
|
|
return NULL;
|
return NULL;
|
}
|
}
|
|
|
#if CGEN_INT_INSN_P
|
#if CGEN_INT_INSN_P
|
/* Cover function to store an insn value into an integral insn. Must go here
|
/* Cover function to store an insn value into an integral insn. Must go here
|
because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
|
because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
|
|
|
static void
|
static void
|
put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
CGEN_INSN_BYTES_PTR buf,
|
CGEN_INSN_BYTES_PTR buf,
|
int length,
|
int length,
|
int insn_length,
|
int insn_length,
|
CGEN_INSN_INT value)
|
CGEN_INSN_INT value)
|
{
|
{
|
/* For architectures with insns smaller than the base-insn-bitsize,
|
/* For architectures with insns smaller than the base-insn-bitsize,
|
length may be too big. */
|
length may be too big. */
|
if (length > insn_length)
|
if (length > insn_length)
|
*buf = value;
|
*buf = value;
|
else
|
else
|
{
|
{
|
int shift = insn_length - length;
|
int shift = insn_length - length;
|
/* Written this way to avoid undefined behaviour. */
|
/* Written this way to avoid undefined behaviour. */
|
CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
|
CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
|
|
|
*buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
|
*buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
|
}
|
}
|
}
|
}
|
#endif
|
#endif
|
|
|
/* Operand extraction. */
|
/* Operand extraction. */
|
|
|
#if ! CGEN_INT_INSN_P
|
#if ! CGEN_INT_INSN_P
|
|
|
/* Subroutine of extract_normal.
|
/* Subroutine of extract_normal.
|
Ensure sufficient bytes are cached in EX_INFO.
|
Ensure sufficient bytes are cached in EX_INFO.
|
OFFSET is the offset in bytes from the start of the insn of the value.
|
OFFSET is the offset in bytes from the start of the insn of the value.
|
BYTES is the length of the needed value.
|
BYTES is the length of the needed value.
|
Returns 1 for success, 0 for failure. */
|
Returns 1 for success, 0 for failure. */
|
|
|
static CGEN_INLINE int
|
static CGEN_INLINE int
|
fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
CGEN_EXTRACT_INFO *ex_info,
|
CGEN_EXTRACT_INFO *ex_info,
|
int offset,
|
int offset,
|
int bytes,
|
int bytes,
|
bfd_vma pc)
|
bfd_vma pc)
|
{
|
{
|
/* It's doubtful that the middle part has already been fetched so
|
/* It's doubtful that the middle part has already been fetched so
|
we don't optimize that case. kiss. */
|
we don't optimize that case. kiss. */
|
unsigned int mask;
|
unsigned int mask;
|
disassemble_info *info = (disassemble_info *) ex_info->dis_info;
|
disassemble_info *info = (disassemble_info *) ex_info->dis_info;
|
|
|
/* First do a quick check. */
|
/* First do a quick check. */
|
mask = (1 << bytes) - 1;
|
mask = (1 << bytes) - 1;
|
if (((ex_info->valid >> offset) & mask) == mask)
|
if (((ex_info->valid >> offset) & mask) == mask)
|
return 1;
|
return 1;
|
|
|
/* Search for the first byte we need to read. */
|
/* Search for the first byte we need to read. */
|
for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
|
for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
|
if (! (mask & ex_info->valid))
|
if (! (mask & ex_info->valid))
|
break;
|
break;
|
|
|
if (bytes)
|
if (bytes)
|
{
|
{
|
int status;
|
int status;
|
|
|
pc += offset;
|
pc += offset;
|
status = (*info->read_memory_func)
|
status = (*info->read_memory_func)
|
(pc, ex_info->insn_bytes + offset, bytes, info);
|
(pc, ex_info->insn_bytes + offset, bytes, info);
|
|
|
if (status != 0)
|
if (status != 0)
|
{
|
{
|
(*info->memory_error_func) (status, pc, info);
|
(*info->memory_error_func) (status, pc, info);
|
return 0;
|
return 0;
|
}
|
}
|
|
|
ex_info->valid |= ((1 << bytes) - 1) << offset;
|
ex_info->valid |= ((1 << bytes) - 1) << offset;
|
}
|
}
|
|
|
return 1;
|
return 1;
|
}
|
}
|
|
|
/* Subroutine of extract_normal. */
|
/* Subroutine of extract_normal. */
|
|
|
static CGEN_INLINE long
|
static CGEN_INLINE long
|
extract_1 (CGEN_CPU_DESC cd,
|
extract_1 (CGEN_CPU_DESC cd,
|
CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
|
CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
|
int start,
|
int start,
|
int length,
|
int length,
|
int word_length,
|
int word_length,
|
unsigned char *bufp,
|
unsigned char *bufp,
|
bfd_vma pc ATTRIBUTE_UNUSED)
|
bfd_vma pc ATTRIBUTE_UNUSED)
|
{
|
{
|
unsigned long x;
|
unsigned long x;
|
int shift;
|
int shift;
|
|
|
x = cgen_get_insn_value (cd, bufp, word_length);
|
x = cgen_get_insn_value (cd, bufp, word_length);
|
|
|
if (CGEN_INSN_LSB0_P)
|
if (CGEN_INSN_LSB0_P)
|
shift = (start + 1) - length;
|
shift = (start + 1) - length;
|
else
|
else
|
shift = (word_length - (start + length));
|
shift = (word_length - (start + length));
|
return x >> shift;
|
return x >> shift;
|
}
|
}
|
|
|
#endif /* ! CGEN_INT_INSN_P */
|
#endif /* ! CGEN_INT_INSN_P */
|
|
|
/* Default extraction routine.
|
/* Default extraction routine.
|
|
|
INSN_VALUE is the first base_insn_bitsize bits of the insn in host order,
|
INSN_VALUE is the first base_insn_bitsize bits of the insn in host order,
|
or sometimes less for cases like the m32r where the base insn size is 32
|
or sometimes less for cases like the m32r where the base insn size is 32
|
but some insns are 16 bits.
|
but some insns are 16 bits.
|
ATTRS is a mask of the boolean attributes. We only need `SIGNED',
|
ATTRS is a mask of the boolean attributes. We only need `SIGNED',
|
but for generality we take a bitmask of all of them.
|
but for generality we take a bitmask of all of them.
|
WORD_OFFSET is the offset in bits from the start of the insn of the value.
|
WORD_OFFSET is the offset in bits from the start of the insn of the value.
|
WORD_LENGTH is the length of the word in bits in which the value resides.
|
WORD_LENGTH is the length of the word in bits in which the value resides.
|
START is the starting bit number in the word, architecture origin.
|
START is the starting bit number in the word, architecture origin.
|
LENGTH is the length of VALUE in bits.
|
LENGTH is the length of VALUE in bits.
|
TOTAL_LENGTH is the total length of the insn in bits.
|
TOTAL_LENGTH is the total length of the insn in bits.
|
|
|
Returns 1 for success, 0 for failure. */
|
Returns 1 for success, 0 for failure. */
|
|
|
/* ??? The return code isn't properly used. wip. */
|
/* ??? The return code isn't properly used. wip. */
|
|
|
/* ??? This doesn't handle bfd_vma's. Create another function when
|
/* ??? This doesn't handle bfd_vma's. Create another function when
|
necessary. */
|
necessary. */
|
|
|
static int
|
static int
|
extract_normal (CGEN_CPU_DESC cd,
|
extract_normal (CGEN_CPU_DESC cd,
|
#if ! CGEN_INT_INSN_P
|
#if ! CGEN_INT_INSN_P
|
CGEN_EXTRACT_INFO *ex_info,
|
CGEN_EXTRACT_INFO *ex_info,
|
#else
|
#else
|
CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
|
CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
|
#endif
|
#endif
|
CGEN_INSN_INT insn_value,
|
CGEN_INSN_INT insn_value,
|
unsigned int attrs,
|
unsigned int attrs,
|
unsigned int word_offset,
|
unsigned int word_offset,
|
unsigned int start,
|
unsigned int start,
|
unsigned int length,
|
unsigned int length,
|
unsigned int word_length,
|
unsigned int word_length,
|
unsigned int total_length,
|
unsigned int total_length,
|
#if ! CGEN_INT_INSN_P
|
#if ! CGEN_INT_INSN_P
|
bfd_vma pc,
|
bfd_vma pc,
|
#else
|
#else
|
bfd_vma pc ATTRIBUTE_UNUSED,
|
bfd_vma pc ATTRIBUTE_UNUSED,
|
#endif
|
#endif
|
long *valuep)
|
long *valuep)
|
{
|
{
|
long value, mask;
|
long value, mask;
|
|
|
/* If LENGTH is zero, this operand doesn't contribute to the value
|
/* If LENGTH is zero, this operand doesn't contribute to the value
|
so give it a standard value of zero. */
|
so give it a standard value of zero. */
|
if (length == 0)
|
if (length == 0)
|
{
|
{
|
*valuep = 0;
|
*valuep = 0;
|
return 1;
|
return 1;
|
}
|
}
|
|
|
if (word_length > 32)
|
if (word_length > 32)
|
abort ();
|
abort ();
|
|
|
/* For architectures with insns smaller than the insn-base-bitsize,
|
/* For architectures with insns smaller than the insn-base-bitsize,
|
word_length may be too big. */
|
word_length may be too big. */
|
if (cd->min_insn_bitsize < cd->base_insn_bitsize)
|
if (cd->min_insn_bitsize < cd->base_insn_bitsize)
|
{
|
{
|
if (word_offset + word_length > total_length)
|
if (word_offset + word_length > total_length)
|
word_length = total_length - word_offset;
|
word_length = total_length - word_offset;
|
}
|
}
|
|
|
/* Does the value reside in INSN_VALUE, and at the right alignment? */
|
/* Does the value reside in INSN_VALUE, and at the right alignment? */
|
|
|
if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length))
|
if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length))
|
{
|
{
|
if (CGEN_INSN_LSB0_P)
|
if (CGEN_INSN_LSB0_P)
|
value = insn_value >> ((word_offset + start + 1) - length);
|
value = insn_value >> ((word_offset + start + 1) - length);
|
else
|
else
|
value = insn_value >> (total_length - ( word_offset + start + length));
|
value = insn_value >> (total_length - ( word_offset + start + length));
|
}
|
}
|
|
|
#if ! CGEN_INT_INSN_P
|
#if ! CGEN_INT_INSN_P
|
|
|
else
|
else
|
{
|
{
|
unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
|
unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
|
|
|
if (word_length > 32)
|
if (word_length > 32)
|
abort ();
|
abort ();
|
|
|
if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
|
if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
|
return 0;
|
return 0;
|
|
|
value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc);
|
value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc);
|
}
|
}
|
|
|
#endif /* ! CGEN_INT_INSN_P */
|
#endif /* ! CGEN_INT_INSN_P */
|
|
|
/* Written this way to avoid undefined behaviour. */
|
/* Written this way to avoid undefined behaviour. */
|
mask = (((1L << (length - 1)) - 1) << 1) | 1;
|
mask = (((1L << (length - 1)) - 1) << 1) | 1;
|
|
|
value &= mask;
|
value &= mask;
|
/* sign extend? */
|
/* sign extend? */
|
if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)
|
if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)
|
&& (value & (1L << (length - 1))))
|
&& (value & (1L << (length - 1))))
|
value |= ~mask;
|
value |= ~mask;
|
|
|
*valuep = value;
|
*valuep = value;
|
|
|
return 1;
|
return 1;
|
}
|
}
|
|
|
/* Default insn extractor.
|
/* Default insn extractor.
|
|
|
INSN_VALUE is the first base_insn_bitsize bits, translated to host order.
|
INSN_VALUE is the first base_insn_bitsize bits, translated to host order.
|
The extracted fields are stored in FIELDS.
|
The extracted fields are stored in FIELDS.
|
EX_INFO is used to handle reading variable length insns.
|
EX_INFO is used to handle reading variable length insns.
|
Return the length of the insn in bits, or 0 if no match,
|
Return the length of the insn in bits, or 0 if no match,
|
or -1 if an error occurs fetching data (memory_error_func will have
|
or -1 if an error occurs fetching data (memory_error_func will have
|
been called). */
|
been called). */
|
|
|
static int
|
static int
|
extract_insn_normal (CGEN_CPU_DESC cd,
|
extract_insn_normal (CGEN_CPU_DESC cd,
|
const CGEN_INSN *insn,
|
const CGEN_INSN *insn,
|
CGEN_EXTRACT_INFO *ex_info,
|
CGEN_EXTRACT_INFO *ex_info,
|
CGEN_INSN_INT insn_value,
|
CGEN_INSN_INT insn_value,
|
CGEN_FIELDS *fields,
|
CGEN_FIELDS *fields,
|
bfd_vma pc)
|
bfd_vma pc)
|
{
|
{
|
const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
|
const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
|
const CGEN_SYNTAX_CHAR_TYPE *syn;
|
const CGEN_SYNTAX_CHAR_TYPE *syn;
|
|
|
CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
|
CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
|
|
|
CGEN_INIT_EXTRACT (cd);
|
CGEN_INIT_EXTRACT (cd);
|
|
|
for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
|
for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
|
{
|
{
|
int length;
|
int length;
|
|
|
if (CGEN_SYNTAX_CHAR_P (*syn))
|
if (CGEN_SYNTAX_CHAR_P (*syn))
|
continue;
|
continue;
|
|
|
length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
|
length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
|
ex_info, insn_value, fields, pc);
|
ex_info, insn_value, fields, pc);
|
if (length <= 0)
|
if (length <= 0)
|
return length;
|
return length;
|
}
|
}
|
|
|
/* We recognized and successfully extracted this insn. */
|
/* We recognized and successfully extracted this insn. */
|
return CGEN_INSN_BITSIZE (insn);
|
return CGEN_INSN_BITSIZE (insn);
|
}
|
}
|
|
|
/* Machine generated code added here. */
|
/* Machine generated code added here. */
|
|
|
const char * m32r_cgen_insert_operand
|
const char * m32r_cgen_insert_operand
|
(CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
|
(CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
|
|
|
/* Main entry point for operand insertion.
|
/* Main entry point for operand insertion.
|
|
|
This function is basically just a big switch statement. Earlier versions
|
This function is basically just a big switch statement. Earlier versions
|
used tables to look up the function to use, but
|
used tables to look up the function to use, but
|
- if the table contains both assembler and disassembler functions then
|
- if the table contains both assembler and disassembler functions then
|
the disassembler contains much of the assembler and vice-versa,
|
the disassembler contains much of the assembler and vice-versa,
|
- there's a lot of inlining possibilities as things grow,
|
- there's a lot of inlining possibilities as things grow,
|
- using a switch statement avoids the function call overhead.
|
- using a switch statement avoids the function call overhead.
|
|
|
This function could be moved into `parse_insn_normal', but keeping it
|
This function could be moved into `parse_insn_normal', but keeping it
|
separate makes clear the interface between `parse_insn_normal' and each of
|
separate makes clear the interface between `parse_insn_normal' and each of
|
the handlers. It's also needed by GAS to insert operands that couldn't be
|
the handlers. It's also needed by GAS to insert operands that couldn't be
|
resolved during parsing. */
|
resolved during parsing. */
|
|
|
const char *
|
const char *
|
m32r_cgen_insert_operand (CGEN_CPU_DESC cd,
|
m32r_cgen_insert_operand (CGEN_CPU_DESC cd,
|
int opindex,
|
int opindex,
|
CGEN_FIELDS * fields,
|
CGEN_FIELDS * fields,
|
CGEN_INSN_BYTES_PTR buffer,
|
CGEN_INSN_BYTES_PTR buffer,
|
bfd_vma pc ATTRIBUTE_UNUSED)
|
bfd_vma pc ATTRIBUTE_UNUSED)
|
{
|
{
|
const char * errmsg = NULL;
|
const char * errmsg = NULL;
|
unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
|
unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
|
|
|
switch (opindex)
|
switch (opindex)
|
{
|
{
|
case M32R_OPERAND_ACC :
|
case M32R_OPERAND_ACC :
|
errmsg = insert_normal (cd, fields->f_acc, 0, 0, 8, 1, 32, total_length, buffer);
|
errmsg = insert_normal (cd, fields->f_acc, 0, 0, 8, 1, 32, total_length, buffer);
|
break;
|
break;
|
case M32R_OPERAND_ACCD :
|
case M32R_OPERAND_ACCD :
|
errmsg = insert_normal (cd, fields->f_accd, 0, 0, 4, 2, 32, total_length, buffer);
|
errmsg = insert_normal (cd, fields->f_accd, 0, 0, 4, 2, 32, total_length, buffer);
|
break;
|
break;
|
case M32R_OPERAND_ACCS :
|
case M32R_OPERAND_ACCS :
|
errmsg = insert_normal (cd, fields->f_accs, 0, 0, 12, 2, 32, total_length, buffer);
|
errmsg = insert_normal (cd, fields->f_accs, 0, 0, 12, 2, 32, total_length, buffer);
|
break;
|
break;
|
case M32R_OPERAND_DCR :
|
case M32R_OPERAND_DCR :
|
errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer);
|
errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer);
|
break;
|
break;
|
case M32R_OPERAND_DISP16 :
|
case M32R_OPERAND_DISP16 :
|
{
|
{
|
long value = fields->f_disp16;
|
long value = fields->f_disp16;
|
value = ((int) (((value) - (pc))) >> (2));
|
value = ((int) (((value) - (pc))) >> (2));
|
errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 16, 16, 32, total_length, buffer);
|
errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 16, 16, 32, total_length, buffer);
|
}
|
}
|
break;
|
break;
|
case M32R_OPERAND_DISP24 :
|
case M32R_OPERAND_DISP24 :
|
{
|
{
|
long value = fields->f_disp24;
|
long value = fields->f_disp24;
|
value = ((int) (((value) - (pc))) >> (2));
|
value = ((int) (((value) - (pc))) >> (2));
|
errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 24, 32, total_length, buffer);
|
errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 24, 32, total_length, buffer);
|
}
|
}
|
break;
|
break;
|
case M32R_OPERAND_DISP8 :
|
case M32R_OPERAND_DISP8 :
|
{
|
{
|
long value = fields->f_disp8;
|
long value = fields->f_disp8;
|
value = ((int) (((value) - (((pc) & (-4))))) >> (2));
|
value = ((int) (((value) - (((pc) & (-4))))) >> (2));
|
errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 32, total_length, buffer);
|
errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 32, total_length, buffer);
|
}
|
}
|
break;
|
break;
|
case M32R_OPERAND_DR :
|
case M32R_OPERAND_DR :
|
errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer);
|
errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer);
|
break;
|
break;
|
case M32R_OPERAND_HASH :
|
case M32R_OPERAND_HASH :
|
break;
|
break;
|
case M32R_OPERAND_HI16 :
|
case M32R_OPERAND_HI16 :
|
errmsg = insert_normal (cd, fields->f_hi16, 0|(1<<CGEN_IFLD_SIGN_OPT), 0, 16, 16, 32, total_length, buffer);
|
errmsg = insert_normal (cd, fields->f_hi16, 0|(1<<CGEN_IFLD_SIGN_OPT), 0, 16, 16, 32, total_length, buffer);
|
break;
|
break;
|
case M32R_OPERAND_IMM1 :
|
case M32R_OPERAND_IMM1 :
|
{
|
{
|
long value = fields->f_imm1;
|
long value = fields->f_imm1;
|
value = ((value) - (1));
|
value = ((value) - (1));
|
errmsg = insert_normal (cd, value, 0, 0, 15, 1, 32, total_length, buffer);
|
errmsg = insert_normal (cd, value, 0, 0, 15, 1, 32, total_length, buffer);
|
}
|
}
|
break;
|
break;
|
case M32R_OPERAND_SCR :
|
case M32R_OPERAND_SCR :
|
errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer);
|
errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer);
|
break;
|
break;
|
case M32R_OPERAND_SIMM16 :
|
case M32R_OPERAND_SIMM16 :
|
errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, buffer);
|
errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, buffer);
|
break;
|
break;
|
case M32R_OPERAND_SIMM8 :
|
case M32R_OPERAND_SIMM8 :
|
errmsg = insert_normal (cd, fields->f_simm8, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 32, total_length, buffer);
|
errmsg = insert_normal (cd, fields->f_simm8, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 32, total_length, buffer);
|
break;
|
break;
|
case M32R_OPERAND_SLO16 :
|
case M32R_OPERAND_SLO16 :
|
errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, buffer);
|
errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, buffer);
|
break;
|
break;
|
case M32R_OPERAND_SR :
|
case M32R_OPERAND_SR :
|
errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer);
|
errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer);
|
break;
|
break;
|
case M32R_OPERAND_SRC1 :
|
case M32R_OPERAND_SRC1 :
|
errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer);
|
errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer);
|
break;
|
break;
|
case M32R_OPERAND_SRC2 :
|
case M32R_OPERAND_SRC2 :
|
errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer);
|
errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer);
|
break;
|
break;
|
case M32R_OPERAND_UIMM16 :
|
case M32R_OPERAND_UIMM16 :
|
errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 16, 16, 32, total_length, buffer);
|
errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 16, 16, 32, total_length, buffer);
|
break;
|
break;
|
case M32R_OPERAND_UIMM24 :
|
case M32R_OPERAND_UIMM24 :
|
errmsg = insert_normal (cd, fields->f_uimm24, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 24, 32, total_length, buffer);
|
errmsg = insert_normal (cd, fields->f_uimm24, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 24, 32, total_length, buffer);
|
break;
|
break;
|
case M32R_OPERAND_UIMM3 :
|
case M32R_OPERAND_UIMM3 :
|
errmsg = insert_normal (cd, fields->f_uimm3, 0, 0, 5, 3, 32, total_length, buffer);
|
errmsg = insert_normal (cd, fields->f_uimm3, 0, 0, 5, 3, 32, total_length, buffer);
|
break;
|
break;
|
case M32R_OPERAND_UIMM4 :
|
case M32R_OPERAND_UIMM4 :
|
errmsg = insert_normal (cd, fields->f_uimm4, 0, 0, 12, 4, 32, total_length, buffer);
|
errmsg = insert_normal (cd, fields->f_uimm4, 0, 0, 12, 4, 32, total_length, buffer);
|
break;
|
break;
|
case M32R_OPERAND_UIMM5 :
|
case M32R_OPERAND_UIMM5 :
|
errmsg = insert_normal (cd, fields->f_uimm5, 0, 0, 11, 5, 32, total_length, buffer);
|
errmsg = insert_normal (cd, fields->f_uimm5, 0, 0, 11, 5, 32, total_length, buffer);
|
break;
|
break;
|
case M32R_OPERAND_UIMM8 :
|
case M32R_OPERAND_UIMM8 :
|
errmsg = insert_normal (cd, fields->f_uimm8, 0, 0, 8, 8, 32, total_length, buffer);
|
errmsg = insert_normal (cd, fields->f_uimm8, 0, 0, 8, 8, 32, total_length, buffer);
|
break;
|
break;
|
case M32R_OPERAND_ULO16 :
|
case M32R_OPERAND_ULO16 :
|
errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 16, 16, 32, total_length, buffer);
|
errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 16, 16, 32, total_length, buffer);
|
break;
|
break;
|
|
|
default :
|
default :
|
/* xgettext:c-format */
|
/* xgettext:c-format */
|
fprintf (stderr, _("Unrecognized field %d while building insn.\n"),
|
fprintf (stderr, _("Unrecognized field %d while building insn.\n"),
|
opindex);
|
opindex);
|
abort ();
|
abort ();
|
}
|
}
|
|
|
return errmsg;
|
return errmsg;
|
}
|
}
|
|
|
int m32r_cgen_extract_operand
|
int m32r_cgen_extract_operand
|
(CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
|
(CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
|
|
|
/* Main entry point for operand extraction.
|
/* Main entry point for operand extraction.
|
The result is <= 0 for error, >0 for success.
|
The result is <= 0 for error, >0 for success.
|
??? Actual values aren't well defined right now.
|
??? Actual values aren't well defined right now.
|
|
|
This function is basically just a big switch statement. Earlier versions
|
This function is basically just a big switch statement. Earlier versions
|
used tables to look up the function to use, but
|
used tables to look up the function to use, but
|
- if the table contains both assembler and disassembler functions then
|
- if the table contains both assembler and disassembler functions then
|
the disassembler contains much of the assembler and vice-versa,
|
the disassembler contains much of the assembler and vice-versa,
|
- there's a lot of inlining possibilities as things grow,
|
- there's a lot of inlining possibilities as things grow,
|
- using a switch statement avoids the function call overhead.
|
- using a switch statement avoids the function call overhead.
|
|
|
This function could be moved into `print_insn_normal', but keeping it
|
This function could be moved into `print_insn_normal', but keeping it
|
separate makes clear the interface between `print_insn_normal' and each of
|
separate makes clear the interface between `print_insn_normal' and each of
|
the handlers. */
|
the handlers. */
|
|
|
int
|
int
|
m32r_cgen_extract_operand (CGEN_CPU_DESC cd,
|
m32r_cgen_extract_operand (CGEN_CPU_DESC cd,
|
int opindex,
|
int opindex,
|
CGEN_EXTRACT_INFO *ex_info,
|
CGEN_EXTRACT_INFO *ex_info,
|
CGEN_INSN_INT insn_value,
|
CGEN_INSN_INT insn_value,
|
CGEN_FIELDS * fields,
|
CGEN_FIELDS * fields,
|
bfd_vma pc)
|
bfd_vma pc)
|
{
|
{
|
/* Assume success (for those operands that are nops). */
|
/* Assume success (for those operands that are nops). */
|
int length = 1;
|
int length = 1;
|
unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
|
unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
|
|
|
switch (opindex)
|
switch (opindex)
|
{
|
{
|
case M32R_OPERAND_ACC :
|
case M32R_OPERAND_ACC :
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 1, 32, total_length, pc, & fields->f_acc);
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 1, 32, total_length, pc, & fields->f_acc);
|
break;
|
break;
|
case M32R_OPERAND_ACCD :
|
case M32R_OPERAND_ACCD :
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 2, 32, total_length, pc, & fields->f_accd);
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 2, 32, total_length, pc, & fields->f_accd);
|
break;
|
break;
|
case M32R_OPERAND_ACCS :
|
case M32R_OPERAND_ACCS :
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 2, 32, total_length, pc, & fields->f_accs);
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 2, 32, total_length, pc, & fields->f_accs);
|
break;
|
break;
|
case M32R_OPERAND_DCR :
|
case M32R_OPERAND_DCR :
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1);
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1);
|
break;
|
break;
|
case M32R_OPERAND_DISP16 :
|
case M32R_OPERAND_DISP16 :
|
{
|
{
|
long value;
|
long value;
|
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 16, 16, 32, total_length, pc, & value);
|
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 16, 16, 32, total_length, pc, & value);
|
value = ((((value) << (2))) + (pc));
|
value = ((((value) << (2))) + (pc));
|
fields->f_disp16 = value;
|
fields->f_disp16 = value;
|
}
|
}
|
break;
|
break;
|
case M32R_OPERAND_DISP24 :
|
case M32R_OPERAND_DISP24 :
|
{
|
{
|
long value;
|
long value;
|
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 24, 32, total_length, pc, & value);
|
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 24, 32, total_length, pc, & value);
|
value = ((((value) << (2))) + (pc));
|
value = ((((value) << (2))) + (pc));
|
fields->f_disp24 = value;
|
fields->f_disp24 = value;
|
}
|
}
|
break;
|
break;
|
case M32R_OPERAND_DISP8 :
|
case M32R_OPERAND_DISP8 :
|
{
|
{
|
long value;
|
long value;
|
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 32, total_length, pc, & value);
|
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 32, total_length, pc, & value);
|
value = ((((value) << (2))) + (((pc) & (-4))));
|
value = ((((value) << (2))) + (((pc) & (-4))));
|
fields->f_disp8 = value;
|
fields->f_disp8 = value;
|
}
|
}
|
break;
|
break;
|
case M32R_OPERAND_DR :
|
case M32R_OPERAND_DR :
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1);
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1);
|
break;
|
break;
|
case M32R_OPERAND_HASH :
|
case M32R_OPERAND_HASH :
|
break;
|
break;
|
case M32R_OPERAND_HI16 :
|
case M32R_OPERAND_HI16 :
|
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGN_OPT), 0, 16, 16, 32, total_length, pc, & fields->f_hi16);
|
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGN_OPT), 0, 16, 16, 32, total_length, pc, & fields->f_hi16);
|
break;
|
break;
|
case M32R_OPERAND_IMM1 :
|
case M32R_OPERAND_IMM1 :
|
{
|
{
|
long value;
|
long value;
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 1, 32, total_length, pc, & value);
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 1, 32, total_length, pc, & value);
|
value = ((value) + (1));
|
value = ((value) + (1));
|
fields->f_imm1 = value;
|
fields->f_imm1 = value;
|
}
|
}
|
break;
|
break;
|
case M32R_OPERAND_SCR :
|
case M32R_OPERAND_SCR :
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2);
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2);
|
break;
|
break;
|
case M32R_OPERAND_SIMM16 :
|
case M32R_OPERAND_SIMM16 :
|
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, pc, & fields->f_simm16);
|
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, pc, & fields->f_simm16);
|
break;
|
break;
|
case M32R_OPERAND_SIMM8 :
|
case M32R_OPERAND_SIMM8 :
|
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 32, total_length, pc, & fields->f_simm8);
|
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 32, total_length, pc, & fields->f_simm8);
|
break;
|
break;
|
case M32R_OPERAND_SLO16 :
|
case M32R_OPERAND_SLO16 :
|
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, pc, & fields->f_simm16);
|
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, pc, & fields->f_simm16);
|
break;
|
break;
|
case M32R_OPERAND_SR :
|
case M32R_OPERAND_SR :
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2);
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2);
|
break;
|
break;
|
case M32R_OPERAND_SRC1 :
|
case M32R_OPERAND_SRC1 :
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1);
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1);
|
break;
|
break;
|
case M32R_OPERAND_SRC2 :
|
case M32R_OPERAND_SRC2 :
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2);
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2);
|
break;
|
break;
|
case M32R_OPERAND_UIMM16 :
|
case M32R_OPERAND_UIMM16 :
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_uimm16);
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_uimm16);
|
break;
|
break;
|
case M32R_OPERAND_UIMM24 :
|
case M32R_OPERAND_UIMM24 :
|
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 24, 32, total_length, pc, & fields->f_uimm24);
|
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 24, 32, total_length, pc, & fields->f_uimm24);
|
break;
|
break;
|
case M32R_OPERAND_UIMM3 :
|
case M32R_OPERAND_UIMM3 :
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_uimm3);
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_uimm3);
|
break;
|
break;
|
case M32R_OPERAND_UIMM4 :
|
case M32R_OPERAND_UIMM4 :
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_uimm4);
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_uimm4);
|
break;
|
break;
|
case M32R_OPERAND_UIMM5 :
|
case M32R_OPERAND_UIMM5 :
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 5, 32, total_length, pc, & fields->f_uimm5);
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 5, 32, total_length, pc, & fields->f_uimm5);
|
break;
|
break;
|
case M32R_OPERAND_UIMM8 :
|
case M32R_OPERAND_UIMM8 :
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & fields->f_uimm8);
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & fields->f_uimm8);
|
break;
|
break;
|
case M32R_OPERAND_ULO16 :
|
case M32R_OPERAND_ULO16 :
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_uimm16);
|
length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_uimm16);
|
break;
|
break;
|
|
|
default :
|
default :
|
/* xgettext:c-format */
|
/* xgettext:c-format */
|
fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"),
|
fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"),
|
opindex);
|
opindex);
|
abort ();
|
abort ();
|
}
|
}
|
|
|
return length;
|
return length;
|
}
|
}
|
|
|
cgen_insert_fn * const m32r_cgen_insert_handlers[] =
|
cgen_insert_fn * const m32r_cgen_insert_handlers[] =
|
{
|
{
|
insert_insn_normal,
|
insert_insn_normal,
|
};
|
};
|
|
|
cgen_extract_fn * const m32r_cgen_extract_handlers[] =
|
cgen_extract_fn * const m32r_cgen_extract_handlers[] =
|
{
|
{
|
extract_insn_normal,
|
extract_insn_normal,
|
};
|
};
|
|
|
int m32r_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
|
int m32r_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
|
bfd_vma m32r_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
|
bfd_vma m32r_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
|
|
|
/* Getting values from cgen_fields is handled by a collection of functions.
|
/* Getting values from cgen_fields is handled by a collection of functions.
|
They are distinguished by the type of the VALUE argument they return.
|
They are distinguished by the type of the VALUE argument they return.
|
TODO: floating point, inlining support, remove cases where result type
|
TODO: floating point, inlining support, remove cases where result type
|
not appropriate. */
|
not appropriate. */
|
|
|
int
|
int
|
m32r_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
m32r_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
int opindex,
|
int opindex,
|
const CGEN_FIELDS * fields)
|
const CGEN_FIELDS * fields)
|
{
|
{
|
int value;
|
int value;
|
|
|
switch (opindex)
|
switch (opindex)
|
{
|
{
|
case M32R_OPERAND_ACC :
|
case M32R_OPERAND_ACC :
|
value = fields->f_acc;
|
value = fields->f_acc;
|
break;
|
break;
|
case M32R_OPERAND_ACCD :
|
case M32R_OPERAND_ACCD :
|
value = fields->f_accd;
|
value = fields->f_accd;
|
break;
|
break;
|
case M32R_OPERAND_ACCS :
|
case M32R_OPERAND_ACCS :
|
value = fields->f_accs;
|
value = fields->f_accs;
|
break;
|
break;
|
case M32R_OPERAND_DCR :
|
case M32R_OPERAND_DCR :
|
value = fields->f_r1;
|
value = fields->f_r1;
|
break;
|
break;
|
case M32R_OPERAND_DISP16 :
|
case M32R_OPERAND_DISP16 :
|
value = fields->f_disp16;
|
value = fields->f_disp16;
|
break;
|
break;
|
case M32R_OPERAND_DISP24 :
|
case M32R_OPERAND_DISP24 :
|
value = fields->f_disp24;
|
value = fields->f_disp24;
|
break;
|
break;
|
case M32R_OPERAND_DISP8 :
|
case M32R_OPERAND_DISP8 :
|
value = fields->f_disp8;
|
value = fields->f_disp8;
|
break;
|
break;
|
case M32R_OPERAND_DR :
|
case M32R_OPERAND_DR :
|
value = fields->f_r1;
|
value = fields->f_r1;
|
break;
|
break;
|
case M32R_OPERAND_HASH :
|
case M32R_OPERAND_HASH :
|
value = 0;
|
value = 0;
|
break;
|
break;
|
case M32R_OPERAND_HI16 :
|
case M32R_OPERAND_HI16 :
|
value = fields->f_hi16;
|
value = fields->f_hi16;
|
break;
|
break;
|
case M32R_OPERAND_IMM1 :
|
case M32R_OPERAND_IMM1 :
|
value = fields->f_imm1;
|
value = fields->f_imm1;
|
break;
|
break;
|
case M32R_OPERAND_SCR :
|
case M32R_OPERAND_SCR :
|
value = fields->f_r2;
|
value = fields->f_r2;
|
break;
|
break;
|
case M32R_OPERAND_SIMM16 :
|
case M32R_OPERAND_SIMM16 :
|
value = fields->f_simm16;
|
value = fields->f_simm16;
|
break;
|
break;
|
case M32R_OPERAND_SIMM8 :
|
case M32R_OPERAND_SIMM8 :
|
value = fields->f_simm8;
|
value = fields->f_simm8;
|
break;
|
break;
|
case M32R_OPERAND_SLO16 :
|
case M32R_OPERAND_SLO16 :
|
value = fields->f_simm16;
|
value = fields->f_simm16;
|
break;
|
break;
|
case M32R_OPERAND_SR :
|
case M32R_OPERAND_SR :
|
value = fields->f_r2;
|
value = fields->f_r2;
|
break;
|
break;
|
case M32R_OPERAND_SRC1 :
|
case M32R_OPERAND_SRC1 :
|
value = fields->f_r1;
|
value = fields->f_r1;
|
break;
|
break;
|
case M32R_OPERAND_SRC2 :
|
case M32R_OPERAND_SRC2 :
|
value = fields->f_r2;
|
value = fields->f_r2;
|
break;
|
break;
|
case M32R_OPERAND_UIMM16 :
|
case M32R_OPERAND_UIMM16 :
|
value = fields->f_uimm16;
|
value = fields->f_uimm16;
|
break;
|
break;
|
case M32R_OPERAND_UIMM24 :
|
case M32R_OPERAND_UIMM24 :
|
value = fields->f_uimm24;
|
value = fields->f_uimm24;
|
break;
|
break;
|
case M32R_OPERAND_UIMM3 :
|
case M32R_OPERAND_UIMM3 :
|
value = fields->f_uimm3;
|
value = fields->f_uimm3;
|
break;
|
break;
|
case M32R_OPERAND_UIMM4 :
|
case M32R_OPERAND_UIMM4 :
|
value = fields->f_uimm4;
|
value = fields->f_uimm4;
|
break;
|
break;
|
case M32R_OPERAND_UIMM5 :
|
case M32R_OPERAND_UIMM5 :
|
value = fields->f_uimm5;
|
value = fields->f_uimm5;
|
break;
|
break;
|
case M32R_OPERAND_UIMM8 :
|
case M32R_OPERAND_UIMM8 :
|
value = fields->f_uimm8;
|
value = fields->f_uimm8;
|
break;
|
break;
|
case M32R_OPERAND_ULO16 :
|
case M32R_OPERAND_ULO16 :
|
value = fields->f_uimm16;
|
value = fields->f_uimm16;
|
break;
|
break;
|
|
|
default :
|
default :
|
/* xgettext:c-format */
|
/* xgettext:c-format */
|
fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
|
fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
|
opindex);
|
opindex);
|
abort ();
|
abort ();
|
}
|
}
|
|
|
return value;
|
return value;
|
}
|
}
|
|
|
bfd_vma
|
bfd_vma
|
m32r_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
m32r_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
int opindex,
|
int opindex,
|
const CGEN_FIELDS * fields)
|
const CGEN_FIELDS * fields)
|
{
|
{
|
bfd_vma value;
|
bfd_vma value;
|
|
|
switch (opindex)
|
switch (opindex)
|
{
|
{
|
case M32R_OPERAND_ACC :
|
case M32R_OPERAND_ACC :
|
value = fields->f_acc;
|
value = fields->f_acc;
|
break;
|
break;
|
case M32R_OPERAND_ACCD :
|
case M32R_OPERAND_ACCD :
|
value = fields->f_accd;
|
value = fields->f_accd;
|
break;
|
break;
|
case M32R_OPERAND_ACCS :
|
case M32R_OPERAND_ACCS :
|
value = fields->f_accs;
|
value = fields->f_accs;
|
break;
|
break;
|
case M32R_OPERAND_DCR :
|
case M32R_OPERAND_DCR :
|
value = fields->f_r1;
|
value = fields->f_r1;
|
break;
|
break;
|
case M32R_OPERAND_DISP16 :
|
case M32R_OPERAND_DISP16 :
|
value = fields->f_disp16;
|
value = fields->f_disp16;
|
break;
|
break;
|
case M32R_OPERAND_DISP24 :
|
case M32R_OPERAND_DISP24 :
|
value = fields->f_disp24;
|
value = fields->f_disp24;
|
break;
|
break;
|
case M32R_OPERAND_DISP8 :
|
case M32R_OPERAND_DISP8 :
|
value = fields->f_disp8;
|
value = fields->f_disp8;
|
break;
|
break;
|
case M32R_OPERAND_DR :
|
case M32R_OPERAND_DR :
|
value = fields->f_r1;
|
value = fields->f_r1;
|
break;
|
break;
|
case M32R_OPERAND_HASH :
|
case M32R_OPERAND_HASH :
|
value = 0;
|
value = 0;
|
break;
|
break;
|
case M32R_OPERAND_HI16 :
|
case M32R_OPERAND_HI16 :
|
value = fields->f_hi16;
|
value = fields->f_hi16;
|
break;
|
break;
|
case M32R_OPERAND_IMM1 :
|
case M32R_OPERAND_IMM1 :
|
value = fields->f_imm1;
|
value = fields->f_imm1;
|
break;
|
break;
|
case M32R_OPERAND_SCR :
|
case M32R_OPERAND_SCR :
|
value = fields->f_r2;
|
value = fields->f_r2;
|
break;
|
break;
|
case M32R_OPERAND_SIMM16 :
|
case M32R_OPERAND_SIMM16 :
|
value = fields->f_simm16;
|
value = fields->f_simm16;
|
break;
|
break;
|
case M32R_OPERAND_SIMM8 :
|
case M32R_OPERAND_SIMM8 :
|
value = fields->f_simm8;
|
value = fields->f_simm8;
|
break;
|
break;
|
case M32R_OPERAND_SLO16 :
|
case M32R_OPERAND_SLO16 :
|
value = fields->f_simm16;
|
value = fields->f_simm16;
|
break;
|
break;
|
case M32R_OPERAND_SR :
|
case M32R_OPERAND_SR :
|
value = fields->f_r2;
|
value = fields->f_r2;
|
break;
|
break;
|
case M32R_OPERAND_SRC1 :
|
case M32R_OPERAND_SRC1 :
|
value = fields->f_r1;
|
value = fields->f_r1;
|
break;
|
break;
|
case M32R_OPERAND_SRC2 :
|
case M32R_OPERAND_SRC2 :
|
value = fields->f_r2;
|
value = fields->f_r2;
|
break;
|
break;
|
case M32R_OPERAND_UIMM16 :
|
case M32R_OPERAND_UIMM16 :
|
value = fields->f_uimm16;
|
value = fields->f_uimm16;
|
break;
|
break;
|
case M32R_OPERAND_UIMM24 :
|
case M32R_OPERAND_UIMM24 :
|
value = fields->f_uimm24;
|
value = fields->f_uimm24;
|
break;
|
break;
|
case M32R_OPERAND_UIMM3 :
|
case M32R_OPERAND_UIMM3 :
|
value = fields->f_uimm3;
|
value = fields->f_uimm3;
|
break;
|
break;
|
case M32R_OPERAND_UIMM4 :
|
case M32R_OPERAND_UIMM4 :
|
value = fields->f_uimm4;
|
value = fields->f_uimm4;
|
break;
|
break;
|
case M32R_OPERAND_UIMM5 :
|
case M32R_OPERAND_UIMM5 :
|
value = fields->f_uimm5;
|
value = fields->f_uimm5;
|
break;
|
break;
|
case M32R_OPERAND_UIMM8 :
|
case M32R_OPERAND_UIMM8 :
|
value = fields->f_uimm8;
|
value = fields->f_uimm8;
|
break;
|
break;
|
case M32R_OPERAND_ULO16 :
|
case M32R_OPERAND_ULO16 :
|
value = fields->f_uimm16;
|
value = fields->f_uimm16;
|
break;
|
break;
|
|
|
default :
|
default :
|
/* xgettext:c-format */
|
/* xgettext:c-format */
|
fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
|
fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
|
opindex);
|
opindex);
|
abort ();
|
abort ();
|
}
|
}
|
|
|
return value;
|
return value;
|
}
|
}
|
|
|
void m32r_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
|
void m32r_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
|
void m32r_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
|
void m32r_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
|
|
|
/* Stuffing values in cgen_fields is handled by a collection of functions.
|
/* Stuffing values in cgen_fields is handled by a collection of functions.
|
They are distinguished by the type of the VALUE argument they accept.
|
They are distinguished by the type of the VALUE argument they accept.
|
TODO: floating point, inlining support, remove cases where argument type
|
TODO: floating point, inlining support, remove cases where argument type
|
not appropriate. */
|
not appropriate. */
|
|
|
void
|
void
|
m32r_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
m32r_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
int opindex,
|
int opindex,
|
CGEN_FIELDS * fields,
|
CGEN_FIELDS * fields,
|
int value)
|
int value)
|
{
|
{
|
switch (opindex)
|
switch (opindex)
|
{
|
{
|
case M32R_OPERAND_ACC :
|
case M32R_OPERAND_ACC :
|
fields->f_acc = value;
|
fields->f_acc = value;
|
break;
|
break;
|
case M32R_OPERAND_ACCD :
|
case M32R_OPERAND_ACCD :
|
fields->f_accd = value;
|
fields->f_accd = value;
|
break;
|
break;
|
case M32R_OPERAND_ACCS :
|
case M32R_OPERAND_ACCS :
|
fields->f_accs = value;
|
fields->f_accs = value;
|
break;
|
break;
|
case M32R_OPERAND_DCR :
|
case M32R_OPERAND_DCR :
|
fields->f_r1 = value;
|
fields->f_r1 = value;
|
break;
|
break;
|
case M32R_OPERAND_DISP16 :
|
case M32R_OPERAND_DISP16 :
|
fields->f_disp16 = value;
|
fields->f_disp16 = value;
|
break;
|
break;
|
case M32R_OPERAND_DISP24 :
|
case M32R_OPERAND_DISP24 :
|
fields->f_disp24 = value;
|
fields->f_disp24 = value;
|
break;
|
break;
|
case M32R_OPERAND_DISP8 :
|
case M32R_OPERAND_DISP8 :
|
fields->f_disp8 = value;
|
fields->f_disp8 = value;
|
break;
|
break;
|
case M32R_OPERAND_DR :
|
case M32R_OPERAND_DR :
|
fields->f_r1 = value;
|
fields->f_r1 = value;
|
break;
|
break;
|
case M32R_OPERAND_HASH :
|
case M32R_OPERAND_HASH :
|
break;
|
break;
|
case M32R_OPERAND_HI16 :
|
case M32R_OPERAND_HI16 :
|
fields->f_hi16 = value;
|
fields->f_hi16 = value;
|
break;
|
break;
|
case M32R_OPERAND_IMM1 :
|
case M32R_OPERAND_IMM1 :
|
fields->f_imm1 = value;
|
fields->f_imm1 = value;
|
break;
|
break;
|
case M32R_OPERAND_SCR :
|
case M32R_OPERAND_SCR :
|
fields->f_r2 = value;
|
fields->f_r2 = value;
|
break;
|
break;
|
case M32R_OPERAND_SIMM16 :
|
case M32R_OPERAND_SIMM16 :
|
fields->f_simm16 = value;
|
fields->f_simm16 = value;
|
break;
|
break;
|
case M32R_OPERAND_SIMM8 :
|
case M32R_OPERAND_SIMM8 :
|
fields->f_simm8 = value;
|
fields->f_simm8 = value;
|
break;
|
break;
|
case M32R_OPERAND_SLO16 :
|
case M32R_OPERAND_SLO16 :
|
fields->f_simm16 = value;
|
fields->f_simm16 = value;
|
break;
|
break;
|
case M32R_OPERAND_SR :
|
case M32R_OPERAND_SR :
|
fields->f_r2 = value;
|
fields->f_r2 = value;
|
break;
|
break;
|
case M32R_OPERAND_SRC1 :
|
case M32R_OPERAND_SRC1 :
|
fields->f_r1 = value;
|
fields->f_r1 = value;
|
break;
|
break;
|
case M32R_OPERAND_SRC2 :
|
case M32R_OPERAND_SRC2 :
|
fields->f_r2 = value;
|
fields->f_r2 = value;
|
break;
|
break;
|
case M32R_OPERAND_UIMM16 :
|
case M32R_OPERAND_UIMM16 :
|
fields->f_uimm16 = value;
|
fields->f_uimm16 = value;
|
break;
|
break;
|
case M32R_OPERAND_UIMM24 :
|
case M32R_OPERAND_UIMM24 :
|
fields->f_uimm24 = value;
|
fields->f_uimm24 = value;
|
break;
|
break;
|
case M32R_OPERAND_UIMM3 :
|
case M32R_OPERAND_UIMM3 :
|
fields->f_uimm3 = value;
|
fields->f_uimm3 = value;
|
break;
|
break;
|
case M32R_OPERAND_UIMM4 :
|
case M32R_OPERAND_UIMM4 :
|
fields->f_uimm4 = value;
|
fields->f_uimm4 = value;
|
break;
|
break;
|
case M32R_OPERAND_UIMM5 :
|
case M32R_OPERAND_UIMM5 :
|
fields->f_uimm5 = value;
|
fields->f_uimm5 = value;
|
break;
|
break;
|
case M32R_OPERAND_UIMM8 :
|
case M32R_OPERAND_UIMM8 :
|
fields->f_uimm8 = value;
|
fields->f_uimm8 = value;
|
break;
|
break;
|
case M32R_OPERAND_ULO16 :
|
case M32R_OPERAND_ULO16 :
|
fields->f_uimm16 = value;
|
fields->f_uimm16 = value;
|
break;
|
break;
|
|
|
default :
|
default :
|
/* xgettext:c-format */
|
/* xgettext:c-format */
|
fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
|
fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
|
opindex);
|
opindex);
|
abort ();
|
abort ();
|
}
|
}
|
}
|
}
|
|
|
void
|
void
|
m32r_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
m32r_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
|
int opindex,
|
int opindex,
|
CGEN_FIELDS * fields,
|
CGEN_FIELDS * fields,
|
bfd_vma value)
|
bfd_vma value)
|
{
|
{
|
switch (opindex)
|
switch (opindex)
|
{
|
{
|
case M32R_OPERAND_ACC :
|
case M32R_OPERAND_ACC :
|
fields->f_acc = value;
|
fields->f_acc = value;
|
break;
|
break;
|
case M32R_OPERAND_ACCD :
|
case M32R_OPERAND_ACCD :
|
fields->f_accd = value;
|
fields->f_accd = value;
|
break;
|
break;
|
case M32R_OPERAND_ACCS :
|
case M32R_OPERAND_ACCS :
|
fields->f_accs = value;
|
fields->f_accs = value;
|
break;
|
break;
|
case M32R_OPERAND_DCR :
|
case M32R_OPERAND_DCR :
|
fields->f_r1 = value;
|
fields->f_r1 = value;
|
break;
|
break;
|
case M32R_OPERAND_DISP16 :
|
case M32R_OPERAND_DISP16 :
|
fields->f_disp16 = value;
|
fields->f_disp16 = value;
|
break;
|
break;
|
case M32R_OPERAND_DISP24 :
|
case M32R_OPERAND_DISP24 :
|
fields->f_disp24 = value;
|
fields->f_disp24 = value;
|
break;
|
break;
|
case M32R_OPERAND_DISP8 :
|
case M32R_OPERAND_DISP8 :
|
fields->f_disp8 = value;
|
fields->f_disp8 = value;
|
break;
|
break;
|
case M32R_OPERAND_DR :
|
case M32R_OPERAND_DR :
|
fields->f_r1 = value;
|
fields->f_r1 = value;
|
break;
|
break;
|
case M32R_OPERAND_HASH :
|
case M32R_OPERAND_HASH :
|
break;
|
break;
|
case M32R_OPERAND_HI16 :
|
case M32R_OPERAND_HI16 :
|
fields->f_hi16 = value;
|
fields->f_hi16 = value;
|
break;
|
break;
|
case M32R_OPERAND_IMM1 :
|
case M32R_OPERAND_IMM1 :
|
fields->f_imm1 = value;
|
fields->f_imm1 = value;
|
break;
|
break;
|
case M32R_OPERAND_SCR :
|
case M32R_OPERAND_SCR :
|
fields->f_r2 = value;
|
fields->f_r2 = value;
|
break;
|
break;
|
case M32R_OPERAND_SIMM16 :
|
case M32R_OPERAND_SIMM16 :
|
fields->f_simm16 = value;
|
fields->f_simm16 = value;
|
break;
|
break;
|
case M32R_OPERAND_SIMM8 :
|
case M32R_OPERAND_SIMM8 :
|
fields->f_simm8 = value;
|
fields->f_simm8 = value;
|
break;
|
break;
|
case M32R_OPERAND_SLO16 :
|
case M32R_OPERAND_SLO16 :
|
fields->f_simm16 = value;
|
fields->f_simm16 = value;
|
break;
|
break;
|
case M32R_OPERAND_SR :
|
case M32R_OPERAND_SR :
|
fields->f_r2 = value;
|
fields->f_r2 = value;
|
break;
|
break;
|
case M32R_OPERAND_SRC1 :
|
case M32R_OPERAND_SRC1 :
|
fields->f_r1 = value;
|
fields->f_r1 = value;
|
break;
|
break;
|
case M32R_OPERAND_SRC2 :
|
case M32R_OPERAND_SRC2 :
|
fields->f_r2 = value;
|
fields->f_r2 = value;
|
break;
|
break;
|
case M32R_OPERAND_UIMM16 :
|
case M32R_OPERAND_UIMM16 :
|
fields->f_uimm16 = value;
|
fields->f_uimm16 = value;
|
break;
|
break;
|
case M32R_OPERAND_UIMM24 :
|
case M32R_OPERAND_UIMM24 :
|
fields->f_uimm24 = value;
|
fields->f_uimm24 = value;
|
break;
|
break;
|
case M32R_OPERAND_UIMM3 :
|
case M32R_OPERAND_UIMM3 :
|
fields->f_uimm3 = value;
|
fields->f_uimm3 = value;
|
break;
|
break;
|
case M32R_OPERAND_UIMM4 :
|
case M32R_OPERAND_UIMM4 :
|
fields->f_uimm4 = value;
|
fields->f_uimm4 = value;
|
break;
|
break;
|
case M32R_OPERAND_UIMM5 :
|
case M32R_OPERAND_UIMM5 :
|
fields->f_uimm5 = value;
|
fields->f_uimm5 = value;
|
break;
|
break;
|
case M32R_OPERAND_UIMM8 :
|
case M32R_OPERAND_UIMM8 :
|
fields->f_uimm8 = value;
|
fields->f_uimm8 = value;
|
break;
|
break;
|
case M32R_OPERAND_ULO16 :
|
case M32R_OPERAND_ULO16 :
|
fields->f_uimm16 = value;
|
fields->f_uimm16 = value;
|
break;
|
break;
|
|
|
default :
|
default :
|
/* xgettext:c-format */
|
/* xgettext:c-format */
|
fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
|
fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
|
opindex);
|
opindex);
|
abort ();
|
abort ();
|
}
|
}
|
}
|
}
|
|
|
/* Function to call before using the instruction builder tables. */
|
/* Function to call before using the instruction builder tables. */
|
|
|
void
|
void
|
m32r_cgen_init_ibld_table (CGEN_CPU_DESC cd)
|
m32r_cgen_init_ibld_table (CGEN_CPU_DESC cd)
|
{
|
{
|
cd->insert_handlers = & m32r_cgen_insert_handlers[0];
|
cd->insert_handlers = & m32r_cgen_insert_handlers[0];
|
cd->extract_handlers = & m32r_cgen_extract_handlers[0];
|
cd->extract_handlers = & m32r_cgen_extract_handlers[0];
|
|
|
cd->insert_operand = m32r_cgen_insert_operand;
|
cd->insert_operand = m32r_cgen_insert_operand;
|
cd->extract_operand = m32r_cgen_extract_operand;
|
cd->extract_operand = m32r_cgen_extract_operand;
|
|
|
cd->get_int_operand = m32r_cgen_get_int_operand;
|
cd->get_int_operand = m32r_cgen_get_int_operand;
|
cd->set_int_operand = m32r_cgen_set_int_operand;
|
cd->set_int_operand = m32r_cgen_set_int_operand;
|
cd->get_vma_operand = m32r_cgen_get_vma_operand;
|
cd->get_vma_operand = m32r_cgen_get_vma_operand;
|
cd->set_vma_operand = m32r_cgen_set_vma_operand;
|
cd->set_vma_operand = m32r_cgen_set_vma_operand;
|
}
|
}
|
|
|
