// -*- C -*-
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// -*- C -*-
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//
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//
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// ::=
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// ::=
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// { "+" }
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// { "+" }
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// ":"
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// ":"
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// ":"
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// ":"
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// ":"
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// ":"
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// ":"
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// ":"
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//
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//
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// { }
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// { }
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// { }
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// { }
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//
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//
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//
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//
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// IGEN config - mips16
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// IGEN config - mips16
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// :option:16::insn-bit-size:16
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// :option:16::insn-bit-size:16
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// :option:16::hi-bit-nr:15
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// :option:16::hi-bit-nr:15
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:option:16::insn-specifying-widths:true
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:option:16::insn-specifying-widths:true
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:option:16::gen-delayed-branch:false
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:option:16::gen-delayed-branch:false
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// IGEN config - mips32/64..
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// IGEN config - mips32/64..
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// :option:32::insn-bit-size:32
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// :option:32::insn-bit-size:32
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// :option:32::hi-bit-nr:31
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// :option:32::hi-bit-nr:31
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:option:32::insn-specifying-widths:true
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:option:32::insn-specifying-widths:true
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:option:32::gen-delayed-branch:false
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:option:32::gen-delayed-branch:false
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// Generate separate simulators for each target
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// Generate separate simulators for each target
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// :option:::multi-sim:true
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// :option:::multi-sim:true
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// Models known by this simulator are defined below.
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// Models known by this simulator are defined below.
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//
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//
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// When placing models in the instruction descriptions, please place
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// When placing models in the instruction descriptions, please place
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// them one per line, in the order given here.
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// them one per line, in the order given here.
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// MIPS ISAs:
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// MIPS ISAs:
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//
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//
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// Instructions and related functions for these models are included in
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// Instructions and related functions for these models are included in
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// this file.
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// this file.
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:model:::mipsI:mips3000:
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:model:::mipsI:mips3000:
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:model:::mipsII:mips6000:
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:model:::mipsII:mips6000:
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:model:::mipsIII:mips4000:
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:model:::mipsIII:mips4000:
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:model:::mipsIV:mips8000:
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:model:::mipsIV:mips8000:
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:model:::mipsV:mipsisaV:
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:model:::mipsV:mipsisaV:
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:model:::mips32:mipsisa32:
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:model:::mips32:mipsisa32:
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:model:::mips32r2:mipsisa32r2:
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:model:::mips32r2:mipsisa32r2:
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:model:::mips64:mipsisa64:
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:model:::mips64:mipsisa64:
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:model:::mips64r2:mipsisa64r2:
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:model:::mips64r2:mipsisa64r2:
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// Vendor ISAs:
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// Vendor ISAs:
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//
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//
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// Standard MIPS ISA instructions used for these models are listed here,
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// Standard MIPS ISA instructions used for these models are listed here,
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// as are functions needed by those standard instructions. Instructions
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// as are functions needed by those standard instructions. Instructions
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// which are model-dependent and which are not in the standard MIPS ISAs
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// which are model-dependent and which are not in the standard MIPS ISAs
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// (or which pre-date or use different encodings than the standard
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// (or which pre-date or use different encodings than the standard
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// instructions) are (for the most part) in separate .igen files.
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// instructions) are (for the most part) in separate .igen files.
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:model:::vr4100:mips4100: // vr.igen
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:model:::vr4100:mips4100: // vr.igen
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:model:::vr4120:mips4120:
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:model:::vr4120:mips4120:
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:model:::vr5000:mips5000:
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:model:::vr5000:mips5000:
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:model:::vr5400:mips5400:
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:model:::vr5400:mips5400:
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:model:::vr5500:mips5500:
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:model:::vr5500:mips5500:
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:model:::r3900:mips3900: // tx.igen
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:model:::r3900:mips3900: // tx.igen
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// MIPS Application Specific Extensions (ASEs)
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// MIPS Application Specific Extensions (ASEs)
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//
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//
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// Instructions for the ASEs are in separate .igen files.
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// Instructions for the ASEs are in separate .igen files.
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// ASEs add instructions on to a base ISA.
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// ASEs add instructions on to a base ISA.
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:model:::mips16:mips16: // m16.igen (and m16.dc)
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:model:::mips16:mips16: // m16.igen (and m16.dc)
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:model:::mips16e:mips16e: // m16e.igen
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:model:::mips16e:mips16e: // m16e.igen
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:model:::mips3d:mips3d: // mips3d.igen
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:model:::mips3d:mips3d: // mips3d.igen
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:model:::mdmx:mdmx: // mdmx.igen
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:model:::mdmx:mdmx: // mdmx.igen
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:model:::dsp:dsp: // dsp.igen
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:model:::dsp:dsp: // dsp.igen
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:model:::dsp2:dsp2: // dsp2.igen
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:model:::dsp2:dsp2: // dsp2.igen
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:model:::smartmips:smartmips: // smartmips.igen
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:model:::smartmips:smartmips: // smartmips.igen
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// Vendor Extensions
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// Vendor Extensions
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//
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//
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// Instructions specific to these extensions are in separate .igen files.
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// Instructions specific to these extensions are in separate .igen files.
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// Extensions add instructions on to a base ISA.
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// Extensions add instructions on to a base ISA.
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:model:::sb1:sb1: // sb1.igen
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:model:::sb1:sb1: // sb1.igen
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// Pseudo instructions known by IGEN
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// Pseudo instructions known by IGEN
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:internal::::illegal:
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:internal::::illegal:
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{
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{
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SignalException (ReservedInstruction, 0);
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SignalException (ReservedInstruction, 0);
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}
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}
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// Pseudo instructions known by interp.c
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// Pseudo instructions known by interp.c
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// For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
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// For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
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000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
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000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
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"rsvd "
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"rsvd "
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{
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{
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SignalException (ReservedInstruction, instruction_0);
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SignalException (ReservedInstruction, instruction_0);
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}
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}
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// Helper:
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// Helper:
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//
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//
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// Simulate a 32 bit delayslot instruction
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// Simulate a 32 bit delayslot instruction
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//
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//
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:function:::address_word:delayslot32:address_word target
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:function:::address_word:delayslot32:address_word target
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{
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{
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instruction_word delay_insn;
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instruction_word delay_insn;
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sim_events_slip (SD, 1);
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sim_events_slip (SD, 1);
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DSPC = CIA;
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DSPC = CIA;
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CIA = CIA + 4; /* NOTE not mips16 */
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CIA = CIA + 4; /* NOTE not mips16 */
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STATE |= simDELAYSLOT;
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STATE |= simDELAYSLOT;
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delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
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delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
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ENGINE_ISSUE_PREFIX_HOOK();
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ENGINE_ISSUE_PREFIX_HOOK();
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idecode_issue (CPU_, delay_insn, (CIA));
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idecode_issue (CPU_, delay_insn, (CIA));
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STATE &= ~simDELAYSLOT;
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STATE &= ~simDELAYSLOT;
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return target;
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return target;
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}
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}
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:function:::address_word:nullify_next_insn32:
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:function:::address_word:nullify_next_insn32:
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{
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{
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sim_events_slip (SD, 1);
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sim_events_slip (SD, 1);
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dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
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dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
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return CIA + 8;
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return CIA + 8;
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}
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}
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// Helper:
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// Helper:
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//
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//
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// Calculate an effective address given a base and an offset.
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// Calculate an effective address given a base and an offset.
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//
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//
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:function:::address_word:loadstore_ea:address_word base, address_word offset
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:function:::address_word:loadstore_ea:address_word base, address_word offset
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*mipsI:
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*mipsI:
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*mipsII:
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*mipsII:
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*mipsIII:
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*mipsIII:
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*mipsIV:
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*mipsIV:
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*mipsV:
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*mipsV:
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*mips32:
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*mips32:
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*mips32r2:
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*mips32r2:
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*vr4100:
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*vr4100:
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*vr5000:
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*vr5000:
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*r3900:
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*r3900:
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{
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{
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return base + offset;
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return base + offset;
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}
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}
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:function:::address_word:loadstore_ea:address_word base, address_word offset
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:function:::address_word:loadstore_ea:address_word base, address_word offset
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*mips64:
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*mips64:
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*mips64r2:
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*mips64r2:
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{
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{
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#if 0 /* XXX FIXME: enable this only after some additional testing. */
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#if 0 /* XXX FIXME: enable this only after some additional testing. */
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/* If in user mode and UX is not set, use 32-bit compatibility effective
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/* If in user mode and UX is not set, use 32-bit compatibility effective
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address computations as defined in the MIPS64 Architecture for
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address computations as defined in the MIPS64 Architecture for
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Programmers Volume III, Revision 0.95, section 4.9. */
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Programmers Volume III, Revision 0.95, section 4.9. */
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if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX))
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if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX))
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== (ksu_user << status_KSU_shift))
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== (ksu_user << status_KSU_shift))
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return (address_word)((signed32)base + (signed32)offset);
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return (address_word)((signed32)base + (signed32)offset);
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#endif
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#endif
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return base + offset;
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return base + offset;
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}
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}
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// Helper:
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// Helper:
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//
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//
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// Check that a 32-bit register value is properly sign-extended.
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// Check that a 32-bit register value is properly sign-extended.
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// (See NotWordValue in ISA spec.)
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// (See NotWordValue in ISA spec.)
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//
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//
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:function:::int:not_word_value:unsigned_word value
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:function:::int:not_word_value:unsigned_word value
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*mipsI:
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*mipsI:
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*mipsII:
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*mipsII:
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*mipsIII:
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*mipsIII:
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*mipsIV:
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*mipsIV:
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*mipsV:
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*mipsV:
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*vr4100:
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*vr4100:
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*vr5000:
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*vr5000:
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*r3900:
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*r3900:
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*mips32:
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*mips32:
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*mips32r2:
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*mips32r2:
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*mips64:
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*mips64:
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*mips64r2:
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*mips64r2:
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{
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{
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#if WITH_TARGET_WORD_BITSIZE == 64
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#if WITH_TARGET_WORD_BITSIZE == 64
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return value != (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
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return value != (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
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#else
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#else
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return 0;
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return 0;
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#endif
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#endif
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}
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}
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// Helper:
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// Helper:
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//
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//
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// Handle UNPREDICTABLE operation behaviour. The goal here is to prevent
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// Handle UNPREDICTABLE operation behaviour. The goal here is to prevent
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// theoretically portable code which invokes non-portable behaviour from
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// theoretically portable code which invokes non-portable behaviour from
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// running with no indication of the portability issue.
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// running with no indication of the portability issue.
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// (See definition of UNPREDICTABLE in ISA spec.)
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// (See definition of UNPREDICTABLE in ISA spec.)
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//
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//
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:function:::void:unpredictable:
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:function:::void:unpredictable:
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*mipsI:
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*mipsI:
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*mipsII:
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*mipsII:
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*mipsIII:
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*mipsIII:
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*mipsIV:
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*mipsIV:
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*mipsV:
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*mipsV:
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*vr4100:
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*vr4100:
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*vr5000:
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*vr5000:
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*r3900:
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*r3900:
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{
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{
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}
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}
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:function:::void:unpredictable:
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:function:::void:unpredictable:
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*mips32:
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*mips32:
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*mips32r2:
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*mips32r2:
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*mips64:
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*mips64:
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*mips64r2:
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*mips64r2:
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{
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{
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unpredictable_action (CPU, CIA);
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unpredictable_action (CPU, CIA);
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}
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}
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// Helpers:
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// Helpers:
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//
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//
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// Check that an access to a HI/LO register meets timing requirements
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// Check that an access to a HI/LO register meets timing requirements
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//
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//
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// In all MIPS ISAs,
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// In all MIPS ISAs,
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//
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//
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// OP {HI and LO} followed by MT{LO or HI} (and not MT{HI or LO})
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// OP {HI and LO} followed by MT{LO or HI} (and not MT{HI or LO})
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// makes subsequent MF{HI or LO} UNPREDICTABLE. (1)
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// makes subsequent MF{HI or LO} UNPREDICTABLE. (1)
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//
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//
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// The following restrictions exist for MIPS I - MIPS III:
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// The following restrictions exist for MIPS I - MIPS III:
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//
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//
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// MF{HI or LO} followed by MT{HI or LO} w/ less than 2 instructions
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// MF{HI or LO} followed by MT{HI or LO} w/ less than 2 instructions
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// in between makes MF UNPREDICTABLE. (2)
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// in between makes MF UNPREDICTABLE. (2)
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//
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//
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// MF{HI or LO} followed by OP {HI and LO} w/ less than 2 instructions
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// MF{HI or LO} followed by OP {HI and LO} w/ less than 2 instructions
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// in between makes MF UNPREDICTABLE. (3)
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// in between makes MF UNPREDICTABLE. (3)
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//
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//
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// On the r3900, restriction (2) is not present, and restriction (3) is not
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// On the r3900, restriction (2) is not present, and restriction (3) is not
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// present for multiplication.
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// present for multiplication.
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//
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//
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// Unfortunately, there seems to be some confusion about whether the last
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// Unfortunately, there seems to be some confusion about whether the last
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// two restrictions should apply to "MIPS IV" as well. One edition of
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// two restrictions should apply to "MIPS IV" as well. One edition of
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// the MIPS IV ISA says they do, but references in later ISA documents
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// the MIPS IV ISA says they do, but references in later ISA documents
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// suggest they don't.
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// suggest they don't.
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//
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//
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// In reality, some MIPS IV parts, such as the VR5000 and VR5400, do have
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// In reality, some MIPS IV parts, such as the VR5000 and VR5400, do have
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// these restrictions, while others, like the VR5500, don't. To accomodate
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// these restrictions, while others, like the VR5500, don't. To accomodate
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// such differences, the MIPS IV and MIPS V version of these helper functions
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// such differences, the MIPS IV and MIPS V version of these helper functions
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// use auxillary routines to determine whether the restriction applies.
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// use auxillary routines to determine whether the restriction applies.
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// check_mf_cycles:
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// check_mf_cycles:
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//
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//
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// Helper used by check_mt_hilo, check_mult_hilo, and check_div_hilo
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// Helper used by check_mt_hilo, check_mult_hilo, and check_div_hilo
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// to check for restrictions (2) and (3) above.
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// to check for restrictions (2) and (3) above.
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//
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//
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:function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
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:function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
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{
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{
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if (history->mf.timestamp + 3 > time)
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if (history->mf.timestamp + 3 > time)
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{
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{
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sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
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sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
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itable[MY_INDEX].name,
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itable[MY_INDEX].name,
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new, (long) CIA,
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new, (long) CIA,
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(long) history->mf.cia);
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(long) history->mf.cia);
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return 0;
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return 0;
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}
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}
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return 1;
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return 1;
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}
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}
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|
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// check_mt_hilo:
|
// check_mt_hilo:
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//
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//
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// Check for restriction (2) above (for ISAs/processors that have it),
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// Check for restriction (2) above (for ISAs/processors that have it),
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// and record timestamps for restriction (1) above.
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// and record timestamps for restriction (1) above.
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//
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//
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:function:::int:check_mt_hilo:hilo_history *history
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:function:::int:check_mt_hilo:hilo_history *history
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*mipsI:
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*mipsI:
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*mipsII:
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*mipsII:
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*mipsIII:
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*mipsIII:
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*vr4100:
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*vr4100:
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*vr5000:
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*vr5000:
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{
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{
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signed64 time = sim_events_time (SD);
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signed64 time = sim_events_time (SD);
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int ok = check_mf_cycles (SD_, history, time, "MT");
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int ok = check_mf_cycles (SD_, history, time, "MT");
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history->mt.timestamp = time;
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history->mt.timestamp = time;
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history->mt.cia = CIA;
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history->mt.cia = CIA;
|
return ok;
|
return ok;
|
}
|
}
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|
|
:function:::int:check_mt_hilo:hilo_history *history
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:function:::int:check_mt_hilo:hilo_history *history
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*mipsIV:
|
*mipsIV:
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*mipsV:
|
*mipsV:
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{
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{
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signed64 time = sim_events_time (SD);
|
signed64 time = sim_events_time (SD);
|
int ok = (! MIPS_MACH_HAS_MT_HILO_HAZARD (SD)
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int ok = (! MIPS_MACH_HAS_MT_HILO_HAZARD (SD)
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|| check_mf_cycles (SD_, history, time, "MT"));
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|| check_mf_cycles (SD_, history, time, "MT"));
|
history->mt.timestamp = time;
|
history->mt.timestamp = time;
|
history->mt.cia = CIA;
|
history->mt.cia = CIA;
|
return ok;
|
return ok;
|
}
|
}
|
|
|
:function:::int:check_mt_hilo:hilo_history *history
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:function:::int:check_mt_hilo:hilo_history *history
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
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*mips64:
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*mips64r2:
|
*mips64r2:
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*r3900:
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*r3900:
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{
|
{
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signed64 time = sim_events_time (SD);
|
signed64 time = sim_events_time (SD);
|
history->mt.timestamp = time;
|
history->mt.timestamp = time;
|
history->mt.cia = CIA;
|
history->mt.cia = CIA;
|
return 1;
|
return 1;
|
}
|
}
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|
|
|
|
// check_mf_hilo:
|
// check_mf_hilo:
|
//
|
//
|
// Check for restriction (1) above, and record timestamps for
|
// Check for restriction (1) above, and record timestamps for
|
// restriction (2) and (3) above.
|
// restriction (2) and (3) above.
|
//
|
//
|
:function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
|
:function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
signed64 time = sim_events_time (SD);
|
signed64 time = sim_events_time (SD);
|
int ok = 1;
|
int ok = 1;
|
if (peer != NULL
|
if (peer != NULL
|
&& peer->mt.timestamp > history->op.timestamp
|
&& peer->mt.timestamp > history->op.timestamp
|
&& history->mt.timestamp < history->op.timestamp
|
&& history->mt.timestamp < history->op.timestamp
|
&& ! (history->mf.timestamp > history->op.timestamp
|
&& ! (history->mf.timestamp > history->op.timestamp
|
&& history->mf.timestamp < peer->mt.timestamp)
|
&& history->mf.timestamp < peer->mt.timestamp)
|
&& ! (peer->mf.timestamp > history->op.timestamp
|
&& ! (peer->mf.timestamp > history->op.timestamp
|
&& peer->mf.timestamp < peer->mt.timestamp))
|
&& peer->mf.timestamp < peer->mt.timestamp))
|
{
|
{
|
/* The peer has been written to since the last OP yet we have
|
/* The peer has been written to since the last OP yet we have
|
not */
|
not */
|
sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
|
sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
|
itable[MY_INDEX].name,
|
itable[MY_INDEX].name,
|
(long) CIA,
|
(long) CIA,
|
(long) history->op.cia,
|
(long) history->op.cia,
|
(long) peer->mt.cia);
|
(long) peer->mt.cia);
|
ok = 0;
|
ok = 0;
|
}
|
}
|
history->mf.timestamp = time;
|
history->mf.timestamp = time;
|
history->mf.cia = CIA;
|
history->mf.cia = CIA;
|
return ok;
|
return ok;
|
}
|
}
|
|
|
|
|
|
|
// check_mult_hilo:
|
// check_mult_hilo:
|
//
|
//
|
// Check for restriction (3) above (for ISAs/processors that have it)
|
// Check for restriction (3) above (for ISAs/processors that have it)
|
// for MULT ops, and record timestamps for restriction (1) above.
|
// for MULT ops, and record timestamps for restriction (1) above.
|
//
|
//
|
:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
|
:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
signed64 time = sim_events_time (SD);
|
signed64 time = sim_events_time (SD);
|
int ok = (check_mf_cycles (SD_, hi, time, "OP")
|
int ok = (check_mf_cycles (SD_, hi, time, "OP")
|
&& check_mf_cycles (SD_, lo, time, "OP"));
|
&& check_mf_cycles (SD_, lo, time, "OP"));
|
hi->op.timestamp = time;
|
hi->op.timestamp = time;
|
lo->op.timestamp = time;
|
lo->op.timestamp = time;
|
hi->op.cia = CIA;
|
hi->op.cia = CIA;
|
lo->op.cia = CIA;
|
lo->op.cia = CIA;
|
return ok;
|
return ok;
|
}
|
}
|
|
|
:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
|
:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
{
|
{
|
signed64 time = sim_events_time (SD);
|
signed64 time = sim_events_time (SD);
|
int ok = (! MIPS_MACH_HAS_MULT_HILO_HAZARD (SD)
|
int ok = (! MIPS_MACH_HAS_MULT_HILO_HAZARD (SD)
|
|| (check_mf_cycles (SD_, hi, time, "OP")
|
|| (check_mf_cycles (SD_, hi, time, "OP")
|
&& check_mf_cycles (SD_, lo, time, "OP")));
|
&& check_mf_cycles (SD_, lo, time, "OP")));
|
hi->op.timestamp = time;
|
hi->op.timestamp = time;
|
lo->op.timestamp = time;
|
lo->op.timestamp = time;
|
hi->op.cia = CIA;
|
hi->op.cia = CIA;
|
lo->op.cia = CIA;
|
lo->op.cia = CIA;
|
return ok;
|
return ok;
|
}
|
}
|
|
|
:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
|
:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*r3900:
|
*r3900:
|
{
|
{
|
/* FIXME: could record the fact that a stall occured if we want */
|
/* FIXME: could record the fact that a stall occured if we want */
|
signed64 time = sim_events_time (SD);
|
signed64 time = sim_events_time (SD);
|
hi->op.timestamp = time;
|
hi->op.timestamp = time;
|
lo->op.timestamp = time;
|
lo->op.timestamp = time;
|
hi->op.cia = CIA;
|
hi->op.cia = CIA;
|
lo->op.cia = CIA;
|
lo->op.cia = CIA;
|
return 1;
|
return 1;
|
}
|
}
|
|
|
|
|
// check_div_hilo:
|
// check_div_hilo:
|
//
|
//
|
// Check for restriction (3) above (for ISAs/processors that have it)
|
// Check for restriction (3) above (for ISAs/processors that have it)
|
// for DIV ops, and record timestamps for restriction (1) above.
|
// for DIV ops, and record timestamps for restriction (1) above.
|
//
|
//
|
:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
|
:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
signed64 time = sim_events_time (SD);
|
signed64 time = sim_events_time (SD);
|
int ok = (check_mf_cycles (SD_, hi, time, "OP")
|
int ok = (check_mf_cycles (SD_, hi, time, "OP")
|
&& check_mf_cycles (SD_, lo, time, "OP"));
|
&& check_mf_cycles (SD_, lo, time, "OP"));
|
hi->op.timestamp = time;
|
hi->op.timestamp = time;
|
lo->op.timestamp = time;
|
lo->op.timestamp = time;
|
hi->op.cia = CIA;
|
hi->op.cia = CIA;
|
lo->op.cia = CIA;
|
lo->op.cia = CIA;
|
return ok;
|
return ok;
|
}
|
}
|
|
|
:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
|
:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
{
|
{
|
signed64 time = sim_events_time (SD);
|
signed64 time = sim_events_time (SD);
|
int ok = (! MIPS_MACH_HAS_DIV_HILO_HAZARD (SD)
|
int ok = (! MIPS_MACH_HAS_DIV_HILO_HAZARD (SD)
|
|| (check_mf_cycles (SD_, hi, time, "OP")
|
|| (check_mf_cycles (SD_, hi, time, "OP")
|
&& check_mf_cycles (SD_, lo, time, "OP")));
|
&& check_mf_cycles (SD_, lo, time, "OP")));
|
hi->op.timestamp = time;
|
hi->op.timestamp = time;
|
lo->op.timestamp = time;
|
lo->op.timestamp = time;
|
hi->op.cia = CIA;
|
hi->op.cia = CIA;
|
lo->op.cia = CIA;
|
lo->op.cia = CIA;
|
return ok;
|
return ok;
|
}
|
}
|
|
|
:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
|
:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
{
|
{
|
signed64 time = sim_events_time (SD);
|
signed64 time = sim_events_time (SD);
|
hi->op.timestamp = time;
|
hi->op.timestamp = time;
|
lo->op.timestamp = time;
|
lo->op.timestamp = time;
|
hi->op.cia = CIA;
|
hi->op.cia = CIA;
|
lo->op.cia = CIA;
|
lo->op.cia = CIA;
|
return 1;
|
return 1;
|
}
|
}
|
|
|
|
|
// Helper:
|
// Helper:
|
//
|
//
|
// Check that the 64-bit instruction can currently be used, and signal
|
// Check that the 64-bit instruction can currently be used, and signal
|
// a ReservedInstruction exception if not.
|
// a ReservedInstruction exception if not.
|
//
|
//
|
|
|
:function:::void:check_u64:instruction_word insn
|
:function:::void:check_u64:instruction_word insn
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*vr5400:
|
*vr5400:
|
*vr5500:
|
*vr5500:
|
{
|
{
|
// The check should be similar to mips64 for any with PX/UX bit equivalents.
|
// The check should be similar to mips64 for any with PX/UX bit equivalents.
|
}
|
}
|
|
|
:function:::void:check_u64:instruction_word insn
|
:function:::void:check_u64:instruction_word insn
|
*mips16e:
|
*mips16e:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
{
|
{
|
#if 0 /* XXX FIXME: enable this only after some additional testing. */
|
#if 0 /* XXX FIXME: enable this only after some additional testing. */
|
if (UserMode && (SR & (status_UX|status_PX)) == 0)
|
if (UserMode && (SR & (status_UX|status_PX)) == 0)
|
SignalException (ReservedInstruction, insn);
|
SignalException (ReservedInstruction, insn);
|
#endif
|
#endif
|
}
|
}
|
|
|
|
|
|
|
//
|
//
|
// MIPS Architecture:
|
// MIPS Architecture:
|
//
|
//
|
// CPU Instruction Set (mipsI - mipsV, mips32/r2, mips64/r2)
|
// CPU Instruction Set (mipsI - mipsV, mips32/r2, mips64/r2)
|
//
|
//
|
|
|
|
|
|
|
000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
|
000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
|
"add r, r, r
|
"add r, r, r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
Unpredictable ();
|
Unpredictable ();
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
{
|
{
|
ALU32_BEGIN (GPR[RS]);
|
ALU32_BEGIN (GPR[RS]);
|
ALU32_ADD (GPR[RT]);
|
ALU32_ADD (GPR[RT]);
|
ALU32_END (GPR[RD]); /* This checks for overflow. */
|
ALU32_END (GPR[RD]); /* This checks for overflow. */
|
}
|
}
|
TRACE_ALU_RESULT (GPR[RD]);
|
TRACE_ALU_RESULT (GPR[RD]);
|
}
|
}
|
|
|
|
|
|
|
001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
|
001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
|
"addi r
|
"addi r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
if (NotWordValue (GPR[RS]))
|
if (NotWordValue (GPR[RS]))
|
Unpredictable ();
|
Unpredictable ();
|
TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
|
TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
|
{
|
{
|
ALU32_BEGIN (GPR[RS]);
|
ALU32_BEGIN (GPR[RS]);
|
ALU32_ADD (EXTEND16 (IMMEDIATE));
|
ALU32_ADD (EXTEND16 (IMMEDIATE));
|
ALU32_END (GPR[RT]); /* This checks for overflow. */
|
ALU32_END (GPR[RT]); /* This checks for overflow. */
|
}
|
}
|
TRACE_ALU_RESULT (GPR[RT]);
|
TRACE_ALU_RESULT (GPR[RT]);
|
}
|
}
|
|
|
|
|
|
|
:function:::void:do_addiu:int rs, int rt, unsigned16 immediate
|
:function:::void:do_addiu:int rs, int rt, unsigned16 immediate
|
{
|
{
|
if (NotWordValue (GPR[rs]))
|
if (NotWordValue (GPR[rs]))
|
Unpredictable ();
|
Unpredictable ();
|
TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
|
TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
|
GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
|
GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
|
TRACE_ALU_RESULT (GPR[rt]);
|
TRACE_ALU_RESULT (GPR[rt]);
|
}
|
}
|
|
|
001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
|
001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
|
"addiu r
|
"addiu r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
do_addiu (SD_, RS, RT, IMMEDIATE);
|
do_addiu (SD_, RS, RT, IMMEDIATE);
|
}
|
}
|
|
|
|
|
|
|
:function:::void:do_addu:int rs, int rt, int rd
|
:function:::void:do_addu:int rs, int rt, int rd
|
{
|
{
|
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
|
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
|
Unpredictable ();
|
Unpredictable ();
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
|
GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
|
TRACE_ALU_RESULT (GPR[rd]);
|
TRACE_ALU_RESULT (GPR[rd]);
|
}
|
}
|
|
|
000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
|
000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
|
"addu r, r, r
|
"addu r, r, r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
do_addu (SD_, RS, RT, RD);
|
do_addu (SD_, RS, RT, RD);
|
}
|
}
|
|
|
|
|
|
|
:function:::void:do_and:int rs, int rt, int rd
|
:function:::void:do_and:int rs, int rt, int rd
|
{
|
{
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
GPR[rd] = GPR[rs] & GPR[rt];
|
GPR[rd] = GPR[rs] & GPR[rt];
|
TRACE_ALU_RESULT (GPR[rd]);
|
TRACE_ALU_RESULT (GPR[rd]);
|
}
|
}
|
|
|
000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
|
000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
|
"and r, r, r
|
"and r, r, r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
do_and (SD_, RS, RT, RD);
|
do_and (SD_, RS, RT, RD);
|
}
|
}
|
|
|
|
|
|
|
001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
|
001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
|
"andi r
|
"andi r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
|
TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
|
GPR[RT] = GPR[RS] & IMMEDIATE;
|
GPR[RT] = GPR[RS] & IMMEDIATE;
|
TRACE_ALU_RESULT (GPR[RT]);
|
TRACE_ALU_RESULT (GPR[RT]);
|
}
|
}
|
|
|
|
|
|
|
000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
|
000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
|
"beq r, r
|
"beq r, r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
|
if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
|
{
|
{
|
DELAY_SLOT (NIA + offset);
|
DELAY_SLOT (NIA + offset);
|
}
|
}
|
}
|
}
|
|
|
|
|
|
|
010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
|
010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
|
"beql r, r
|
"beql r, r
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
|
if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
|
{
|
{
|
DELAY_SLOT (NIA + offset);
|
DELAY_SLOT (NIA + offset);
|
}
|
}
|
else
|
else
|
NULLIFY_NEXT_INSTRUCTION ();
|
NULLIFY_NEXT_INSTRUCTION ();
|
}
|
}
|
|
|
|
|
|
|
000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
|
000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
|
"bgez r, "
|
"bgez r, "
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
if ((signed_word) GPR[RS] >= 0)
|
if ((signed_word) GPR[RS] >= 0)
|
{
|
{
|
DELAY_SLOT (NIA + offset);
|
DELAY_SLOT (NIA + offset);
|
}
|
}
|
}
|
}
|
|
|
|
|
|
|
000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
|
000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
|
"bgezal r, "
|
"bgezal r, "
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
if (RS == 31)
|
if (RS == 31)
|
Unpredictable ();
|
Unpredictable ();
|
RA = (CIA + 8);
|
RA = (CIA + 8);
|
if ((signed_word) GPR[RS] >= 0)
|
if ((signed_word) GPR[RS] >= 0)
|
{
|
{
|
DELAY_SLOT (NIA + offset);
|
DELAY_SLOT (NIA + offset);
|
}
|
}
|
}
|
}
|
|
|
|
|
|
|
000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
|
000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
|
"bgezall r, "
|
"bgezall r, "
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
if (RS == 31)
|
if (RS == 31)
|
Unpredictable ();
|
Unpredictable ();
|
RA = (CIA + 8);
|
RA = (CIA + 8);
|
/* NOTE: The branch occurs AFTER the next instruction has been
|
/* NOTE: The branch occurs AFTER the next instruction has been
|
executed */
|
executed */
|
if ((signed_word) GPR[RS] >= 0)
|
if ((signed_word) GPR[RS] >= 0)
|
{
|
{
|
DELAY_SLOT (NIA + offset);
|
DELAY_SLOT (NIA + offset);
|
}
|
}
|
else
|
else
|
NULLIFY_NEXT_INSTRUCTION ();
|
NULLIFY_NEXT_INSTRUCTION ();
|
}
|
}
|
|
|
|
|
|
|
000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
|
000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
|
"bgezl r, "
|
"bgezl r, "
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
if ((signed_word) GPR[RS] >= 0)
|
if ((signed_word) GPR[RS] >= 0)
|
{
|
{
|
DELAY_SLOT (NIA + offset);
|
DELAY_SLOT (NIA + offset);
|
}
|
}
|
else
|
else
|
NULLIFY_NEXT_INSTRUCTION ();
|
NULLIFY_NEXT_INSTRUCTION ();
|
}
|
}
|
|
|
|
|
|
|
000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
|
000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
|
"bgtz r, "
|
"bgtz r, "
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
if ((signed_word) GPR[RS] > 0)
|
if ((signed_word) GPR[RS] > 0)
|
{
|
{
|
DELAY_SLOT (NIA + offset);
|
DELAY_SLOT (NIA + offset);
|
}
|
}
|
}
|
}
|
|
|
|
|
|
|
010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
|
010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
|
"bgtzl r, "
|
"bgtzl r, "
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
/* NOTE: The branch occurs AFTER the next instruction has been
|
/* NOTE: The branch occurs AFTER the next instruction has been
|
executed */
|
executed */
|
if ((signed_word) GPR[RS] > 0)
|
if ((signed_word) GPR[RS] > 0)
|
{
|
{
|
DELAY_SLOT (NIA + offset);
|
DELAY_SLOT (NIA + offset);
|
}
|
}
|
else
|
else
|
NULLIFY_NEXT_INSTRUCTION ();
|
NULLIFY_NEXT_INSTRUCTION ();
|
}
|
}
|
|
|
|
|
|
|
000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
|
000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
|
"blez r, "
|
"blez r, "
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
/* NOTE: The branch occurs AFTER the next instruction has been
|
/* NOTE: The branch occurs AFTER the next instruction has been
|
executed */
|
executed */
|
if ((signed_word) GPR[RS] <= 0)
|
if ((signed_word) GPR[RS] <= 0)
|
{
|
{
|
DELAY_SLOT (NIA + offset);
|
DELAY_SLOT (NIA + offset);
|
}
|
}
|
}
|
}
|
|
|
|
|
|
|
010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
|
010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
|
"bgezl r, "
|
"bgezl r, "
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
if ((signed_word) GPR[RS] <= 0)
|
if ((signed_word) GPR[RS] <= 0)
|
{
|
{
|
DELAY_SLOT (NIA + offset);
|
DELAY_SLOT (NIA + offset);
|
}
|
}
|
else
|
else
|
NULLIFY_NEXT_INSTRUCTION ();
|
NULLIFY_NEXT_INSTRUCTION ();
|
}
|
}
|
|
|
|
|
|
|
000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
|
000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
|
"bltz r, "
|
"bltz r, "
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
if ((signed_word) GPR[RS] < 0)
|
if ((signed_word) GPR[RS] < 0)
|
{
|
{
|
DELAY_SLOT (NIA + offset);
|
DELAY_SLOT (NIA + offset);
|
}
|
}
|
}
|
}
|
|
|
|
|
|
|
000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
|
000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
|
"bltzal r, "
|
"bltzal r, "
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
if (RS == 31)
|
if (RS == 31)
|
Unpredictable ();
|
Unpredictable ();
|
RA = (CIA + 8);
|
RA = (CIA + 8);
|
/* NOTE: The branch occurs AFTER the next instruction has been
|
/* NOTE: The branch occurs AFTER the next instruction has been
|
executed */
|
executed */
|
if ((signed_word) GPR[RS] < 0)
|
if ((signed_word) GPR[RS] < 0)
|
{
|
{
|
DELAY_SLOT (NIA + offset);
|
DELAY_SLOT (NIA + offset);
|
}
|
}
|
}
|
}
|
|
|
|
|
|
|
000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
|
000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
|
"bltzall r, "
|
"bltzall r, "
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
if (RS == 31)
|
if (RS == 31)
|
Unpredictable ();
|
Unpredictable ();
|
RA = (CIA + 8);
|
RA = (CIA + 8);
|
if ((signed_word) GPR[RS] < 0)
|
if ((signed_word) GPR[RS] < 0)
|
{
|
{
|
DELAY_SLOT (NIA + offset);
|
DELAY_SLOT (NIA + offset);
|
}
|
}
|
else
|
else
|
NULLIFY_NEXT_INSTRUCTION ();
|
NULLIFY_NEXT_INSTRUCTION ();
|
}
|
}
|
|
|
|
|
|
|
000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
|
000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
|
"bltzl r, "
|
"bltzl r, "
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
/* NOTE: The branch occurs AFTER the next instruction has been
|
/* NOTE: The branch occurs AFTER the next instruction has been
|
executed */
|
executed */
|
if ((signed_word) GPR[RS] < 0)
|
if ((signed_word) GPR[RS] < 0)
|
{
|
{
|
DELAY_SLOT (NIA + offset);
|
DELAY_SLOT (NIA + offset);
|
}
|
}
|
else
|
else
|
NULLIFY_NEXT_INSTRUCTION ();
|
NULLIFY_NEXT_INSTRUCTION ();
|
}
|
}
|
|
|
|
|
|
|
000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
|
000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
|
"bne r, r
|
"bne r, r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
|
if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
|
{
|
{
|
DELAY_SLOT (NIA + offset);
|
DELAY_SLOT (NIA + offset);
|
}
|
}
|
}
|
}
|
|
|
|
|
|
|
010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
|
010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
|
"bnel r, r
|
"bnel r, r
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
|
if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
|
{
|
{
|
DELAY_SLOT (NIA + offset);
|
DELAY_SLOT (NIA + offset);
|
}
|
}
|
else
|
else
|
NULLIFY_NEXT_INSTRUCTION ();
|
NULLIFY_NEXT_INSTRUCTION ();
|
}
|
}
|
|
|
|
|
|
|
000000,20.CODE,001101:SPECIAL:32::BREAK
|
000000,20.CODE,001101:SPECIAL:32::BREAK
|
"break %#lx"
|
"break %#lx"
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
/* Check for some break instruction which are reserved for use by the simulator. */
|
/* Check for some break instruction which are reserved for use by the simulator. */
|
unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
|
unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
|
if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
|
if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
|
break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
|
break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
|
{
|
{
|
sim_engine_halt (SD, CPU, NULL, cia,
|
sim_engine_halt (SD, CPU, NULL, cia,
|
sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
|
sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
|
}
|
}
|
else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
|
else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
|
break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
|
break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
|
{
|
{
|
if (STATE & simDELAYSLOT)
|
if (STATE & simDELAYSLOT)
|
PC = cia - 4; /* reference the branch instruction */
|
PC = cia - 4; /* reference the branch instruction */
|
else
|
else
|
PC = cia;
|
PC = cia;
|
SignalException (BreakPoint, instruction_0);
|
SignalException (BreakPoint, instruction_0);
|
}
|
}
|
|
|
else
|
else
|
{
|
{
|
/* If we get this far, we're not an instruction reserved by the sim. Raise
|
/* If we get this far, we're not an instruction reserved by the sim. Raise
|
the exception. */
|
the exception. */
|
SignalException (BreakPoint, instruction_0);
|
SignalException (BreakPoint, instruction_0);
|
}
|
}
|
}
|
}
|
|
|
|
|
|
|
011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO
|
011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO
|
"clo r, r"
|
"clo r, r"
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr5500:
|
*vr5500:
|
{
|
{
|
unsigned32 temp = GPR[RS];
|
unsigned32 temp = GPR[RS];
|
unsigned32 i, mask;
|
unsigned32 i, mask;
|
if (RT != RD)
|
if (RT != RD)
|
Unpredictable ();
|
Unpredictable ();
|
if (NotWordValue (GPR[RS]))
|
if (NotWordValue (GPR[RS]))
|
Unpredictable ();
|
Unpredictable ();
|
TRACE_ALU_INPUT1 (GPR[RS]);
|
TRACE_ALU_INPUT1 (GPR[RS]);
|
for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
|
for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
|
{
|
{
|
if ((temp & mask) == 0)
|
if ((temp & mask) == 0)
|
break;
|
break;
|
mask >>= 1;
|
mask >>= 1;
|
}
|
}
|
GPR[RD] = EXTEND32 (i);
|
GPR[RD] = EXTEND32 (i);
|
TRACE_ALU_RESULT (GPR[RD]);
|
TRACE_ALU_RESULT (GPR[RD]);
|
}
|
}
|
|
|
|
|
|
|
011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ
|
011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ
|
"clz r, r"
|
"clz r, r"
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr5500:
|
*vr5500:
|
{
|
{
|
unsigned32 temp = GPR[RS];
|
unsigned32 temp = GPR[RS];
|
unsigned32 i, mask;
|
unsigned32 i, mask;
|
if (RT != RD)
|
if (RT != RD)
|
Unpredictable ();
|
Unpredictable ();
|
if (NotWordValue (GPR[RS]))
|
if (NotWordValue (GPR[RS]))
|
Unpredictable ();
|
Unpredictable ();
|
TRACE_ALU_INPUT1 (GPR[RS]);
|
TRACE_ALU_INPUT1 (GPR[RS]);
|
for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
|
for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
|
{
|
{
|
if ((temp & mask) != 0)
|
if ((temp & mask) != 0)
|
break;
|
break;
|
mask >>= 1;
|
mask >>= 1;
|
}
|
}
|
GPR[RD] = EXTEND32 (i);
|
GPR[RD] = EXTEND32 (i);
|
TRACE_ALU_RESULT (GPR[RD]);
|
TRACE_ALU_RESULT (GPR[RD]);
|
}
|
}
|
|
|
|
|
|
|
000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
|
000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
|
"dadd r, r, r
|
"dadd r, r, r
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
{
|
{
|
ALU64_BEGIN (GPR[RS]);
|
ALU64_BEGIN (GPR[RS]);
|
ALU64_ADD (GPR[RT]);
|
ALU64_ADD (GPR[RT]);
|
ALU64_END (GPR[RD]); /* This checks for overflow. */
|
ALU64_END (GPR[RD]); /* This checks for overflow. */
|
}
|
}
|
TRACE_ALU_RESULT (GPR[RD]);
|
TRACE_ALU_RESULT (GPR[RD]);
|
}
|
}
|
|
|
|
|
|
|
011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
|
011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
|
"daddi r
|
"daddi r
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
|
TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
|
{
|
{
|
ALU64_BEGIN (GPR[RS]);
|
ALU64_BEGIN (GPR[RS]);
|
ALU64_ADD (EXTEND16 (IMMEDIATE));
|
ALU64_ADD (EXTEND16 (IMMEDIATE));
|
ALU64_END (GPR[RT]); /* This checks for overflow. */
|
ALU64_END (GPR[RT]); /* This checks for overflow. */
|
}
|
}
|
TRACE_ALU_RESULT (GPR[RT]);
|
TRACE_ALU_RESULT (GPR[RT]);
|
}
|
}
|
|
|
|
|
|
|
:function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
|
:function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
|
{
|
{
|
TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
|
TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
|
GPR[rt] = GPR[rs] + EXTEND16 (immediate);
|
GPR[rt] = GPR[rs] + EXTEND16 (immediate);
|
TRACE_ALU_RESULT (GPR[rt]);
|
TRACE_ALU_RESULT (GPR[rt]);
|
}
|
}
|
|
|
011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
|
011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
|
"daddiu r
|
"daddiu r
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
do_daddiu (SD_, RS, RT, IMMEDIATE);
|
do_daddiu (SD_, RS, RT, IMMEDIATE);
|
}
|
}
|
|
|
|
|
|
|
:function:::void:do_daddu:int rs, int rt, int rd
|
:function:::void:do_daddu:int rs, int rt, int rd
|
{
|
{
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
GPR[rd] = GPR[rs] + GPR[rt];
|
GPR[rd] = GPR[rs] + GPR[rt];
|
TRACE_ALU_RESULT (GPR[rd]);
|
TRACE_ALU_RESULT (GPR[rd]);
|
}
|
}
|
|
|
000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
|
000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
|
"daddu r, r, r
|
"daddu r, r, r
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
do_daddu (SD_, RS, RT, RD);
|
do_daddu (SD_, RS, RT, RD);
|
}
|
}
|
|
|
|
|
|
|
011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
|
011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
|
"dclo r, r"
|
"dclo r, r"
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr5500:
|
*vr5500:
|
{
|
{
|
unsigned64 temp = GPR[RS];
|
unsigned64 temp = GPR[RS];
|
unsigned32 i;
|
unsigned32 i;
|
unsigned64 mask;
|
unsigned64 mask;
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
if (RT != RD)
|
if (RT != RD)
|
Unpredictable ();
|
Unpredictable ();
|
TRACE_ALU_INPUT1 (GPR[RS]);
|
TRACE_ALU_INPUT1 (GPR[RS]);
|
for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
|
for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
|
{
|
{
|
if ((temp & mask) == 0)
|
if ((temp & mask) == 0)
|
break;
|
break;
|
mask >>= 1;
|
mask >>= 1;
|
}
|
}
|
GPR[RD] = EXTEND32 (i);
|
GPR[RD] = EXTEND32 (i);
|
TRACE_ALU_RESULT (GPR[RD]);
|
TRACE_ALU_RESULT (GPR[RD]);
|
}
|
}
|
|
|
|
|
|
|
011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
|
011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
|
"dclz r, r"
|
"dclz r, r"
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr5500:
|
*vr5500:
|
{
|
{
|
unsigned64 temp = GPR[RS];
|
unsigned64 temp = GPR[RS];
|
unsigned32 i;
|
unsigned32 i;
|
unsigned64 mask;
|
unsigned64 mask;
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
if (RT != RD)
|
if (RT != RD)
|
Unpredictable ();
|
Unpredictable ();
|
TRACE_ALU_INPUT1 (GPR[RS]);
|
TRACE_ALU_INPUT1 (GPR[RS]);
|
for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
|
for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
|
{
|
{
|
if ((temp & mask) != 0)
|
if ((temp & mask) != 0)
|
break;
|
break;
|
mask >>= 1;
|
mask >>= 1;
|
}
|
}
|
GPR[RD] = EXTEND32 (i);
|
GPR[RD] = EXTEND32 (i);
|
TRACE_ALU_RESULT (GPR[RD]);
|
TRACE_ALU_RESULT (GPR[RD]);
|
}
|
}
|
|
|
|
|
|
|
:function:::void:do_ddiv:int rs, int rt
|
:function:::void:do_ddiv:int rs, int rt
|
{
|
{
|
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
|
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
{
|
{
|
signed64 n = GPR[rs];
|
signed64 n = GPR[rs];
|
signed64 d = GPR[rt];
|
signed64 d = GPR[rt];
|
signed64 hi;
|
signed64 hi;
|
signed64 lo;
|
signed64 lo;
|
if (d == 0)
|
if (d == 0)
|
{
|
{
|
lo = SIGNED64 (0x8000000000000000);
|
lo = SIGNED64 (0x8000000000000000);
|
hi = 0;
|
hi = 0;
|
}
|
}
|
else if (d == -1 && n == SIGNED64 (0x8000000000000000))
|
else if (d == -1 && n == SIGNED64 (0x8000000000000000))
|
{
|
{
|
lo = SIGNED64 (0x8000000000000000);
|
lo = SIGNED64 (0x8000000000000000);
|
hi = 0;
|
hi = 0;
|
}
|
}
|
else
|
else
|
{
|
{
|
lo = (n / d);
|
lo = (n / d);
|
hi = (n % d);
|
hi = (n % d);
|
}
|
}
|
HI = hi;
|
HI = hi;
|
LO = lo;
|
LO = lo;
|
}
|
}
|
TRACE_ALU_RESULT2 (HI, LO);
|
TRACE_ALU_RESULT2 (HI, LO);
|
}
|
}
|
|
|
000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
|
000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
|
"ddiv r, r
|
"ddiv r, r
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
do_ddiv (SD_, RS, RT);
|
do_ddiv (SD_, RS, RT);
|
}
|
}
|
|
|
|
|
|
|
:function:::void:do_ddivu:int rs, int rt
|
:function:::void:do_ddivu:int rs, int rt
|
{
|
{
|
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
|
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
{
|
{
|
unsigned64 n = GPR[rs];
|
unsigned64 n = GPR[rs];
|
unsigned64 d = GPR[rt];
|
unsigned64 d = GPR[rt];
|
unsigned64 hi;
|
unsigned64 hi;
|
unsigned64 lo;
|
unsigned64 lo;
|
if (d == 0)
|
if (d == 0)
|
{
|
{
|
lo = SIGNED64 (0x8000000000000000);
|
lo = SIGNED64 (0x8000000000000000);
|
hi = 0;
|
hi = 0;
|
}
|
}
|
else
|
else
|
{
|
{
|
lo = (n / d);
|
lo = (n / d);
|
hi = (n % d);
|
hi = (n % d);
|
}
|
}
|
HI = hi;
|
HI = hi;
|
LO = lo;
|
LO = lo;
|
}
|
}
|
TRACE_ALU_RESULT2 (HI, LO);
|
TRACE_ALU_RESULT2 (HI, LO);
|
}
|
}
|
|
|
000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
|
000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
|
"ddivu r, r
|
"ddivu r, r
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
do_ddivu (SD_, RS, RT);
|
do_ddivu (SD_, RS, RT);
|
}
|
}
|
|
|
:function:::void:do_div:int rs, int rt
|
:function:::void:do_div:int rs, int rt
|
{
|
{
|
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
|
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
{
|
{
|
signed32 n = GPR[rs];
|
signed32 n = GPR[rs];
|
signed32 d = GPR[rt];
|
signed32 d = GPR[rt];
|
if (d == 0)
|
if (d == 0)
|
{
|
{
|
LO = EXTEND32 (0x80000000);
|
LO = EXTEND32 (0x80000000);
|
HI = EXTEND32 (0);
|
HI = EXTEND32 (0);
|
}
|
}
|
else if (n == SIGNED32 (0x80000000) && d == -1)
|
else if (n == SIGNED32 (0x80000000) && d == -1)
|
{
|
{
|
LO = EXTEND32 (0x80000000);
|
LO = EXTEND32 (0x80000000);
|
HI = EXTEND32 (0);
|
HI = EXTEND32 (0);
|
}
|
}
|
else
|
else
|
{
|
{
|
LO = EXTEND32 (n / d);
|
LO = EXTEND32 (n / d);
|
HI = EXTEND32 (n % d);
|
HI = EXTEND32 (n % d);
|
}
|
}
|
}
|
}
|
TRACE_ALU_RESULT2 (HI, LO);
|
TRACE_ALU_RESULT2 (HI, LO);
|
}
|
}
|
|
|
000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
|
000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
|
"div r, r
|
"div r, r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
do_div (SD_, RS, RT);
|
do_div (SD_, RS, RT);
|
}
|
}
|
|
|
|
|
|
|
:function:::void:do_divu:int rs, int rt
|
:function:::void:do_divu:int rs, int rt
|
{
|
{
|
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
|
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
{
|
{
|
unsigned32 n = GPR[rs];
|
unsigned32 n = GPR[rs];
|
unsigned32 d = GPR[rt];
|
unsigned32 d = GPR[rt];
|
if (d == 0)
|
if (d == 0)
|
{
|
{
|
LO = EXTEND32 (0x80000000);
|
LO = EXTEND32 (0x80000000);
|
HI = EXTEND32 (0);
|
HI = EXTEND32 (0);
|
}
|
}
|
else
|
else
|
{
|
{
|
LO = EXTEND32 (n / d);
|
LO = EXTEND32 (n / d);
|
HI = EXTEND32 (n % d);
|
HI = EXTEND32 (n % d);
|
}
|
}
|
}
|
}
|
TRACE_ALU_RESULT2 (HI, LO);
|
TRACE_ALU_RESULT2 (HI, LO);
|
}
|
}
|
|
|
000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
|
000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
|
"divu r, r
|
"divu r, r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
do_divu (SD_, RS, RT);
|
do_divu (SD_, RS, RT);
|
}
|
}
|
|
|
|
|
:function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
|
:function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
|
{
|
{
|
unsigned64 lo;
|
unsigned64 lo;
|
unsigned64 hi;
|
unsigned64 hi;
|
unsigned64 m00;
|
unsigned64 m00;
|
unsigned64 m01;
|
unsigned64 m01;
|
unsigned64 m10;
|
unsigned64 m10;
|
unsigned64 m11;
|
unsigned64 m11;
|
unsigned64 mid;
|
unsigned64 mid;
|
int sign;
|
int sign;
|
unsigned64 op1 = GPR[rs];
|
unsigned64 op1 = GPR[rs];
|
unsigned64 op2 = GPR[rt];
|
unsigned64 op2 = GPR[rt];
|
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
/* make signed multiply unsigned */
|
/* make signed multiply unsigned */
|
sign = 0;
|
sign = 0;
|
if (signed_p)
|
if (signed_p)
|
{
|
{
|
if ((signed64) op1 < 0)
|
if ((signed64) op1 < 0)
|
{
|
{
|
op1 = - op1;
|
op1 = - op1;
|
++sign;
|
++sign;
|
}
|
}
|
if ((signed64) op2 < 0)
|
if ((signed64) op2 < 0)
|
{
|
{
|
op2 = - op2;
|
op2 = - op2;
|
++sign;
|
++sign;
|
}
|
}
|
}
|
}
|
/* multiply out the 4 sub products */
|
/* multiply out the 4 sub products */
|
m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
|
m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
|
m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
|
m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
|
m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
|
m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
|
m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
|
m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
|
/* add the products */
|
/* add the products */
|
mid = ((unsigned64) VH4_8 (m00)
|
mid = ((unsigned64) VH4_8 (m00)
|
+ (unsigned64) VL4_8 (m10)
|
+ (unsigned64) VL4_8 (m10)
|
+ (unsigned64) VL4_8 (m01));
|
+ (unsigned64) VL4_8 (m01));
|
lo = U8_4 (mid, m00);
|
lo = U8_4 (mid, m00);
|
hi = (m11
|
hi = (m11
|
+ (unsigned64) VH4_8 (mid)
|
+ (unsigned64) VH4_8 (mid)
|
+ (unsigned64) VH4_8 (m01)
|
+ (unsigned64) VH4_8 (m01)
|
+ (unsigned64) VH4_8 (m10));
|
+ (unsigned64) VH4_8 (m10));
|
/* fix the sign */
|
/* fix the sign */
|
if (sign & 1)
|
if (sign & 1)
|
{
|
{
|
lo = -lo;
|
lo = -lo;
|
if (lo == 0)
|
if (lo == 0)
|
hi = -hi;
|
hi = -hi;
|
else
|
else
|
hi = -hi - 1;
|
hi = -hi - 1;
|
}
|
}
|
/* save the result HI/LO (and a gpr) */
|
/* save the result HI/LO (and a gpr) */
|
LO = lo;
|
LO = lo;
|
HI = hi;
|
HI = hi;
|
if (rd != 0)
|
if (rd != 0)
|
GPR[rd] = lo;
|
GPR[rd] = lo;
|
TRACE_ALU_RESULT2 (HI, LO);
|
TRACE_ALU_RESULT2 (HI, LO);
|
}
|
}
|
|
|
:function:::void:do_dmult:int rs, int rt, int rd
|
:function:::void:do_dmult:int rs, int rt, int rd
|
{
|
{
|
do_dmultx (SD_, rs, rt, rd, 1);
|
do_dmultx (SD_, rs, rt, rd, 1);
|
}
|
}
|
|
|
000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
|
000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
|
"dmult r, r
|
"dmult r, r
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
do_dmult (SD_, RS, RT, 0);
|
do_dmult (SD_, RS, RT, 0);
|
}
|
}
|
|
|
000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
|
000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
|
"dmult r, r
|
"dmult r, r
|
"dmult r, r, r
|
"dmult r, r, r
|
*vr5000:
|
*vr5000:
|
{
|
{
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
do_dmult (SD_, RS, RT, RD);
|
do_dmult (SD_, RS, RT, RD);
|
}
|
}
|
|
|
|
|
|
|
:function:::void:do_dmultu:int rs, int rt, int rd
|
:function:::void:do_dmultu:int rs, int rt, int rd
|
{
|
{
|
do_dmultx (SD_, rs, rt, rd, 0);
|
do_dmultx (SD_, rs, rt, rd, 0);
|
}
|
}
|
|
|
000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
|
000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
|
"dmultu r, r
|
"dmultu r, r
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
do_dmultu (SD_, RS, RT, 0);
|
do_dmultu (SD_, RS, RT, 0);
|
}
|
}
|
|
|
000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
|
000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
|
"dmultu r, r, r
|
"dmultu r, r, r
|
"dmultu r, r
|
"dmultu r, r
|
*vr5000:
|
*vr5000:
|
{
|
{
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
do_dmultu (SD_, RS, RT, RD);
|
do_dmultu (SD_, RS, RT, RD);
|
}
|
}
|
|
|
|
|
:function:::unsigned64:do_dror:unsigned64 x,unsigned64 y
|
:function:::unsigned64:do_dror:unsigned64 x,unsigned64 y
|
{
|
{
|
unsigned64 result;
|
unsigned64 result;
|
|
|
y &= 63;
|
y &= 63;
|
TRACE_ALU_INPUT2 (x, y);
|
TRACE_ALU_INPUT2 (x, y);
|
result = ROTR64 (x, y);
|
result = ROTR64 (x, y);
|
TRACE_ALU_RESULT (result);
|
TRACE_ALU_RESULT (result);
|
return result;
|
return result;
|
}
|
}
|
|
|
000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR
|
000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR
|
"dror r, r
|
"dror r, r
|
*mips64r2:
|
*mips64r2:
|
*vr5400:
|
*vr5400:
|
*vr5500:
|
*vr5500:
|
{
|
{
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
GPR[RD] = do_dror (SD_, GPR[RT], SHIFT);
|
GPR[RD] = do_dror (SD_, GPR[RT], SHIFT);
|
}
|
}
|
|
|
000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32
|
000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32
|
"dror32 r, r
|
"dror32 r, r
|
*mips64r2:
|
*mips64r2:
|
*vr5400:
|
*vr5400:
|
*vr5500:
|
*vr5500:
|
{
|
{
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
GPR[RD] = do_dror (SD_, GPR[RT], SHIFT + 32);
|
GPR[RD] = do_dror (SD_, GPR[RT], SHIFT + 32);
|
}
|
}
|
|
|
000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV
|
000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV
|
"drorv r, r
|
"drorv r, r
|
*mips64r2:
|
*mips64r2:
|
*vr5400:
|
*vr5400:
|
*vr5500:
|
*vr5500:
|
{
|
{
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]);
|
GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]);
|
}
|
}
|
|
|
|
|
:function:::void:do_dsll:int rt, int rd, int shift
|
:function:::void:do_dsll:int rt, int rd, int shift
|
{
|
{
|
TRACE_ALU_INPUT2 (GPR[rt], shift);
|
TRACE_ALU_INPUT2 (GPR[rt], shift);
|
GPR[rd] = GPR[rt] << shift;
|
GPR[rd] = GPR[rt] << shift;
|
TRACE_ALU_RESULT (GPR[rd]);
|
TRACE_ALU_RESULT (GPR[rd]);
|
}
|
}
|
|
|
000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
|
000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
|
"dsll r, r
|
"dsll r, r
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
do_dsll (SD_, RT, RD, SHIFT);
|
do_dsll (SD_, RT, RD, SHIFT);
|
}
|
}
|
|
|
|
|
000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
|
000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
|
"dsll32 r, r
|
"dsll32 r, r
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
int s = 32 + SHIFT;
|
int s = 32 + SHIFT;
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
TRACE_ALU_INPUT2 (GPR[RT], s);
|
TRACE_ALU_INPUT2 (GPR[RT], s);
|
GPR[RD] = GPR[RT] << s;
|
GPR[RD] = GPR[RT] << s;
|
TRACE_ALU_RESULT (GPR[RD]);
|
TRACE_ALU_RESULT (GPR[RD]);
|
}
|
}
|
|
|
:function:::void:do_dsllv:int rs, int rt, int rd
|
:function:::void:do_dsllv:int rs, int rt, int rd
|
{
|
{
|
int s = MASKED64 (GPR[rs], 5, 0);
|
int s = MASKED64 (GPR[rs], 5, 0);
|
TRACE_ALU_INPUT2 (GPR[rt], s);
|
TRACE_ALU_INPUT2 (GPR[rt], s);
|
GPR[rd] = GPR[rt] << s;
|
GPR[rd] = GPR[rt] << s;
|
TRACE_ALU_RESULT (GPR[rd]);
|
TRACE_ALU_RESULT (GPR[rd]);
|
}
|
}
|
|
|
000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
|
000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
|
"dsllv r, r
|
"dsllv r, r
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
do_dsllv (SD_, RS, RT, RD);
|
do_dsllv (SD_, RS, RT, RD);
|
}
|
}
|
|
|
:function:::void:do_dsra:int rt, int rd, int shift
|
:function:::void:do_dsra:int rt, int rd, int shift
|
{
|
{
|
TRACE_ALU_INPUT2 (GPR[rt], shift);
|
TRACE_ALU_INPUT2 (GPR[rt], shift);
|
GPR[rd] = ((signed64) GPR[rt]) >> shift;
|
GPR[rd] = ((signed64) GPR[rt]) >> shift;
|
TRACE_ALU_RESULT (GPR[rd]);
|
TRACE_ALU_RESULT (GPR[rd]);
|
}
|
}
|
|
|
|
|
000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
|
000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
|
"dsra r, r
|
"dsra r, r
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
do_dsra (SD_, RT, RD, SHIFT);
|
do_dsra (SD_, RT, RD, SHIFT);
|
}
|
}
|
|
|
|
|
000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
|
000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
|
"dsra32 r, r
|
"dsra32 r, r
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
int s = 32 + SHIFT;
|
int s = 32 + SHIFT;
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
TRACE_ALU_INPUT2 (GPR[RT], s);
|
TRACE_ALU_INPUT2 (GPR[RT], s);
|
GPR[RD] = ((signed64) GPR[RT]) >> s;
|
GPR[RD] = ((signed64) GPR[RT]) >> s;
|
TRACE_ALU_RESULT (GPR[RD]);
|
TRACE_ALU_RESULT (GPR[RD]);
|
}
|
}
|
|
|
|
|
:function:::void:do_dsrav:int rs, int rt, int rd
|
:function:::void:do_dsrav:int rs, int rt, int rd
|
{
|
{
|
int s = MASKED64 (GPR[rs], 5, 0);
|
int s = MASKED64 (GPR[rs], 5, 0);
|
TRACE_ALU_INPUT2 (GPR[rt], s);
|
TRACE_ALU_INPUT2 (GPR[rt], s);
|
GPR[rd] = ((signed64) GPR[rt]) >> s;
|
GPR[rd] = ((signed64) GPR[rt]) >> s;
|
TRACE_ALU_RESULT (GPR[rd]);
|
TRACE_ALU_RESULT (GPR[rd]);
|
}
|
}
|
|
|
000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
|
000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
|
"dsrav r, r
|
"dsrav r, r
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
do_dsrav (SD_, RS, RT, RD);
|
do_dsrav (SD_, RS, RT, RD);
|
}
|
}
|
|
|
:function:::void:do_dsrl:int rt, int rd, int shift
|
:function:::void:do_dsrl:int rt, int rd, int shift
|
{
|
{
|
TRACE_ALU_INPUT2 (GPR[rt], shift);
|
TRACE_ALU_INPUT2 (GPR[rt], shift);
|
GPR[rd] = (unsigned64) GPR[rt] >> shift;
|
GPR[rd] = (unsigned64) GPR[rt] >> shift;
|
TRACE_ALU_RESULT (GPR[rd]);
|
TRACE_ALU_RESULT (GPR[rd]);
|
}
|
}
|
|
|
|
|
000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
|
000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
|
"dsrl r, r
|
"dsrl r, r
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
do_dsrl (SD_, RT, RD, SHIFT);
|
do_dsrl (SD_, RT, RD, SHIFT);
|
}
|
}
|
|
|
|
|
000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
|
000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
|
"dsrl32 r, r
|
"dsrl32 r, r
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
int s = 32 + SHIFT;
|
int s = 32 + SHIFT;
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
TRACE_ALU_INPUT2 (GPR[RT], s);
|
TRACE_ALU_INPUT2 (GPR[RT], s);
|
GPR[RD] = (unsigned64) GPR[RT] >> s;
|
GPR[RD] = (unsigned64) GPR[RT] >> s;
|
TRACE_ALU_RESULT (GPR[RD]);
|
TRACE_ALU_RESULT (GPR[RD]);
|
}
|
}
|
|
|
|
|
:function:::void:do_dsrlv:int rs, int rt, int rd
|
:function:::void:do_dsrlv:int rs, int rt, int rd
|
{
|
{
|
int s = MASKED64 (GPR[rs], 5, 0);
|
int s = MASKED64 (GPR[rs], 5, 0);
|
TRACE_ALU_INPUT2 (GPR[rt], s);
|
TRACE_ALU_INPUT2 (GPR[rt], s);
|
GPR[rd] = (unsigned64) GPR[rt] >> s;
|
GPR[rd] = (unsigned64) GPR[rt] >> s;
|
TRACE_ALU_RESULT (GPR[rd]);
|
TRACE_ALU_RESULT (GPR[rd]);
|
}
|
}
|
|
|
|
|
|
|
000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
|
000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
|
"dsrlv r, r
|
"dsrlv r, r
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
do_dsrlv (SD_, RS, RT, RD);
|
do_dsrlv (SD_, RS, RT, RD);
|
}
|
}
|
|
|
|
|
000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
|
000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
|
"dsub r, r, r
|
"dsub r, r, r
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
{
|
{
|
ALU64_BEGIN (GPR[RS]);
|
ALU64_BEGIN (GPR[RS]);
|
ALU64_SUB (GPR[RT]);
|
ALU64_SUB (GPR[RT]);
|
ALU64_END (GPR[RD]); /* This checks for overflow. */
|
ALU64_END (GPR[RD]); /* This checks for overflow. */
|
}
|
}
|
TRACE_ALU_RESULT (GPR[RD]);
|
TRACE_ALU_RESULT (GPR[RD]);
|
}
|
}
|
|
|
|
|
:function:::void:do_dsubu:int rs, int rt, int rd
|
:function:::void:do_dsubu:int rs, int rt, int rd
|
{
|
{
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
GPR[rd] = GPR[rs] - GPR[rt];
|
GPR[rd] = GPR[rs] - GPR[rt];
|
TRACE_ALU_RESULT (GPR[rd]);
|
TRACE_ALU_RESULT (GPR[rd]);
|
}
|
}
|
|
|
000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
|
000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
|
"dsubu r, r, r
|
"dsubu r, r, r
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
do_dsubu (SD_, RS, RT, RD);
|
do_dsubu (SD_, RS, RT, RD);
|
}
|
}
|
|
|
|
|
000010,26.INSTR_INDEX:NORMAL:32::J
|
000010,26.INSTR_INDEX:NORMAL:32::J
|
"j "
|
"j "
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
/* NOTE: The region used is that of the delay slot NIA and NOT the
|
/* NOTE: The region used is that of the delay slot NIA and NOT the
|
current instruction */
|
current instruction */
|
address_word region = (NIA & MASK (63, 28));
|
address_word region = (NIA & MASK (63, 28));
|
DELAY_SLOT (region | (INSTR_INDEX << 2));
|
DELAY_SLOT (region | (INSTR_INDEX << 2));
|
}
|
}
|
|
|
|
|
000011,26.INSTR_INDEX:NORMAL:32::JAL
|
000011,26.INSTR_INDEX:NORMAL:32::JAL
|
"jal "
|
"jal "
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
/* NOTE: The region used is that of the delay slot and NOT the
|
/* NOTE: The region used is that of the delay slot and NOT the
|
current instruction */
|
current instruction */
|
address_word region = (NIA & MASK (63, 28));
|
address_word region = (NIA & MASK (63, 28));
|
GPR[31] = CIA + 8;
|
GPR[31] = CIA + 8;
|
DELAY_SLOT (region | (INSTR_INDEX << 2));
|
DELAY_SLOT (region | (INSTR_INDEX << 2));
|
}
|
}
|
|
|
000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
|
000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
|
"jalr r":RD == 31
|
"jalr r":RD == 31
|
"jalr r, r"
|
"jalr r, r"
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
address_word temp = GPR[RS];
|
address_word temp = GPR[RS];
|
GPR[RD] = CIA + 8;
|
GPR[RD] = CIA + 8;
|
DELAY_SLOT (temp);
|
DELAY_SLOT (temp);
|
}
|
}
|
|
|
000000,5.RS,00000,5.RD,10000,001001:SPECIAL:32::JALR_HB
|
000000,5.RS,00000,5.RD,10000,001001:SPECIAL:32::JALR_HB
|
"jalr.hb r":RD == 31
|
"jalr.hb r":RD == 31
|
"jalr.hb r, r"
|
"jalr.hb r, r"
|
*mips32r2:
|
*mips32r2:
|
*mips64r2:
|
*mips64r2:
|
{
|
{
|
address_word temp = GPR[RS];
|
address_word temp = GPR[RS];
|
GPR[RD] = CIA + 8;
|
GPR[RD] = CIA + 8;
|
DELAY_SLOT (temp);
|
DELAY_SLOT (temp);
|
}
|
}
|
|
|
000000,5.RS,0000000000,00000,001000:SPECIAL:32::JR
|
000000,5.RS,0000000000,00000,001000:SPECIAL:32::JR
|
"jr r"
|
"jr r"
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
DELAY_SLOT (GPR[RS]);
|
DELAY_SLOT (GPR[RS]);
|
}
|
}
|
|
|
000000,5.RS,0000000000,10000,001000:SPECIAL:32::JR_HB
|
000000,5.RS,0000000000,10000,001000:SPECIAL:32::JR_HB
|
"jr.hb r"
|
"jr.hb r"
|
*mips32r2:
|
*mips32r2:
|
*mips64r2:
|
*mips64r2:
|
{
|
{
|
DELAY_SLOT (GPR[RS]);
|
DELAY_SLOT (GPR[RS]);
|
}
|
}
|
|
|
:function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
|
:function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
|
{
|
{
|
address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
|
address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
|
address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
|
address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
|
address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
|
address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
|
unsigned int byte;
|
unsigned int byte;
|
address_word paddr;
|
address_word paddr;
|
int uncached;
|
int uncached;
|
unsigned64 memval;
|
unsigned64 memval;
|
address_word vaddr;
|
address_word vaddr;
|
|
|
vaddr = loadstore_ea (SD_, base, offset);
|
vaddr = loadstore_ea (SD_, base, offset);
|
if ((vaddr & access) != 0)
|
if ((vaddr & access) != 0)
|
{
|
{
|
SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
|
SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
|
}
|
}
|
AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
|
AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
|
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
|
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
|
LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
|
LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
|
byte = ((vaddr & mask) ^ bigendiancpu);
|
byte = ((vaddr & mask) ^ bigendiancpu);
|
return (memval >> (8 * byte));
|
return (memval >> (8 * byte));
|
}
|
}
|
|
|
:function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
|
:function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
|
{
|
{
|
address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
|
address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
|
address_word reverseendian = (ReverseEndian ? -1 : 0);
|
address_word reverseendian = (ReverseEndian ? -1 : 0);
|
address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
|
address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
|
unsigned int byte;
|
unsigned int byte;
|
unsigned int word;
|
unsigned int word;
|
address_word paddr;
|
address_word paddr;
|
int uncached;
|
int uncached;
|
unsigned64 memval;
|
unsigned64 memval;
|
address_word vaddr;
|
address_word vaddr;
|
int nr_lhs_bits;
|
int nr_lhs_bits;
|
int nr_rhs_bits;
|
int nr_rhs_bits;
|
unsigned_word lhs_mask;
|
unsigned_word lhs_mask;
|
unsigned_word temp;
|
unsigned_word temp;
|
|
|
vaddr = loadstore_ea (SD_, base, offset);
|
vaddr = loadstore_ea (SD_, base, offset);
|
AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
|
AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
|
paddr = (paddr ^ (reverseendian & mask));
|
paddr = (paddr ^ (reverseendian & mask));
|
if (BigEndianMem == 0)
|
if (BigEndianMem == 0)
|
paddr = paddr & ~access;
|
paddr = paddr & ~access;
|
|
|
/* compute where within the word/mem we are */
|
/* compute where within the word/mem we are */
|
byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
|
byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
|
word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
|
word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
|
nr_lhs_bits = 8 * byte + 8;
|
nr_lhs_bits = 8 * byte + 8;
|
nr_rhs_bits = 8 * access - 8 * byte;
|
nr_rhs_bits = 8 * access - 8 * byte;
|
/* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
|
/* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
|
|
|
/* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
|
/* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
|
(long) ((unsigned64) vaddr >> 32), (long) vaddr,
|
(long) ((unsigned64) vaddr >> 32), (long) vaddr,
|
(long) ((unsigned64) paddr >> 32), (long) paddr,
|
(long) ((unsigned64) paddr >> 32), (long) paddr,
|
word, byte, nr_lhs_bits, nr_rhs_bits); */
|
word, byte, nr_lhs_bits, nr_rhs_bits); */
|
|
|
LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
|
LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
|
if (word == 0)
|
if (word == 0)
|
{
|
{
|
/* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
|
/* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
|
temp = (memval << nr_rhs_bits);
|
temp = (memval << nr_rhs_bits);
|
}
|
}
|
else
|
else
|
{
|
{
|
/* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
|
/* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
|
temp = (memval >> nr_lhs_bits);
|
temp = (memval >> nr_lhs_bits);
|
}
|
}
|
lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
|
lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
|
rt = (rt & ~lhs_mask) | (temp & lhs_mask);
|
rt = (rt & ~lhs_mask) | (temp & lhs_mask);
|
|
|
/* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
|
/* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
|
(long) ((unsigned64) memval >> 32), (long) memval,
|
(long) ((unsigned64) memval >> 32), (long) memval,
|
(long) ((unsigned64) temp >> 32), (long) temp,
|
(long) ((unsigned64) temp >> 32), (long) temp,
|
(long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
|
(long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
|
(long) (rt >> 32), (long) rt); */
|
(long) (rt >> 32), (long) rt); */
|
return rt;
|
return rt;
|
}
|
}
|
|
|
:function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
|
:function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
|
{
|
{
|
address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
|
address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
|
address_word reverseendian = (ReverseEndian ? -1 : 0);
|
address_word reverseendian = (ReverseEndian ? -1 : 0);
|
address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
|
address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
|
unsigned int byte;
|
unsigned int byte;
|
address_word paddr;
|
address_word paddr;
|
int uncached;
|
int uncached;
|
unsigned64 memval;
|
unsigned64 memval;
|
address_word vaddr;
|
address_word vaddr;
|
|
|
vaddr = loadstore_ea (SD_, base, offset);
|
vaddr = loadstore_ea (SD_, base, offset);
|
AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
|
AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
|
/* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
|
/* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
|
paddr = (paddr ^ (reverseendian & mask));
|
paddr = (paddr ^ (reverseendian & mask));
|
if (BigEndianMem != 0)
|
if (BigEndianMem != 0)
|
paddr = paddr & ~access;
|
paddr = paddr & ~access;
|
byte = ((vaddr & mask) ^ (bigendiancpu & mask));
|
byte = ((vaddr & mask) ^ (bigendiancpu & mask));
|
/* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
|
/* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
|
LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
|
LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
|
/* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
|
/* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
|
(long) paddr, byte, (long) paddr, (long) memval); */
|
(long) paddr, byte, (long) paddr, (long) memval); */
|
{
|
{
|
unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
|
unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
|
rt &= ~screen;
|
rt &= ~screen;
|
rt |= (memval >> (8 * byte)) & screen;
|
rt |= (memval >> (8 * byte)) & screen;
|
}
|
}
|
return rt;
|
return rt;
|
}
|
}
|
|
|
|
|
100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
|
100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
|
"lb r
|
"lb r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
|
GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
|
}
|
}
|
|
|
|
|
100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
|
100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
|
"lbu r
|
"lbu r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
|
GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
|
}
|
}
|
|
|
|
|
110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
|
110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
|
"ld r
|
"ld r
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
|
GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
|
}
|
}
|
|
|
|
|
1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
|
1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
|
"ldc r
|
"ldc r
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
|
COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
|
}
|
}
|
|
|
|
|
|
|
|
|
011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
|
011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
|
"ldl r
|
"ldl r
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
|
GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
|
}
|
}
|
|
|
|
|
011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
|
011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
|
"ldr r
|
"ldr r
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
|
GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
|
}
|
}
|
|
|
|
|
100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
|
100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
|
"lh r
|
"lh r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
|
GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
|
}
|
}
|
|
|
|
|
100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
|
100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
|
"lhu r
|
"lhu r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
|
GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
|
}
|
}
|
|
|
|
|
110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
|
110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
|
"ll r
|
"ll r
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
address_word base = GPR[BASE];
|
address_word base = GPR[BASE];
|
address_word offset = EXTEND16 (OFFSET);
|
address_word offset = EXTEND16 (OFFSET);
|
{
|
{
|
address_word vaddr = loadstore_ea (SD_, base, offset);
|
address_word vaddr = loadstore_ea (SD_, base, offset);
|
address_word paddr;
|
address_word paddr;
|
int uncached;
|
int uncached;
|
if ((vaddr & 3) != 0)
|
if ((vaddr & 3) != 0)
|
{
|
{
|
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
|
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
|
}
|
}
|
else
|
else
|
{
|
{
|
if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
|
if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
|
{
|
{
|
unsigned64 memval = 0;
|
unsigned64 memval = 0;
|
unsigned64 memval1 = 0;
|
unsigned64 memval1 = 0;
|
unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
|
unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
|
unsigned int shift = 2;
|
unsigned int shift = 2;
|
unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
|
unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
|
unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
|
unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
|
unsigned int byte;
|
unsigned int byte;
|
paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
|
paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
|
LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
|
LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
|
byte = ((vaddr & mask) ^ (bigend << shift));
|
byte = ((vaddr & mask) ^ (bigend << shift));
|
GPR[RT] = EXTEND32 (memval >> (8 * byte));
|
GPR[RT] = EXTEND32 (memval >> (8 * byte));
|
LLBIT = 1;
|
LLBIT = 1;
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
|
|
110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
|
110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
|
"lld r
|
"lld r
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
address_word base = GPR[BASE];
|
address_word base = GPR[BASE];
|
address_word offset = EXTEND16 (OFFSET);
|
address_word offset = EXTEND16 (OFFSET);
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
{
|
{
|
address_word vaddr = loadstore_ea (SD_, base, offset);
|
address_word vaddr = loadstore_ea (SD_, base, offset);
|
address_word paddr;
|
address_word paddr;
|
int uncached;
|
int uncached;
|
if ((vaddr & 7) != 0)
|
if ((vaddr & 7) != 0)
|
{
|
{
|
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
|
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
|
}
|
}
|
else
|
else
|
{
|
{
|
if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
|
if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
|
{
|
{
|
unsigned64 memval = 0;
|
unsigned64 memval = 0;
|
unsigned64 memval1 = 0;
|
unsigned64 memval1 = 0;
|
LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
|
LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
|
GPR[RT] = memval;
|
GPR[RT] = memval;
|
LLBIT = 1;
|
LLBIT = 1;
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
|
|
001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
|
001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
|
"lui r
|
"lui r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
TRACE_ALU_INPUT1 (IMMEDIATE);
|
TRACE_ALU_INPUT1 (IMMEDIATE);
|
GPR[RT] = EXTEND32 (IMMEDIATE << 16);
|
GPR[RT] = EXTEND32 (IMMEDIATE << 16);
|
TRACE_ALU_RESULT (GPR[RT]);
|
TRACE_ALU_RESULT (GPR[RT]);
|
}
|
}
|
|
|
|
|
100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
|
100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
|
"lw r
|
"lw r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
|
GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
|
}
|
}
|
|
|
|
|
1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
|
1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
|
"lwc r
|
"lwc r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
|
COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
|
}
|
}
|
|
|
|
|
100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
|
100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
|
"lwl r
|
"lwl r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
|
GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
|
}
|
}
|
|
|
|
|
100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
|
100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
|
"lwr r
|
"lwr r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
|
GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
|
}
|
}
|
|
|
|
|
100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU
|
100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU
|
"lwu r
|
"lwu r
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
|
GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
|
}
|
}
|
|
|
|
|
|
|
011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD
|
011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD
|
"madd r, r
|
"madd r, r
|
*mips32:
|
*mips32:
|
*mips64:
|
*mips64:
|
*vr5500:
|
*vr5500:
|
{
|
{
|
signed64 temp;
|
signed64 temp;
|
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
Unpredictable ();
|
Unpredictable ();
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
|
temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
|
+ ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
|
+ ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
|
LO = EXTEND32 (temp);
|
LO = EXTEND32 (temp);
|
HI = EXTEND32 (VH4_8 (temp));
|
HI = EXTEND32 (VH4_8 (temp));
|
TRACE_ALU_RESULT2 (HI, LO);
|
TRACE_ALU_RESULT2 (HI, LO);
|
}
|
}
|
|
|
|
|
011100,5.RS,5.RT,000,2.AC,00000,000000:SPECIAL2:32::MADD
|
011100,5.RS,5.RT,000,2.AC,00000,000000:SPECIAL2:32::MADD
|
"madd r, r
|
"madd r, r
|
"madd ac, r, r
|
"madd ac, r, r
|
*mips32r2:
|
*mips32r2:
|
*mips64r2:
|
*mips64r2:
|
*dsp2:
|
*dsp2:
|
{
|
{
|
signed64 temp;
|
signed64 temp;
|
if (AC == 0)
|
if (AC == 0)
|
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
Unpredictable ();
|
Unpredictable ();
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC)))
|
temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC)))
|
+ ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
|
+ ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
|
DSPLO(AC) = EXTEND32 (temp);
|
DSPLO(AC) = EXTEND32 (temp);
|
DSPHI(AC) = EXTEND32 (VH4_8 (temp));
|
DSPHI(AC) = EXTEND32 (VH4_8 (temp));
|
if (AC == 0)
|
if (AC == 0)
|
TRACE_ALU_RESULT2 (HI, LO);
|
TRACE_ALU_RESULT2 (HI, LO);
|
}
|
}
|
|
|
|
|
011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU
|
011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU
|
"maddu r, r
|
"maddu r, r
|
*mips32:
|
*mips32:
|
*mips64:
|
*mips64:
|
*vr5500:
|
*vr5500:
|
{
|
{
|
unsigned64 temp;
|
unsigned64 temp;
|
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
Unpredictable ();
|
Unpredictable ();
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
|
temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
|
+ ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
|
+ ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
|
ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */
|
ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */
|
LO = EXTEND32 (temp);
|
LO = EXTEND32 (temp);
|
HI = EXTEND32 (VH4_8 (temp));
|
HI = EXTEND32 (VH4_8 (temp));
|
TRACE_ALU_RESULT2 (HI, LO);
|
TRACE_ALU_RESULT2 (HI, LO);
|
}
|
}
|
|
|
|
|
011100,5.RS,5.RT,000,2.AC,00000,000001:SPECIAL2:32::MADDU
|
011100,5.RS,5.RT,000,2.AC,00000,000001:SPECIAL2:32::MADDU
|
"maddu r, r
|
"maddu r, r
|
"maddu ac, r, r
|
"maddu ac, r, r
|
*mips32r2:
|
*mips32r2:
|
*mips64r2:
|
*mips64r2:
|
*dsp2:
|
*dsp2:
|
{
|
{
|
unsigned64 temp;
|
unsigned64 temp;
|
if (AC == 0)
|
if (AC == 0)
|
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
Unpredictable ();
|
Unpredictable ();
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC)))
|
temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC)))
|
+ ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
|
+ ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
|
if (AC == 0)
|
if (AC == 0)
|
ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */
|
ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */
|
DSPLO(AC) = EXTEND32 (temp);
|
DSPLO(AC) = EXTEND32 (temp);
|
DSPHI(AC) = EXTEND32 (VH4_8 (temp));
|
DSPHI(AC) = EXTEND32 (VH4_8 (temp));
|
if (AC == 0)
|
if (AC == 0)
|
TRACE_ALU_RESULT2 (HI, LO);
|
TRACE_ALU_RESULT2 (HI, LO);
|
}
|
}
|
|
|
|
|
:function:::void:do_mfhi:int rd
|
:function:::void:do_mfhi:int rd
|
{
|
{
|
check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
|
check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
|
TRACE_ALU_INPUT1 (HI);
|
TRACE_ALU_INPUT1 (HI);
|
GPR[rd] = HI;
|
GPR[rd] = HI;
|
TRACE_ALU_RESULT (GPR[rd]);
|
TRACE_ALU_RESULT (GPR[rd]);
|
}
|
}
|
|
|
000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
|
000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
|
"mfhi r"
|
"mfhi r"
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
*mips32:
|
*mips32:
|
*mips64:
|
*mips64:
|
{
|
{
|
do_mfhi (SD_, RD);
|
do_mfhi (SD_, RD);
|
}
|
}
|
|
|
|
|
000000,000,2.AC,00000,5.RD,00000,010000:SPECIAL:32::MFHI
|
000000,000,2.AC,00000,5.RD,00000,010000:SPECIAL:32::MFHI
|
"mfhi r":AC == 0
|
"mfhi r":AC == 0
|
"mfhi r, ac"
|
"mfhi r, ac"
|
*mips32r2:
|
*mips32r2:
|
*mips64r2:
|
*mips64r2:
|
*dsp:
|
*dsp:
|
{
|
{
|
if (AC == 0)
|
if (AC == 0)
|
do_mfhi (SD_, RD);
|
do_mfhi (SD_, RD);
|
else
|
else
|
GPR[RD] = DSPHI(AC);
|
GPR[RD] = DSPHI(AC);
|
}
|
}
|
|
|
|
|
:function:::void:do_mflo:int rd
|
:function:::void:do_mflo:int rd
|
{
|
{
|
check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
|
check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
|
TRACE_ALU_INPUT1 (LO);
|
TRACE_ALU_INPUT1 (LO);
|
GPR[rd] = LO;
|
GPR[rd] = LO;
|
TRACE_ALU_RESULT (GPR[rd]);
|
TRACE_ALU_RESULT (GPR[rd]);
|
}
|
}
|
|
|
000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
|
000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
|
"mflo r"
|
"mflo r"
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
*mips32:
|
*mips32:
|
*mips64:
|
*mips64:
|
{
|
{
|
do_mflo (SD_, RD);
|
do_mflo (SD_, RD);
|
}
|
}
|
|
|
|
|
000000,000,2.AC,00000,5.RD,00000,010010:SPECIAL:32::MFLO
|
000000,000,2.AC,00000,5.RD,00000,010010:SPECIAL:32::MFLO
|
"mflo r":AC == 0
|
"mflo r":AC == 0
|
"mflo r, ac"
|
"mflo r, ac"
|
*mips32r2:
|
*mips32r2:
|
*mips64r2:
|
*mips64r2:
|
*dsp:
|
*dsp:
|
{
|
{
|
if (AC == 0)
|
if (AC == 0)
|
do_mflo (SD_, RD);
|
do_mflo (SD_, RD);
|
else
|
else
|
GPR[RD] = DSPLO(AC);
|
GPR[RD] = DSPLO(AC);
|
}
|
}
|
|
|
|
|
000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
|
000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
|
"movn r, r, r
|
"movn r, r, r
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
if (GPR[RT] != 0)
|
if (GPR[RT] != 0)
|
{
|
{
|
GPR[RD] = GPR[RS];
|
GPR[RD] = GPR[RS];
|
TRACE_ALU_RESULT (GPR[RD]);
|
TRACE_ALU_RESULT (GPR[RD]);
|
}
|
}
|
}
|
}
|
|
|
|
|
|
|
000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
|
000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
|
"movz r, r, r
|
"movz r, r, r
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
if (GPR[RT] == 0)
|
if (GPR[RT] == 0)
|
{
|
{
|
GPR[RD] = GPR[RS];
|
GPR[RD] = GPR[RS];
|
TRACE_ALU_RESULT (GPR[RD]);
|
TRACE_ALU_RESULT (GPR[RD]);
|
}
|
}
|
}
|
}
|
|
|
|
|
|
|
011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB
|
011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB
|
"msub r, r
|
"msub r, r
|
*mips32:
|
*mips32:
|
*mips64:
|
*mips64:
|
*vr5500:
|
*vr5500:
|
{
|
{
|
signed64 temp;
|
signed64 temp;
|
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
Unpredictable ();
|
Unpredictable ();
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
|
temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
|
- ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
|
- ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
|
LO = EXTEND32 (temp);
|
LO = EXTEND32 (temp);
|
HI = EXTEND32 (VH4_8 (temp));
|
HI = EXTEND32 (VH4_8 (temp));
|
TRACE_ALU_RESULT2 (HI, LO);
|
TRACE_ALU_RESULT2 (HI, LO);
|
}
|
}
|
|
|
|
|
011100,5.RS,5.RT,000,2.AC,00000,000100:SPECIAL2:32::MSUB
|
011100,5.RS,5.RT,000,2.AC,00000,000100:SPECIAL2:32::MSUB
|
"msub r, r
|
"msub r, r
|
"msub ac, r, r
|
"msub ac, r, r
|
*mips32r2:
|
*mips32r2:
|
*mips64r2:
|
*mips64r2:
|
*dsp2:
|
*dsp2:
|
{
|
{
|
signed64 temp;
|
signed64 temp;
|
if (AC == 0)
|
if (AC == 0)
|
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
Unpredictable ();
|
Unpredictable ();
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC)))
|
temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC)))
|
- ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
|
- ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
|
DSPLO(AC) = EXTEND32 (temp);
|
DSPLO(AC) = EXTEND32 (temp);
|
DSPHI(AC) = EXTEND32 (VH4_8 (temp));
|
DSPHI(AC) = EXTEND32 (VH4_8 (temp));
|
if (AC == 0)
|
if (AC == 0)
|
TRACE_ALU_RESULT2 (HI, LO);
|
TRACE_ALU_RESULT2 (HI, LO);
|
}
|
}
|
|
|
|
|
011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU
|
011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU
|
"msubu r, r
|
"msubu r, r
|
*mips32:
|
*mips32:
|
*mips64:
|
*mips64:
|
*vr5500:
|
*vr5500:
|
{
|
{
|
unsigned64 temp;
|
unsigned64 temp;
|
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
Unpredictable ();
|
Unpredictable ();
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
|
temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
|
- ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
|
- ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
|
LO = EXTEND32 (temp);
|
LO = EXTEND32 (temp);
|
HI = EXTEND32 (VH4_8 (temp));
|
HI = EXTEND32 (VH4_8 (temp));
|
TRACE_ALU_RESULT2 (HI, LO);
|
TRACE_ALU_RESULT2 (HI, LO);
|
}
|
}
|
|
|
|
|
011100,5.RS,5.RT,000,2.AC,00000,000101:SPECIAL2:32::MSUBU
|
011100,5.RS,5.RT,000,2.AC,00000,000101:SPECIAL2:32::MSUBU
|
"msubu r, r
|
"msubu r, r
|
"msubu ac, r, r
|
"msubu ac, r, r
|
*mips32r2:
|
*mips32r2:
|
*mips64r2:
|
*mips64r2:
|
*dsp2:
|
*dsp2:
|
{
|
{
|
unsigned64 temp;
|
unsigned64 temp;
|
if (AC == 0)
|
if (AC == 0)
|
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
Unpredictable ();
|
Unpredictable ();
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC)))
|
temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC)))
|
- ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
|
- ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
|
DSPLO(AC) = EXTEND32 (temp);
|
DSPLO(AC) = EXTEND32 (temp);
|
DSPHI(AC) = EXTEND32 (VH4_8 (temp));
|
DSPHI(AC) = EXTEND32 (VH4_8 (temp));
|
if (AC == 0)
|
if (AC == 0)
|
TRACE_ALU_RESULT2 (HI, LO);
|
TRACE_ALU_RESULT2 (HI, LO);
|
}
|
}
|
|
|
|
|
000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
|
000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
|
"mthi r"
|
"mthi r"
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
*mips32:
|
*mips32:
|
*mips64:
|
*mips64:
|
{
|
{
|
check_mt_hilo (SD_, HIHISTORY);
|
check_mt_hilo (SD_, HIHISTORY);
|
HI = GPR[RS];
|
HI = GPR[RS];
|
}
|
}
|
|
|
|
|
000000,5.RS,00000,000,2.AC,00000,010001:SPECIAL:32::MTHI
|
000000,5.RS,00000,000,2.AC,00000,010001:SPECIAL:32::MTHI
|
"mthi r":AC == 0
|
"mthi r":AC == 0
|
"mthi r, ac"
|
"mthi r, ac"
|
*mips32r2:
|
*mips32r2:
|
*mips64r2:
|
*mips64r2:
|
*dsp:
|
*dsp:
|
{
|
{
|
if (AC == 0)
|
if (AC == 0)
|
check_mt_hilo (SD_, HIHISTORY);
|
check_mt_hilo (SD_, HIHISTORY);
|
DSPHI(AC) = GPR[RS];
|
DSPHI(AC) = GPR[RS];
|
}
|
}
|
|
|
|
|
000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
|
000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
|
"mtlo r"
|
"mtlo r"
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
*mips32:
|
*mips32:
|
*mips64:
|
*mips64:
|
{
|
{
|
check_mt_hilo (SD_, LOHISTORY);
|
check_mt_hilo (SD_, LOHISTORY);
|
LO = GPR[RS];
|
LO = GPR[RS];
|
}
|
}
|
|
|
|
|
000000,5.RS,00000,000,2.AC,00000,010011:SPECIAL:32::MTLO
|
000000,5.RS,00000,000,2.AC,00000,010011:SPECIAL:32::MTLO
|
"mtlo r":AC == 0
|
"mtlo r":AC == 0
|
"mtlo r, ac"
|
"mtlo r, ac"
|
*mips32r2:
|
*mips32r2:
|
*mips64r2:
|
*mips64r2:
|
*dsp:
|
*dsp:
|
{
|
{
|
if (AC == 0)
|
if (AC == 0)
|
check_mt_hilo (SD_, LOHISTORY);
|
check_mt_hilo (SD_, LOHISTORY);
|
DSPLO(AC) = GPR[RS];
|
DSPLO(AC) = GPR[RS];
|
}
|
}
|
|
|
|
|
011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL
|
011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL
|
"mul r, r, r
|
"mul r, r, r
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr5500:
|
*vr5500:
|
{
|
{
|
signed64 prod;
|
signed64 prod;
|
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
Unpredictable ();
|
Unpredictable ();
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
prod = (((signed64)(signed32) GPR[RS])
|
prod = (((signed64)(signed32) GPR[RS])
|
* ((signed64)(signed32) GPR[RT]));
|
* ((signed64)(signed32) GPR[RT]));
|
GPR[RD] = EXTEND32 (VL4_8 (prod));
|
GPR[RD] = EXTEND32 (VL4_8 (prod));
|
TRACE_ALU_RESULT (GPR[RD]);
|
TRACE_ALU_RESULT (GPR[RD]);
|
}
|
}
|
|
|
|
|
|
|
:function:::void:do_mult:int rs, int rt, int rd
|
:function:::void:do_mult:int rs, int rt, int rd
|
{
|
{
|
signed64 prod;
|
signed64 prod;
|
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
|
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
|
Unpredictable ();
|
Unpredictable ();
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
prod = (((signed64)(signed32) GPR[rs])
|
prod = (((signed64)(signed32) GPR[rs])
|
* ((signed64)(signed32) GPR[rt]));
|
* ((signed64)(signed32) GPR[rt]));
|
LO = EXTEND32 (VL4_8 (prod));
|
LO = EXTEND32 (VL4_8 (prod));
|
HI = EXTEND32 (VH4_8 (prod));
|
HI = EXTEND32 (VH4_8 (prod));
|
ACX = 0; /* SmartMIPS */
|
ACX = 0; /* SmartMIPS */
|
if (rd != 0)
|
if (rd != 0)
|
GPR[rd] = LO;
|
GPR[rd] = LO;
|
TRACE_ALU_RESULT2 (HI, LO);
|
TRACE_ALU_RESULT2 (HI, LO);
|
}
|
}
|
|
|
000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
|
000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
|
"mult r, r
|
"mult r, r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips64:
|
*mips64:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_mult (SD_, RS, RT, 0);
|
do_mult (SD_, RS, RT, 0);
|
}
|
}
|
|
|
|
|
000000,5.RS,5.RT,000,2.AC,00000,011000:SPECIAL:32::MULT
|
000000,5.RS,5.RT,000,2.AC,00000,011000:SPECIAL:32::MULT
|
"mult r, r
|
"mult r, r
|
"mult ac, r, r
|
"mult ac, r, r
|
*mips32r2:
|
*mips32r2:
|
*mips64r2:
|
*mips64r2:
|
*dsp2:
|
*dsp2:
|
{
|
{
|
signed64 prod;
|
signed64 prod;
|
if (AC == 0)
|
if (AC == 0)
|
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
Unpredictable ();
|
Unpredictable ();
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
prod = ((signed64)(signed32) GPR[RS])
|
prod = ((signed64)(signed32) GPR[RS])
|
* ((signed64)(signed32) GPR[RT]);
|
* ((signed64)(signed32) GPR[RT]);
|
DSPLO(AC) = EXTEND32 (VL4_8 (prod));
|
DSPLO(AC) = EXTEND32 (VL4_8 (prod));
|
DSPHI(AC) = EXTEND32 (VH4_8 (prod));
|
DSPHI(AC) = EXTEND32 (VH4_8 (prod));
|
if (AC == 0)
|
if (AC == 0)
|
{
|
{
|
ACX = 0; /* SmartMIPS */
|
ACX = 0; /* SmartMIPS */
|
TRACE_ALU_RESULT2 (HI, LO);
|
TRACE_ALU_RESULT2 (HI, LO);
|
}
|
}
|
}
|
}
|
|
|
|
|
000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
|
000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
|
"mult r, r
|
"mult r, r
|
"mult r, r, r
|
"mult r, r, r
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
do_mult (SD_, RS, RT, RD);
|
do_mult (SD_, RS, RT, RD);
|
}
|
}
|
|
|
|
|
:function:::void:do_multu:int rs, int rt, int rd
|
:function:::void:do_multu:int rs, int rt, int rd
|
{
|
{
|
unsigned64 prod;
|
unsigned64 prod;
|
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
|
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
|
Unpredictable ();
|
Unpredictable ();
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
prod = (((unsigned64)(unsigned32) GPR[rs])
|
prod = (((unsigned64)(unsigned32) GPR[rs])
|
* ((unsigned64)(unsigned32) GPR[rt]));
|
* ((unsigned64)(unsigned32) GPR[rt]));
|
LO = EXTEND32 (VL4_8 (prod));
|
LO = EXTEND32 (VL4_8 (prod));
|
HI = EXTEND32 (VH4_8 (prod));
|
HI = EXTEND32 (VH4_8 (prod));
|
if (rd != 0)
|
if (rd != 0)
|
GPR[rd] = LO;
|
GPR[rd] = LO;
|
TRACE_ALU_RESULT2 (HI, LO);
|
TRACE_ALU_RESULT2 (HI, LO);
|
}
|
}
|
|
|
000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
|
000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
|
"multu r, r
|
"multu r, r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips64:
|
*mips64:
|
*vr4100:
|
*vr4100:
|
{
|
{
|
do_multu (SD_, RS, RT, 0);
|
do_multu (SD_, RS, RT, 0);
|
}
|
}
|
|
|
|
|
000000,5.RS,5.RT,000,2.AC,00000,011001:SPECIAL:32::MULTU
|
000000,5.RS,5.RT,000,2.AC,00000,011001:SPECIAL:32::MULTU
|
"multu r, r
|
"multu r, r
|
"multu r, r
|
"multu r, r
|
*mips32r2:
|
*mips32r2:
|
*mips64r2:
|
*mips64r2:
|
*dsp2:
|
*dsp2:
|
{
|
{
|
unsigned64 prod;
|
unsigned64 prod;
|
if (AC == 0)
|
if (AC == 0)
|
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
Unpredictable ();
|
Unpredictable ();
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
prod = ((unsigned64)(unsigned32) GPR[RS])
|
prod = ((unsigned64)(unsigned32) GPR[RS])
|
* ((unsigned64)(unsigned32) GPR[RT]);
|
* ((unsigned64)(unsigned32) GPR[RT]);
|
DSPLO(AC) = EXTEND32 (VL4_8 (prod));
|
DSPLO(AC) = EXTEND32 (VL4_8 (prod));
|
DSPHI(AC) = EXTEND32 (VH4_8 (prod));
|
DSPHI(AC) = EXTEND32 (VH4_8 (prod));
|
if (AC == 0)
|
if (AC == 0)
|
TRACE_ALU_RESULT2 (HI, LO);
|
TRACE_ALU_RESULT2 (HI, LO);
|
}
|
}
|
|
|
|
|
000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
|
000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
|
"multu r, r
|
"multu r, r
|
"multu r, r, r
|
"multu r, r, r
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
do_multu (SD_, RS, RT, RD);
|
do_multu (SD_, RS, RT, RD);
|
}
|
}
|
|
|
|
|
:function:::void:do_nor:int rs, int rt, int rd
|
:function:::void:do_nor:int rs, int rt, int rd
|
{
|
{
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
GPR[rd] = ~ (GPR[rs] | GPR[rt]);
|
GPR[rd] = ~ (GPR[rs] | GPR[rt]);
|
TRACE_ALU_RESULT (GPR[rd]);
|
TRACE_ALU_RESULT (GPR[rd]);
|
}
|
}
|
|
|
000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
|
000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
|
"nor r, r, r
|
"nor r, r, r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
do_nor (SD_, RS, RT, RD);
|
do_nor (SD_, RS, RT, RD);
|
}
|
}
|
|
|
|
|
:function:::void:do_or:int rs, int rt, int rd
|
:function:::void:do_or:int rs, int rt, int rd
|
{
|
{
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
GPR[rd] = (GPR[rs] | GPR[rt]);
|
GPR[rd] = (GPR[rs] | GPR[rt]);
|
TRACE_ALU_RESULT (GPR[rd]);
|
TRACE_ALU_RESULT (GPR[rd]);
|
}
|
}
|
|
|
000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
|
000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
|
"or r, r, r
|
"or r, r, r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
do_or (SD_, RS, RT, RD);
|
do_or (SD_, RS, RT, RD);
|
}
|
}
|
|
|
|
|
|
|
:function:::void:do_ori:int rs, int rt, unsigned immediate
|
:function:::void:do_ori:int rs, int rt, unsigned immediate
|
{
|
{
|
TRACE_ALU_INPUT2 (GPR[rs], immediate);
|
TRACE_ALU_INPUT2 (GPR[rs], immediate);
|
GPR[rt] = (GPR[rs] | immediate);
|
GPR[rt] = (GPR[rs] | immediate);
|
TRACE_ALU_RESULT (GPR[rt]);
|
TRACE_ALU_RESULT (GPR[rt]);
|
}
|
}
|
|
|
001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
|
001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
|
"ori r
|
"ori r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
do_ori (SD_, RS, RT, IMMEDIATE);
|
do_ori (SD_, RS, RT, IMMEDIATE);
|
}
|
}
|
|
|
|
|
110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF
|
110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF
|
"pref , (r)"
|
"pref , (r)"
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
address_word base = GPR[BASE];
|
address_word base = GPR[BASE];
|
address_word offset = EXTEND16 (OFFSET);
|
address_word offset = EXTEND16 (OFFSET);
|
{
|
{
|
address_word vaddr = loadstore_ea (SD_, base, offset);
|
address_word vaddr = loadstore_ea (SD_, base, offset);
|
address_word paddr;
|
address_word paddr;
|
int uncached;
|
int uncached;
|
{
|
{
|
if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
|
if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
|
Prefetch(uncached,paddr,vaddr,isDATA,HINT);
|
Prefetch(uncached,paddr,vaddr,isDATA,HINT);
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
|
|
:function:::unsigned64:do_ror:unsigned32 x,unsigned32 y
|
:function:::unsigned64:do_ror:unsigned32 x,unsigned32 y
|
{
|
{
|
unsigned64 result;
|
unsigned64 result;
|
|
|
y &= 31;
|
y &= 31;
|
TRACE_ALU_INPUT2 (x, y);
|
TRACE_ALU_INPUT2 (x, y);
|
result = EXTEND32 (ROTR32 (x, y));
|
result = EXTEND32 (ROTR32 (x, y));
|
TRACE_ALU_RESULT (result);
|
TRACE_ALU_RESULT (result);
|
return result;
|
return result;
|
}
|
}
|
|
|
000000,00001,5.RT,5.RD,5.SHIFT,000010::32::ROR
|
000000,00001,5.RT,5.RD,5.SHIFT,000010::32::ROR
|
"ror r, r
|
"ror r, r
|
*mips32r2:
|
*mips32r2:
|
*mips64r2:
|
*mips64r2:
|
*smartmips:
|
*smartmips:
|
*vr5400:
|
*vr5400:
|
*vr5500:
|
*vr5500:
|
{
|
{
|
GPR[RD] = do_ror (SD_, GPR[RT], SHIFT);
|
GPR[RD] = do_ror (SD_, GPR[RT], SHIFT);
|
}
|
}
|
|
|
000000,5.RS,5.RT,5.RD,00001,000110::32::RORV
|
000000,5.RS,5.RT,5.RD,00001,000110::32::RORV
|
"rorv r, r
|
"rorv r, r
|
*mips32r2:
|
*mips32r2:
|
*mips64r2:
|
*mips64r2:
|
*smartmips:
|
*smartmips:
|
*vr5400:
|
*vr5400:
|
*vr5500:
|
*vr5500:
|
{
|
{
|
GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]);
|
GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]);
|
}
|
}
|
|
|
|
|
:function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
|
:function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
|
{
|
{
|
address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
|
address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
|
address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
|
address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
|
address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
|
address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
|
unsigned int byte;
|
unsigned int byte;
|
address_word paddr;
|
address_word paddr;
|
int uncached;
|
int uncached;
|
unsigned64 memval;
|
unsigned64 memval;
|
address_word vaddr;
|
address_word vaddr;
|
|
|
vaddr = loadstore_ea (SD_, base, offset);
|
vaddr = loadstore_ea (SD_, base, offset);
|
if ((vaddr & access) != 0)
|
if ((vaddr & access) != 0)
|
{
|
{
|
SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
|
SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
|
}
|
}
|
AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
|
AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
|
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
|
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
|
byte = ((vaddr & mask) ^ bigendiancpu);
|
byte = ((vaddr & mask) ^ bigendiancpu);
|
memval = (word << (8 * byte));
|
memval = (word << (8 * byte));
|
StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
|
StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
|
}
|
}
|
|
|
:function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
|
:function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
|
{
|
{
|
address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
|
address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
|
address_word reverseendian = (ReverseEndian ? -1 : 0);
|
address_word reverseendian = (ReverseEndian ? -1 : 0);
|
address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
|
address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
|
unsigned int byte;
|
unsigned int byte;
|
unsigned int word;
|
unsigned int word;
|
address_word paddr;
|
address_word paddr;
|
int uncached;
|
int uncached;
|
unsigned64 memval;
|
unsigned64 memval;
|
address_word vaddr;
|
address_word vaddr;
|
int nr_lhs_bits;
|
int nr_lhs_bits;
|
int nr_rhs_bits;
|
int nr_rhs_bits;
|
|
|
vaddr = loadstore_ea (SD_, base, offset);
|
vaddr = loadstore_ea (SD_, base, offset);
|
AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
|
AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
|
paddr = (paddr ^ (reverseendian & mask));
|
paddr = (paddr ^ (reverseendian & mask));
|
if (BigEndianMem == 0)
|
if (BigEndianMem == 0)
|
paddr = paddr & ~access;
|
paddr = paddr & ~access;
|
|
|
/* compute where within the word/mem we are */
|
/* compute where within the word/mem we are */
|
byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
|
byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
|
word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
|
word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
|
nr_lhs_bits = 8 * byte + 8;
|
nr_lhs_bits = 8 * byte + 8;
|
nr_rhs_bits = 8 * access - 8 * byte;
|
nr_rhs_bits = 8 * access - 8 * byte;
|
/* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
|
/* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
|
/* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
|
/* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
|
(long) ((unsigned64) vaddr >> 32), (long) vaddr,
|
(long) ((unsigned64) vaddr >> 32), (long) vaddr,
|
(long) ((unsigned64) paddr >> 32), (long) paddr,
|
(long) ((unsigned64) paddr >> 32), (long) paddr,
|
word, byte, nr_lhs_bits, nr_rhs_bits); */
|
word, byte, nr_lhs_bits, nr_rhs_bits); */
|
|
|
if (word == 0)
|
if (word == 0)
|
{
|
{
|
memval = (rt >> nr_rhs_bits);
|
memval = (rt >> nr_rhs_bits);
|
}
|
}
|
else
|
else
|
{
|
{
|
memval = (rt << nr_lhs_bits);
|
memval = (rt << nr_lhs_bits);
|
}
|
}
|
/* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
|
/* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
|
(long) ((unsigned64) rt >> 32), (long) rt,
|
(long) ((unsigned64) rt >> 32), (long) rt,
|
(long) ((unsigned64) memval >> 32), (long) memval); */
|
(long) ((unsigned64) memval >> 32), (long) memval); */
|
StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
|
StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
|
}
|
}
|
|
|
:function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
|
:function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
|
{
|
{
|
address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
|
address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
|
address_word reverseendian = (ReverseEndian ? -1 : 0);
|
address_word reverseendian = (ReverseEndian ? -1 : 0);
|
address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
|
address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
|
unsigned int byte;
|
unsigned int byte;
|
address_word paddr;
|
address_word paddr;
|
int uncached;
|
int uncached;
|
unsigned64 memval;
|
unsigned64 memval;
|
address_word vaddr;
|
address_word vaddr;
|
|
|
vaddr = loadstore_ea (SD_, base, offset);
|
vaddr = loadstore_ea (SD_, base, offset);
|
AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
|
AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
|
paddr = (paddr ^ (reverseendian & mask));
|
paddr = (paddr ^ (reverseendian & mask));
|
if (BigEndianMem != 0)
|
if (BigEndianMem != 0)
|
paddr &= ~access;
|
paddr &= ~access;
|
byte = ((vaddr & mask) ^ (bigendiancpu & mask));
|
byte = ((vaddr & mask) ^ (bigendiancpu & mask));
|
memval = (rt << (byte * 8));
|
memval = (rt << (byte * 8));
|
StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
|
StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
|
}
|
}
|
|
|
|
|
101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
|
101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
|
"sb r
|
"sb r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
|
do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
|
}
|
}
|
|
|
|
|
111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
|
111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
|
"sc r
|
"sc r
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
unsigned32 instruction = instruction_0;
|
unsigned32 instruction = instruction_0;
|
address_word base = GPR[BASE];
|
address_word base = GPR[BASE];
|
address_word offset = EXTEND16 (OFFSET);
|
address_word offset = EXTEND16 (OFFSET);
|
{
|
{
|
address_word vaddr = loadstore_ea (SD_, base, offset);
|
address_word vaddr = loadstore_ea (SD_, base, offset);
|
address_word paddr;
|
address_word paddr;
|
int uncached;
|
int uncached;
|
if ((vaddr & 3) != 0)
|
if ((vaddr & 3) != 0)
|
{
|
{
|
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
|
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
|
}
|
}
|
else
|
else
|
{
|
{
|
if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
|
if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
|
{
|
{
|
unsigned64 memval = 0;
|
unsigned64 memval = 0;
|
unsigned64 memval1 = 0;
|
unsigned64 memval1 = 0;
|
unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
|
unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
|
address_word reverseendian = (ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
|
address_word reverseendian = (ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
|
address_word bigendiancpu = (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0);
|
address_word bigendiancpu = (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0);
|
unsigned int byte;
|
unsigned int byte;
|
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
|
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
|
byte = ((vaddr & mask) ^ bigendiancpu);
|
byte = ((vaddr & mask) ^ bigendiancpu);
|
memval = ((unsigned64) GPR[RT] << (8 * byte));
|
memval = ((unsigned64) GPR[RT] << (8 * byte));
|
if (LLBIT)
|
if (LLBIT)
|
{
|
{
|
StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
|
StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
|
}
|
}
|
GPR[RT] = LLBIT;
|
GPR[RT] = LLBIT;
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
|
|
111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
|
111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
|
"scd r
|
"scd r
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
address_word base = GPR[BASE];
|
address_word base = GPR[BASE];
|
address_word offset = EXTEND16 (OFFSET);
|
address_word offset = EXTEND16 (OFFSET);
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
{
|
{
|
address_word vaddr = loadstore_ea (SD_, base, offset);
|
address_word vaddr = loadstore_ea (SD_, base, offset);
|
address_word paddr;
|
address_word paddr;
|
int uncached;
|
int uncached;
|
if ((vaddr & 7) != 0)
|
if ((vaddr & 7) != 0)
|
{
|
{
|
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
|
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
|
}
|
}
|
else
|
else
|
{
|
{
|
if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
|
if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
|
{
|
{
|
unsigned64 memval = 0;
|
unsigned64 memval = 0;
|
unsigned64 memval1 = 0;
|
unsigned64 memval1 = 0;
|
memval = GPR[RT];
|
memval = GPR[RT];
|
if (LLBIT)
|
if (LLBIT)
|
{
|
{
|
StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
|
StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
|
}
|
}
|
GPR[RT] = LLBIT;
|
GPR[RT] = LLBIT;
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
|
|
111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
|
111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
|
"sd r
|
"sd r
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
|
do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
|
}
|
}
|
|
|
|
|
1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
|
1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
|
"sdc r
|
"sdc r
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
|
do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
|
}
|
}
|
|
|
|
|
101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
|
101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
|
"sdl r
|
"sdl r
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
|
do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
|
}
|
}
|
|
|
|
|
101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
|
101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
|
"sdr r
|
"sdr r
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
|
do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
|
}
|
}
|
|
|
|
|
|
|
101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
|
101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
|
"sh r
|
"sh r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
|
do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
|
}
|
}
|
|
|
|
|
:function:::void:do_sll:int rt, int rd, int shift
|
:function:::void:do_sll:int rt, int rd, int shift
|
{
|
{
|
unsigned32 temp = (GPR[rt] << shift);
|
unsigned32 temp = (GPR[rt] << shift);
|
TRACE_ALU_INPUT2 (GPR[rt], shift);
|
TRACE_ALU_INPUT2 (GPR[rt], shift);
|
GPR[rd] = EXTEND32 (temp);
|
GPR[rd] = EXTEND32 (temp);
|
TRACE_ALU_RESULT (GPR[rd]);
|
TRACE_ALU_RESULT (GPR[rd]);
|
}
|
}
|
|
|
000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLa
|
000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLa
|
"nop":RD == 0 && RT == 0 && SHIFT == 0
|
"nop":RD == 0 && RT == 0 && SHIFT == 0
|
"sll r, r
|
"sll r, r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
/* Skip shift for NOP, so that there won't be lots of extraneous
|
/* Skip shift for NOP, so that there won't be lots of extraneous
|
trace output. */
|
trace output. */
|
if (RD != 0 || RT != 0 || SHIFT != 0)
|
if (RD != 0 || RT != 0 || SHIFT != 0)
|
do_sll (SD_, RT, RD, SHIFT);
|
do_sll (SD_, RT, RD, SHIFT);
|
}
|
}
|
|
|
000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLb
|
000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLb
|
"nop":RD == 0 && RT == 0 && SHIFT == 0
|
"nop":RD == 0 && RT == 0 && SHIFT == 0
|
"ssnop":RD == 0 && RT == 0 && SHIFT == 1
|
"ssnop":RD == 0 && RT == 0 && SHIFT == 1
|
"sll r, r
|
"sll r, r
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
{
|
{
|
/* Skip shift for NOP and SSNOP, so that there won't be lots of
|
/* Skip shift for NOP and SSNOP, so that there won't be lots of
|
extraneous trace output. */
|
extraneous trace output. */
|
if (RD != 0 || RT != 0 || (SHIFT != 0 && SHIFT != 1))
|
if (RD != 0 || RT != 0 || (SHIFT != 0 && SHIFT != 1))
|
do_sll (SD_, RT, RD, SHIFT);
|
do_sll (SD_, RT, RD, SHIFT);
|
}
|
}
|
|
|
|
|
:function:::void:do_sllv:int rs, int rt, int rd
|
:function:::void:do_sllv:int rs, int rt, int rd
|
{
|
{
|
int s = MASKED (GPR[rs], 4, 0);
|
int s = MASKED (GPR[rs], 4, 0);
|
unsigned32 temp = (GPR[rt] << s);
|
unsigned32 temp = (GPR[rt] << s);
|
TRACE_ALU_INPUT2 (GPR[rt], s);
|
TRACE_ALU_INPUT2 (GPR[rt], s);
|
GPR[rd] = EXTEND32 (temp);
|
GPR[rd] = EXTEND32 (temp);
|
TRACE_ALU_RESULT (GPR[rd]);
|
TRACE_ALU_RESULT (GPR[rd]);
|
}
|
}
|
|
|
000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
|
000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
|
"sllv r, r
|
"sllv r, r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
do_sllv (SD_, RS, RT, RD);
|
do_sllv (SD_, RS, RT, RD);
|
}
|
}
|
|
|
|
|
:function:::void:do_slt:int rs, int rt, int rd
|
:function:::void:do_slt:int rs, int rt, int rd
|
{
|
{
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
|
GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
|
TRACE_ALU_RESULT (GPR[rd]);
|
TRACE_ALU_RESULT (GPR[rd]);
|
}
|
}
|
|
|
000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
|
000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
|
"slt r, r, r
|
"slt r, r, r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
do_slt (SD_, RS, RT, RD);
|
do_slt (SD_, RS, RT, RD);
|
}
|
}
|
|
|
|
|
:function:::void:do_slti:int rs, int rt, unsigned16 immediate
|
:function:::void:do_slti:int rs, int rt, unsigned16 immediate
|
{
|
{
|
TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
|
TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
|
GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
|
GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
|
TRACE_ALU_RESULT (GPR[rt]);
|
TRACE_ALU_RESULT (GPR[rt]);
|
}
|
}
|
|
|
001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
|
001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
|
"slti r
|
"slti r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
do_slti (SD_, RS, RT, IMMEDIATE);
|
do_slti (SD_, RS, RT, IMMEDIATE);
|
}
|
}
|
|
|
|
|
:function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
|
:function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
|
{
|
{
|
TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
|
TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
|
GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
|
GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
|
TRACE_ALU_RESULT (GPR[rt]);
|
TRACE_ALU_RESULT (GPR[rt]);
|
}
|
}
|
|
|
001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
|
001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
|
"sltiu r
|
"sltiu r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
do_sltiu (SD_, RS, RT, IMMEDIATE);
|
do_sltiu (SD_, RS, RT, IMMEDIATE);
|
}
|
}
|
|
|
|
|
|
|
:function:::void:do_sltu:int rs, int rt, int rd
|
:function:::void:do_sltu:int rs, int rt, int rd
|
{
|
{
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
|
GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
|
TRACE_ALU_RESULT (GPR[rd]);
|
TRACE_ALU_RESULT (GPR[rd]);
|
}
|
}
|
|
|
000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
|
000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
|
"sltu r, r, r
|
"sltu r, r, r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
do_sltu (SD_, RS, RT, RD);
|
do_sltu (SD_, RS, RT, RD);
|
}
|
}
|
|
|
|
|
:function:::void:do_sra:int rt, int rd, int shift
|
:function:::void:do_sra:int rt, int rd, int shift
|
{
|
{
|
signed32 temp = (signed32) GPR[rt] >> shift;
|
signed32 temp = (signed32) GPR[rt] >> shift;
|
if (NotWordValue (GPR[rt]))
|
if (NotWordValue (GPR[rt]))
|
Unpredictable ();
|
Unpredictable ();
|
TRACE_ALU_INPUT2 (GPR[rt], shift);
|
TRACE_ALU_INPUT2 (GPR[rt], shift);
|
GPR[rd] = EXTEND32 (temp);
|
GPR[rd] = EXTEND32 (temp);
|
TRACE_ALU_RESULT (GPR[rd]);
|
TRACE_ALU_RESULT (GPR[rd]);
|
}
|
}
|
|
|
000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
|
000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
|
"sra r, r
|
"sra r, r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
do_sra (SD_, RT, RD, SHIFT);
|
do_sra (SD_, RT, RD, SHIFT);
|
}
|
}
|
|
|
|
|
|
|
:function:::void:do_srav:int rs, int rt, int rd
|
:function:::void:do_srav:int rs, int rt, int rd
|
{
|
{
|
int s = MASKED (GPR[rs], 4, 0);
|
int s = MASKED (GPR[rs], 4, 0);
|
signed32 temp = (signed32) GPR[rt] >> s;
|
signed32 temp = (signed32) GPR[rt] >> s;
|
if (NotWordValue (GPR[rt]))
|
if (NotWordValue (GPR[rt]))
|
Unpredictable ();
|
Unpredictable ();
|
TRACE_ALU_INPUT2 (GPR[rt], s);
|
TRACE_ALU_INPUT2 (GPR[rt], s);
|
GPR[rd] = EXTEND32 (temp);
|
GPR[rd] = EXTEND32 (temp);
|
TRACE_ALU_RESULT (GPR[rd]);
|
TRACE_ALU_RESULT (GPR[rd]);
|
}
|
}
|
|
|
000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
|
000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
|
"srav r, r
|
"srav r, r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
do_srav (SD_, RS, RT, RD);
|
do_srav (SD_, RS, RT, RD);
|
}
|
}
|
|
|
|
|
|
|
:function:::void:do_srl:int rt, int rd, int shift
|
:function:::void:do_srl:int rt, int rd, int shift
|
{
|
{
|
unsigned32 temp = (unsigned32) GPR[rt] >> shift;
|
unsigned32 temp = (unsigned32) GPR[rt] >> shift;
|
if (NotWordValue (GPR[rt]))
|
if (NotWordValue (GPR[rt]))
|
Unpredictable ();
|
Unpredictable ();
|
TRACE_ALU_INPUT2 (GPR[rt], shift);
|
TRACE_ALU_INPUT2 (GPR[rt], shift);
|
GPR[rd] = EXTEND32 (temp);
|
GPR[rd] = EXTEND32 (temp);
|
TRACE_ALU_RESULT (GPR[rd]);
|
TRACE_ALU_RESULT (GPR[rd]);
|
}
|
}
|
|
|
000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
|
000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
|
"srl r, r
|
"srl r, r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
do_srl (SD_, RT, RD, SHIFT);
|
do_srl (SD_, RT, RD, SHIFT);
|
}
|
}
|
|
|
|
|
:function:::void:do_srlv:int rs, int rt, int rd
|
:function:::void:do_srlv:int rs, int rt, int rd
|
{
|
{
|
int s = MASKED (GPR[rs], 4, 0);
|
int s = MASKED (GPR[rs], 4, 0);
|
unsigned32 temp = (unsigned32) GPR[rt] >> s;
|
unsigned32 temp = (unsigned32) GPR[rt] >> s;
|
if (NotWordValue (GPR[rt]))
|
if (NotWordValue (GPR[rt]))
|
Unpredictable ();
|
Unpredictable ();
|
TRACE_ALU_INPUT2 (GPR[rt], s);
|
TRACE_ALU_INPUT2 (GPR[rt], s);
|
GPR[rd] = EXTEND32 (temp);
|
GPR[rd] = EXTEND32 (temp);
|
TRACE_ALU_RESULT (GPR[rd]);
|
TRACE_ALU_RESULT (GPR[rd]);
|
}
|
}
|
|
|
000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
|
000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
|
"srlv r, r
|
"srlv r, r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
do_srlv (SD_, RS, RT, RD);
|
do_srlv (SD_, RS, RT, RD);
|
}
|
}
|
|
|
|
|
000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
|
000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
|
"sub r, r, r
|
"sub r, r, r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
Unpredictable ();
|
Unpredictable ();
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
{
|
{
|
ALU32_BEGIN (GPR[RS]);
|
ALU32_BEGIN (GPR[RS]);
|
ALU32_SUB (GPR[RT]);
|
ALU32_SUB (GPR[RT]);
|
ALU32_END (GPR[RD]); /* This checks for overflow. */
|
ALU32_END (GPR[RD]); /* This checks for overflow. */
|
}
|
}
|
TRACE_ALU_RESULT (GPR[RD]);
|
TRACE_ALU_RESULT (GPR[RD]);
|
}
|
}
|
|
|
|
|
:function:::void:do_subu:int rs, int rt, int rd
|
:function:::void:do_subu:int rs, int rt, int rd
|
{
|
{
|
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
|
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
|
Unpredictable ();
|
Unpredictable ();
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
|
GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
|
TRACE_ALU_RESULT (GPR[rd]);
|
TRACE_ALU_RESULT (GPR[rd]);
|
}
|
}
|
|
|
000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
|
000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
|
"subu r, r, r
|
"subu r, r, r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
do_subu (SD_, RS, RT, RD);
|
do_subu (SD_, RS, RT, RD);
|
}
|
}
|
|
|
|
|
101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
|
101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
|
"sw r
|
"sw r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*r3900:
|
*r3900:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
|
do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
|
}
|
}
|
|
|
|
|
1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
|
1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
|
"swc r
|
"swc r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
|
do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
|
}
|
}
|
|
|
|
|
101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
|
101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
|
"swl r
|
"swl r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
|
do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
|
}
|
}
|
|
|
|
|
101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
|
101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
|
"swr r
|
"swr r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
|
do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
|
}
|
}
|
|
|
|
|
000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
|
000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
|
"sync":STYPE == 0
|
"sync":STYPE == 0
|
"sync "
|
"sync "
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
SyncOperation (STYPE);
|
SyncOperation (STYPE);
|
}
|
}
|
|
|
|
|
000000,20.CODE,001100:SPECIAL:32::SYSCALL
|
000000,20.CODE,001100:SPECIAL:32::SYSCALL
|
"syscall %#lx"
|
"syscall %#lx"
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
SignalException (SystemCall, instruction_0);
|
SignalException (SystemCall, instruction_0);
|
}
|
}
|
|
|
|
|
000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
|
000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
|
"teq r, r
|
"teq r, r
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
|
if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
|
SignalException (Trap, instruction_0);
|
SignalException (Trap, instruction_0);
|
}
|
}
|
|
|
|
|
000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
|
000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
|
"teqi r, "
|
"teqi r, "
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
|
if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
|
SignalException (Trap, instruction_0);
|
SignalException (Trap, instruction_0);
|
}
|
}
|
|
|
|
|
000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
|
000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
|
"tge r, r
|
"tge r, r
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
|
if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
|
SignalException (Trap, instruction_0);
|
SignalException (Trap, instruction_0);
|
}
|
}
|
|
|
|
|
000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
|
000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
|
"tgei r, "
|
"tgei r, "
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
|
if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
|
SignalException (Trap, instruction_0);
|
SignalException (Trap, instruction_0);
|
}
|
}
|
|
|
|
|
000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
|
000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
|
"tgeiu r, "
|
"tgeiu r, "
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
|
if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
|
SignalException (Trap, instruction_0);
|
SignalException (Trap, instruction_0);
|
}
|
}
|
|
|
|
|
000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
|
000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
|
"tgeu r, r
|
"tgeu r, r
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
|
if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
|
SignalException (Trap, instruction_0);
|
SignalException (Trap, instruction_0);
|
}
|
}
|
|
|
|
|
000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
|
000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
|
"tlt r, r
|
"tlt r, r
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
|
if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
|
SignalException (Trap, instruction_0);
|
SignalException (Trap, instruction_0);
|
}
|
}
|
|
|
|
|
000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
|
000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
|
"tlti r, "
|
"tlti r, "
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
|
if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
|
SignalException (Trap, instruction_0);
|
SignalException (Trap, instruction_0);
|
}
|
}
|
|
|
|
|
000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
|
000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
|
"tltiu r, "
|
"tltiu r, "
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
|
if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
|
SignalException (Trap, instruction_0);
|
SignalException (Trap, instruction_0);
|
}
|
}
|
|
|
|
|
000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
|
000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
|
"tltu r, r
|
"tltu r, r
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
|
if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
|
SignalException (Trap, instruction_0);
|
SignalException (Trap, instruction_0);
|
}
|
}
|
|
|
|
|
000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
|
000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
|
"tne r, r
|
"tne r, r
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
|
if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
|
SignalException (Trap, instruction_0);
|
SignalException (Trap, instruction_0);
|
}
|
}
|
|
|
|
|
000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
|
000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
|
"tnei r, "
|
"tnei r, "
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
|
if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
|
SignalException (Trap, instruction_0);
|
SignalException (Trap, instruction_0);
|
}
|
}
|
|
|
|
|
:function:::void:do_xor:int rs, int rt, int rd
|
:function:::void:do_xor:int rs, int rt, int rd
|
{
|
{
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
GPR[rd] = GPR[rs] ^ GPR[rt];
|
GPR[rd] = GPR[rs] ^ GPR[rt];
|
TRACE_ALU_RESULT (GPR[rd]);
|
TRACE_ALU_RESULT (GPR[rd]);
|
}
|
}
|
|
|
000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
|
000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
|
"xor r, r, r
|
"xor r, r, r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
do_xor (SD_, RS, RT, RD);
|
do_xor (SD_, RS, RT, RD);
|
}
|
}
|
|
|
|
|
:function:::void:do_xori:int rs, int rt, unsigned16 immediate
|
:function:::void:do_xori:int rs, int rt, unsigned16 immediate
|
{
|
{
|
TRACE_ALU_INPUT2 (GPR[rs], immediate);
|
TRACE_ALU_INPUT2 (GPR[rs], immediate);
|
GPR[rt] = GPR[rs] ^ immediate;
|
GPR[rt] = GPR[rs] ^ immediate;
|
TRACE_ALU_RESULT (GPR[rt]);
|
TRACE_ALU_RESULT (GPR[rt]);
|
}
|
}
|
|
|
001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
|
001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
|
"xori r
|
"xori r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
do_xori (SD_, RS, RT, IMMEDIATE);
|
do_xori (SD_, RS, RT, IMMEDIATE);
|
}
|
}
|
|
|
|
|
//
|
//
|
// MIPS Architecture:
|
// MIPS Architecture:
|
//
|
//
|
// FPU Instruction Set (COP1 & COP1X)
|
// FPU Instruction Set (COP1 & COP1X)
|
//
|
//
|
|
|
|
|
:%s::::FMT:int fmt
|
:%s::::FMT:int fmt
|
{
|
{
|
switch (fmt)
|
switch (fmt)
|
{
|
{
|
case fmt_single: return "s";
|
case fmt_single: return "s";
|
case fmt_double: return "d";
|
case fmt_double: return "d";
|
case fmt_word: return "w";
|
case fmt_word: return "w";
|
case fmt_long: return "l";
|
case fmt_long: return "l";
|
case fmt_ps: return "ps";
|
case fmt_ps: return "ps";
|
default: return "?";
|
default: return "?";
|
}
|
}
|
}
|
}
|
|
|
:%s::::TF:int tf
|
:%s::::TF:int tf
|
{
|
{
|
if (tf)
|
if (tf)
|
return "t";
|
return "t";
|
else
|
else
|
return "f";
|
return "f";
|
}
|
}
|
|
|
:%s::::ND:int nd
|
:%s::::ND:int nd
|
{
|
{
|
if (nd)
|
if (nd)
|
return "l";
|
return "l";
|
else
|
else
|
return "";
|
return "";
|
}
|
}
|
|
|
:%s::::COND:int cond
|
:%s::::COND:int cond
|
{
|
{
|
switch (cond)
|
switch (cond)
|
{
|
{
|
case 00: return "f";
|
case 00: return "f";
|
case 01: return "un";
|
case 01: return "un";
|
case 02: return "eq";
|
case 02: return "eq";
|
case 03: return "ueq";
|
case 03: return "ueq";
|
case 04: return "olt";
|
case 04: return "olt";
|
case 05: return "ult";
|
case 05: return "ult";
|
case 06: return "ole";
|
case 06: return "ole";
|
case 07: return "ule";
|
case 07: return "ule";
|
case 010: return "sf";
|
case 010: return "sf";
|
case 011: return "ngle";
|
case 011: return "ngle";
|
case 012: return "seq";
|
case 012: return "seq";
|
case 013: return "ngl";
|
case 013: return "ngl";
|
case 014: return "lt";
|
case 014: return "lt";
|
case 015: return "nge";
|
case 015: return "nge";
|
case 016: return "le";
|
case 016: return "le";
|
case 017: return "ngt";
|
case 017: return "ngt";
|
default: return "?";
|
default: return "?";
|
}
|
}
|
}
|
}
|
|
|
|
|
// Helpers:
|
// Helpers:
|
//
|
//
|
// Check that the given FPU format is usable, and signal a
|
// Check that the given FPU format is usable, and signal a
|
// ReservedInstruction exception if not.
|
// ReservedInstruction exception if not.
|
//
|
//
|
|
|
// check_fmt_p checks that the format is single, double, or paired single.
|
// check_fmt_p checks that the format is single, double, or paired single.
|
:function:::void:check_fmt_p:int fmt, instruction_word insn
|
:function:::void:check_fmt_p:int fmt, instruction_word insn
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mips32:
|
*mips32:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
/* None of these ISAs support Paired Single, so just fall back to
|
/* None of these ISAs support Paired Single, so just fall back to
|
the single/double check. */
|
the single/double check. */
|
if ((fmt != fmt_single) && (fmt != fmt_double))
|
if ((fmt != fmt_single) && (fmt != fmt_double))
|
SignalException (ReservedInstruction, insn);
|
SignalException (ReservedInstruction, insn);
|
}
|
}
|
|
|
:function:::void:check_fmt_p:int fmt, instruction_word insn
|
:function:::void:check_fmt_p:int fmt, instruction_word insn
|
*mips32r2:
|
*mips32r2:
|
{
|
{
|
if ((fmt != fmt_single) && (fmt != fmt_double) && (fmt != fmt_ps))
|
if ((fmt != fmt_single) && (fmt != fmt_double) && (fmt != fmt_ps))
|
SignalException (ReservedInstruction, insn);
|
SignalException (ReservedInstruction, insn);
|
}
|
}
|
|
|
:function:::void:check_fmt_p:int fmt, instruction_word insn
|
:function:::void:check_fmt_p:int fmt, instruction_word insn
|
*mipsV:
|
*mipsV:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
{
|
{
|
if ((fmt != fmt_single) && (fmt != fmt_double)
|
if ((fmt != fmt_single) && (fmt != fmt_double)
|
&& (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0)))
|
&& (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0)))
|
SignalException (ReservedInstruction, insn);
|
SignalException (ReservedInstruction, insn);
|
}
|
}
|
|
|
|
|
// Helper:
|
// Helper:
|
//
|
//
|
// Check that the FPU is currently usable, and signal a CoProcessorUnusable
|
// Check that the FPU is currently usable, and signal a CoProcessorUnusable
|
// exception if not.
|
// exception if not.
|
//
|
//
|
|
|
:function:::void:check_fpu:
|
:function:::void:check_fpu:
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
if (! COP_Usable (1))
|
if (! COP_Usable (1))
|
SignalExceptionCoProcessorUnusable (1);
|
SignalExceptionCoProcessorUnusable (1);
|
}
|
}
|
|
|
|
|
// Helper:
|
// Helper:
|
//
|
//
|
// Load a double word FP value using 2 32-bit memory cycles a la MIPS II
|
// Load a double word FP value using 2 32-bit memory cycles a la MIPS II
|
// or MIPS32. do_load cannot be used instead because it returns an
|
// or MIPS32. do_load cannot be used instead because it returns an
|
// unsigned_word, which is limited to the size of the machine's registers.
|
// unsigned_word, which is limited to the size of the machine's registers.
|
//
|
//
|
|
|
:function:::unsigned64:do_load_double:address_word base, address_word offset
|
:function:::unsigned64:do_load_double:address_word base, address_word offset
|
*mipsII:
|
*mipsII:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
{
|
{
|
int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
|
int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
|
address_word vaddr;
|
address_word vaddr;
|
address_word paddr;
|
address_word paddr;
|
int uncached;
|
int uncached;
|
unsigned64 memval;
|
unsigned64 memval;
|
unsigned64 v;
|
unsigned64 v;
|
|
|
vaddr = loadstore_ea (SD_, base, offset);
|
vaddr = loadstore_ea (SD_, base, offset);
|
if ((vaddr & AccessLength_DOUBLEWORD) != 0)
|
if ((vaddr & AccessLength_DOUBLEWORD) != 0)
|
{
|
{
|
SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map,
|
SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map,
|
AccessLength_DOUBLEWORD + 1, vaddr, read_transfer,
|
AccessLength_DOUBLEWORD + 1, vaddr, read_transfer,
|
sim_core_unaligned_signal);
|
sim_core_unaligned_signal);
|
}
|
}
|
AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET,
|
AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET,
|
isREAL);
|
isREAL);
|
LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr, vaddr,
|
LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr, vaddr,
|
isDATA, isREAL);
|
isDATA, isREAL);
|
v = (unsigned64)memval;
|
v = (unsigned64)memval;
|
LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr + 4, vaddr + 4,
|
LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr + 4, vaddr + 4,
|
isDATA, isREAL);
|
isDATA, isREAL);
|
return (bigendian ? ((v << 32) | memval) : (v | (memval << 32)));
|
return (bigendian ? ((v << 32) | memval) : (v | (memval << 32)));
|
}
|
}
|
|
|
|
|
// Helper:
|
// Helper:
|
//
|
//
|
// Store a double word FP value using 2 32-bit memory cycles a la MIPS II
|
// Store a double word FP value using 2 32-bit memory cycles a la MIPS II
|
// or MIPS32. do_load cannot be used instead because it returns an
|
// or MIPS32. do_load cannot be used instead because it returns an
|
// unsigned_word, which is limited to the size of the machine's registers.
|
// unsigned_word, which is limited to the size of the machine's registers.
|
//
|
//
|
|
|
:function:::void:do_store_double:address_word base, address_word offset, unsigned64 v
|
:function:::void:do_store_double:address_word base, address_word offset, unsigned64 v
|
*mipsII:
|
*mipsII:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
{
|
{
|
int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
|
int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
|
address_word vaddr;
|
address_word vaddr;
|
address_word paddr;
|
address_word paddr;
|
int uncached;
|
int uncached;
|
unsigned64 memval;
|
unsigned64 memval;
|
|
|
vaddr = loadstore_ea (SD_, base, offset);
|
vaddr = loadstore_ea (SD_, base, offset);
|
if ((vaddr & AccessLength_DOUBLEWORD) != 0)
|
if ((vaddr & AccessLength_DOUBLEWORD) != 0)
|
{
|
{
|
SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map,
|
SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map,
|
AccessLength_DOUBLEWORD + 1, vaddr, write_transfer,
|
AccessLength_DOUBLEWORD + 1, vaddr, write_transfer,
|
sim_core_unaligned_signal);
|
sim_core_unaligned_signal);
|
}
|
}
|
AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET,
|
AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET,
|
isREAL);
|
isREAL);
|
memval = (bigendian ? (v >> 32) : (v & 0xFFFFFFFF));
|
memval = (bigendian ? (v >> 32) : (v & 0xFFFFFFFF));
|
StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
|
StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
|
isREAL);
|
isREAL);
|
memval = (bigendian ? (v & 0xFFFFFFFF) : (v >> 32));
|
memval = (bigendian ? (v & 0xFFFFFFFF) : (v >> 32));
|
StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr + 4, vaddr + 4,
|
StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr + 4, vaddr + 4,
|
isREAL);
|
isREAL);
|
}
|
}
|
|
|
|
|
010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
|
010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
|
"abs.%s f, f"
|
"abs.%s f, f"
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
int fmt = FMT;
|
int fmt = FMT;
|
check_fpu (SD_);
|
check_fpu (SD_);
|
check_fmt_p (SD_, fmt, instruction_0);
|
check_fmt_p (SD_, fmt, instruction_0);
|
StoreFPR (FD, fmt, AbsoluteValue (ValueFPR (FS, fmt), fmt));
|
StoreFPR (FD, fmt, AbsoluteValue (ValueFPR (FS, fmt), fmt));
|
}
|
}
|
|
|
|
|
|
|
010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
|
010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
|
"add.%s f, f, f"
|
"add.%s f, f, f"
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
int fmt = FMT;
|
int fmt = FMT;
|
check_fpu (SD_);
|
check_fpu (SD_);
|
check_fmt_p (SD_, fmt, instruction_0);
|
check_fmt_p (SD_, fmt, instruction_0);
|
StoreFPR (FD, fmt, Add (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
|
StoreFPR (FD, fmt, Add (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
|
}
|
}
|
|
|
|
|
010011,5.RS,5.FT,5.FS,5.FD,011,110:COP1X:32,f::ALNV.PS
|
010011,5.RS,5.FT,5.FS,5.FD,011,110:COP1X:32,f::ALNV.PS
|
"alnv.ps f, f, f, r"
|
"alnv.ps f, f, f, r"
|
*mipsV:
|
*mipsV:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
{
|
{
|
unsigned64 fs;
|
unsigned64 fs;
|
unsigned64 ft;
|
unsigned64 ft;
|
unsigned64 fd;
|
unsigned64 fd;
|
check_fpu (SD_);
|
check_fpu (SD_);
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
fs = ValueFPR (FS, fmt_ps);
|
fs = ValueFPR (FS, fmt_ps);
|
if ((GPR[RS] & 0x3) != 0)
|
if ((GPR[RS] & 0x3) != 0)
|
Unpredictable ();
|
Unpredictable ();
|
if ((GPR[RS] & 0x4) == 0)
|
if ((GPR[RS] & 0x4) == 0)
|
fd = fs;
|
fd = fs;
|
else
|
else
|
{
|
{
|
ft = ValueFPR (FT, fmt_ps);
|
ft = ValueFPR (FT, fmt_ps);
|
if (BigEndianCPU)
|
if (BigEndianCPU)
|
fd = PackPS (PSLower (fs), PSUpper (ft));
|
fd = PackPS (PSLower (fs), PSUpper (ft));
|
else
|
else
|
fd = PackPS (PSLower (ft), PSUpper (fs));
|
fd = PackPS (PSLower (ft), PSUpper (fs));
|
}
|
}
|
StoreFPR (FD, fmt_ps, fd);
|
StoreFPR (FD, fmt_ps, fd);
|
}
|
}
|
|
|
|
|
// BC1F
|
// BC1F
|
// BC1FL
|
// BC1FL
|
// BC1T
|
// BC1T
|
// BC1TL
|
// BC1TL
|
|
|
010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
|
010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
|
"bc1%s%s "
|
"bc1%s%s "
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
{
|
{
|
check_fpu (SD_);
|
check_fpu (SD_);
|
TRACE_BRANCH_INPUT (PREVCOC1());
|
TRACE_BRANCH_INPUT (PREVCOC1());
|
if (PREVCOC1() == TF)
|
if (PREVCOC1() == TF)
|
{
|
{
|
address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
|
address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
|
TRACE_BRANCH_RESULT (dest);
|
TRACE_BRANCH_RESULT (dest);
|
DELAY_SLOT (dest);
|
DELAY_SLOT (dest);
|
}
|
}
|
else if (ND)
|
else if (ND)
|
{
|
{
|
TRACE_BRANCH_RESULT (0);
|
TRACE_BRANCH_RESULT (0);
|
NULLIFY_NEXT_INSTRUCTION ();
|
NULLIFY_NEXT_INSTRUCTION ();
|
}
|
}
|
else
|
else
|
{
|
{
|
TRACE_BRANCH_RESULT (NIA);
|
TRACE_BRANCH_RESULT (NIA);
|
}
|
}
|
}
|
}
|
|
|
010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
|
010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
|
"bc1%s%s ":CC == 0
|
"bc1%s%s ":CC == 0
|
"bc1%s%s , "
|
"bc1%s%s , "
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
#*vr4100:
|
#*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
check_fpu (SD_);
|
check_fpu (SD_);
|
if (GETFCC(CC) == TF)
|
if (GETFCC(CC) == TF)
|
{
|
{
|
address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
|
address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
|
DELAY_SLOT (dest);
|
DELAY_SLOT (dest);
|
}
|
}
|
else if (ND)
|
else if (ND)
|
{
|
{
|
NULLIFY_NEXT_INSTRUCTION ();
|
NULLIFY_NEXT_INSTRUCTION ();
|
}
|
}
|
}
|
}
|
|
|
|
|
010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
|
010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
|
"c.%s.%s f, f"
|
"c.%s.%s f, f"
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
{
|
{
|
int fmt = FMT;
|
int fmt = FMT;
|
check_fpu (SD_);
|
check_fpu (SD_);
|
Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, 0);
|
Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, 0);
|
TRACE_ALU_RESULT (ValueFCR (31));
|
TRACE_ALU_RESULT (ValueFCR (31));
|
}
|
}
|
|
|
010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
|
010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
|
"c.%s.%s f, f":CC == 0
|
"c.%s.%s f, f":CC == 0
|
"c.%s.%s , f, f"
|
"c.%s.%s , f, f"
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
int fmt = FMT;
|
int fmt = FMT;
|
check_fpu (SD_);
|
check_fpu (SD_);
|
check_fmt_p (SD_, fmt, instruction_0);
|
check_fmt_p (SD_, fmt, instruction_0);
|
Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, CC);
|
Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, CC);
|
TRACE_ALU_RESULT (ValueFCR (31));
|
TRACE_ALU_RESULT (ValueFCR (31));
|
}
|
}
|
|
|
|
|
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001010:COP1:32,f::CEIL.L.fmt
|
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001010:COP1:32,f::CEIL.L.fmt
|
"ceil.l.%s f, f"
|
"ceil.l.%s f, f"
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
int fmt = FMT;
|
int fmt = FMT;
|
check_fpu (SD_);
|
check_fpu (SD_);
|
StoreFPR (FD, fmt_long, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
|
StoreFPR (FD, fmt_long, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
|
fmt_long));
|
fmt_long));
|
}
|
}
|
|
|
|
|
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
|
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
|
"ceil.w.%s f, f"
|
"ceil.w.%s f, f"
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
int fmt = FMT;
|
int fmt = FMT;
|
check_fpu (SD_);
|
check_fpu (SD_);
|
StoreFPR (FD, fmt_word, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
|
StoreFPR (FD, fmt_word, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
|
fmt_word));
|
fmt_word));
|
}
|
}
|
|
|
|
|
010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1a
|
010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1a
|
"cfc1 r
|
"cfc1 r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
{
|
{
|
check_fpu (SD_);
|
check_fpu (SD_);
|
if (FS == 0)
|
if (FS == 0)
|
PENDING_FILL (RT, EXTEND32 (FCR0));
|
PENDING_FILL (RT, EXTEND32 (FCR0));
|
else if (FS == 31)
|
else if (FS == 31)
|
PENDING_FILL (RT, EXTEND32 (FCR31));
|
PENDING_FILL (RT, EXTEND32 (FCR31));
|
/* else NOP */
|
/* else NOP */
|
}
|
}
|
|
|
010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1b
|
010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1b
|
"cfc1 r
|
"cfc1 r
|
*mipsIV:
|
*mipsIV:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
check_fpu (SD_);
|
check_fpu (SD_);
|
if (FS == 0 || FS == 31)
|
if (FS == 0 || FS == 31)
|
{
|
{
|
unsigned_word fcr = ValueFCR (FS);
|
unsigned_word fcr = ValueFCR (FS);
|
TRACE_ALU_INPUT1 (fcr);
|
TRACE_ALU_INPUT1 (fcr);
|
GPR[RT] = fcr;
|
GPR[RT] = fcr;
|
}
|
}
|
/* else NOP */
|
/* else NOP */
|
TRACE_ALU_RESULT (GPR[RT]);
|
TRACE_ALU_RESULT (GPR[RT]);
|
}
|
}
|
|
|
010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1c
|
010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1c
|
"cfc1 r
|
"cfc1 r
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
{
|
{
|
check_fpu (SD_);
|
check_fpu (SD_);
|
if (FS == 0 || FS == 25 || FS == 26 || FS == 28 || FS == 31)
|
if (FS == 0 || FS == 25 || FS == 26 || FS == 28 || FS == 31)
|
{
|
{
|
unsigned_word fcr = ValueFCR (FS);
|
unsigned_word fcr = ValueFCR (FS);
|
TRACE_ALU_INPUT1 (fcr);
|
TRACE_ALU_INPUT1 (fcr);
|
GPR[RT] = fcr;
|
GPR[RT] = fcr;
|
}
|
}
|
/* else NOP */
|
/* else NOP */
|
TRACE_ALU_RESULT (GPR[RT]);
|
TRACE_ALU_RESULT (GPR[RT]);
|
}
|
}
|
|
|
010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1a
|
010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1a
|
"ctc1 r
|
"ctc1 r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
{
|
{
|
check_fpu (SD_);
|
check_fpu (SD_);
|
if (FS == 31)
|
if (FS == 31)
|
PENDING_FILL (FCRCS_REGNUM, VL4_8 (GPR[RT]));
|
PENDING_FILL (FCRCS_REGNUM, VL4_8 (GPR[RT]));
|
/* else NOP */
|
/* else NOP */
|
}
|
}
|
|
|
010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1b
|
010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1b
|
"ctc1 r
|
"ctc1 r
|
*mipsIV:
|
*mipsIV:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
check_fpu (SD_);
|
check_fpu (SD_);
|
TRACE_ALU_INPUT1 (GPR[RT]);
|
TRACE_ALU_INPUT1 (GPR[RT]);
|
if (FS == 31)
|
if (FS == 31)
|
StoreFCR (FS, GPR[RT]);
|
StoreFCR (FS, GPR[RT]);
|
/* else NOP */
|
/* else NOP */
|
}
|
}
|
|
|
010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1c
|
010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1c
|
"ctc1 r
|
"ctc1 r
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
{
|
{
|
check_fpu (SD_);
|
check_fpu (SD_);
|
TRACE_ALU_INPUT1 (GPR[RT]);
|
TRACE_ALU_INPUT1 (GPR[RT]);
|
if (FS == 25 || FS == 26 || FS == 28 || FS == 31)
|
if (FS == 25 || FS == 26 || FS == 28 || FS == 31)
|
StoreFCR (FS, GPR[RT]);
|
StoreFCR (FS, GPR[RT]);
|
/* else NOP */
|
/* else NOP */
|
}
|
}
|
|
|
|
|
//
|
//
|
// FIXME: Does not correctly differentiate between mips*
|
// FIXME: Does not correctly differentiate between mips*
|
//
|
//
|
010001,10,3.FMT!1!2!3!6!7,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
|
010001,10,3.FMT!1!2!3!6!7,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
|
"cvt.d.%s f, f"
|
"cvt.d.%s f, f"
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
int fmt = FMT;
|
int fmt = FMT;
|
check_fpu (SD_);
|
check_fpu (SD_);
|
if ((fmt == fmt_double) | 0)
|
if ((fmt == fmt_double) | 0)
|
SignalException (ReservedInstruction, instruction_0);
|
SignalException (ReservedInstruction, instruction_0);
|
StoreFPR (FD, fmt_double, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
|
StoreFPR (FD, fmt_double, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
|
fmt_double));
|
fmt_double));
|
}
|
}
|
|
|
|
|
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100101:COP1:32,f::CVT.L.fmt
|
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100101:COP1:32,f::CVT.L.fmt
|
"cvt.l.%s f, f"
|
"cvt.l.%s f, f"
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
int fmt = FMT;
|
int fmt = FMT;
|
check_fpu (SD_);
|
check_fpu (SD_);
|
if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
|
if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
|
SignalException (ReservedInstruction, instruction_0);
|
SignalException (ReservedInstruction, instruction_0);
|
StoreFPR (FD, fmt_long, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
|
StoreFPR (FD, fmt_long, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
|
fmt_long));
|
fmt_long));
|
}
|
}
|
|
|
|
|
010001,10,000,5.FT,5.FS,5.FD,100110:COP1:32,f::CVT.PS.S
|
010001,10,000,5.FT,5.FS,5.FD,100110:COP1:32,f::CVT.PS.S
|
"cvt.ps.s f, f, f"
|
"cvt.ps.s f, f, f"
|
*mipsV:
|
*mipsV:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
{
|
{
|
check_fpu (SD_);
|
check_fpu (SD_);
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
StoreFPR (FD, fmt_ps, PackPS (ValueFPR (FS, fmt_single),
|
StoreFPR (FD, fmt_ps, PackPS (ValueFPR (FS, fmt_single),
|
ValueFPR (FT, fmt_single)));
|
ValueFPR (FT, fmt_single)));
|
}
|
}
|
|
|
|
|
//
|
//
|
// FIXME: Does not correctly differentiate between mips*
|
// FIXME: Does not correctly differentiate between mips*
|
//
|
//
|
010001,10,3.FMT!0!2!3!6!7,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
|
010001,10,3.FMT!0!2!3!6!7,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
|
"cvt.s.%s f, f"
|
"cvt.s.%s f, f"
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
int fmt = FMT;
|
int fmt = FMT;
|
check_fpu (SD_);
|
check_fpu (SD_);
|
if ((fmt == fmt_single) | 0)
|
if ((fmt == fmt_single) | 0)
|
SignalException (ReservedInstruction, instruction_0);
|
SignalException (ReservedInstruction, instruction_0);
|
StoreFPR (FD, fmt_single, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
|
StoreFPR (FD, fmt_single, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
|
fmt_single));
|
fmt_single));
|
}
|
}
|
|
|
|
|
010001,10,110,00000,5.FS,5.FD,101000:COP1:32,f::CVT.S.PL
|
010001,10,110,00000,5.FS,5.FD,101000:COP1:32,f::CVT.S.PL
|
"cvt.s.pl f, f"
|
"cvt.s.pl f, f"
|
*mipsV:
|
*mipsV:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
{
|
{
|
check_fpu (SD_);
|
check_fpu (SD_);
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
StoreFPR (FD, fmt_single, PSLower (ValueFPR (FS, fmt_ps)));
|
StoreFPR (FD, fmt_single, PSLower (ValueFPR (FS, fmt_ps)));
|
}
|
}
|
|
|
|
|
010001,10,110,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.PU
|
010001,10,110,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.PU
|
"cvt.s.pu f, f"
|
"cvt.s.pu f, f"
|
*mipsV:
|
*mipsV:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
{
|
{
|
check_fpu (SD_);
|
check_fpu (SD_);
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
StoreFPR (FD, fmt_single, PSUpper (ValueFPR (FS, fmt_ps)));
|
StoreFPR (FD, fmt_single, PSUpper (ValueFPR (FS, fmt_ps)));
|
}
|
}
|
|
|
|
|
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
|
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
|
"cvt.w.%s f, f"
|
"cvt.w.%s f, f"
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
int fmt = FMT;
|
int fmt = FMT;
|
check_fpu (SD_);
|
check_fpu (SD_);
|
if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
|
if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
|
SignalException (ReservedInstruction, instruction_0);
|
SignalException (ReservedInstruction, instruction_0);
|
StoreFPR (FD, fmt_word, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
|
StoreFPR (FD, fmt_word, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
|
fmt_word));
|
fmt_word));
|
}
|
}
|
|
|
|
|
010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
|
010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
|
"div.%s f, f, f"
|
"div.%s f, f, f"
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
int fmt = FMT;
|
int fmt = FMT;
|
check_fpu (SD_);
|
check_fpu (SD_);
|
StoreFPR (FD, fmt, Divide (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
|
StoreFPR (FD, fmt, Divide (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
|
}
|
}
|
|
|
|
|
010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1a
|
010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1a
|
"dmfc1 r
|
"dmfc1 r
|
*mipsIII:
|
*mipsIII:
|
{
|
{
|
unsigned64 v;
|
unsigned64 v;
|
check_fpu (SD_);
|
check_fpu (SD_);
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
if (SizeFGR () == 64)
|
if (SizeFGR () == 64)
|
v = FGR[FS];
|
v = FGR[FS];
|
else if ((FS & 0x1) == 0)
|
else if ((FS & 0x1) == 0)
|
v = SET64HI (FGR[FS+1]) | FGR[FS];
|
v = SET64HI (FGR[FS+1]) | FGR[FS];
|
else
|
else
|
v = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
|
v = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
|
PENDING_FILL (RT, v);
|
PENDING_FILL (RT, v);
|
TRACE_ALU_RESULT (v);
|
TRACE_ALU_RESULT (v);
|
}
|
}
|
|
|
010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1b
|
010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1b
|
"dmfc1 r
|
"dmfc1 r
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
check_fpu (SD_);
|
check_fpu (SD_);
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
if (SizeFGR () == 64)
|
if (SizeFGR () == 64)
|
GPR[RT] = FGR[FS];
|
GPR[RT] = FGR[FS];
|
else if ((FS & 0x1) == 0)
|
else if ((FS & 0x1) == 0)
|
GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
|
GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
|
else
|
else
|
GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
|
GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
|
TRACE_ALU_RESULT (GPR[RT]);
|
TRACE_ALU_RESULT (GPR[RT]);
|
}
|
}
|
|
|
|
|
010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1a
|
010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1a
|
"dmtc1 r
|
"dmtc1 r
|
*mipsIII:
|
*mipsIII:
|
{
|
{
|
unsigned64 v;
|
unsigned64 v;
|
check_fpu (SD_);
|
check_fpu (SD_);
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
if (SizeFGR () == 64)
|
if (SizeFGR () == 64)
|
PENDING_FILL ((FS + FGR_BASE), GPR[RT]);
|
PENDING_FILL ((FS + FGR_BASE), GPR[RT]);
|
else if ((FS & 0x1) == 0)
|
else if ((FS & 0x1) == 0)
|
{
|
{
|
PENDING_FILL (((FS + 1) + FGR_BASE), VH4_8 (GPR[RT]));
|
PENDING_FILL (((FS + 1) + FGR_BASE), VH4_8 (GPR[RT]));
|
PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
|
PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
|
}
|
}
|
else
|
else
|
Unpredictable ();
|
Unpredictable ();
|
TRACE_FP_RESULT (GPR[RT]);
|
TRACE_FP_RESULT (GPR[RT]);
|
}
|
}
|
|
|
010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1b
|
010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1b
|
"dmtc1 r
|
"dmtc1 r
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
check_fpu (SD_);
|
check_fpu (SD_);
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
if (SizeFGR () == 64)
|
if (SizeFGR () == 64)
|
StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
|
StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
|
else if ((FS & 0x1) == 0)
|
else if ((FS & 0x1) == 0)
|
StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
|
StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
|
else
|
else
|
Unpredictable ();
|
Unpredictable ();
|
}
|
}
|
|
|
|
|
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001011:COP1:32,f::FLOOR.L.fmt
|
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001011:COP1:32,f::FLOOR.L.fmt
|
"floor.l.%s f, f"
|
"floor.l.%s f, f"
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
int fmt = FMT;
|
int fmt = FMT;
|
check_fpu (SD_);
|
check_fpu (SD_);
|
StoreFPR (FD, fmt_long, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
|
StoreFPR (FD, fmt_long, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
|
fmt_long));
|
fmt_long));
|
}
|
}
|
|
|
|
|
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
|
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
|
"floor.w.%s f, f"
|
"floor.w.%s f, f"
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
int fmt = FMT;
|
int fmt = FMT;
|
check_fpu (SD_);
|
check_fpu (SD_);
|
StoreFPR (FD, fmt_word, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
|
StoreFPR (FD, fmt_word, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
|
fmt_word));
|
fmt_word));
|
}
|
}
|
|
|
|
|
110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1a
|
110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1a
|
"ldc1 f, (r)"
|
"ldc1 f, (r)"
|
*mipsII:
|
*mipsII:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
{
|
{
|
check_fpu (SD_);
|
check_fpu (SD_);
|
COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (OFFSET)));
|
COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (OFFSET)));
|
}
|
}
|
|
|
|
|
110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1b
|
110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1b
|
"ldc1 f, (r)"
|
"ldc1 f, (r)"
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
check_fpu (SD_);
|
check_fpu (SD_);
|
COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
|
COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
|
}
|
}
|
|
|
|
|
010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:32,f::LDXC1
|
010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:32,f::LDXC1
|
"ldxc1 f, r(r)"
|
"ldxc1 f, r(r)"
|
*mips32r2:
|
*mips32r2:
|
{
|
{
|
check_fpu (SD_);
|
check_fpu (SD_);
|
COP_LD (1, FD, do_load_double (SD_, GPR[BASE], GPR[INDEX]));
|
COP_LD (1, FD, do_load_double (SD_, GPR[BASE], GPR[INDEX]));
|
}
|
}
|
|
|
|
|
010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1
|
010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1
|
"ldxc1 f, r(r)"
|
"ldxc1 f, r(r)"
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
check_fpu (SD_);
|
check_fpu (SD_);
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
|
COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
|
}
|
}
|
|
|
|
|
010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:32,f::LUXC1
|
010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:32,f::LUXC1
|
"luxc1 f, r(r)"
|
"luxc1 f, r(r)"
|
*mips32r2:
|
*mips32r2:
|
{
|
{
|
address_word base = GPR[BASE];
|
address_word base = GPR[BASE];
|
address_word index = GPR[INDEX];
|
address_word index = GPR[INDEX];
|
address_word vaddr = base + index;
|
address_word vaddr = base + index;
|
check_fpu (SD_);
|
check_fpu (SD_);
|
if (SizeFGR () != 64)
|
if (SizeFGR () != 64)
|
Unpredictable ();
|
Unpredictable ();
|
/* Arrange for the bottom 3 bits of (base + index) to be 0. */
|
/* Arrange for the bottom 3 bits of (base + index) to be 0. */
|
if ((vaddr & 0x7) != 0)
|
if ((vaddr & 0x7) != 0)
|
index -= (vaddr & 0x7);
|
index -= (vaddr & 0x7);
|
COP_LD (1, FD, do_load_double (SD_, base, index));
|
COP_LD (1, FD, do_load_double (SD_, base, index));
|
}
|
}
|
|
|
|
|
010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64,f::LUXC1
|
010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64,f::LUXC1
|
"luxc1 f, r(r)"
|
"luxc1 f, r(r)"
|
*mipsV:
|
*mipsV:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
{
|
{
|
address_word base = GPR[BASE];
|
address_word base = GPR[BASE];
|
address_word index = GPR[INDEX];
|
address_word index = GPR[INDEX];
|
address_word vaddr = base + index;
|
address_word vaddr = base + index;
|
check_fpu (SD_);
|
check_fpu (SD_);
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
if (SizeFGR () != 64)
|
if (SizeFGR () != 64)
|
Unpredictable ();
|
Unpredictable ();
|
/* Arrange for the bottom 3 bits of (base + index) to be 0. */
|
/* Arrange for the bottom 3 bits of (base + index) to be 0. */
|
if ((vaddr & 0x7) != 0)
|
if ((vaddr & 0x7) != 0)
|
index -= (vaddr & 0x7);
|
index -= (vaddr & 0x7);
|
COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, base, index));
|
COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, base, index));
|
}
|
}
|
|
|
|
|
110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
|
110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
|
"lwc1 f, (r)"
|
"lwc1 f, (r)"
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
check_fpu (SD_);
|
check_fpu (SD_);
|
COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
|
COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
|
}
|
}
|
|
|
|
|
010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32,f::LWXC1
|
010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32,f::LWXC1
|
"lwxc1 f, r(r)"
|
"lwxc1 f, r(r)"
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
check_fpu (SD_);
|
check_fpu (SD_);
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
|
COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
|
}
|
}
|
|
|
|
|
|
|
010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT!2!3!4!5!7:COP1X:32,f::MADD.fmt
|
010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT!2!3!4!5!7:COP1X:32,f::MADD.fmt
|
"madd.%s f, f, f, f"
|
"madd.%s f, f, f, f"
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
int fmt = FMT;
|
int fmt = FMT;
|
check_fpu (SD_);
|
check_fpu (SD_);
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
check_fmt_p (SD_, fmt, instruction_0);
|
check_fmt_p (SD_, fmt, instruction_0);
|
StoreFPR (FD, fmt, MultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
|
StoreFPR (FD, fmt, MultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
|
ValueFPR (FR, fmt), fmt));
|
ValueFPR (FR, fmt), fmt));
|
}
|
}
|
|
|
|
|
010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1a
|
010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1a
|
"mfc1 r
|
"mfc1 r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
{
|
{
|
unsigned64 v;
|
unsigned64 v;
|
check_fpu (SD_);
|
check_fpu (SD_);
|
v = EXTEND32 (FGR[FS]);
|
v = EXTEND32 (FGR[FS]);
|
PENDING_FILL (RT, v);
|
PENDING_FILL (RT, v);
|
TRACE_ALU_RESULT (v);
|
TRACE_ALU_RESULT (v);
|
}
|
}
|
|
|
010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1b
|
010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1b
|
"mfc1 r
|
"mfc1 r
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
check_fpu (SD_);
|
check_fpu (SD_);
|
GPR[RT] = EXTEND32 (FGR[FS]);
|
GPR[RT] = EXTEND32 (FGR[FS]);
|
TRACE_ALU_RESULT (GPR[RT]);
|
TRACE_ALU_RESULT (GPR[RT]);
|
}
|
}
|
|
|
|
|
010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
|
010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
|
"mov.%s f, f"
|
"mov.%s f, f"
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
int fmt = FMT;
|
int fmt = FMT;
|
check_fpu (SD_);
|
check_fpu (SD_);
|
check_fmt_p (SD_, fmt, instruction_0);
|
check_fmt_p (SD_, fmt, instruction_0);
|
StoreFPR (FD, fmt, ValueFPR (FS, fmt));
|
StoreFPR (FD, fmt, ValueFPR (FS, fmt));
|
}
|
}
|
|
|
|
|
// MOVF
|
// MOVF
|
// MOVT
|
// MOVT
|
000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf
|
000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf
|
"mov%s r, r, "
|
"mov%s r, r, "
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
check_fpu (SD_);
|
check_fpu (SD_);
|
if (GETFCC(CC) == TF)
|
if (GETFCC(CC) == TF)
|
GPR[RD] = GPR[RS];
|
GPR[RD] = GPR[RS];
|
}
|
}
|
|
|
|
|
// MOVF.fmt
|
// MOVF.fmt
|
// MOVT.fmt
|
// MOVT.fmt
|
010001,10,3.FMT!2!3!4!5!7,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
|
010001,10,3.FMT!2!3!4!5!7,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
|
"mov%s.%s f, f, "
|
"mov%s.%s f, f, "
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
int fmt = FMT;
|
int fmt = FMT;
|
check_fpu (SD_);
|
check_fpu (SD_);
|
if (fmt != fmt_ps)
|
if (fmt != fmt_ps)
|
{
|
{
|
if (GETFCC(CC) == TF)
|
if (GETFCC(CC) == TF)
|
StoreFPR (FD, fmt, ValueFPR (FS, fmt));
|
StoreFPR (FD, fmt, ValueFPR (FS, fmt));
|
else
|
else
|
StoreFPR (FD, fmt, ValueFPR (FD, fmt)); /* set fmt */
|
StoreFPR (FD, fmt, ValueFPR (FD, fmt)); /* set fmt */
|
}
|
}
|
else
|
else
|
{
|
{
|
unsigned64 fd;
|
unsigned64 fd;
|
fd = PackPS (PSUpper (ValueFPR ((GETFCC (CC+1) == TF) ? FS : FD,
|
fd = PackPS (PSUpper (ValueFPR ((GETFCC (CC+1) == TF) ? FS : FD,
|
fmt_ps)),
|
fmt_ps)),
|
PSLower (ValueFPR ((GETFCC (CC+0) == TF) ? FS : FD,
|
PSLower (ValueFPR ((GETFCC (CC+0) == TF) ? FS : FD,
|
fmt_ps)));
|
fmt_ps)));
|
StoreFPR (FD, fmt_ps, fd);
|
StoreFPR (FD, fmt_ps, fd);
|
}
|
}
|
}
|
}
|
|
|
|
|
010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
|
010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
|
"movn.%s f, f, r
|
"movn.%s f, f, r
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
check_fpu (SD_);
|
check_fpu (SD_);
|
if (GPR[RT] != 0)
|
if (GPR[RT] != 0)
|
StoreFPR (FD, FMT, ValueFPR (FS, FMT));
|
StoreFPR (FD, FMT, ValueFPR (FS, FMT));
|
else
|
else
|
StoreFPR (FD, FMT, ValueFPR (FD, FMT));
|
StoreFPR (FD, FMT, ValueFPR (FD, FMT));
|
}
|
}
|
|
|
|
|
// MOVT see MOVtf
|
// MOVT see MOVtf
|
|
|
|
|
// MOVT.fmt see MOVtf.fmt
|
// MOVT.fmt see MOVtf.fmt
|
|
|
|
|
|
|
010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
|
010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
|
"movz.%s f, f, r
|
"movz.%s f, f, r
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
check_fpu (SD_);
|
check_fpu (SD_);
|
if (GPR[RT] == 0)
|
if (GPR[RT] == 0)
|
StoreFPR (FD, FMT, ValueFPR (FS, FMT));
|
StoreFPR (FD, FMT, ValueFPR (FS, FMT));
|
else
|
else
|
StoreFPR (FD, FMT, ValueFPR (FD, FMT));
|
StoreFPR (FD, FMT, ValueFPR (FD, FMT));
|
}
|
}
|
|
|
|
|
010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT!2!3!4!5!7:COP1X:32,f::MSUB.fmt
|
010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT!2!3!4!5!7:COP1X:32,f::MSUB.fmt
|
"msub.%s f, f, f, f"
|
"msub.%s f, f, f, f"
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
int fmt = FMT;
|
int fmt = FMT;
|
check_fpu (SD_);
|
check_fpu (SD_);
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
check_fmt_p (SD_, fmt, instruction_0);
|
check_fmt_p (SD_, fmt, instruction_0);
|
StoreFPR (FD, fmt, MultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
|
StoreFPR (FD, fmt, MultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
|
ValueFPR (FR, fmt), fmt));
|
ValueFPR (FR, fmt), fmt));
|
}
|
}
|
|
|
|
|
010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1a
|
010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1a
|
"mtc1 r
|
"mtc1 r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
{
|
{
|
check_fpu (SD_);
|
check_fpu (SD_);
|
if (SizeFGR () == 64)
|
if (SizeFGR () == 64)
|
PENDING_FILL ((FS + FGR_BASE), (SET64HI (0xDEADC0DE) | VL4_8 (GPR[RT])));
|
PENDING_FILL ((FS + FGR_BASE), (SET64HI (0xDEADC0DE) | VL4_8 (GPR[RT])));
|
else
|
else
|
PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
|
PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
|
TRACE_FP_RESULT (GPR[RT]);
|
TRACE_FP_RESULT (GPR[RT]);
|
}
|
}
|
|
|
010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1b
|
010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1b
|
"mtc1 r
|
"mtc1 r
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
check_fpu (SD_);
|
check_fpu (SD_);
|
StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
|
StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
|
}
|
}
|
|
|
|
|
010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
|
010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
|
"mul.%s f, f, f"
|
"mul.%s f, f, f"
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
int fmt = FMT;
|
int fmt = FMT;
|
check_fpu (SD_);
|
check_fpu (SD_);
|
check_fmt_p (SD_, fmt, instruction_0);
|
check_fmt_p (SD_, fmt, instruction_0);
|
StoreFPR (FD, fmt, Multiply (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
|
StoreFPR (FD, fmt, Multiply (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
|
}
|
}
|
|
|
|
|
010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
|
010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
|
"neg.%s f, f"
|
"neg.%s f, f"
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
int fmt = FMT;
|
int fmt = FMT;
|
check_fpu (SD_);
|
check_fpu (SD_);
|
check_fmt_p (SD_, fmt, instruction_0);
|
check_fmt_p (SD_, fmt, instruction_0);
|
StoreFPR (FD, fmt, Negate (ValueFPR (FS, fmt), fmt));
|
StoreFPR (FD, fmt, Negate (ValueFPR (FS, fmt), fmt));
|
}
|
}
|
|
|
|
|
010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT!2!3!4!5!7:COP1X:32,f::NMADD.fmt
|
010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT!2!3!4!5!7:COP1X:32,f::NMADD.fmt
|
"nmadd.%s f, f, f, f"
|
"nmadd.%s f, f, f, f"
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
int fmt = FMT;
|
int fmt = FMT;
|
check_fpu (SD_);
|
check_fpu (SD_);
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
check_fmt_p (SD_, fmt, instruction_0);
|
check_fmt_p (SD_, fmt, instruction_0);
|
StoreFPR (FD, fmt, NegMultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
|
StoreFPR (FD, fmt, NegMultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
|
ValueFPR (FR, fmt), fmt));
|
ValueFPR (FR, fmt), fmt));
|
}
|
}
|
|
|
|
|
010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT!2!3!4!5!7:COP1X:32,f::NMSUB.fmt
|
010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT!2!3!4!5!7:COP1X:32,f::NMSUB.fmt
|
"nmsub.%s f, f, f, f"
|
"nmsub.%s f, f, f, f"
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
int fmt = FMT;
|
int fmt = FMT;
|
check_fpu (SD_);
|
check_fpu (SD_);
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
check_fmt_p (SD_, fmt, instruction_0);
|
check_fmt_p (SD_, fmt, instruction_0);
|
StoreFPR (FD, fmt, NegMultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
|
StoreFPR (FD, fmt, NegMultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
|
ValueFPR (FR, fmt), fmt));
|
ValueFPR (FR, fmt), fmt));
|
}
|
}
|
|
|
|
|
010001,10,110,5.FT,5.FS,5.FD,101100:COP1:32,f::PLL.PS
|
010001,10,110,5.FT,5.FS,5.FD,101100:COP1:32,f::PLL.PS
|
"pll.ps f, f, f"
|
"pll.ps f, f, f"
|
*mipsV:
|
*mipsV:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
{
|
{
|
check_fpu (SD_);
|
check_fpu (SD_);
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
|
StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
|
PSLower (ValueFPR (FT, fmt_ps))));
|
PSLower (ValueFPR (FT, fmt_ps))));
|
}
|
}
|
|
|
|
|
010001,10,110,5.FT,5.FS,5.FD,101101:COP1:32,f::PLU.PS
|
010001,10,110,5.FT,5.FS,5.FD,101101:COP1:32,f::PLU.PS
|
"plu.ps f, f, f"
|
"plu.ps f, f, f"
|
*mipsV:
|
*mipsV:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
{
|
{
|
check_fpu (SD_);
|
check_fpu (SD_);
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
|
StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
|
PSUpper (ValueFPR (FT, fmt_ps))));
|
PSUpper (ValueFPR (FT, fmt_ps))));
|
}
|
}
|
|
|
|
|
010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:32::PREFX
|
010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:32::PREFX
|
"prefx , r(r)"
|
"prefx , r(r)"
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
address_word base = GPR[BASE];
|
address_word base = GPR[BASE];
|
address_word index = GPR[INDEX];
|
address_word index = GPR[INDEX];
|
{
|
{
|
address_word vaddr = loadstore_ea (SD_, base, index);
|
address_word vaddr = loadstore_ea (SD_, base, index);
|
address_word paddr;
|
address_word paddr;
|
int uncached;
|
int uncached;
|
if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
|
if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
|
Prefetch(uncached,paddr,vaddr,isDATA,HINT);
|
Prefetch(uncached,paddr,vaddr,isDATA,HINT);
|
}
|
}
|
}
|
}
|
|
|
|
|
010001,10,110,5.FT,5.FS,5.FD,101110:COP1:32,f::PUL.PS
|
010001,10,110,5.FT,5.FS,5.FD,101110:COP1:32,f::PUL.PS
|
"pul.ps f, f, f"
|
"pul.ps f, f, f"
|
*mipsV:
|
*mipsV:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
{
|
{
|
check_fpu (SD_);
|
check_fpu (SD_);
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
|
StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
|
PSLower (ValueFPR (FT, fmt_ps))));
|
PSLower (ValueFPR (FT, fmt_ps))));
|
}
|
}
|
|
|
|
|
010001,10,110,5.FT,5.FS,5.FD,101111:COP1:32,f::PUU.PS
|
010001,10,110,5.FT,5.FS,5.FD,101111:COP1:32,f::PUU.PS
|
"puu.ps f, f, f"
|
"puu.ps f, f, f"
|
*mipsV:
|
*mipsV:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
{
|
{
|
check_fpu (SD_);
|
check_fpu (SD_);
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
|
StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
|
PSUpper (ValueFPR (FT, fmt_ps))));
|
PSUpper (ValueFPR (FT, fmt_ps))));
|
}
|
}
|
|
|
|
|
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
|
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
|
"recip.%s f, f"
|
"recip.%s f, f"
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
int fmt = FMT;
|
int fmt = FMT;
|
check_fpu (SD_);
|
check_fpu (SD_);
|
StoreFPR (FD, fmt, Recip (ValueFPR (FS, fmt), fmt));
|
StoreFPR (FD, fmt, Recip (ValueFPR (FS, fmt), fmt));
|
}
|
}
|
|
|
|
|
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001000:COP1:32,f::ROUND.L.fmt
|
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001000:COP1:32,f::ROUND.L.fmt
|
"round.l.%s f, f"
|
"round.l.%s f, f"
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
int fmt = FMT;
|
int fmt = FMT;
|
check_fpu (SD_);
|
check_fpu (SD_);
|
StoreFPR (FD, fmt_long, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
|
StoreFPR (FD, fmt_long, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
|
fmt_long));
|
fmt_long));
|
}
|
}
|
|
|
|
|
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
|
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
|
"round.w.%s f, f"
|
"round.w.%s f, f"
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
int fmt = FMT;
|
int fmt = FMT;
|
check_fpu (SD_);
|
check_fpu (SD_);
|
StoreFPR (FD, fmt_word, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
|
StoreFPR (FD, fmt_word, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
|
fmt_word));
|
fmt_word));
|
}
|
}
|
|
|
|
|
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
|
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
|
"rsqrt.%s f, f"
|
"rsqrt.%s f, f"
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
int fmt = FMT;
|
int fmt = FMT;
|
check_fpu (SD_);
|
check_fpu (SD_);
|
StoreFPR (FD, fmt, RSquareRoot (ValueFPR (FS, fmt), fmt));
|
StoreFPR (FD, fmt, RSquareRoot (ValueFPR (FS, fmt), fmt));
|
}
|
}
|
|
|
|
|
111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1a
|
111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1a
|
"sdc1 f, (r)"
|
"sdc1 f, (r)"
|
*mipsII:
|
*mipsII:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
{
|
{
|
check_fpu (SD_);
|
check_fpu (SD_);
|
do_store_double (SD_, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
|
do_store_double (SD_, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
|
}
|
}
|
|
|
|
|
111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1b
|
111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1b
|
"sdc1 f, (r)"
|
"sdc1 f, (r)"
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
check_fpu (SD_);
|
check_fpu (SD_);
|
do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
|
do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
|
}
|
}
|
|
|
|
|
010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:32,f::SDXC1
|
010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:32,f::SDXC1
|
"sdxc1 f, r(r)"
|
"sdxc1 f, r(r)"
|
*mips32r2
|
*mips32r2
|
{
|
{
|
check_fpu (SD_);
|
check_fpu (SD_);
|
do_store_double (SD_, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
|
do_store_double (SD_, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
|
}
|
}
|
|
|
|
|
010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1
|
010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1
|
"sdxc1 f, r(r)"
|
"sdxc1 f, r(r)"
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
check_fpu (SD_);
|
check_fpu (SD_);
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
|
do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
|
}
|
}
|
|
|
|
|
010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:32,f::SUXC1
|
010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:32,f::SUXC1
|
"suxc1 f, r(r)"
|
"suxc1 f, r(r)"
|
*mips32r2:
|
*mips32r2:
|
{
|
{
|
address_word base = GPR[BASE];
|
address_word base = GPR[BASE];
|
address_word index = GPR[INDEX];
|
address_word index = GPR[INDEX];
|
address_word vaddr = base + index;
|
address_word vaddr = base + index;
|
check_fpu (SD_);
|
check_fpu (SD_);
|
if (SizeFGR () != 64)
|
if (SizeFGR () != 64)
|
Unpredictable ();
|
Unpredictable ();
|
/* Arrange for the bottom 3 bits of (base + index) to be 0. */
|
/* Arrange for the bottom 3 bits of (base + index) to be 0. */
|
if ((vaddr & 0x7) != 0)
|
if ((vaddr & 0x7) != 0)
|
index -= (vaddr & 0x7);
|
index -= (vaddr & 0x7);
|
do_store_double (SD_, base, index, COP_SD (1, FS));
|
do_store_double (SD_, base, index, COP_SD (1, FS));
|
}
|
}
|
|
|
|
|
010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:64,f::SUXC1
|
010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:64,f::SUXC1
|
"suxc1 f, r(r)"
|
"suxc1 f, r(r)"
|
*mipsV:
|
*mipsV:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
{
|
{
|
address_word base = GPR[BASE];
|
address_word base = GPR[BASE];
|
address_word index = GPR[INDEX];
|
address_word index = GPR[INDEX];
|
address_word vaddr = base + index;
|
address_word vaddr = base + index;
|
check_fpu (SD_);
|
check_fpu (SD_);
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
if (SizeFGR () != 64)
|
if (SizeFGR () != 64)
|
Unpredictable ();
|
Unpredictable ();
|
/* Arrange for the bottom 3 bits of (base + index) to be 0. */
|
/* Arrange for the bottom 3 bits of (base + index) to be 0. */
|
if ((vaddr & 0x7) != 0)
|
if ((vaddr & 0x7) != 0)
|
index -= (vaddr & 0x7);
|
index -= (vaddr & 0x7);
|
do_store (SD_, AccessLength_DOUBLEWORD, base, index, COP_SD (1, FS));
|
do_store (SD_, AccessLength_DOUBLEWORD, base, index, COP_SD (1, FS));
|
}
|
}
|
|
|
|
|
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
|
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
|
"sqrt.%s f, f"
|
"sqrt.%s f, f"
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
int fmt = FMT;
|
int fmt = FMT;
|
check_fpu (SD_);
|
check_fpu (SD_);
|
StoreFPR (FD, fmt, (SquareRoot (ValueFPR (FS, fmt), fmt)));
|
StoreFPR (FD, fmt, (SquareRoot (ValueFPR (FS, fmt), fmt)));
|
}
|
}
|
|
|
|
|
010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
|
010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
|
"sub.%s f, f, f"
|
"sub.%s f, f, f"
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
int fmt = FMT;
|
int fmt = FMT;
|
check_fpu (SD_);
|
check_fpu (SD_);
|
check_fmt_p (SD_, fmt, instruction_0);
|
check_fmt_p (SD_, fmt, instruction_0);
|
StoreFPR (FD, fmt, Sub (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
|
StoreFPR (FD, fmt, Sub (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
|
}
|
}
|
|
|
|
|
|
|
111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1
|
111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1
|
"swc1 f, (r)"
|
"swc1 f, (r)"
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
address_word base = GPR[BASE];
|
address_word base = GPR[BASE];
|
address_word offset = EXTEND16 (OFFSET);
|
address_word offset = EXTEND16 (OFFSET);
|
check_fpu (SD_);
|
check_fpu (SD_);
|
{
|
{
|
address_word vaddr = loadstore_ea (SD_, base, offset);
|
address_word vaddr = loadstore_ea (SD_, base, offset);
|
address_word paddr;
|
address_word paddr;
|
int uncached;
|
int uncached;
|
if ((vaddr & 3) != 0)
|
if ((vaddr & 3) != 0)
|
{
|
{
|
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
|
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
|
}
|
}
|
else
|
else
|
{
|
{
|
if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
|
if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
|
{
|
{
|
uword64 memval = 0;
|
uword64 memval = 0;
|
uword64 memval1 = 0;
|
uword64 memval1 = 0;
|
uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
|
uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
|
address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
|
address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
|
address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
|
address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
|
unsigned int byte;
|
unsigned int byte;
|
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
|
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
|
byte = ((vaddr & mask) ^ bigendiancpu);
|
byte = ((vaddr & mask) ^ bigendiancpu);
|
memval = (((uword64)COP_SW(((instruction_0 >> 26) & 0x3),FT)) << (8 * byte));
|
memval = (((uword64)COP_SW(((instruction_0 >> 26) & 0x3),FT)) << (8 * byte));
|
StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
|
StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
|
|
010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1
|
010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1
|
"swxc1 f, r(r)"
|
"swxc1 f, r(r)"
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
|
|
address_word base = GPR[BASE];
|
address_word base = GPR[BASE];
|
address_word index = GPR[INDEX];
|
address_word index = GPR[INDEX];
|
check_fpu (SD_);
|
check_fpu (SD_);
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
{
|
{
|
address_word vaddr = loadstore_ea (SD_, base, index);
|
address_word vaddr = loadstore_ea (SD_, base, index);
|
address_word paddr;
|
address_word paddr;
|
int uncached;
|
int uncached;
|
if ((vaddr & 3) != 0)
|
if ((vaddr & 3) != 0)
|
{
|
{
|
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
|
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
|
}
|
}
|
else
|
else
|
{
|
{
|
if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
|
if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
|
{
|
{
|
unsigned64 memval = 0;
|
unsigned64 memval = 0;
|
unsigned64 memval1 = 0;
|
unsigned64 memval1 = 0;
|
unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
|
unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
|
address_word reverseendian = (ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
|
address_word reverseendian = (ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
|
address_word bigendiancpu = (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0);
|
address_word bigendiancpu = (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0);
|
unsigned int byte;
|
unsigned int byte;
|
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
|
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
|
byte = ((vaddr & mask) ^ bigendiancpu);
|
byte = ((vaddr & mask) ^ bigendiancpu);
|
memval = (((unsigned64)COP_SW(1,FS)) << (8 * byte));
|
memval = (((unsigned64)COP_SW(1,FS)) << (8 * byte));
|
{
|
{
|
StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
|
StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
|
|
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001001:COP1:32,f::TRUNC.L.fmt
|
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001001:COP1:32,f::TRUNC.L.fmt
|
"trunc.l.%s f, f"
|
"trunc.l.%s f, f"
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
int fmt = FMT;
|
int fmt = FMT;
|
check_fpu (SD_);
|
check_fpu (SD_);
|
StoreFPR (FD, fmt_long, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
|
StoreFPR (FD, fmt_long, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
|
fmt_long));
|
fmt_long));
|
}
|
}
|
|
|
|
|
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
|
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
|
"trunc.w.%s f, f"
|
"trunc.w.%s f, f"
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
int fmt = FMT;
|
int fmt = FMT;
|
check_fpu (SD_);
|
check_fpu (SD_);
|
StoreFPR (FD, fmt_word, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
|
StoreFPR (FD, fmt_word, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
|
fmt_word));
|
fmt_word));
|
}
|
}
|
|
|
|
|
//
|
//
|
// MIPS Architecture:
|
// MIPS Architecture:
|
//
|
//
|
// System Control Instruction Set (COP0)
|
// System Control Instruction Set (COP0)
|
//
|
//
|
|
|
|
|
010000,01000,00000,16.OFFSET:COP0:32::BC0F
|
010000,01000,00000,16.OFFSET:COP0:32::BC0F
|
"bc0f "
|
"bc0f "
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
|
|
010000,01000,00000,16.OFFSET:COP0:32::BC0F
|
010000,01000,00000,16.OFFSET:COP0:32::BC0F
|
"bc0f "
|
"bc0f "
|
// stub needed for eCos as tx39 hardware bug workaround
|
// stub needed for eCos as tx39 hardware bug workaround
|
*r3900:
|
*r3900:
|
{
|
{
|
/* do nothing */
|
/* do nothing */
|
}
|
}
|
|
|
|
|
010000,01000,00010,16.OFFSET:COP0:32::BC0FL
|
010000,01000,00010,16.OFFSET:COP0:32::BC0FL
|
"bc0fl "
|
"bc0fl "
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
|
|
|
|
010000,01000,00001,16.OFFSET:COP0:32::BC0T
|
010000,01000,00001,16.OFFSET:COP0:32::BC0T
|
"bc0t "
|
"bc0t "
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
|
|
|
|
010000,01000,00011,16.OFFSET:COP0:32::BC0TL
|
010000,01000,00011,16.OFFSET:COP0:32::BC0TL
|
"bc0tl "
|
"bc0tl "
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
|
|
|
|
101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
|
101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
|
"cache , (r)"
|
"cache , (r)"
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
address_word base = GPR[BASE];
|
address_word base = GPR[BASE];
|
address_word offset = EXTEND16 (OFFSET);
|
address_word offset = EXTEND16 (OFFSET);
|
{
|
{
|
address_word vaddr = loadstore_ea (SD_, base, offset);
|
address_word vaddr = loadstore_ea (SD_, base, offset);
|
address_word paddr;
|
address_word paddr;
|
int uncached;
|
int uncached;
|
if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
|
if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
|
CacheOp(OP,vaddr,paddr,instruction_0);
|
CacheOp(OP,vaddr,paddr,instruction_0);
|
}
|
}
|
}
|
}
|
|
|
|
|
010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
|
010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
|
"dmfc0 r
|
"dmfc0 r
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
{
|
{
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
DecodeCoproc (instruction_0);
|
DecodeCoproc (instruction_0);
|
}
|
}
|
|
|
|
|
010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0
|
010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0
|
"dmtc0 r
|
"dmtc0 r
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
{
|
{
|
check_u64 (SD_, instruction_0);
|
check_u64 (SD_, instruction_0);
|
DecodeCoproc (instruction_0);
|
DecodeCoproc (instruction_0);
|
}
|
}
|
|
|
|
|
010000,1,0000000000000000000,011000:COP0:32::ERET
|
010000,1,0000000000000000000,011000:COP0:32::ERET
|
"eret"
|
"eret"
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
{
|
{
|
if (SR & status_ERL)
|
if (SR & status_ERL)
|
{
|
{
|
/* Oops, not yet available */
|
/* Oops, not yet available */
|
sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
|
sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
|
NIA = EPC;
|
NIA = EPC;
|
SR &= ~status_ERL;
|
SR &= ~status_ERL;
|
}
|
}
|
else
|
else
|
{
|
{
|
NIA = EPC;
|
NIA = EPC;
|
SR &= ~status_EXL;
|
SR &= ~status_EXL;
|
}
|
}
|
}
|
}
|
|
|
|
|
010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
|
010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
|
"mfc0 r
|
"mfc0 r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
TRACE_ALU_INPUT0 ();
|
TRACE_ALU_INPUT0 ();
|
DecodeCoproc (instruction_0);
|
DecodeCoproc (instruction_0);
|
TRACE_ALU_RESULT (GPR[RT]);
|
TRACE_ALU_RESULT (GPR[RT]);
|
}
|
}
|
|
|
010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
|
010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
|
"mtc0 r
|
"mtc0 r
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
DecodeCoproc (instruction_0);
|
DecodeCoproc (instruction_0);
|
}
|
}
|
|
|
|
|
010000,1,0000000000000000000,010000:COP0:32::RFE
|
010000,1,0000000000000000000,010000:COP0:32::RFE
|
"rfe"
|
"rfe"
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
*r3900:
|
*r3900:
|
{
|
{
|
DecodeCoproc (instruction_0);
|
DecodeCoproc (instruction_0);
|
}
|
}
|
|
|
|
|
0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
|
0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
|
"cop "
|
"cop "
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*r3900:
|
*r3900:
|
{
|
{
|
DecodeCoproc (instruction_0);
|
DecodeCoproc (instruction_0);
|
}
|
}
|
|
|
|
|
|
|
010000,1,0000000000000000000,001000:COP0:32::TLBP
|
010000,1,0000000000000000000,001000:COP0:32::TLBP
|
"tlbp"
|
"tlbp"
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
|
|
|
|
010000,1,0000000000000000000,000001:COP0:32::TLBR
|
010000,1,0000000000000000000,000001:COP0:32::TLBR
|
"tlbr"
|
"tlbr"
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
|
|
|
|
010000,1,0000000000000000000,000010:COP0:32::TLBWI
|
010000,1,0000000000000000000,000010:COP0:32::TLBWI
|
"tlbwi"
|
"tlbwi"
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
|
|
|
|
010000,1,0000000000000000000,000110:COP0:32::TLBWR
|
010000,1,0000000000000000000,000110:COP0:32::TLBWR
|
"tlbwr"
|
"tlbwr"
|
*mipsI:
|
*mipsI:
|
*mipsII:
|
*mipsII:
|
*mipsIII:
|
*mipsIII:
|
*mipsIV:
|
*mipsIV:
|
*mipsV:
|
*mipsV:
|
*mips32:
|
*mips32:
|
*mips32r2:
|
*mips32r2:
|
*mips64:
|
*mips64:
|
*mips64r2:
|
*mips64r2:
|
*vr4100:
|
*vr4100:
|
*vr5000:
|
*vr5000:
|
|
|
|
|
:include:::mips3264r2.igen
|
:include:::mips3264r2.igen
|
:include:::m16.igen
|
:include:::m16.igen
|
:include:::m16e.igen
|
:include:::m16e.igen
|
:include:::mdmx.igen
|
:include:::mdmx.igen
|
:include:::mips3d.igen
|
:include:::mips3d.igen
|
:include:::sb1.igen
|
:include:::sb1.igen
|
:include:::tx.igen
|
:include:::tx.igen
|
:include:::vr.igen
|
:include:::vr.igen
|
:include:::dsp.igen
|
:include:::dsp.igen
|
:include:::dsp2.igen
|
:include:::dsp2.igen
|
:include:::smartmips.igen
|
:include:::smartmips.igen
|
|
|
|
|
