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OpenRISC 1200
IP Core
Specification
Author: Damjan Lampret
lampret@opencores.org
Rev. 0.7
Sep 6, 2001
Preliminary Draft
Revision History
Rev.DateAuthorDescription0.128/3/01Damjan LampretFirst Draft0.216/4/01Damjan LampretFirst time published0.329/4/01Damjan LampretAll chapters almost finished. Some bugs hidden waiting for an update. Awaiting feedback.0.416/5/01Damjan LampretSynchronization with OR1K Arch Manual0.524/5/01Damjan LampretFixed bugs0.628/5/01Damjan LampretChanged some SPR addresses.0.706/9/01Damjan LampretSimplified debug unit. Table Of Contents
TOC \o "2-2" \h \z \t "Headeing 1 Name,1" HYPERLINK \l "_Toc511161474" Introduction PAGEREF _Toc511161474 \h 7
HYPERLINK \l "_Toc511161475" OpenRISC Family PAGEREF _Toc511161475 \h 7
HYPERLINK \l "_Toc511161476" OpenRISC 1200 PAGEREF _Toc511161476 \h 8
HYPERLINK \l "_Toc511161477" Features PAGEREF _Toc511161477 \h 8
HYPERLINK \l "_Toc511161478" Architecture PAGEREF _Toc511161478 \h 9
HYPERLINK \l "_Toc511161479" CPU/DSP PAGEREF _Toc511161479 \h 10
HYPERLINK \l "_Toc511161480" Data Cache PAGEREF _Toc511161480 \h 13
HYPERLINK \l "_Toc511161481" Instruction Cache PAGEREF _Toc511161481 \h 15
HYPERLINK \l "_Toc511161482" Data MMU PAGEREF _Toc511161482 \h 17
HYPERLINK \l "_Toc511161483" Instruction MMU PAGEREF _Toc511161483 \h 19
HYPERLINK \l "_Toc511161484" Programmable Interrupt Controller PAGEREF _Toc511161484 \h 21
HYPERLINK \l "_Toc511161485" Tick Timer PAGEREF _Toc511161485 \h 21
HYPERLINK \l "_Toc511161486" Power Management Support PAGEREF _Toc511161486 \h 22
HYPERLINK \l "_Toc511161487" Debug unit PAGEREF _Toc511161487 \h 22
HYPERLINK \l "_Toc511161488" Clocks & Reset PAGEREF _Toc511161488 \h 23
HYPERLINK \l "_Toc511161489" WISHBONE Interfaces PAGEREF _Toc511161489 \h 23
HYPERLINK \l "_Toc511161490" Operation PAGEREF _Toc511161490 \h 25
HYPERLINK \l "_Toc511161491" Reset PAGEREF _Toc511161491 \h 25
HYPERLINK \l "_Toc511161492" CPU/DSP PAGEREF _Toc511161492 \h 25
HYPERLINK \l "_Toc511161493" Data Cache Operation PAGEREF _Toc511161493 \h 32
HYPERLINK \l "_Toc511161494" Instruction Cache Operation PAGEREF _Toc511161494 \h 35
HYPERLINK \l "_Toc511161495" Data MMU PAGEREF _Toc511161495 \h 37
HYPERLINK \l "_Toc511161496" Instruction MMU PAGEREF _Toc511161496 \h 41
HYPERLINK \l "_Toc511161497" Programmable Interrupt Controller PAGEREF _Toc511161497 \h 44
HYPERLINK \l "_Toc511161498" Tick Timer PAGEREF _Toc511161498 \h 45
HYPERLINK \l "_Toc511161499" Power Management PAGEREF _Toc511161499 \h 45
HYPERLINK \l "_Toc511161500" Debug Unit PAGEREF _Toc511161500 \h 46
HYPERLINK \l "_Toc511161501" Development Interface PAGEREF _Toc511161501 \h 47
HYPERLINK \l "_Toc511161502" Registers PAGEREF _Toc511161502 \h 50
HYPERLINK \l "_Toc511161503" Registers list PAGEREF _Toc511161503 \h 50
HYPERLINK \l "_Toc511161504" Register VR description PAGEREF _Toc511161504 \h 51
HYPERLINK \l "_Toc511161505" Register UPR description PAGEREF _Toc511161505 \h 52
HYPERLINK \l "_Toc511161506" Register CPUCFGR description PAGEREF _Toc511161506 \h 53
HYPERLINK \l "_Toc511161507" Register DMMUCFGR description PAGEREF _Toc511161507 \h 53
HYPERLINK \l "_Toc511161508" Register IMMUCFGR description PAGEREF _Toc511161508 \h 54
HYPERLINK \l "_Toc511161509" Register DCCFGR description PAGEREF _Toc511161509 \h 54
HYPERLINK \l "_Toc511161510" Register ICCFGR description PAGEREF _Toc511161510 \h 55
HYPERLINK \l "_Toc511161511" Register DCFGR description PAGEREF _Toc511161511 \h 56
HYPERLINK \l "_Toc511161512" IO ports PAGEREF _Toc511161512 \h 57
HYPERLINK \l "_Toc511161513" Instruction WISHBONE Master Interface PAGEREF _Toc511161513 \h 57
HYPERLINK \l "_Toc511161514" Data WISHBONE Master Interface PAGEREF _Toc511161514 \h 58
HYPERLINK \l "_Toc511161515" System Interface PAGEREF _Toc511161515 \h 59
HYPERLINK \l "_Toc511161516" Development Interface PAGEREF _Toc511161516 \h 59
HYPERLINK \l "_Toc511161517" Power Management Interface PAGEREF _Toc511161517 \h 59
HYPERLINK \l "_Toc511161518" Interrupt Interface PAGEREF _Toc511161518 \h 60
HYPERLINK \l "_Toc511161519" Core HW Configuration PAGEREF _Toc511161519 \h 61
Table Of Figures
TOC \h \z \c "Figure" HYPERLINK \l "_Toc511161520" Figure 1. Core's Architecture PAGEREF _Toc511161520 \h 9
HYPERLINK \l "_Toc511161521" Figure 2. CPU/DSP Block Diagram PAGEREF _Toc511161521 \h 10
HYPERLINK \l "_Toc511161522" Figure 3. Block Diagram of Debug Unit PAGEREF _Toc511161522 \h 23
HYPERLINK \l "_Toc511161523" Figure 4. Power-Up and Reset Sequence PAGEREF _Toc511161523 \h 25
HYPERLINK \l "_Toc511161524" Figure 5. Power-Up and Reset Sequence w/ Gated Clock PAGEREF _Toc511161524 \h 25
HYPERLINK \l "_Toc511161525" Figure 6. WISHBONE Write Cycle PAGEREF _Toc511161525 \h 33
HYPERLINK \l "_Toc511161526" Figure 7. WISHBONE Block Read Cycle PAGEREF _Toc511161526 \h 33
HYPERLINK \l "_Toc511161527" Figure 8. WISHBONE Block Read/Write Cycle PAGEREF _Toc511161527 \h 34
HYPERLINK \l "_Toc511161528" Figure 9. WISHBONE Block Read Cycle PAGEREF _Toc511161528 \h 36
HYPERLINK \l "_Toc511161529" Figure 10. 32-bit Address Translation Mechanism using Two-Level Page Table PAGEREF _Toc511161529 \h 38
HYPERLINK \l "_Toc511161530" Figure 11. 32-bit Address Translation Mechanism using Two-Level Page Table PAGEREF _Toc511161530 \h 42
HYPERLINK \l "_Toc511161531" Figure 12. Development Interface Cycles PAGEREF _Toc511161531 \h 48
HYPERLINK \l "_Toc511161532" Figure 13. Assertion of External Watchpoint Trigger PAGEREF _Toc511161532 \h 49
HYPERLINK \l "_Toc511161533" Figure 14. Cores Interfaces PAGEREF _Toc511161533 \h 57
Table Of Tables
TOC \h \z \c "Table" HYPERLINK \l "_Toc511161534" Table 1. Possible Data Cache Configurations of OR1200 PAGEREF _Toc511161534 \h 13
HYPERLINK \l "_Toc511161535" Table 2. Possible Instruction Cache Configurations of OR1200 PAGEREF _Toc511161535 \h 15
HYPERLINK \l "_Toc511161536" Table 3. Possible Data TLB Configurations of OR1200 PAGEREF _Toc511161536 \h 17
HYPERLINK \l "_Toc511161537" Table 4. Possible Instruction TLB Configurations of OR1200 PAGEREF _Toc511161537 \h 19
HYPERLINK \l "_Toc511161538" Table 5. Block Diagram of the Interrupt Controller PAGEREF _Toc511161538 \h 21
HYPERLINK \l "_Toc511161539" Table 6. Power Consumption PAGEREF _Toc511161539 \h 22
HYPERLINK \l "_Toc511161540" Table 7. List of 32-bit Implemented Instructions PAGEREF _Toc511161540 \h 29
HYPERLINK \l "_Toc511161541" Table 8. Execution Time of Integer Instructions PAGEREF _Toc511161541 \h 30
HYPERLINK \l "_Toc511161542" Table 9. List of Implemented Exceptions PAGEREF _Toc511161542 \h 32
HYPERLINK \l "_Toc511161543" Table 10. Protection Attributes for Load/Store Accesses PAGEREF _Toc511161543 \h 39
HYPERLINK \l "_Toc511161544" Table 11. Cached and uncached regions PAGEREF _Toc511161544 \h 40
HYPERLINK \l "_Toc511161545" Table 11. Protection Attributes for Instruction Fetch Accesses PAGEREF _Toc511161545 \h 43
HYPERLINK \l "_Toc511161546" Table 13. Cached and uncached regions PAGEREF _Toc511161546 \h 44
HYPERLINK \l "_Toc511161547" Table 12. Development Interface Operation Commands PAGEREF _Toc511161547 \h 47
HYPERLINK \l "_Toc511161548" Table 13. Status of the Load/Store Unit PAGEREF _Toc511161548 \h 48
HYPERLINK \l "_Toc511161549" Table 14. Status of the Instruction Unit PAGEREF _Toc511161549 \h 49
HYPERLINK \l "_Toc511161550" Table 15. List of All Registers PAGEREF _Toc511161550 \h 51
HYPERLINK \l "_Toc511161551" Table 16. VR Register PAGEREF _Toc511161551 \h 52
HYPERLINK \l "_Toc511161552" Table 17. UPR Register PAGEREF _Toc511161552 \h 52
HYPERLINK \l "_Toc511161553" Table 18. CPUCFGR Register PAGEREF _Toc511161553 \h 53
HYPERLINK \l "_Toc511161554" Table 19. DMMUCFGR Register PAGEREF _Toc511161554 \h 54
HYPERLINK \l "_Toc511161555" Table 20. IMMUCFGR Register PAGEREF _Toc511161555 \h 54
HYPERLINK \l "_Toc511161556" Table 21. DCCFGR Register PAGEREF _Toc511161556 \h 55
HYPERLINK \l "_Toc511161557" Table 22. ICCFGR Register PAGEREF _Toc511161557 \h 55
HYPERLINK \l "_Toc511161558" Table 23. DCFGR Register PAGEREF _Toc511161558 \h 56
HYPERLINK \l "_Toc511161559" Table 24. Instruction WISHBONE Master Interface Signals PAGEREF _Toc511161559 \h 58
HYPERLINK \l "_Toc511161560" Table 25. Data WISHBONE Master Interface Signals PAGEREF _Toc511161560 \h 58
HYPERLINK \l "_Toc511161561" Table 26. System Interface Signals PAGEREF _Toc511161561 \h 59
HYPERLINK \l "_Toc511161562" Table 27. Development Interface PAGEREF _Toc511161562 \h 59
HYPERLINK \l "_Toc511161563" Table 28. Power Management Interface PAGEREF _Toc511161563 \h 60
HYPERLINK \l "_Toc511161564" Table 29. Interrupt Interface PAGEREF _Toc511161564 \h 60
1
Introduction
Purpose of this document is to define specifications of the OpenRISC 1200 implementation. This specification defines all implementation specific variables that are not part of the general architecture specification. This includes type and size of data and instruction caches, type and size of data and instruction MMUs, details of all execution pipelines, implementation of exception unit, interrupt controller and other supplemental units.
This document does not cover general architecture topics like instruction set, memory addressing modes and other architectural definitions. See OpenRISC 1000 System Architecture Manual for more information about architecture.
OpenRISC Family
OpenRISC 1000 is architecture for a family of free, open source RISC processor cores. As architecture, OpenRISC 1000 allows for a spectrum of chip and system implementations at a variety of price/performance points for a range of applications. It is a 32/64-bit load and store RISC architecture designed with emphasis on performance, simplicity, low power requirements, scalability and versatility. OpenRISC 1000 architecture targets medium and high performance networking, embedded, automotive and portable computer environments.
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All OpenRISC implementations, whose first digit in identification number is 1, belong to OpenRISC 1000 family. Second digit defines which features of OpenRISC 1000 architecture are implemented and in which way they are implemented. Last two digits define how an implementation is configured before it is used in a real application.
OpenRISC 1200
The OR1200 is a 32-bit scalar RISC with Harvard microarchitecture, 5 stage integer pipeline, virtual memory support (MMU) and basic DSP capabilities.
Default caches are 1-way direct-mapped 8KB data cache and 1-way direct-mapped 8KB instruction cache, each with 16-byte line size. Both caches are physically tagged.
By default MMUs are implemented and they are constructed of 64-entry hash based 1-way direct-mpped data TLB and 64-entry hash based 1-way direct-mapped instruction TLB.
Supplemental facilities include debug unit for real-time debugging, high resolution tick timer, programmable interrupt controller and power management support.
When implemented in a typical 0.18u 6LM process it should provide over 300 dhrystone 2.1 MIPS at 300MHz and 300 DSP MAC 32x32 operations, at least 20% more than any other competitor in this class. OR1200 in default configuration has about 1M transistors.
OR1200 is intended for embedded, portable and networking applications. It can successfully compete with latest scalar 32-bit RISC processors in his class and can efficiently run any modern operating system.
Competitors include ARM10, ARC and Tensilica RISC processors.
Features
The following lists the main features of OR1200 IP core:
All major characteristics of the core can be set by the user
High performance of 300 Dhrystone 2.1 MIPS at 300 MHz using 0.18u process
High performance cache and MMU subsystems
WISHBONE SoC Interconnection Rev. B compliant interface
2
Architecture
REF _Ref511206923 \h Figure 1 below shows general architecture of OR1200 IP core. It consists of several building blocks:
CPU/DSP central block
Direct-mapped data cache
Direct-mapped instruction cache
Data MMU based on hash based DTLB
Instruction MMU based on hash based ITLB
Power management unit and power management interface
Tick timer
Debug unit and development interface
Interrupt controller and interrupt interface
Instruction and Data WISHBONE host interfaces
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Figure SEQ Figure \* ARABIC 1. Core's Architecture
CPU/DSP
CPU/DSP is a central part of the OR1200 RISC processor. REF _Ref511208730 \h \* MERGEFORMAT Figure 2 shows basic block diagram of the CPU/DSP.
OR1200 CPU/DSP implements only 32-bit part of the OpenRISC 1000 architecture. 64-bit part of the architecture as well as floating-point and vector operations are not implemented in OR1200.
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Figure SEQ Figure \* ARABIC 2. CPU/DSP Block Diagram
Instruction unit
The instruction unit implements the basic instruction pipeline, fetches instructions from the memory subsystem, dispatches them to available execution units, and maintains a state history to ensure a precise exception model and that operations finish in order. It also executes conditional branch and unconditional jump instructions.
The sequencer can dispatch a sequential instruction on each clock if the appropriate execution unit is available. The execution unit must discern whether source data is available and to ensure that no other instruction is targeting the same destination register.
Instruction unit handles only ORBIS32 instruction class. ORFPX32/64 and ORVDX64 instruction classes are not supported by current OR1200.
General-Purpose Registers
OpenRISC 1200 implements 32 general-purpose 32-bit registers. OpenRISC 1000 architecture also support shadow copies of register file to implement fast switching between working contexts, however this feature is not implemented in current OR1200 implementation.
OR1200 implements general-purpose register file as two synchronous dual-port memories with capacity of 32 words by 32 bits per word.
Load/Store Unit
The load/store unit (LSU) transfers all data between the GPRs and the CPU's internal bus. It is implemented as an independent execution unit so that stalls in memory subsystem only affect master pipeline if there is a data dependency.
The following are LSU's main features:
all load/store instruction implemented in hardware (atomic instructions included)
address entry buffer
pipelined operation
aligned accesses for fast memory access
When load and store instructions are issued, the LSU determines if all operands are available. These operands include the following:
address register operand
source data register operand (for store instructions)
destination data register operand (for load instructions)
Integer Execution Pipeline
The core implements the following types of 32-bit integer instructions:
Arithmetic instructions
Compare instructions
Logical instructions
Rotate and shift instructions
Most integer instructions can execute in one cycle. For details about timing see table TBD.
MAC Unit
The MAC unit executes DSP MAC operations. MAC operations are 32x32 with 48-bit accumulator. MAC unit is fully pipelined and can accept new MAC operation in each new clock cycle.
System Unit
The system unit connects all other signals of the CPU/DSP that are not connected through instruction and data interfaces. It also implements all system special-purpose registers (e.g. supervisor register).
Exceptions
Core exceptions can be generated when an exception condition occurs. Exception sources in OR1200 include the following:
External interrupt request
Certain memory access condition
Internal errors, such as an attempt to execute unimplemented opcode
System call
Internal exception, such as breakpoint exceptions
Exception handling is transparent to user software and uses the same mechanism to handle all types of exceptions. When an exception is taken, control is transferred to an exception handler at an offset defined by for the type of exception encountered. Exceptions are handled in supervisor mode.
Data Cache
The default configuration of OR1200 data cache is 8-Kbyte, 1-way direct-mapped data cache, which allows rapid core access to data. However data cache can be configured according to the REF _Ref512098491 \h \* MERGEFORMAT Table 1.
Direct mapped1KB per set1KB2KB per set2KB4KB per set4KB8KB per set8KB (default)Table SEQ Table \* ARABIC 1. Possible Data Cache Configurations of OR1200
Features:
data cache is separate from instruction cache (Harvard architecture)
data cache implements a least-recently used (LRU) replacement algorithm within each set
the cache directory is physically addressed. The physical address tag is stored in the cache directory
write-through operation
it can be disabled or invalidated by writing to cache special purpose registers
On a miss, the cache is filled in with 16-byte bursts. The burst fill is performed as a critical-word-first operation; the critical word is simultaneously written to the cache and forwarded to the requesting unit, thus minimizing stalls due to cache fill latency. Data cache provides storage for cache tags and performs cache line replacement function.
Data cache is tightly coupled to external interface to allow efficient access to the system memory controller.
The data cache supplies data to the GPRs by means of a 32-bit interface to the load/store unit. The LSU provides all logic required to calculate effective addresses, handles data alignment to and from the data cache, and provides sequencing for load and store operations. Write operations to the data cache can be performed on a byte, half-word or word basis.
The data cache is organized as 512 sets of one line. Each line consists of 16 bytes, state bits and an address tag.
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Each line contains four contiguous words from memory that are loaded from a four-word aligned boundary. As a result, cache lines are aligned with page boundaries.
Instruction Cache
The default configuration of OR1200 instruction cache is 8-Kbyte, 1-way direct mapped instruction cache, which allows rapid core access to instructions. However instruction cache can be configured according to the REF _Ref512099081 \h \* MERGEFORMAT
Direct mapped1KB per set1KB2KB per set2KB4KB per set4KB8KB per set8KB (default)Table 2.
Direct mapped1KB per set1KB2KB per set2KB4KB per set4KB8KB per set8KB (default)Table SEQ Table \* ARABIC 2. Possible Instruction Cache Configurations of OR1200
Features:
instruction cache is separate from data cache (Harvard architecture)
instruction cache implements a least-recently used (LRU) replacement algorithm within each set
the cache directory is physically addressed. The physical address tag is stored in the cache directory
it can be disabled or invalidated by writing to cache special purpose registers
On a miss, the cache is filled in with 16-byte bursts. The burst fill is performed as a critical-word-first operation; the critical word is simultaneously written to the cache and forwarded to the requesting unit, thus minimizing stalls due to cache fill latency. Instruction cache provides storage for cache tags and performs cache line replacement function.
Instruction cache is tightly coupled to external interface to allow efficient access to the system memory controller.
The instruction cache supplies instructions to the instruction sequencer by means of a 32-bit interface to the instruction fetch subunit. The instruction fetch subunit provides all logic required to calculate effective addresses.
The data cache is organized as 512 sets of one line. Each line consists of 16 bytes, state bits and an address tag.
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Each line contains four contiguous words from memory that are loaded from a four-word aligned boundary. As a result, cache lines are aligned with page boundaries.
Data MMU
The OR1200 implements a virtual memory management scheme that provides memory access protection and effective-to-physical address translation. Protection granularity is as defined by OpenRISC 1000 architecture - 8-Kbyte and 16-Mbyte pages.
Direct mapped16 entries per way16 DTLB entries32 entries per way32 DTLB entries64 entries per way64 DTLB entries (default)128 entries per way128 DTLB entriesTable SEQ Table \* ARABIC 4. Possible Data TLB Configurations of OR1200
Features:
data MMU is separate from instruction MMU
page size 8-Kbyte
comprehensive page protection scheme
direct mapped hash based translation lookaside buffer (DTLB) with the default of 1 way and the following features:
miss and fault exceptions
software tablewalk
high performance because of hashed based design
variable number DTLB entries with default of 64 per each way
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The MMU hardware supports two-level software tablewalk.
Instruction MMU
The OR1200 implements a virtual memory management scheme that provides memory access protection and effective-to-physical address translation. Protection granularity is as defined by OpenRISC 1000 architecture - 8-Kbyte and 16-Mbyte pages.
Direct mapped16 entries per way16 DTLB entries32 entries per way32 DTLB entries64 entries per way64 DTLB entries (default)128 entries per way128 DTLB entriesTable SEQ Table \* ARABIC 5. Possible Instruction TLB Configurations of OR1200
Features:
instruction MMU is separate from data MMU
pages size 8-Kbyte
comprehensive page protection scheme
1 way direct-mapped hash based translation lookaside buffer (ITLB) with the following features:
miss and fault exceptions
software tablewalk
high performance because of hashed based design
Variable number of ITLB entries with default of 64 entries per way
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The MMU hardware supports two-level software tablewalk.
Programmable Interrupt Controller
The interrupt controller receives interrupts from external sources and forwards them as low or high priority interrupt exception to the CPU core.
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Table SEQ Table \* ARABIC 6. Block Diagram of the Interrupt Controller
Programmable interrupt controller has three special-purpose registers and 32 interrupt inputs. Interrupt input 0 and 1 are always enabled and connected to high and low priority interrupt input, respectively.
30 other interrupt inputs can be masked and assigned low or high priority through programming special-purpose registers.
Tick Timer
OR1200 implements tick timer facility. Basically this is a timer that is clocked by RISC clock and is used by the operating system to precisely measure time and schedule system tasks.
OR1200 precisely follow architectural definition of the tick timer facility:
Maximum timer count of 2^32 clock cycles
Maximum time period of 2^28 clock cycles between interrupts
Maskable tick timer interrupt
Single run, restartable or continues timer
Tick timer operates from independent clock source so that doze power management mode can be implemented.
Power Management Support
To optimize power consumption, the OR1200 provides low-power modes that can be used to dynamically activate and deactivate certain internal modules.
OR1200 has three major features to minimize power consumption:
Slow and Idle Modes (SW controlled clock freq reduction)
Doze and Sleep Modes (interrupt wake-up)
Power Minimization FeatureApprox Power Consumption ReductionSlow and Idle mode2x 10xDoze mode100xSleep mode200xDynamic clock gatingN/ATable SEQ Table \* ARABIC 7. Power Consumption
Slow down mode takes advantage of the low-power dividers in external clock generation circuitry to enable full functionality, but at a lower frequency so that a power consumption is reduced.
PMR[SDF] 4 bits are broadcasted on pm_clksd and external clock generation for the RISC should adapt RISC clock frequency according to the value on pm_clksd.
When software initiates the doze mode, software processing on the core suspends. The clocks to the RISC internal modules are disabled except to the tick timer. However any other on-chip blocks can continue to function as normal.
The OR1200 will leave doze mode and enter normal mode when a pending interrupt occurs.
In sleep mode, all OR1200 internal units are disabled and clocks gated. Optionally implementation may choose to lower the operating voltage of the OR1200 core.
The OR1200 should leave sleep mode and enter normal mode when a pending interrupt occurs.
Dynamic Clock gating (unit clock gating on clock by clock basis) is not supported by OR1200.
Debug unit
Debug unit assists software developers to debug their systems. It provides support only for basic debugging and does not have support for more advanced debug features of OpenRISC 1000 architecture such as watchpoints, breakpoints and program-flow control registers.
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Figure SEQ Figure \* ARABIC 3. Block Diagram of Debug Unit
Watchpoints and breakpoints are events triggered by program- or data-flow matching the conditions programmed in the debug registers. Breakpoints unlike watchpoints also suspend execution of the current program-flow and start breakpoint exception.
Clocks & Reset
The OR1200 core has several clock inputs. Clock input clk_cpu clocks CPU/DSP block and all other parts of the RISC that do not have separate clocks. Data cache is clocked by clk_dc, instruction cache is clocked by clk_ic, data MMU is clocked by clk_dmmu, instruction MMU is clocked by clk_immu and tick timer is clocked by clk_tt. All clocks must have the same phase and as low clock skew as possible.
OR1200 has asynchronous reset signal. Reset signal rst, when asserted high, immediately resets all flip-flops inside OR1200. When deasserted, OR1200 will start reset exception.
WISHBONE Interfaces
Two WISHBONE interfaces connect OR1200 core to external peripherals and external memory subsystem. They are WISHBONE SoC Interconnection specification Rev. B compliant. The implementation implements a 32-bit bus width and does not support other bus widths.
3
Operation
This section describes the operation of the OR1200 core. For operations that pertain to the architectural definitions, see OpenRISC 1000 System Architecture Manual.
Reset
OR1200 has one asynchronous reset signal that can be used by a soft and hard reset on a higher system hierarchy levels.
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Figure SEQ Figure \* ARABIC 4. Power-Up and Reset Sequence
REF _Ref513206810 \h Figure 4 shows how asynchronous reset is applied after powering up the OR1200 core. Reset is connected to asynchronous reset of almost all flip-flops inside RISC core. Special care must be taken to ensure hold and setup times of all flip-flops compared to main RISC clock.
If system implements gated clocks, then clock gating can be used to ensure proper reset timing.
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Figure SEQ Figure \* ARABIC 5. Power-Up and Reset Sequence w/ Gated Clock
CPU/DSP
CPU/DSP is implementation of the 32-bit part of the OpenRISC 1000 architecture and only a subset of all features is implemented.
Instructions
REF _Ref515320693 \h Table 8 shows all instructions implemented by OR1200.
Insn313131313126252525252120202020161515151511109877743330l.addopcode 0x38DABreservedopcode 0x0reservedopcode 0x0313029282726252423222120191817161514131211109876543210l.addcopcode 0x38DABreservedopcode 0x0reservedopcode 0x1313029282726252423222120191817161514131211109876543210l.addiopcode 0x27DAI313029282726252423222120191817161514131211109876543210l.andopcode 0x38DABreservedopcode 0x0reservedopcode 0x3313029282726252423222120191817161514131211109876543210l.andiopcode 0x29DAK313029282726252423222120191817161514131211109876543210l.bfopcode 0x4N313029282726252423222120191817161514131211109876543210l.bnfopcode 0x3N313029282726252423222120191817161514131211109876543210l.trapopcode 0x2100K313029282726252423222120191817161514131211109876543210l.jopcode 0x0N313029282726252423222120191817161514131211109876543210l.jalopcode 0x1N313029282726252423222120191817161514131211109876543210l.jalropcode 0x12ReservedBreserved313029282726252423222120191817161514131211109876543210l.jropcode 0x11ReservedBreserved313029282726252423222120191817161514131211109876543210l.lbsopcode 0x24DAI313029282726252423222120191817161514131211109876543210l.lbzopcode 0x23DAI313029282726252423222120191817161514131211109876543210l.lhsopcode 0x26DAI313029282726252423222120191817161514131211109876543210l.lhzopcode 0x25DAI313029282726252423222120191817161514131211109876543210l.lwsopcode 0x22DAI313029282726252423222120191817161514131211109876543210l.lwzopcode 0x21DAI313029282726252423222120191817161514131211109876543210l.mfspropcode 0x7DAK313029282726252423222120191817161514131211109876543210l.movhiopcode 0x6DReservedK313029282726252423222120191817161514131211109876543210l.mtspropcode 0x10KABK313029282726252423222120191817161514131211109876543210l.mulopcode 0x38DABreservedopcode 0x3reservedopcode 0x6313029282726252423222120191817161514131211109876543210l.muliopcode 0x2cDAI313029282726252423222120191817161514131211109876543210l.muluopcode 0x38DABreservedopcode 0x3reservedopcode 0xb313029282726252423222120191817161514131211109876543210l.nopopcode 0x15reserved313029282726252423222120191817161514131211109876543210l.oropcode 0x38DABreservedopcode 0x0reservedopcode 0x4313029282726252423222120191817161514131211109876543210l.oriopcode 0x2aDAK313029282726252423222120191817161514131211109876543210l.rfeopcode 0x9reserved313029282726252423222120191817161514131211109876543210l.roriopcode 0x2eDAreservedopcode 0x3L313029282726252423222120191817161514131211109876543210l.sbopcode 0x36IABI313029282726252423222120191817161514131211109876543210l.sfeqopcode 0x720ABreserved313029282726252423222120191817161514131211109876543210l.sfgesopcode 0x72bABreserved313029282726252423222120191817161514131211109876543210l.sfgeuopcode 0x723ABreserved313029282726252423222120191817161514131211109876543210l.sfgtsopcode 0x72aABreserved313029282726252423222120191817161514131211109876543210l.sfgtuopcode 0x722ABreserved313029282726252423222120191817161514131211109876543210l.sflesopcode 0x72dABreserved313029282726252423222120191817161514131211109876543210l.sfleuopcode 0x725ABreserved313029282726252423222120191817161514131211109876543210l.sfltsopcode 0x72cABreserved313029282726252423222120191817161514131211109876543210l.sfltuopcode 0x724ABreserved313029282726252423222120191817161514131211109876543210l.sfneopcode 0x721ABreserved313029282726252423222120191817161514131211109876543210l.shopcode 0x37IABI313029282726252423222120191817161514131211109876543210l.sllopcode 0x38DABreservedopcode 0x0reservedopcode 0x8313029282726252423222120191817161514131211109876543210l.slliopcode 0x2eDAreservedopcode 0x0L313029282726252423222120191817161514131211109876543210l.sraopcode 0x38DABreservedopcode 0x2reservedopcode 0x8313029282726252423222120191817161514131211109876543210l.sraiopcode 0x2eDAreservedopcode 0x2L313029282726252423222120191817161514131211109876543210l.srlopcode 0x38DABreservedopcode 0x1reservedopcode 0x8313029282726252423222120191817161514131211109876543210l.srliopcode 0x2eDAreservedopcode 0x1L313029282726252423222120191817161514131211109876543210l.subopcode 0x38DABreservedopcode 0x0reservedopcode 0x2313029282726252423222120191817161514131211109876543210l.swopcode 0x35IABI313029282726252423222120191817161514131211109876543210l.sysopcode 0x2000K313029282726252423222120191817161514131211109876543210l.xoropcode 0x38DABreservedopcode 0x0reservedopcode 0x5313029282726252423222120191817161514131211109876543210l.xoriopcode 0x2bDAITable SEQ Table \* ARABIC 8. List of 32-bit Implemented Instructions
For a complete description how instruction operate refer to OpenRISC 1000 System Architecture Manual.
Instruction Unit
Instruction unit generates instruction fetch effective address and fetches instructions from instruction cache. Each clock cycle one instruction can be fetched. Instruction fetch EA is further translated into physical address by IMMU.
General-Purpose Registers
General-purpose register file can supply two read operands each clock cycle and store one result in a destination register.
GPRs can be also read and written through development interface.
Load/Store Unit
LSU can execute one load instruction every two clock cycles assuming load instruction have a hit in the data cache. Execution of store instructions takes one clock cycle assuming they have a hit in the data cache.
LSU performs calculation of the load/store effective address. EA is further translated into physical address by DMMU.
Load/store effective address and load and store data can be also accessed through development interface.
Integer Execution Pipeline
The core implements the following types of 32-bit integer instructions:
Arithmetic instructions
Compare instructions
Logical instructions
Rotate and shift instructions
Instruction GroupClock Cycles to ExecuteArithmetic except Multiply/Divide1Multiply3DivideNot implementedCompare1Logical1Rotate and Shift1Others1Table SEQ Table \* ARABIC 9. Execution Time of Integer Instructions
REF _Ref513308588 \h \* MERGEFORMAT Table 9 lists execution times for instructions executed by integer execution pipeline. Most instructions are executed in one clock cycle.
MAC Unit
MAC unit executes l.mac instructions. MAC unit implements 32x32 fully pipelined multiplier and 48-bit accumulator. MAC unit can accept one new l.mac instruction each clock cycle.
System Unit
System unit implements system control and status special-purpose registers and executes all l.mtspr/l.mfspr instructions.
Exceptions
The core implements a precise exception model. This means that when an exception is taken, the following conditions are met:
Subsequent instructions in program flow are discarded
Previous instructions finish and write back their results
The address of faulting instruction is saved in EPCR registers and the machine state is saved to ESR registers
Exception TypeVector Offsetcausing conditionsReset0x100Caused by reset.Bus Error0x200Caused by an attempt to access invalid physical address.Data Page Fault0x300Generated artificially by DTLB miss exception handler when no matching PTE found in page tables or page protection violation for load/store operations.Instruction Page Fault0x400Generated artificially by ITLB miss exception handler when no matching PTE found in page tables or page protection violation for instruction fetch.Low Priority External Interrupt0x500Low priority external interrupt asserted.Alignment0x600Load/store access to naturally not aligned location.Illegal Instruction0x700Illegal instruction in the instruction stream.High Priority External Interrupt0x800High priority external interrupt asserted.D-TLB Miss0x900No matching entry in DTLB (DTLB miss).I-TLB Miss0xA00No matching entry in ITLB (ITLB miss).System Call0xC00System call initiated by software.Breakpoint0xD00Initiated by the debug unit.Table SEQ Table \* ARABIC 10. List of Implemented Exceptions
The OR1200 exception support does not include support for fast context switching.
Data Cache Operation
Data Cache Load/Store Access
Load/store unit requests data from the data cache and stores them into the general-purpose register file and forwards them to integer execution units. Therefore LSU is tightly coupled with the data cache.
If there is no data cache line miss nor DTLB miss, load operations take two clock cycles to execute and store operations take one clock cycle to execute. LSU does all the data alignment work.
Data can be written to the data cache on a word, half-word or byte basis. Since data cache only operates in write-through mode, all writes are immediately written back to main memory or to the next level of caches.
EMBED Timing.Document.1
Figure SEQ Figure \* ARABIC 6. WISHBONE Write Cycle
REF _Ref513193242 \h Figure 6 shows how a write-through cycle on data WISHBONE interface is performed when a store instruction hits in the data cache.
If dwb_ERR_I or dwb_RTY_I is asserted instead of usual dwb_ACK_I, bus error exception is invoked.
Data Cache Line Fill Operation
When executing load instruction and a cache miss occurs, a 4 beat sequential read burst with critical word first is performed. Critical word is forwarded to the load/store unit to minimize performance loss because of the cache miss.
EMBED Timing.Document.1
Figure SEQ Figure \* ARABIC 7. WISHBONE Block Read Cycle
REF _Ref513194821 \h Figure 7 shows how a cache line is read in WISHBONE read block cycle composed out of four read transfers.
If dwb_ERR_I or dwb_RTY_I is asserted instead of usual dwb_ACK_I, bus error exception is invoked.
When executing store instruction and a cache miss occurs, a 4 beat sequential read burst with critical word first is performed. After read burst single word write is performed to write data of the store instruction back to main memory or next level of caches. Regardless of the wideness of store instruction, always a word write is performed.
EMBED Timing.Document.1
Figure SEQ Figure \* ARABIC 8. WISHBONE Block Read/Write Cycle
REF _Ref513195072 \h Figure 8 shows how a cache line is read in WISHBONE read block cycle followed by a write transfer.
If dwb_ERR_I or dwb_RTY_I is asserted instead of usual dwb_ACK_I, bus error exception is invoked.
Cache/Memory Coherency
Data cache in OR1200 operates only in write-through mode. Furthermore OR1200 is not intended for use in multiprocessor environments. Therefore no support for coherency between local data cache and caches of other processors or main memory is implemented.
Data Cache Enabling/Disabling
Data cache is disabled at power up. Entire data cache can be enabled by setting bit SR[DCE] to one. Before data cache is enabled, it must be invalidated.
Data Cache Invalidation
Data cache in OR1200 does not support invalidation of entire data cache. Normal procedure to invalidate entire data cache is to cycle through all data cache lines and invalidate each line separately.
Data Cache Locking
Data cache implements way locking bits in data cache control register DCCR. Bits LWx lock individual ways when they are set to one.
Data Cache Line Prefetch
Data cache line prefetch is optional in the OpenRISC 1000 architecture and is not implemented in OR1200.
Data Cache Line Flush
Because data cache operates only in write-through mode, data cache line flush performs only line invalidation. Operation is performed by writing effective address to the DCBFR register.
Virtually the is no difference between data cache line flush and data cache line invalidate operation.
Data Cache Line Invalidate
Data cache line invalidate invalidates a single data cache line. Operation is performed by writing effective address to the DCBIR register.
Data Cache Line Write-back
Data cache line write-back operation does not do anything because data cache operates only in write-through mode.
Data Cache Line Lock
Locking of individual data cache lines is not implemented in OR1200.
Instruction Cache Operation
Instruction Cache Instruction Fetch Access
Instruction unit requests instruction from the instruction cache and forwards them to the instruction queue inside instruction unit. Therefore instruction unit is tightly coupled with the instruction cache.
If there is no instruction cache line miss nor ITLB miss, instruction fetch operation takes one clock cycle to execute.
Instruction cache cannot be explicitly modified like data cache can be with store instructions.
Instruction Cache Line Fill Operation
On a cache miss, a 4 beat sequential read burst with critical word first is performed. Critical word is forwarded to the instruction unit to minimize performance loss because of the cache miss.
EMBED Timing.Document.1
Figure SEQ Figure \* ARABIC 9. WISHBONE Block Read Cycle
REF _Ref513197552 \h Figure 9 shows how a cache line is read in WISHBONE read block cycle composed out of four read transfers.
If iwb_ERR_I or iwb_RTY_I is asserted instead of usual dwb_ACK_I, bus error exception is invoked.
Cache/Memory Coherency
OR1200 is not intended for use in multiprocessor environments. Therefore no support for coherency between local instruction cache and caches of other processors or main memory is implemented.
Instruction Cache Enabling/Disabling
Instruction cache is disabled at power up. Entire instruction cache can be enabled by setting bit SR[ICE] to one. Before instruction cache is enabled, it must be invalidated.
Instruction Cache Invalidation
Instruction cache in OR1200 does not support invalidation of entire instruction cache. Normal procedure to invalidate entire instruction cache is to cycle through all instruction cache lines and invalidate each line separately.
Instruction Cache Locking
Instruction cache implements way locking bits in instruction cache control register ICCR. Bits LWx lock individual ways when they are set to one.
Instruction Cache Line Prefetch
Instruction cache line prefetch is optional in the OpenRISC 1000 architecture and is not implemented in OR1200.
Instruction Cache Line Invalidate
Instruction cache line invalidate invalidates a single instruction cache line. Operation is performed by writing effective address to the ICBIR register.
Instruction Cache Line Lock
Locking of individual instruction cache lines is not implemented in OR1200.
Data MMU
Translation Disabled
Load/store address translation can be disabled by clearing bit SR[DME]. If translation is disabled, then physical address used to access data cache and optionally provided on dwb_ADDR_O, is the same as load/store effective address.
Translation Enabled
Load/store address translation can be enabled by setting bit SR[DME]. If translation is enabled, it provides load/store effective address to physical address translation and page protection for memory accesses.
EMBED Visio.Drawing.6
Figure SEQ Figure \* ARABIC 10. 32-bit Address Translation Mechanism using Two-Level Page Table
In OR1200 case, page tables must be managed by operating systems virtual memory management subsystem. REF _Ref513343227 \h Figure 10 shows address translation using two-level page table. Refer to OpenRISC 1000 System Architecture Manual for one-level page table address translation as well as for details about address translation and page table content.
DMMUCR and Flush of Entire DTLB
DMMUCR is not implemented in OR1200. Therefore page table base pointer (PTBP) must be stored in software variable. Flush of entire DTLB must be performed by software flush of every DTLB entry separately. Software flush is performed by manually writing bits from the TLB entries back to PTEs.
Page Protection
After a virtual address is determined to be within a page covered by the valid PTE, the access is validated by the memory protection mechanism. If this protection mechanism prohibits the access, a data page fault exception is generated.
The memory protection mechanism allows selectively granting read access and write access for both supervisor and user modes. The page protection mechanism provides protection at all page level granularities.
Protection attributeMeaningDTLBWyTR[SREx]Enable load operations in supervisor mode to the page.DTLBWyTR[SWEx]Enable store operations in supervisor mode to the page.DTLBWyTR[UREx]Enable load operations in user mode to the page.DTLBWyTR[UWEx]Enable store operations in user mode to the page.Table SEQ Table \* ARABIC 11. Protection Attributes for Load/Store Accesses
REF _Ref513346094 \h \* MERGEFORMAT Table 11 lists page protection attributes defined in DTLBWyTR pregister. For the individual page appropriate strategy out of seven possible strategies programmed with the PPI field of the PTE. Because OR1200 does not implement DMMUPR, translation of PTE[PPI] into suitable set of protection bits must be performed by software and written into DTLBWyTR.
DTLB Entry Reload
OR1200 does not implement DTLB entry reloads in hardware. Instead software routine must be used to search page table for correct page table entry (PTE) and copy it into the DTLB. Software is responsible for maintaining accessed and dirty bits in the page tables.
When LSU computes load/store effective address whose physical address is not already cached by DTLB, a DTLB miss exception is invoked.
DTLB reload routine must load the correct PTE to correct DTLBWyMR and DTLBWyTR register from one of possible DTLB ways.
DTLB Entry Invalidation
Special-purpose register DTLBEIR must be written with the effective address and corresponding DTLB entry will be invalidated in the local DTLB.
Locking DTLB Entries
Since all DTLB entry reloads are performed in software, there is no hardware locking of DTLB entries. Instead it is up to the software reload routine to avoid replacing some of the entries if so desired.
Page Attribute Dirty (D)
Dirty (D) attribute is not implemented in OR1200 DTLB. It is up to the operating system to generate dirty attribute bit with page protection mechanism.
Page Attribute Accessed (A)
Accessed (A) attribute is not implemented in OR1200 DTLB. It is up to the operating system to generate accessed attribute bit with page protection mechanism.
Page Attribute Weakly Ordered Memory (WOM)
Weakly ordered memory (WOM) attribute is not needed in OR1200 because all memory accesses are serialized and therefore this attribute is not implemented.
Page Attribute Write-Back Cache (WBC)
Write-back cache (WBC) attribute is not needed in OR1200 because data cache operates only in write-through mode and therefore this attribute is not implemented.
Page Attribute Caching-Inhibited (CI)
Caching-inhibited (CI) attribute is not implemented in OR1200 DTLB. Cached and uncached regions are divided by bit 30 of data effective address.
Effective AddressRegion0x00000000 - 0x3FFFFFFFCached0x40000000 - 0x7FFFFFFFUncached0x80000000 - 0xBFFFFFFFCached0xC0000000 - 0xFFFFFFFFUncachedTable SEQ Table \* ARABIC 12. Cached and uncached regions
Uncached accesses must be performed when I/O registers are memory mapped and all reads and writes must be always performed directly to the external interface and not to the data cache.
Page Attribute Cache Coherency (CC)
Cache coherency (CC) attribute is not needed in OR1200 because it doesnt implement support for multiprocessor environments and because data cache operates only in write-through mode and therefore this attribute is not implemented.
Instruction MMU
Translation Disabled
Instruction fetch address translation can be disabled by clearing bit SR[IME]. If translation is disabled, then physical address used to access instruction cache and optionally provided on iwb_ADDR_O, is the same as instruction fetch effective address.
Translation Enabled
Instruction fetch address translation can be enabled by setting bit SR[IME]. If translation is enabled, it provides instruction fetch effective address to physical address translation and page protection for instruction fetch accesses.
EMBED Visio.Drawing.6
Figure SEQ Figure \* ARABIC 11. 32-bit Address Translation Mechanism using Two-Level Page Table
In OR1200 case, page tables must be managed by operating systems virtual memory management subsystem. REF _Ref513343227 \h Figure 10 shows address translation using two-level page table. Refer to OpenRISC 1000 System Architecture Manual for one-level page table address translation as well as for details about address translation and page table content.
IMMUCR and Flush of Entire ITLB
IMMUCR is not implemented in OR1200. Therefore page table base pointer (PTBP) must be stored in software variable. Flush of entire ITLB must be performed by software flush of every ITLB entry separately. Software flush is performed by manually writing bits from the TLB entries back to PTEs.
Page Protection
After a virtual address is determined to be within a page covered by the valid PTE, the access is validated by the memory protection mechanism. If this protection mechanism prohibits the access, an instruction page fault exception is generated.
The memory protection mechanism allows selectively granting execute access for both supervisor and user modes. The page protection mechanism provides protection at all page level granularities.
Protection attributeMeaningITLBWyTR[SXEx]Enable execute operations in supervisor mode of the page.ITLBWyTR[UXEx]Enable execute operations in user mode of the page.Table SEQ Table \* ARABIC 13. Protection Attributes for Instruction Fetch Accesses
REF _Ref513346094 \h \* MERGEFORMAT Table 11 lists page protection attributes defined in ITLBWyTR pregister. For the individual page appropriate strategy out of seven possible strategies programmed with PPI field of the PTE. Because OR1200 does not implement IMMUPR, translation of PTE[PPI] into suitable set of protection bits must be performed by software and written into ITLBWyTR.
ITLB Entry Reload
OR1200 does not implement ITLB entry reloads in hardware. Instead software routine must be used to search page table for correct page table entry (PTE) and copy it into the ITLB. Software is responsible for maintaining accessed bit in the page tables.
When LSU computes instruction fetch effective address whose physical address is not already cached by ITLB, an ITLB miss exception is invoked.
ITLB reload routine must load the correct PTE to correct ITLBWyMR and ITLBWyTR register from one of possible ITLB ways.
ITLB Entry Invalidation
Special-purpose register ITLBEIR must be written with the effective address and corresponding ITLB entry will be invalidated in the local ITLB.
Locking ITLB Entries
Since all ITLB entry reloads are performed in software, there is no hardware locking of ITLB entries. Instead it is up to the software reload routine to avoid replacing some of the entries if so desired.
Page Attribute Dirty (D)
Dirty (D) attribute resides in the PTE but it is not used by the IMMU.
Page Attribute Accessed (A)
Accessed (A) attribute is not implemented in OR1200 ITLB. It is up to the operating system to generate accessed attribute bit with page protection mechanism.
Page Attribute Weakly Ordered Memory (WOM)
Weakly ordered memory (WOM) attribute is not needed in OR1200 because all instruction fetch accesses are serialized and therefore this attribute is not implemented.
Page Attribute Write-Back Cache (WBC)
Write-back cache (WBC) attribute resides in the PTE but it is not used by the IMMU.
Page Attribute Caching-Inhibited (CI)
Caching-inhibited (CI) attribute is not implemented in OR1200 ITLB. Cached and uncached regions are divided by bit 30 of instruction effective address.
Effective AddressRegion0x00000000 - 0x3FFFFFFFCached0x40000000 - 0x7FFFFFFFUncached0x80000000 - 0xBFFFFFFFCached0xC0000000 - 0xFFFFFFFFUncachedTable SEQ Table \* ARABIC 14. Cached and uncached regions
Page Attribute Cache Coherency (CC)
Cache coherency (CC) attribute resides in the PTE but it is not used by the IMMU.
Programmable Interrupt Controller
PICMR special-purpose register is used to mask or unmask up to 30 programmable interrupt sources. PICPR special-purpose register is used to assign low or high priority to maximum of 30 interrupt sources.
PICSR special-purpose register is used to determine status of each interrupt input. Bits in PICSR represent status of the interrupt inputs and the actual interrupt must be cleared in the device that is the source of a pending interrupt.
Tick Timer
Tick timer facility is enabled with TTMR[M]. TTCR is incremented with each clock cycle and a high priority interrupt can be asserted whenever lower 28 bits of TTCR match TTMR[TP] and TTMR[IE] is set.
TTCR restarts counting from zero when match event happens and TTMR[M] is 0x1. If TTMR[M] is 0x2, TTCR is stoped when match event happens and TTCR must be changed to start counting again. When TTMR[M] is 0x3, TTCR keeps counting even when match event happens.
Power Management
Clock Gating and Frequency Changing Versus CPU Stalling
If system doesnt support clock gating and if changing clock frequency in slow down mode is not possible, CPU can be stalled for certain number of clock cycles. This is much lower benefit on power consumption however it still reduces power consumption.
Slow Down Mode
Slow down mode is software controlled with the 4-bit value in PMR[SDF]. Lower value specifies higher expected performance from the processor core. Usually PMR[SDF] is dynamically set by the operating systems idle routine, that monitors the usage of the processor core.
PMR[SDF] is broadcasted on pm_clksd. External clock generator should adjust clock frequency according to the value of pm_clksd. Exact slow down factors are not defined but 0xF should go all the way down to 32.768 KHz.
With pm_clksd equal to 0xF, pm_lvolt is asserted. This is an indication for the external power supply to lower the voltage.
Doze Mode
To switch to doze mode, software should set the PMR[DME]. Once an interrupt is received by the programmable interrupt controller (PIC), pm_wakeup is asserted and external clock generation circuitry should enable all clocks. Once clocks are running RISC is switched back again to the normal mode and PMR[DME] is cleared.
When doze mode is enabled, pm_dc_gate, pm_ic_gate, pm_dmmu_gate, pm_immu_gate and pm_cpugate are asserted. As a result all clocks except clk_tt should be gated by external clock generation circuitry.
Sleep Mode
To switch to sleep mode, software should set the PMR[SME]. Once an interrupt is received by the programmable interrupt controller (PIC), pm_wakeup is asserted and external clock generation should enable all clocks. Once clocks are running, RISC is switched back again to the normal mode and PMR[SME] is cleared.
When sleep mode is enabled, pm_dc_gate, pm_ic_gate, pm_dmmu_gate, pm_immu_gate, pm_cpu_gate and pm_tt_gate are asserted. As a result all clocks including clk_tt should be gated by external clock generation circuitry.
In sleep mode, pm_lvolt is asserted. This is an indication for the external power supply to lower the voltage.
Clock Gating
Clock gating feature is not implemented in OR1200 power management.
Disabled Units Force Clock Gating
Units that are disabled in special-purpose register SR, have their clock gate signals asserted. Cleared bits SR[DCE], SR[ICE], SR[DME] and SR[IME] directly force assertion of pm_dc_gate, pm_ic_gate, pm_dmmu_gate and pm_immu_gate.
Debug Unit
Debug unit can be controlled through development interface or it can operate independently programmed and handled by the RISCs resident debug software.
Watchpoints
OR1200 debug unit does not implement OR12000 architecture watchpoints.
Breakpoint Exception
Which breakpointDMR2[WGB] bits specify which watchpoints invoke breakpoint exception. By invoking breakpoint exception, target resident debugger can be built.
Breakpoint is broadcasted on development interface on dbg_bp_o.
Development Interface
An additional development and debug interface IP core may be used to connect OpenRISC 1200 to standard debuggers using IEEE.1149.1 (JTAG) protocol.
Debugging Through Development Interface
The DSR special-purpose register specifies which exceptions cause the core to stop the execution of the exception handler and turn over control to development interface. It can be programmed by the resident debug software or by the development interface.
The DRR special-purpose register is specifies which event caused the core to stop the execution of program flow and turned over control to the development interface. It should be cleared by the resident debug software or by the development interface.
The DIR special-purpose register is not implemented.
Reading PC, Load/Store EA, Load Data, Store Data, Instruction
Crucial information like program counter (PC), load/store effective address (LSEA), load data, store data and current instruction in execution pipeline can be asynchronously read through the development interface.
dbg_op_i[2:0]Meaning0x0Reading Program Counter (PC)0x1Reading Load/Store Effective Address0x2Reading Load Data0x3Reading Store Data0x4Reading SPR0x5Writing SPR0x6Reading Instruction in Execution Pipeline0x7ReservedTable SEQ Table \* ARABIC 15. Development Interface Operation Commands
REF _Ref513329306 \h \* MERGEFORMAT Table 15 lists operation commands that control what is read or written through development interface. All reads except reads and writes of SPRs are asynchronous.
Reading and Writing SPRs Through Development Interface
For reads and write to SPRs dbg_op_i must be set to 0x4 and 0x5, respectively.
EMBED Timing.Document.1
Figure SEQ Figure \* ARABIC 12. Development Interface Cycles
REF _Ref513329852 \h \* MERGEFORMAT Figure 12 shows development interface cycles. Writes must be synchronous to the main RISC clock positive edge and should take one clock cycle. Reads must take two clock cycles because access to synchronous cache lines or to TLB entries introduces one clock cycle of delay.
If required, external debugger can stop the CPU core by asserting dbg_stall_i. This way it can have enough time to read all interesting registers from the RISC or guarantee that writes into SPRs are performed without RISC writing to the same registers.
Tracking Data Flow
An external debugger can monitor and record data flow inside the RISC for debugging purposes and profiling analysis. This is accomplished by monitoring status of the load/store unit, load/store effective address and load/store data, all available at the development interface.
dbg_lss_o[3:0]Load/Store Instruction in Execution0x0No load/store instruction in execution0x1Reserved for load doubleword0x2Load byte and zero extend0x3Load byte and sign extend0x4Load halfword and zero extend0x5Load halfword and sign extend0x6Load singleword and zero extend0x7Load singleword and sign extend0x8Reserved for store doubleword0x9Reserved0xAStore byte0xBReserved0xCStore halfword0xDReserved0xEStore singleword0xFReservedTable SEQ Table \* ARABIC 16. Status of the Load/Store Unit
External trace buffer can capture all interesting data flow events by analyzing status of the load/store unit available on dbg_lss_o. REF _Ref513326484 \h Table 16 lists different status encoding for the load/store unit.
Tracking Program Flow
An external debugger can monitor and record program flow inside the RISC for debugging purposes and profiling analysis. This is accomplished by monitoring status of the instruction unit, PC and fetched instruction word, all available at the development interface.
dbg_is_o[1:0]Instruction Fetch Status0x0No instruction fetch in progress0x1Normal instruction fetch0x2Executing branch instruction0x3Fetching instruction in delay slotTable SEQ Table \* ARABIC 17. Status of the Instruction Unit
External trace buffer can capture all interesting program flow events by analyzing status of the instruction unit available on dbg_is_o. REF _Ref513326219 \h \* MERGEFORMAT Table 17 lists different status encoding for the instruction unit.
Triggering External Watcpoint Event
REF _Ref513324670 \h \* MERGEFORMAT Figure 13 shows how development interface can assert dbg_ewt_I and cause watchpoint event. If programmed, external watchpoint event will cause a breakpoint exception.
EMBED Timing.Document.1
Figure SEQ Figure \* ARABIC 13. Assertion of External Watchpoint Trigger
4
Registers
This section describes all registers inside the OR1200 core. Shifting GRP number 11 bits left and adding REG number computes the address of each special-purpose register. All registers are 32 bits wide from software perspective. USER MODE and SUPV MODE specify the valid access types for each register in user mode and supervisor mode of operation. R/W stands for read and write access and R stands for read only access.
Registers list
Grp
#Reg #Reg NameUSER MODESUPV
MODEDescription00VRRVersion Register01UPRRUnit Present Register02CPUCFGRRCPU Configuration Register03DMMUCFGRRData MMU Configuration Register04IMMUCFGRRInstruction MMU Configuration Register05DCCFGRRData Cache Configuration Register06ICCFGRRInstruction Cache Configuration Register07DCFGRRDebug Configuration Register016PCR/WPC mapped to SPR space017SRR/WSupervision Register032EPCR0R/WException PC Register048EEAR0R/WException EA Register064ESR0R/WException SR Register01024-1055GPR0-GPR31R/WGPRs mapped to SPR space12DTLBEIRWData TLB Entry Invalidate Register11024-1151DTLBW0MR0-DTLBW0MR127R/WData TLB Match Registers Way 011536-1663DTLBW0TR0-DTLBW0TR127R/WData TLB Translate Registers Way 022ITLBEIRWInstruction TLB Entry Invalidate Register21024-1151ITLBW0MR0-ITLBW0MR127R/WInstruction TLB Match Registers Way 021536-1663ITLBW0TR0-ITLBW0TR127R/WInstruction TLB Translate Registers Way 030DCCRR/WDC Control Register31DCBIRWDC Block Invalidate Register3257DCBFRWWDC Block Flush Register40ICCRR/WIC Control Register4256ICBIRWWIC Block Invalidate Register5256MACLOR/WR/WMAC Low5257MACHIR/WR/WMAC High616DMR1R/WDebug Mode Register 1617DMR2R/WDebug Mode Register 2620DSRR/WDebug Stop Register621DRRR/WDebug Reason Register80PMRR/WPower Management Register91PICMRR/WPIC Mask Register92PICPRR/WPIC Priority Register93PICSRR/WPIC Status Register100TTMRR/WTick Timer Mode Register10256TTCRR*R/WTick Timer Count RegisterTable SEQ Table \* ARABIC 18. List of All Registers
REF _Ref513309410 \h \* MERGEFORMAT Table 18 lists all OpenRISC 1000 special-purpose registers implemented in OR1200. Registers VR and UPR are described below. For description of other registers refer to OpenRISC 1000 System Architecture Manual document.
Register VR description
Special-purpose register VR identifies the version (model) and revision level of the OpenRISC 1000 processor. It also specifies possible standard template on which this implementation is based.
Bit #AccessResetDescription5:0RRevisionREV
Revision number15:6R0x0Reserved23:16R0x00CFG
Configuration should be read from UPR and configuration registers31:24R0x12VER
Version number for OR1200 is fixed at 0x1200.Table SEQ Table \* ARABIC 19. VR Register
Register UPR description
Special-purpose register UPR identifies the units present in the processor. It has a bit for each implemented unit or functionality. Lower sixteen bits identify present units defined in the OpenRISC 1000 architecture. Upper sixteen bits define present custom units.
Bit #AccessResetDescription0R1UP
UPR present1R1DCP
Data cache present2R1ICP
Instruction cache present3R1DMP
Data MMU present4R1IMP
Instruction MMU present5R1MP
MAC present6R1DUP
Debug unit present7R0PCUP
Performance counters unit not present8R1PMP
Power Management Present9R1PICP
Programmable interrupt controller present10R1TTP
Tick timer present23:11RXReserved31:24R0xXXXXCUP
The user of the OR1200 core adds custom units.Table SEQ Table \* ARABIC 20. UPR Register
Register CPUCFGR description
Special-purpose register CPUCFGR identifies the capabilities and configuration of the CPU.
Bit #AccessResetDescription3:0R0x0NSGF
Zero number of shadow GPR files4R0HGF
No half GPR files5R1OB32S
ORBIS32 supported6R0OB64S
ORBIS64 not supported7R0OF32S
ORFPX32 not supported8R0OF64S
ORFPX64 not supported9R0OV64S
ORVDX64 not supportedTable SEQ Table \* ARABIC 21. CPUCFGR Register
Register DMMUCFGR description
Special-purpose register DMMUCFGR identifies the capabilities and configuration of the DMMU.
Bit #AccessResetDescription1:0R0x0NTW
One DTLB way4:2R0x4 0x7NTS
16, 32, 64 or 128 DTLB sets7:5R0x0NAE
No ATB Entries8R0CRI
No DMMU control register implemented9R0PRI
No protection register implemented10R1TEIRI
DTLB entry invalidate register implemented11R0HTR
No hardware DTLB reloadTable SEQ Table \* ARABIC 22. DMMUCFGR Register
Register IMMUCFGR description
Special-purpose register IMMUCFGR identifies the capabilities and configuration of the IMMU.
Bit #AccessResetDescription1:0R0x0NTW
One ITLB way4:2R0x4 0x7NTS
16, 32, 64 or 128 ITLB sets7:5R0x0NAE
No ATB Entries8R0CRI
No IMMU control register implemented9R0PRI
No protection register implemented10R1TEIRI
ITLB entry invalidate register implemented11R0HTR
No hardware ITLB reloadTable SEQ Table \* ARABIC 23. IMMUCFGR Register
Register DCCFGR description
Special-purpose register DCCFGR identifies the capabilities and configuration of the data cache.
Bit #AccessResetDescription2:0R0x0NCW
One DC way6:3R0x4 0x7NCS
16, 32, 64 or 128 DC sets7R0x0CBS
16-byte cache block size8R0CWS
Cache write-through strategy9R1CCRI
DC control register implemented10R1CBIRI
DC block invalidate register implemented11R0CBPRI
DC block prefetch register not implemented12R0CBLRI
DC block lock register not implemented13R1CBFRI
DC block flush register implemented14R0CBWBRI
DC block write-back register not implementedTable SEQ Table \* ARABIC 24. DCCFGR Register
Register ICCFGR description
Special-purpose register ICCFGR identifies the capabilities and configuration of the instruction cache.
Bit #AccessResetDescription2:0R0x0NCW
One IC way6:3R0x4 0x7NCS
16, 32, 64 or 128 IC sets7R0x0CBS
16-byte cache block size8R0CWS
Cache write-through strategy9R1CCRI
IC control register implemented10R1CBIRI
IC block invalidate register implemented11R0CBPRI
IC block prefetch register not implemented12R0CBLRI
IC block lock register not implemented13R1CBFRI
IC block flush register implemented14R0CBWBRI
IC block write-back register not implementedTable SEQ Table \* ARABIC 25. ICCFGR Register
Register DCFGR description
Special-purpose register DCFGR identifies the capabilities and configuration of the debut unit.
Bit #AccessResetDescription2:0R0x0NDP
Zero DVR/DCR pairs3R0 WPCI
Watchpoint counters not implementedTable SEQ Table \* ARABIC 26. DCFGR Register
5
IO ports
OR1200 IP core has several interfaces. REF _Ref507257694 \h Figure 14 below shows all interfaces:
Instruction and data WISHBONE host interfaces
Power management interface
Development interface
Interrupts interface
EMBED Visio.Drawing.6
Figure SEQ Figure \* ARABIC 14. Cores Interfaces
Instruction WISHBONE Master Interface
OR1200 has two master WISHBONE Rev B compliant interfaces. Instruction interface is used to connect OR1200 core to memory subsystem for purpose of fetching instructions or instruction cache lines.
PortWidthDirectionDescriptioniwb_CLK_I1InputClock inputiwb_RST_I1InputReset inputiwb_CYC_O1OutputIndicates valid bus cycle (core select)iwb_ADR_O32OutputsAddress outputsiwb_DAT_I32InputsData inputsiwb_DAT_O32OutputsData outputsiwb_SEL_O4OutputsIndicates valid bytes on data bus (during valid cycle it must be 0xf)iwb_ACK_I1InputAcknowledgment input (indicates normal transaction termination)iwb_ERR_I1InputError acknowledgment input (indicates an abnormal transaction termination)iwb_RTY_I1InputIn OR1200 treated same way as iwb_ERR_I.iwb_WE_O1OutputWrite transaction when asserted highiwb_STB_O1OutputsIndicates valid data transfer cycleTable SEQ Table \* ARABIC 27. Instruction WISHBONE Master Interface Signals
Data WISHBONE Master Interface
OR1200 has two master WISHBONE Rev B compliant interfaces. Data interface is used to connect OR1200 core to external peripherals and memory subsystem for purpose of reading and writing data or data cache lines.
PortWidthDirectionDescriptiondwb_CLK_I1InputClock inputdwb_RST_I1InputReset inputdwb_CYC_O1OutputIndicates valid bus cycle (core select)dwb_ADR_O32OutputsAddress outputsdwb_DAT_I32InputsData inputsdwb_DAT_O32OutputsData outputsdwb_SEL_O4OutputsIndicates valid bytes on data bus (during valid cycle it must be 0xf)dwb_ACK_I1InputAcknowledgment input (indicates normal transaction termination)dwb_ERR_I1InputError acknowledgment input (indicates an abnormal transaction termination)dwb_RTY_I1InputIn OR1200 treated same way as dwb_ERR_I.dwb_WE_O1OutputWrite transaction when asserted highdwb_STB_O1OutputsIndicates valid data transfer cycleTable SEQ Table \* ARABIC 28. Data WISHBONE Master Interface Signals
System Interface
System interface connects reset, clock and other system signals to the OR1200 core.
PortWidthDirectionDescriptionRst1InputAsynchronous resetclk_cpu1InputMain clock input to the RISCclk_dc1InputData cache clockclk_ic1InputInstruction cache clockclk_dmmu1InputData MMU clockclk_immu1InputInstruction MMU clockclk_tt1InputTick timer clockTable SEQ Table \* ARABIC 29. System Interface Signals
Development Interface
Development interface connects external development port to the RISCs internal debug facility. Debug facility allows control over program execution inside RISC, setting of breakpoints and watchpoints, and tracing of instruction and data flows.
PortWidthDirectionDescriptiondbg_dat_o32OutputTransfer of data from RISC to external development interfacedbg_dat_i32InputTransfer of data from external development interface to RISCdbg_adr_i32InputAddress of special-purpose register to be read or writtendbg_op_I3InputOperation select for development interfacedbg_lss_o4OutputStatus of load/store unitdbg_is_o2OutputStatus of instruction fetch unitdbg_wp_o11OutputStatus of watchpointsdbg_bp_o1OutputStatus of the breakpointdbg_stall_i1InputStalls RISC CPU coredbg_ewt_i1InputExternal watchpoint triggerTable SEQ Table \* ARABIC 30. Development Interface
Power Management Interface
Power management interface provides signals for interfacing RISC core with external power management circuitry. External power management circuitry is required to implement functions that are technology specific and cannot be implemented inside OR1200 core.
PortWidthDirectionGenerationDescriptionpm_clksd4OutputStatic (in SW)Slow down outputs that control reduction of RISC clock frequencypm_cpustall1Input-Synchronous stall of the RISCs CPU corepm_dc_gate1OutputDynamic (in HW)Gating of data cache clockpm_ic_gate1OutputDynamic (in HW)Gating of instruction cache clockpm_dmmu_gate1OutputDynamic (in HW)Gating of data MMU clockpm_immu_gate1OutputDynamic (in HW)Gating of instruction MMU clockpm_tt_gate1OutputDynamic (in HW)Gating of tick timer clockpm_cpu_gate1OutputStatic (in SW)Gating of main CPU clockpm_wakeup1OutputDynamic (in HW)Activate all clockspm_lvolt1OutputStatic (in SW)Lower voltageTable SEQ Table \* ARABIC 31. Power Management Interface
Interrupt Interface
Interrupt interface has interrupt inputs for interfacing external peripherals interrupt outputs to the RISC core. All interrupt inputs are evaluated on positive edge of main RISC clock.
PortWidthDirectionDescriptionpic_intsPIC_INTSInputExternal interruptsTable SEQ Table \* ARABIC 32. Interrupt Interface
A
Core HW Configuration
This section describes parameters that are set by the user of the core and define configuration of the core. Parameters must be set by the user before actual use of the core in simulation or synthesis.
Variable NameRangeDefaultDescriptionEADDR_WIDTH3232Effective address widthVADDR_WIDTH3232Virtual address widthPADDR_WIDTH24 3632Physical address widthDATA_WIDTH3232Data width / Operation widthDC_IMPL0 11Data cache implementationDC_SETS512512Data cache number of setsDC_WAYS11Data cache number of waysDC_LINE1616Data cache line sizeIC_IMPL0 11Instruction cache implementationIC_SETS512512Instruction cache number of setsIC_WAYS11Instruction cache number of waysIC_LINE1616Instruction cache line size in bytesDMMU_IMPL0 11Data MMU implementationDTLB_SETS6464Data TLB number of setsDTLB_WAYS11Data TLB number of waysIMMU_IMPL0 11Instruction MMU implementationITLB_SETS6464Instruction TLB number of setsITLB_WAYS11Instruction TLB number of waysPIC_INTS2 3230Number of interrupt inputs
OpenCores TITLEOpenRISC 1200 IP Core DATE \@"M/d/yy" 4/6/01
HYPERLINK "http://www.opencores.org/"www.opencores.org Rev 0.6 Preliminary PAGE 19 of NUMPAGES 63
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T O C \ o " 1 - 2 " \ t " H e a d e i n g 1 N a m e ; 1 " \ h H Y P E R L I N K \ l " _ t o c 2 2 9 " T a b l e O f C o n t e n t s 3
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H Y P E R L I N K \ l " _ t o c 2 0 4 5 " T i c k T i m e r 4 3
H Y P E R L I N K \ l " _ t o c 2 0 5 1 " P o w e r M a n a g e m e n t 4 3
H Y P E R L I N K \ l " _ t o c 2 0 8 7 " D e b u g U n i t 4 5
H Y P E R L I N K \ l " _ t o c 2 1 0 1 " D e v e l o p m e n t I n t e r f a c e 4 5
H Y P E R L I N K \ l " _ t o c 2 3 4 8 " 4 4 9
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H Y P E R L I N K \ l " _ t o c 2 3 5 3 " R e g i s t e r s l i s t 4 9
H Y P E R L I N K \ l " _ t o c 3 0 6 5 " R e g i s t e r V R d e s c r i p t i o n 5 0
H Y P E R L I N K \ l " _ t o c 3 1 3 6 " R e g i s t e r U P R d e s c r i p t i o n 5 1
H Y P E R L I N K \ l " _ t o c 3 3 3 8 " R e g i s t e r C P U C F G R d e s c r i p t i o n 5 1
H Y P E R L I N K \ l " _ t o c 3 4 5 1 " R e g i s t e r D M M U C F G R d e s c r i p t i o n 5 2
H Y P E R L I N K \ l " _ t o c 3 5 6 2 " R e g i s t e r I M M U C F G R d e s c r i p t i o n 5 2
H Y P E R L I N K \ l " _ t o c 3 6 7 3 " R e g i s t e r D C C F G R d e s c r i p t i o n 5 3
H Y P E R L I N K \ l " _ t o c 3 8 2 6 " R e g i s t e r I C C F G R d e s c r i p t i o n 5 4
H Y P E R L I N K \ l " _ t o c 3 9 7 6 " R e g i s t e r D C F G R d e s c r i p t i o n 5 4
H Y P E R L I N K \ l " _ t o c 4 0 2 5 " 5 5 6
I O p o r t s 5 6
H Y P E R L I N K \ l " _ t o c 4 0 3 8 " I n s t r u c t i o n W I S H B O N E M a s t e r I n t e r f a c e 5 6
H Y P E R L I N K \ l " _ t o c 4 2 0 2 " D a t a W I S H B O N E M a s t e r I n t e r f a c e 5 7
H Y P E R L I N K \ l " _ t o c 4 3 6 6 " S y s t e m I n t e r f a c e 5 7
H Y P E R L I N K \ l " _ t o c 2 1 0 1 " D e v e l o p m e n t I n t e r f a c e 5 8
H Y P E R L I N K \ l " _ t o c 4 6 1 0 " P o w e r M a n a g e m e n t I n t e r f a c e 5 8
H Y P E R L I N K \ l " _ t o c 4 7 8 3 " I n t e r r u p t I n t e r f a c e 5 9
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F i g u r e 2 . C P U / D S P B l o c k D i a g r a m 1 0
F i g u r e 3 . B l o c k D i a g r a m o f D e b u g U n i t 2 4
F i g u r e 4 . P o w e r - U p a n d R e s e t S e q u e n c e 2 6
F i g u r e 5 . P o w e r - U p a n d R e s e t S e q u e n c e w / G a t e d C l o c k 2 6
F i g u r e 6 . W I S H B O N E W r i t e C y c l e 3 1
F i g u r e 7 . W I S H B O N E B l o c k R e a d C y c l e 3 2
F i g u r e 8 . W I S H B O N E B l o c k R e a d / W r i t e C y c l e 3 2
F i g u r e 9 . W I S H B O N E B l o c k R e a d C y c l e 3 5
F i g u r e 1 0 . 3 2 - b i t A d d r e s s T r a n s l a t i o n M e c h a n i s m u s i n g T w o - L e v e l P a g e T a b l e 3 7
F i g u r e 1 1 . 3 2 - b i t A d d r e s s T r a n s l a t i o n M e c h a n i s m u s i n g T w o - L e v e l P a g e T a b l e 4 0
F i g u r e 1 2 . D e v e l o p m e n t I n t e r f a c e C y c l e s 4 6
F i g u r e 1 3 . A s s e r t i o n o f E x t e r n a l W a t c h p o i n t T r i g g e r 4 8
F i g u r e 1 4 . C o r e s I n t e r f a c e s 5 6
T a b l e O f T a b l e s
T O C \ c " T A B L E " T a b l e 1 . P o s s i b l e D a t a C a c h e C o n f i g u r a t i o n s o f O R 1 2 0 0 1 3
T a b l e 2 . P o s s i b l e I n s t r u c t i o n C a c h e C o n f i g u r a t i o n s o f O R 1 2 0 0 1 6
T a b l e 3 . P o s s i b l e D a t a T L B C o n f i g u r a t i o n s o f O R 1 2 0 0 1 8
T a b l e 4 . P o s s i b l e I n s t r u c t i o n T L B C o n f i g u r a t i o n s o f O R 1 2 0 0 2 0
T a b l e 5 . B l o c k D i a g r a m o f t h e I n t e r r u p t C o n t r o l l e r 2 2
T a b l e 6 . P o w e r C o n s u m p t i o n 2 3
T a b l e 7 : I n s t r u c t i o n s i m p l e m e n t e d i n O R 1 2 0 0 2 7
T a b l e 8 . E x e c u t i o n T i m e o f I n t e g e r I n s t r u c t i o n s 2 9
T a b l e 9 : E x e c u t i o n t i m e o f f l o a t i n g p o i n t i n s t r u c t i o n s 2 9
T a b l e 1 0 . L i s t o f I m p l e m e n t e d E x c e p t i o n s 3 0
T a b l e 1 1 . P r o t e c t i o n A t t r i b u t e s f o r L o a d / S t o r e A c c e s s e s 3 8
T a b l e 1 2 . C a c h e d a n d u n c a c h e d r e g i o n s 3 9
T a b l e 1 3 . P r o t e c t i o n A t t r i b u t e s f o r I n s t r u c t i o n F e t c h A c c e s s e s 4 1
T a b l e 1 4 . C a c h e d a n d u n c a c h e d r e g i o n s 4 2
T a b l e 1 5 . D e v e l o p m e n t I n t e r f a c e O p e r a t i o n C o m m a n d s 4 6
T a b l e 1 6 . S t a t u s o f t h e L o a d / S t o r e U n i t 4 7
T a b l e 1 7 . S t a t u s o f t h e I n s t r u c t i o n U n i t 4 7
T a b l e 1 8 . L i s t o f A l l R e g i s t e r s 5 0
T a b l e 1 9 . V R R e g i s t e r 5 1
T a b l e 2 0 . U P R R e g i s t e r 5 1
T a b l e 2 1 . C P U C F G R R e g i s t e r 5 2
T a b l e 2 2 . D M M U C F G R R e g i s t e r 5 2
T a b l e 2 3 . I M M U C F G R R e g i s t e r 5 3
T a b l e 2 4 . D C C F G R R e g i s t e r 5 4
T a b l e 2 5 . I C C F G R R e g i s t e r 5 4
T a b l e 2 6 . D C F G R R e g i s t e r 5 5
T a b l e 2 7 . I n s t r u c t i o n W I S H B O N E M a s t e r I n t e r f a c e S i g n a l s 5 7
T a b l e 2 8 . D a t a W I S H B O N E M a s t e r I n t e r f a c e S i g n a l s 5 7
T a b l e 2 9 . S y s t e m I n t e r f a c e S i g n a l s 5 8
T a b l e 3 0 . D e v e l o p m e n t I n t e r f a c e 5 8
T a b l e 3 1 . P o w e r M a n a g e m e n t I n t e r f a c e 5 9
T a b l e 3 2 . I n t e r r u p t I n t e r f a c e 5 9
1
I n t r o d u c t i o n
P u r p o s e o f t h i s d o c u m e n t i s t o d e f i n e s p e c i f i c a t i o n s o f t h e O p e n R I S C 1 2 0 0 i m p l e m e n t a t i o n . T h i s s p e c i f i c a t i o n d e f i n e s a l l i m p l e m e n t a t i o n s p e c i f i c v a r i a b l e s t h a t a r e n o t p a r t o f t h e g e n e r a l a r c h i t e c t u r e s p e c i f i c a t i o n . T h i s i n c l u d e s t y p e a n d s i z e o f d a t a a n d i n s t r u c t i o n c a c h e s , t y p e a n d s i z e o f d a t a a n d i n s t r u c t i o n M M U s , d e t a i l s o f a l l e x e c u t i o n p i p e l i n e s , i m p l e m e n t a t i o n o f e x c e p t i o n u n i t , i n t e r r u p t c o n t r o l l e r a n d o t h e r s u p p l e m e n t a l u n i t s .
T h i s d o c u m e n t d o e s n o t c o v e r g e n e r a l a r c h i t e c t u r e t o p i c s l i k e i n s t r u c t i o n s e t , m e m o r y a d d r e s s i n g m o d e s a n d o t h e r a r c h i t e c t u r a l d e f i n i t i o n s . S e e O p e n R I S C 1 0 0 0 S y s t e m A r c h i t e c t u r e M a n u a l f o r m o r e i n f o r m a t i o n a b o u t a r c h i t e c t u r e .
O p e n R I S C F a m i l y
O p e n R I S C 1 0 0 0 i s a r c h i t e c t u r e f o r a f a m i l y o f f r e e , o p e n s o u r c e R I S C p r o c e s s o r c o r e s . A s a r c h i t e c t u r e , O p e n R I S C 1 0 0 0 a l l o w s f o r a s p e c t r u m o f c h i p a n d s y s t e m i m p l e m e n t a t i o n s a t a v a r i e t y o f p r i c e / p e r f o r m a n c e p o i n t s f o r a r a n g e o f a p p l i c a t i o n s . I t i s a 3 2 / 6 4 - b i t l o a d a n d s t o r e R I S C a r c h i t e c t u r e d e s i g n e d w i t h e m p h a s i s o n p e r f o r m a n c e , s i m p l i c i t y , l o w p o w e r r e q u i r e m e n t s , s c a l a b i l i t y a n d v e r s a t i l i t y . O p e n R I S C 1 0 0 0 a r c h i t e c t u r e t a r g e t s m e d i u m a n d h i g h p e r f o r m a n c e n e t w o r k i n g , e m b e d d e d , a u t o m o t i v e a n d p o r t a b l e c o m p u t e r e n v i r o n m e n t s .
E M B E D M i c r o s o f t V i s i o D r a w i n g
A l l O p e n R I S C i m p l e m e n t a t i o n s , w h o s e f i r s t d i g i t i n i d e n t i f i c a t i o n n u m b e r i s 1 , b e l o n g t o O p e n R I S C 1 0 0 0 f a m i l y . S e c o n d d i g i t d e f i n e s w h i c h f e a t u r e s o f O p e n R I S C 1 0 0 0 a r c h i t e c t u r e a r e i m p l e m e n t e d a n d i n w h i c h w a y t h e y a r e i m p l e m e n t e d . L a s t t w o d i g i t s d e f i n e h o w a n i m p l e m e n t a t i o n i s c o n f i g u r e d b e f o r e i t i s u s e d i n a r e a l a p p l i c a t i o n .
O p e n R I S C 1 2 0 0
T h e O R 1 2 0 0 i s a 3 2 - b i t s c a l a r R I S C w i t h H a r v a r d m i c r o a r c h i t e c t u r e , 5 s t a g e i n t e g e r p i p e l i n e , v i r t u a l m e m o r y s u p p o r t ( M M U ) a n d b a s i c D S P c a p a b i l i t i e s .
D e f a u l t c a c h e s a r e 1 - w a y d i r e c t - m a p p e d 8 K B d a t a c a c h e a n d 1 - w a y d i r e c t - m a p p e d 8 K B i n s t r u c t i o n c a c h e , e a c h w i t h 1 6 - b y t e l i n e s i z e . B o t h c a c h e s a r e p h y s i c a l l y t a g g e d .
B y d e f a u l t M M U s a r e i m p l e m e n t e d a n d t h e y a r e c o n s t r u c t e d o f 6 4 - e n t r y h a s h b a s e d 1 - w a y d i r e c t - m p p e d d a t a T L B a n d 6 4 - e n t r y h a s h b a s e d 1 - w a y d i r e c t - m a p p e d i n s t r u c t i o n T L B .
S u p p l e m e n t a l f a c i l i t i e s i n c l u d e d e b u g u n i t f o r r e a l - t i m e d e b u g g i n g , h i g h r e s o l u t i o n t i c k t i m e r , p r o g r a m m a b l e i n t e r r u p t c o n t r o l l e r a n d p o w e r m a n a g e m e n t s u p p o r t .
W h e n i m p l e m e n t e d i n a t y p i c a l 0 . 1 8 u 6 L M p r o c e s s i t s h o u l d p r o v i d e o v e r 3 0 0 d h r y s t o n e 2 . 1 M I P S a t 3 0 0 M H z a n d 3 0 0 D S P M A C 3 2 x 3 2 o p e r a t i o n s , a t l e a s t 2 0 % m o r e t h a n a n y o t h e r c o m p e t i t o r i n t h i s c l a s s . O R 1 2 0 0 i n d e f a u l t c o n f i g u r a t i o n h a s a b o u t 1 M t r a n s i s t o r s .
O R 1 2 0 0 i s i n t e n d e d f o r e m b e d d e d , p o r t a b l e a n d n e t w o r k i n g a p p l i c a t i o n s . I t c a n s u c c e s s f u l l y c o m p e t e w i t h l a t e s t s c a l a r 3 2 - b i t R I S C p r o c e s s o r s i n h i s c l a s s a n d c a n e f f i c i e n t l y r u n a n y m o d e r n o p e r a t i n g s y s t e m .
C o m p e t i t o r s i n c l u d e A R M 1 0 , A R C a n d T e n s i l i c a R I S C p r o c e s s o r s .
F e a t u r e s
T h e f o l l o w i n g l i s t s t h e m a i n f e a t u r e s o f O R 1 2 0 0 I P c o r e :
A l l m a j o r c h a r a c t e r i s t i c s o f t h e c o r e c a n b e s e t b y t h e u s e r
H i g h p e r f o r m a n c e o f 3 0 0 D h r y s t o n e 2 . 1 M I P S a t 3 0 0 M H z u s i n g 0 . 1 8 u p r o c e s s
H i g h p e r f o r m a n c e c a c h e a n d M M U s u b s y s t e m s
W I S H B O N E S o C I n t e r c o n n e c t i o n R e v . B c o m p l i a n t i n t e r f a c e
2
A r c h i t e c t u r e
R E F _ R e f 5 1 1 2 0 6 9 2 3 \ h F i g u r e 1 b e l o w s h o w s g e n e r a l a r c h i t e c t u r e o f O R 1 2 0 0 I P c o r e . I t c o n s i s t s o f s e v e r a l b u i l d i n g b l o c k s :
C P U / D S P c e n t r a l b l o c k
D i r e c t - m a p p e d d a t a c a c h e
D i r e c t - m a p p e d i n s t r u c t i o n c a c h e
D a t a M M U b a s e d o n h a s h b a s e d D T L B
I n s t r u c t i o n M M U b a s e d o n h a s h b a s e d I T L B
P o w e r m a n a g e m e n t u n i t a n d p o w e r m a n a g e m e n t i n t e r f a c e
T i c k t i m e r
D e b u g u n i t a n d d e v e l o p m e n t i n t e r f a c e
I n t e r r u p t c o n t r o l l e r a n d i n t e r r u p t i n t e r f a c e
I n s t r u c t i o n a n d D a t a W I S H B O N E h o s t i n t e r f a c e s
E M B E D M i c r o s o f t V i s i o D r a w i n g
F i g u r e S E Q " F i g u r e " \ * A r a b i c 1 . C o r e ' s A r c h i t e c t u r e
C P U / D S P
C P U / D S P i s a c e n t r a l p a r t o f t h e O R 1 2 0 0 R I S C p r o c e s s o r . R E F _ R e f 5 1 1 2 0 8 7 3 0 \ h F i g u r e 2 s h o w s b a s i c b l o c k d i a g r a m o f t h e C P U / D S P .
O R 1 2 0 0 C P U / D S P i m p l e m e n t s o n l y 3 2 - b i t p a r t o f t h e O p e n R I S C 1 0 0 0 a r c h i t e c t u r e . 6 4 - b i t p a r t o f t h e a r c h i t e c t u r e a s w e l l a s f l o a t i n g - p o i n t a n d v e c t o r o p e r a t i o n s a r e n o t i m p l e m e n t e d i n O R 1 2 0 0 .
E M B E D M i c r o s o f t V i s i o D r a w i n g
F i g u r e S E Q " F i g u r e " \ * A r a b i c 2 . C P U / D S P B l o c k D i a g r a m
I n s t r u c t i o n u n i t
T h e i n s t r u c t i o n u n i t i m p l e m e n t s t h e b a s i c i n s t r u c t i o n p i p e l i n e , f e t c h e s i n s t r u c t i o n s f r o m t h e m e m o r y s u b s y s t e m , d i s p a t c h e s t h e m t o a v a i l a b l e e x e c u t i o n u n i t s , a n d m a i n t a i n s a s t a t e h i s t o r y t o e n s u r e a p r e c i s e e x c e p t i o n m o d e l a n d t h a t o p e r a t i o n s f i n i s h i n o r d e r . I t a l s o e x e c u t e s c o n d i t i o n a l b r a n c h a n d u n c o n d i t i o n a l j u m p i n s t r u c t i o n s .
T h e s e q u e n c e r c a n d i s p a t c h a s e q u e n t i a l i n s t r u c t i o n o n e a c h c l o c k i f t h e a p p r o p r i a t e e x e c u t i o n u n i t i s a v a i l a b l e . T h e e x e c u t i o n u n i t m u s t d i s c e r n w h e t h e r s o u r c e d a t a i s a v a i l a b l e a n d t o e n s u r e t h a t n o o t h e r i n s t r u c t i o n i s t a r g e t i n g t h e s a m e d e s t i n a t i o n r e g i s t e r .
I n s t r u c t i o n u n i t h a n d l e s o n l y O R B I S 3 2 a n d , o p t i o n a l l y , a s u b s e t o f t h e O R F P X 3 2 i n s t r u c t i o n c l a s s . S o m e O R F P X 3 2 a n d a l l O R F P X 3 2 6 4 a n d O R V D X 6 4 i n s t r u c t i o n c l a s s e s a r e n o t s u p p o r t e d b y t h e O R 1 2 0 0 a t p r e s e n t .
G e n e r a l - P u r p o s e R e g i s t e r s
O p e n R I S C 1 2 0 0 i m p l e m e n t s 3 2 g e n e r a l - p u r p o s e 3 2 - b i t r e g i s t e r s . O p e n R I S C 1 0 0 0 a r c h i t e c t u r e a l s o s u p p o r t s h a d o w c o p i e s o f r e g i s t e r f i l e t o i m p l e m e n t f a s t s w i t c h i n g b e t w e e n w o r k i n g c o n t e x t s , h o w e v e r t h i s f e a t u r e i s n o t i m p l e m e n t e d i n c u r r e n t O R 1 2 0 0 i m p l e m e n t a t i o n .
O R 1 2 0 0 i m p l e m e n t s g e n e r a l - p u r p o s e r e g i s t e r f i l e a s t w o s y n c h r o n o u s d u a l - p o r t m e m o r i e s w i t h c a p a c i t y o f 3 2 w o r d s b y 3 2 b i t s p e r w o r d .
L o a d / S t o r e U n i t
T h e l o a d / s t o r e u n i t ( L S U ) t r a n s f e r s a l l d a t a b e t w e e n t h e G P R s a n d t h e C P U ' s i n t e r n a l b u s . I t i s i m p l e m e n t e d a s a n i n d e p e n d e n t e x e c u t i o n u n i t s o t h a t s t a l l s i n m e m o r y s u b s y s t e m o n l y a f f e c t m a s t e r p i p e l i n e i f t h e r e i s a d a t a d e p e n d e n c y .
T h e f o l l o w i n g a r e L S U ' s m a i n f e a t u r e s :
a l l l o a d / s t o r e i n s t r u c t i o n i m p l e m e n t e d i n h a r d w a r e ( a t o m i c i n s t r u c t i o n s i n c l u d e d )
a d d r e s s e n t r y b u f f e r
p i p e l i n e d o p e r a t i o n
a l i g n e d a c c e s s e s f o r f a s t m e m o r y a c c e s s
W h e n l o a d a n d s t o r e i n s t r u c t i o n s a r e i s s u e d , t h e L S U d e t e r m i n e s i f a l l o p e r a n d s a r e a v a i l a b l e . T h e s e o p e r a n d s i n c l u d e t h e f o l l o w i n g :
a d d r e s s r e g i s t e r o p e r a n d
s o u r c e d a t a r e g i s t e r o p e r a n d ( f o r s t o r e i n s t r u c t i o n s )
d e s t i n a t i o n d a t a r e g i s t e r o p e r a n d ( f o r l o a d i n s t r u c t i o n s )
I n t e g e r E x e c u t i o n P i p e l i n e
T h e c o r e i m p l e m e n t s t h e f o l l o w i n g t y p e s o f 3 2 - b i t i n t e g e r i n s t r u c t i o n s :
A r i t h m e t i c i n s t r u c t i o n s
C o m p a r e i n s t r u c t i o n s
L o g i c a l i n s t r u c t i o n s
R o t a t e a n d s h i f t i n s t r u c t i o n s
M o s t i n t e g e r i n s t r u c t i o n s c a n e x e c u t e i n o n e c y c l e . F o r d e t a i l s a b o u t t i m i n g s e e t a b l e T B D .
M A C U n i t
T h e M A C u n i t e x e c u t e s D S P M A C o p e r a t i o n s . M A C o p e r a t i o n s a r e 3 2 x 3 2 w i t h 4 8 - b i t a c c u m u l a t o r . M A C u n i t i s f u l l y p i p e l i n e d a n d c a n a c c e p t n e w M A C o p e r a t i o n i n e a c h n e w c l o c k c y c l e .
F l o a t i n g P o i n t U n i t
T h e F P U i m p l e m e n t a t i o n i s b a s e d o n t w o o t h e r F P U s a v a i l a b l e f r o m O p e n C o r e s . o r g F o r t h e c o m p a r i s o n a n d c o n v e r s i o n f u n c t i o n s , p a r t s w e r e t a k e n f r o m t h e F P U p r o j e c t b y R u d o l f U s s e l m a n n , a n d f o r t h e a r i t h m e t i c o p e r a t i o n s , t h e f p u 1 0 0 p r o j e c t b y J i d a n A l - E r y a n i w a s c o n v e r t e d t o V e r i l o g H D L .
A l l O R F P X 3 2 i n s t r u c t i o n s e x c e p t f o r l f . m a d d . s a n d l f . r e m . s a r e s u p p o r t e d w h e n t h e F P U i s e n a b l e d i n t h e O R 1 2 0 0 c o n f i g u r a t i o n .
S y s t e m U n i t
T h e s y s t e m u n i t c o n n e c t s a l l o t h e r s i g n a l s o f t h e C P U / D S P t h a t a r e n o t c o n n e c t e d t h r o u g h i n s t r u c t i o n a n d d a t a i n t e r f a c e s . I t a l s o i m p l e m e n t s a l l s y s t e m s p e c i a l - p u r p o s e r e g i s t e r s ( e . g . s u p e r v i s o r r e g i s t e r ) .
E x c e p t i o n s
C o r e e x c e p t i o n s c a n b e g e n e r a t e d w h e n a n e x c e p t i o n c o n d i t i o n o c c u r s . E x c e p t i o n s o u r c e s i n O R 1 2 0 0 i n c l u d e t h e f o l l o w i n g :
E x t e r n a l i n t e r r u p t r e q u e s t
C e r t a i n m e m o r y a c c e s s c o n d i t i o n
I n t e r n a l e r r o r s , s u c h a s a n a t t e m p t t o e x e c u t e u n i m p l e m e n t e d o p c o d e
S y s t e m c a l l
I n t e r n a l e x c e p t i o n , s u c h a s b r e a k p o i n t e x c e p t i o n s
E x c e p t i o n h a n d l i n g i s t r a n s p a r e n t t o u s e r s o f t w a r e a n d u s e s t h e s a m e m e c h a n i s m t o h a n d l e a l l t y p e s o f e x c e p t i o n s . W h e n a n e x c e p t i o n i s t a k e n , c o n t r o l i s t r a n s f e r r e d t o a n e x c e p t i o n h a n d l e r a t a n o f f s e t d e f i n e d b y f o r t h e t y p e o f e x c e p t i o n e n c o u n t e r e d . E x c e p t i o n s a r e h a n d l e d i n s u p e r v i s o r m o d e .
D a t a C a c h e
T h e d e f a u l t c o n f i g u r a t i o n o f O R 1 2 0 0 d a t a c a c h e i s 8 - K b y t e , 1 - w a y d i r e c t - m a p p e d d a t a c a c h e , w h i c h a l l o w s r a p i d c o r e a c c e s s t o d a t a . H o w e v e r d a t a c a c h e c a n b e c o n f i g u r e d a c c o r d i n g t o t h e R E F _ R e f 5 1 2 0 9 8 4 9 1 \ h T a b l e 1 .
D i r e c t m a p p e d 1 K B p e r s e t 1 K B 2 K B p e r s e t 2 K B 4 K B p e r s e t 4 K B 8 K B p e r s e t 8 K B ( d e f a u l t ) T a b l e S E Q " T a b l e " \ * A r a b i c 1 . P o s s i b l e D a t a C a c h e C o n f i g u r a t i o n s o f O R 1 2 0 0
I t i s p o s s i b l e t o o p e r a t e t h e d a t a c a c h e w i t h w r i t e - t h r o u g h o r w r i t e - b a c k s t r a t e r g i e s .
F e a t u r e s :
d a t a c a c h e i s s e p a r a t e f r o m i n s t r u c t i o n c a c h e ( H a r v a r d a r c h i t e c t u r e )
d a t a c a c h e i m p l e m e n t s a l e a s t - r e c e n t l y u s e d ( L R U ) r e p l a c e m e n t a l g o r i t h m w i t h i n e a c h s e t
t h e c a c h e d i r e c t o r y i s p h y s i c a l l y a d d r e s s e d . T h e p h y s i c a l a d d r e s s t a g i s s t o r e d i n t h e c a c h e d i r e c t o r y
w r i t e - t h r o u g h o r w r i t e - b a c k o p e r a t i o n
e n t i r e c a c h e c a n b e d i s a b l e d , l i n e s i n v a l i d a t e d , f l u s h e d o r f o r c e d t o b e w r i t t e n b a c k , b y w r i t i n g t o c a c h e s p e c i a l p u r p o s e r e g i s t e r s
O n a m i s s , a n d a p p r o p r i a t e c o n d i t i o n s , t h e c a c h e l i n e i s f i l l e d o r e m p t i e d w i t h 1 6 - b y t e b u r s t s . T h e b u r s t f i l l i s p e r f o r m e d a s a c r i t i c a l - w o r d - f i r s t o p e r a t i o n ; t h e c r i t i c a l w o r d i s s i m u l t a n e o u s l y w r i t t e n t o t h e c a c h e a n d f o r w a r d e d t o t h e r e q u e s t i n g u n i t , t h u s m i n i m i z i n g s t a l l s d u e t o c a c h e f i l l l a t e n c y . D a t a c a c h e p r o v i d e s s t o r a g e f o r c a c h e t a g s a n d p e r f o r m s c a c h e l i n e r e p l a c e m e n t f u n c t i o n .
D a t a c a c h e i s t i g h t l y c o u p l e d t o e x t e r n a l i n t e r f a c e t o a l l o w e f f i c i e n t a c c e s s t o t h e s y s t e m m e m o r y c o n t r o l l e r .
T h e d a t a c a c h e s u p p l i e s d a t a t o t h e G P R s b y m e a n s o f a 3 2 - b i t i n t e r f a c e t o t h e l o a d / s t o r e u n i t . T h e L S U p r o v i d e s a l l l o g i c r e q u i r e d t o c a l c u l a t e e f f e c t i v e a d d r e s s e s , h a n d l e s d a t a a l i g n m e n t t o a n d f r o m t h e d a t a c a c h e , a n d p r o v i d e s s e q u e n c i n g f o r l o a d a n d s t o r e o p e r a t i o n s . W r i t e o p e r a t i o n s t o t h e d a t a c a c h e c a n b e p e r f o r m e d o n a b y t e , h a l f - w o r d o r w o r d b a s i s .
T h e d a t a c a c h e i s o r g a n i z e d a s 5 1 2 s e t s o f o n e l i n e . E a c h l i n e c o n s i s t s o f 1 6 b y t e s , s t a t e b i t s a n d a n a d d r e s s t a g . I t c a n a l s o b e c o n f i g u r e d w i t h 2 5 6 o r 3 2 l i n e s .
E M B E D M i c r o s o f t V i s i o D r a w i n g
E a c h l i n e c o n t a i n s f o u r c o n t i g u o u s w o r d s f r o m m e m o r y t h a t a r e l o a d e d f r o m a f o u r - w o r d a l i g n e d b o u n d a r y . A s a r e s u l t , c a c h e l i n e s a r e a l i g n e d w i t h p a g e b o u n d a r i e s .
I n s t r u c t i o n C a c h e
T h e d e f a u l t c o n f i g u r a t i o n o f O R 1 2 0 0 i n s t r u c t i o n c a c h e i s 8 - K b y t e , 1 - w a y d i r e c t m a p p e d i n s t r u c t i o n c a c h e , w h i c h a l l o w s r a p i d c o r e a c c e s s t o i n s t r u c t i o n s . H o w e v e r i n s t r u c t i o n c a c h e c a n b e c o n f i g u r e d a c c o r d i n g t o t h e R E F _ R e f 5 1 2 0 9 9 0 8 1 \ h .
D i r e c t m a p p e d 1 K B p e r s e t 1 K B 2 K B p e r s e t 2 K B 4 K B p e r s e t 4 K B 8 K B p e r s e t 8 K B ( d e f a u l t ) T a b l e S E Q " T a b l e " \ * A r a b i c 2 . P o s s i b l e I n s t r u c t i o n C a c h e C o n f i g u r a t i o n s o f O R 1 2 0 0
F e a t u r e s :
i n s t r u c t i o n c a c h e i s s e p a r a t e f r o m d a t a c a c h e ( H a r v a r d a r c h i t e c t u r e )
i n s t r u c t i o n c a c h e i m p l e m e n t s a l e a s t - r e c e n t l y u s e d ( L R U ) r e p l a c e m e n t a l g o r i t h m w i t h i n e a c h s e t
t h e c a c h e d i r e c t o r y i s p h y s i c a l l y a d d r e s s e d . T h e p h y s i c a l a d d r e s s t a g i s s t o r e d i n t h e c a c h e d i r e c t o r y
i t c a n b e d i s a b l e d o r i n v a l i d a t e d b y w r i t i n g t o c a c h e s p e c i a l p u r p o s e r e g i s t e r s
O n a m i s s , t h e c a c h e i s f i l l e d i n w i t h 1 6 - b y t e b u r s t s . T h e b u r s t f i l l i s p e r f o r m e d a s a c r i t i c a l - w o r d - f i r s t o p e r a t i o n ; t h e c r i t i c a l w o r d i s s i m u l t a n e o u s l y w r i t t e n t o t h e c a c h e a n d f o r w a r d e d t o t h e r e q u e s t i n g u n i t , t h u s m i n i m i z i n g s t a l l s d u e t o c a c h e f i l l l a t e n c y . I n s t r u c t i o n c a c h e p r o v i d e s s t o r a g e f o r c a c h e t a g s a n d p e r f o r m s c a c h e l i n e r e p l a c e m e n t f u n c t i o n .
I n s t r u c t i o n c a c h e i s t i g h t l y c o u p l e d t o e x t e r n a l i n t e r f a c e t o a l l o w e f f i c i e n t a c c e s s t o t h e s y s t e m m e m o r y c o n t r o l l e r .
T h e i n s t r u c t i o n c a c h e s u p p l i e s i n s t r u c t i o n s t o t h e i n s t r u c t i o n s e q u e n c e r b y m e a n s o f a 3 2 - b i t i n t e r f a c e t o t h e i n s t r u c t i o n f e t c h s u b u n i t . T h e i n s t r u c t i o n f e t c h s u b u n i t p r o v i d e s a l l l o g i c r e q u i r e d t o c a l c u l a t e e f f e c t i v e a d d r e s s e s .
T h e d a t a c a c h e i s o r g a n i z e d a s 5 1 2 s e t s o f o n e l i n e . E a c h l i n e c o n s i s t s o f 1 6 b y t e s , s t a t e b i t s a n d a n a d d r e s s t a g .
E M B E D M i c r o s o f t V i s i o D r a w i n g
E a c h l i n e c o n t a i n s f o u r c o n t i g u o u s w o r d s f r o m m e m o r y t h a t a r e l o a d e d f r o m a f o u r - w o r d a l i g n e d b o u n d a r y . A s a r e s u l t , c a c h e l i n e s a r e a l i g n e d w i t h p a g e b o u n d a r i e s .
D a t a M M U
T h e O R 1 2 0 0 i m p l e m e n t s a v i r t u a l m e m o r y m a n a g e m e n t s c h e m e t h a t p r o v i d e s m e m o r y a c c e s s p r o t e c t i o n a n d e f f e c t i v e - t o - p h y s i c a l a d d r e s s t r a n s l a t i o n . P r o t e c t i o n g r a n u l a r i t y i s a s d e f i n e d b y O p e n R I S C 1 0 0 0 a r c h i t e c t u r e - 8 - K b y t e a n d 1 6 - M b y t e p a g e s .
D i r e c t m a p p e d 1 6 e n t r i e s p e r w a y 1 6 D T L B e n t r i e s 3 2 e n t r i e s p e r w a y 3 2 D T L B e n t r i e s 6 4 e n t r i e s p e r w a y 6 4 D T L B e n t r i e s ( d e f a u l t ) 1 2 8 e n t r i e s p e r w a y 1 2 8 D T L B e n t r i e s T a b l e S E Q " T a b l e " \ * A r a b i c 3 . P o s s i b l e D a t a T L B C o n f i g u r a t i o n s o f O R 1 2 0 0
F e a t u r e s :
d a t a M M U i s s e p a r a t e f r o m i n s t r u c t i o n M M U
p a g e s i z e 8 - K b y t e
c o m p r e h e n s i v e p a g e p r o t e c t i o n s c h e m e
d i r e c t m a p p e d h a s h b a s e d t r a n s l a t i o n l o o k a s i d e b u f f e r ( D T L B ) w i t h t h e d e f a u l t o f 1 w a y a n d t h e f o l l o w i n g f e a t u r e s :
m i s s a n d f a u l t e x c e p t i o n s
s o f t w a r e t a b l e w a l k
h i g h p e r f o r m a n c e b e c a u s e o f h a s h e d b a s e d d e s i g n
v a r i a b l e n u m b e r D T L B e n t r i e s w i t h d e f a u l t o f 6 4 p e r e a c h w a y
E M B E D M i c r o s o f t V i s i o D r a w i n g
T h e M M U h a r d w a r e s u p p o r t s t w o - l e v e l s o f t w a r e t a b l e w a l k .
I n s t r u c t i o n M M U
T h e O R 1 2 0 0 i m p l e m e n t s a v i r t u a l m e m o r y m a n a g e m e n t s c h e m e t h a t p r o v i d e s m e m o r y a c c e s s p r o t e c t i o n a n d
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- - > $ * < L [ h q w ywqh#[+L1<4*641 + # - - Arial ! ! # 8 d d 2 ! ^ K - 2
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! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~
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! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z } ~ e f f e c t i v e - t o - p h y s i c a l a d d r e s s t r a n s l a t i o n . P r o t e c t i o n g r a n u l a r i t y i s a s d e f i n e d b y O p e n R I S C 1 0 0 0 a r c h i t e c t u r e - 8 - K b y t e a n d 1 6 - M b y t e p a g e s .
D i r e c t m a p p e d 1 6 e n t r i e s p e r w a y 1 6 D T L B e n t r i e s 3 2 e n t r i e s p e r w a y 3 2 D T L B e n t r i e s 6 4 e n t r i e s p e r w a y 6 4 D T L B e n t r i e s ( d e f a u l t ) 1 2 8 e n t r i e s p e r w a y 1 2 8 D T L B e n t r i e s T a b l e S E Q " T a b l e " \ * A r a b i c 4 . P o s s i b l e I n s t r u c t i o n T L B C o n f i g u r a t i o n s o f O R 1 2 0 0
F e a t u r e s :
i n s t r u c t i o n M M U i s s e p a r a t e f r o m d a t a M M U
p a g e s s i z e 8 - K b y t e
c o m p r e h e n s i v e p a g e p r o t e c t i o n s c h e m e
1 w a y d i r e c t - m a p p e d h a s h b a s e d t r a n s l a t i o n l o o k a s i d e b u f f e r ( I T L B ) w i t h t h e f o l l o w i n g f e a t u r e s :
m i s s a n d f a u l t e x c e p t i o n s
s o f t w a r e t a b l e w a l k
h i g h p e r f o r m a n c e b e c a u s e o f h a s h e d b a s e d d e s i g n
V a r i a b l e n u m b e r o f I T L B e n t r i e s w i t h d e f a u l t o f 6 4 e n t r i e s p e r w a y
E M B E D M i c r o s o f t V i s i o D r a w i n g
T h e M M U h a r d w a r e s u p p o r t s t w o - l e v e l s o f t w a r e t a b l e w a l k .
P r o g r a m m a b l e I n t e r r u p t C o n t r o l l e r
T h e i n t e r r u p t c o n t r o l l e r r e c e i v e s i n t e r r u p t s f r o m e x t e r n a l s o u r c e s a n d f o r w a r d s t h e m a s l o w o r h i g h p r i o r i t y i n t e r r u p t e x c e p t i o n t o t h e C P U c o r e .
E M B E D M i c r o s o f t V i s i o D r a w i n g
T a b l e S E Q " T a b l e " \ * A r a b i c 5 . B l o c k D i a g r a m o f t h e I n t e r r u p t C o n t r o l l e r
P r o g r a m m a b l e i n t e r r u p t c o n t r o l l e r h a s t h r e e s p e c i a l - p u r p o s e r e g i s t e r s a n d 3 2 i n t e r r u p t i n p u t s . I n t e r r u p t i n p u t 0 a n d 1 a r e a l w a y s e n a b l e d a n d c o n n e c t e d t o h i g h a n d l o w p r i o r i t y i n t e r r u p t i n p u t , r e s p e c t i v e l y .
3 0 o t h e r i n t e r r u p t i n p u t s c a n b e m a s k e d a n d a s s i g n e d l o w o r h i g h p r i o r i t y t h r o u g h p r o g r a m m i n g s p e c i a l - p u r p o s e r e g i s t e r s .
T i c k T i m e r
O R 1 2 0 0 i m p l e m e n t s t i c k t i m e r f a c i l i t y . B a s i c a l l y t h i s i s a t i m e r t h a t i s c l o c k e d b y R I S C c l o c k a n d i s u s e d b y t h e o p e r a t i n g s y s t e m t o p r e c i s e l y m e a s u r e t i m e a n d s c h e d u l e s y s t e m t a s k s .
O R 1 2 0 0 p r e c i s e l y f o l l o w a r c h i t e c t u r a l d e f i n i t i o n o f t h e t i c k t i m e r f a c i l i t y :
M a x i m u m t i m e r c o u n t o f 2 ^ 3 2 c l o c k c y c l e s
M a x i m u m t i m e p e r i o d o f 2 ^ 2 8 c l o c k c y c l e s b e t w e e n i n t e r r u p t s
M a s k a b l e t i c k t i m e r i n t e r r u p t
S i n g l e r u n , r e s t a r t a b l e o r c o n t i n u e s t i m e r
T i c k t i m e r o p e r a t e s f r o m i n d e p e n d e n t c l o c k s o u r c e s o t h a t d o z e p o w e r m a n a g e m e n t m o d e c a n b e i m p l e m e n t e d .
P o w e r M a n a g e m e n t S u p p o r t
T o o p t i m i z e p o w e r c o n s u m p t i o n , t h e O R 1 2 0 0 p r o v i d e s l o w - p o w e r m o d e s t h a t c a n b e u s e d t o d y n a m i c a l l y a c t i v a t e a n d d e a c t i v a t e c e r t a i n i n t e r n a l m o d u l e s .
O R 1 2 0 0 h a s t h r e e m a j o r f e a t u r e s t o m i n i m i z e p o w e r c o n s u m p t i o n :
S l o w a n d I d l e M o d e s ( S W c o n t r o l l e d c l o c k f r e q r e d u c t i o n )
D o z e a n d S l e e p M o d e s ( i n t e r r u p t w a k e - u p )
P o w e r M i n i m i z a t i o n F e a t u r e A p p r o x P o w e r C o n s u m p t i o n R e d u c t i o n S l o w a n d I d l e m o d e 2 x 1 0 x D o z e m o d e 1 0 0 x S l e e p m o d e 2 0 0 x D y n a m i c c l o c k g a t i n g N / A T a b l e S E Q " T a b l e " \ * A r a b i c 6 . P o w e r C o n s u m p t i o n
S l o w d o w n m o d e t a k e s a d v a n t a g e o f t h e l o w - p o w e r d i v i d e r s i n e x t e r n a l c l o c k g e n e r a t i o n c i r c u i t r y t o e n a b l e f u l l f u n c t i o n a l i t y , b u t a t a l o w e r f r e q u e n c y s o t h a t a p o w e r c o n s u m p t i o n i s r e d u c e d .
P M R [ S D F ] 4 b i t s a r e b r o a d c a s t e d o n p m _ c l k s d a n d e x t e r n a l c l o c k g e n e r a t i o n f o r t h e R I S C s h o u l d a d a p t R I S C c l o c k f r e q u e n c y a c c o r d i n g t o t h e v a l u e o n p m _ c l k s d .
W h e n s o f t w a r e i n i t i a t e s t h e d o z e m o d e , s o f t w a r e p r o c e s s i n g o n t h e c o r e s u s p e n d s . T h e c l o c k s t o t h e R I S C i n t e r n a l m o d u l e s a r e d i s a b l e d e x c e p t t o t h e t i c k t i m e r . H o w e v e r a n y o t h e r o n - c h i p b l o c k s c a n c o n t i n u e t o f u n c t i o n a s n o r m a l .
T h e O R 1 2 0 0 w i l l l e a v e d o z e m o d e a n d e n t e r n o r m a l m o d e w h e n a p e n d i n g i n t e r r u p t o c c u r s .
I n s l e e p m o d e , a l l O R 1 2 0 0 i n t e r n a l u n i t s a r e d i s a b l e d a n d c l o c k s g a t e d . O p t i o n a l l y i m p l e m e n t a t i o n m a y c h o o s e t o l o w e r t h e o p e r a t i n g v o l t a g e o f t h e O R 1 2 0 0 c o r e .
T h e O R 1 2 0 0 s h o u l d l e a v e s l e e p m o d e a n d e n t e r n o r m a l m o d e w h e n a p e n d i n g i n t e r r u p t o c c u r s .
D y n a m i c C l o c k g a t i n g ( u n i t c l o c k g a t i n g o n c l o c k b y c l o c k b a s i s ) i s n o t s u p p o r t e d b y O R 1 2 0 0 .
D e b u g u n i t
D e b u g u n i t a s s i s t s s o f t w a r e d e v e l o p e r s t o d e b u g t h e i r s y s t e m s . I t p r o v i d e s s u p p o r t o n l y f o r b a s i c d e b u g g i n g a n d d o e s n o t h a v e s u p p o r t f o r m o r e a d v a n c e d d e b u g f e a t u r e s o f O p e n R I S C 1 0 0 0 a r c h i t e c t u r e s u c h a s w a t c h p o i n t s , b r e a k p o i n t s a n d p r o g r a m - f l o w c o n t r o l r e g i s t e r s .
E M B E D M i c r o s o f t V i s i o D r a w i n g
F i g u r e S E Q " F i g u r e " \ * A r a b i c 3 . B l o c k D i a g r a m o f D e b u g U n i t
W a t c h p o i n t s a n d b r e a k p o i n t s a r e e v e n t s t r i g g e r e d b y p r o g r a m - o r d a t a - f l o w m a t c h i n g t h e c o n d i t i o n s p r o g r a m m e d i n t h e d e b u g r e g i s t e r s . B r e a k p o i n t s u n l i k e w a t c h p o i n t s a l s o s u s p e n d e x e c u t i o n o f t h e c u r r e n t p r o g r a m - f l o w a n d s t a r t b r e a k p o i n t e x c e p t i o n .
C l o c k s & R e s e t
T h e O R 1 2 0 0 c o r e h a s s e v e r a l c l o c k i n p u t s . C l o c k i n p u t c l k _ c p u c l o c k s C P U / D S P b l o c k a n d a l l o t h e r p a r t s o f t h e R I S C t h a t d o n o t h a v e s e p a r a t e c l o c k s . D a t a c a c h e i s c l o c k e d b y c l k _ d c , i n s t r u c t i o n c a c h e i s c l o c k e d b y c l k _ i c , d a t a M M U i s c l o c k e d b y c l k _ d m m u , i n s t r u c t i o n M M U i s c l o c k e d b y c l k _ i m m u a n d t i c k t i m e r i s c l o c k e d b y c l k _ t t . A l l c l o c k s m u s t h a v e t h e s a m e p h a s e a n d a s l o w c l o c k s k e w a s p o s s i b l e .
O R 1 2 0 0 h a s a s y n c h r o n o u s r e s e t s i g n a l . R e s e t s i g n a l r s t , w h e n a s s e r t e d h i g h , i m m e d i a t e l y r e s e t s a l l f l i p - f l o p s i n s i d e O R 1 2 0 0 . W h e n d e a s s e r t e d , O R 1 2 0 0 w i l l s t a r t r e s e t e x c e p t i o n .
W I S H B O N E I n t e r f a c e s
T w o W I S H B O N E i n t e r f a c e s c o n n e c t O R 1 2 0 0 c o r e t o e x t e r n a l p e r i p h e r a l s a n d e x t e r n a l m e m o r y s u b s y s t e m . T h e y a r e W I S H B O N E S o C I n t e r c o n n e c t i o n s p e c i f i c a t i o n R e v . B 3 c o m p l i a n t . T h e i m p l e m e n t a t i o n i m p l e m e n t s a 3 2 - b i t b u s w i d t h a n d d o e s n o t s u p p o r t o t h e r b u s w i d t h s .
3
O p e r a t i o n
T h i s s e c t i o n d e s c r i b e s t h e o p e r a t i o n o f t h e O R 1 2 0 0 c o r e . F o r o p e r a t i o n s t h a t p e r t a i n t o t h e a r c h i t e c t u r a l d e f i n i t i o n s , s e e O p e n R I S C 1 0 0 0 S y s t e m A r c h i t e c t u r e M a n u a l .
R e s e t
O R 1 2 0 0 h a s o n e a s y n c h r o n o u s r e s e t s i g n a l t h a t c a n b e u s e d b y a s o f t a n d h a r d r e s e t o n a h i g h e r s y s t e m h i e r a r c h y l e v e l s .
E M B E D
F i g u r e S E Q " F i g u r e " \ * A r a b i c 4 . P o w e r - U p a n d R e s e t S e q u e n c e
R E F _ R e f 5 1 3 2 0 6 8 1 0 \ h F i g u r e 4 s h o w s h o w a s y n c h r o n o u s r e s e t i s a p p l i e d a f t e r p o w e r i n g u p t h e O R 1 2 0 0 c o r e . R e s e t i s c o n n e c t e d t o a s y n c h r o n o u s r e s e t o f a l m o s t a l l f l i p - f l o p s i n s i d e R I S C c o r e . S p e c i a l c a r e m u s t b e t a k e n t o e n s u r e h o l d a n d s e t u p t i m e s o f a l l f l i p - f l o p s c o m p a r e d t o m a i n R I S C c l o c k .
I f s y s t e m i m p l e m e n t s g a t e d c l o c k s , t h e n c l o c k g a t i n g c a n b e u s e d t o e n s u r e p r o p e r r e s e t t i m i n g .
E M B E D
F i g u r e S E Q " F i g u r e " \ * A r a b i c 5 . P o w e r - U p a n d R e s e t S e q u e n c e w / G a t e d C l o c k
T h e a d d r e s s t h e P C a s s u m e s a t r e s e t i s d e f i n a b l e a t s y n t h e s i s t i m e . T h i s i s n o t t o b e c o n f u s e d w i t h t h e a b i l i t y t o s e t t h e e x c e p t i o n p r e f i x a d d r e s s w i t h t h e E P H b i t .
C P U / D S P
C P U / D S P i s i m p l e m e n t a t i o n o f t h e 3 2 - b i t p a r t o f t h e O p e n R I S C 1 0 0 0 a r c h i t e c t u r e a n d o n l y a s u b s e t o f a l l f e a t u r e s i s i m p l e m e n t e d .
I n s t r u c t i o n s
T h e f o l l o w i n g t a b l e l i s t s t h e i n s t r u c t i o n s i m p l e m e n t e d i n t h e O R 1 2 0 0 . T h o s e o p t i o n a l l y i m p l e m e n t e d a r e i n d i c a t e d a s s u c h .
I n s t r u c t i o n
m n e m o n i c O p t . I n s t r u c t i o n
m n e m o n i c O p t . I n s t r u c t i o n
m n e m o n i c O p t . I n s t r u c t i o n
m n e m o n i c O p t . l . a d d l . m f s p r l . s l l i l f . s u b . s Y l . a d d c Y l . m o v h i l . s r a l . a d d i l . m t s p r l . s r a i l . a n d l . m u l Y l . s r l l . a n d i l . m u l i Y l . s r l i l . b f l . n o p l . s u b Y l . b n f l . o r l . s w l . d i v Y l . o r i l . s y s l . j l . r f e l . t r a p l . j a l l . r o r i l . x o r l . j a l r l . s b l . x o r i l . j r l . s f e q l f . a d d . s Y l . l b s l . s f g e s l f . d i v . s Y l . l b z l . s f g e u l f . f t o i . s Y l . l h s l . s f g t s l f . i t o f . s Y l . l h z l . s f g t u l f . m u l . s Y l . l w s l . s f l e u l f . s f e q . s Y l . l w z l . s f l t s l f . s f g e . s Y l . m a c Y l . s f l t u l f . s f g t . s Y l . m a c i Y l . s f n e l f . s f l e . s Y l . m a c r c Y l . s h l f . s f l t . s Y l . m s b Y l . s l l l f . s f n e . s Y T a b l e S E Q " T a b l e " \ * A r a b i c 7 : I n s t r u c t i o n s i m p l e m e n t e d i n O R 1 2 0 0
F o r a c o m p l e t e d e s c r i p t i o n o f e a c h i n s t r u c t i o n ' s f o r m a t r e f e r t o t h e O p e n R I S C 1 0 0 0 S y s t e m A r c h i t e c t u r e M a n u a l .
I n s t r u c t i o n U n i t
I n s t r u c t i o n u n i t g e n e r a t e s i n s t r u c t i o n f e t c h e f f e c t i v e a d d r e s s a n d f e t c h e s i n s t r u c t i o n s f r o m i n s t r u c t i o n c a c h e . E a c h c l o c k c y c l e o n e i n s t r u c t i o n c a n b e f e t c h e d . I n s t r u c t i o n f e t c h E A i s f u r t h e r t r a n s l a t e d i n t o p h y s i c a l a d d r e s s b y I M M U .
G e n e r a l - P u r p o s e R e g i s t e r s
G e n e r a l - p u r p o s e r e g i s t e r f i l e c a n s u p p l y t w o r e a d o p e r a n d s e a c h c l o c k c y c l e a n d s t o r e o n e r e s u l t i n a d e s t i n a t i o n r e g i s t e r .
G P R s c a n b e a l s o r e a d a n d w r i t t e n t h r o u g h d e v e l o p m e n t i n t e r f a c e .
L o a d / S t o r e U n i t
L S U c a n e x e c u t e o n e l o a d i n s t r u c t i o n e v e r y t w o c l o c k c y c l e s a s s u m i n g l o a d i n s t r u c t i o n h a v e a h i t i n t h e d a t a c a c h e . E x e c u t i o n o f s t o r e i n s t r u c t i o n s t a k e s o n e c l o c k c y c l e a s s u m i n g t h e y h a v e a h i t i n t h e d a t a c a c h e .
L S U p e r f o r m s c a l c u l a t i o n o f t h e l o a d / s t o r e e f f e c t i v e a d d r e s s . E A i s f u r t h e r t r a n s l a t e d i n t o p h y s i c a l a d d r e s s b y D M M U .
L o a d / s t o r e e f f e c t i v e a d d r e s s a n d l o a d a n d s t o r e d a t a c a n b e a l s o a c c e s s e d t h r o u g h d e v e l o p m e n t i n t e r f a c e .
I n t e g e r E x e c u t i o n P i p e l i n e
T h e c o r e i m p l e m e n t s t h e f o l l o w i n g t y p e s o f 3 2 - b i t i n t e g e r i n s t r u c t i o n s :
A r i t h m e t i c i n s t r u c t i o n s
C o m p a r e i n s t r u c t i o n s
L o g i c a l i n s t r u c t i o n s
R o t a t e a n d s h i f t i n s t r u c t i o n s
I n s t r u c t i o n G r o u p C l o c k C y c l e s t o E x e c u t e A r i t h m e t i c e x c e p t M u l t i p l y / D i v i d e 1 M u l t i p l y 3 D i v i d e N o t i m p l e m e n t e d C o m p a r e 1 L o g i c a l 1 R o t a t e a n d S h i f t 1 O t h e r s 1 T a b l e S E Q " T a b l e " \ * A r a b i c 8 . E x e c u t i o n T i m e o f I n t e g e r I n s t r u c t i o n s
R E F _ R e f 5 1 3 3 0 8 5 8 8 \ h T a b l e 8 l i s t s e x e c u t i o n t i m e s f o r i n s t r u c t i o n s e x e c u t e d b y i n t e g e r e x e c u t i o n p i p e l i n e . M o s t i n s t r u c t i o n s a r e e x e c u t e d i n o n e c l o c k c y c l e .
M A C U n i t
M A C u n i t e x e c u t e s l . m a c i n s t r u c t i o n s . M A C u n i t i m p l e m e n t s 3 2 x 3 2 f u l l y p i p e l i n e d m u l t i p l i e r a n d 4 8 - b i t a c c u m u l a t o r . M A C u n i t c a n a c c e p t o n e n e w l . m a c i n s t r u c t i o n e a c h c l o c k c y c l e .
F l o a t i n g P o i n t U n i t
T h e f l o a t i n g p o i n t u n i t h a s a m e c h a n i s m t o s t a l l t h e p r o c e s s o r p i p e l i n e u n t i l p r o c e s s i n g h a s c o m p l e t e d .
T h e f o l l o w i n g t a b l e i n d i c a t e s t h e n u m b e r o f c y c l e s p e r o p e r a t i o n
O p e r a t i o n C y c l e s A d d / s u b t r a c t 1 0 M u l t i p l y 3 8 D i v i d e 3 7 C o m p a r e 2 C o n v e r t 7 T a b l e S E Q " T a b l e " \ * A r a b i c 9 : E x e c u t i o n t i m e o f f l o a t i n g p o i n t i n s t r u c t i o n s
S y s t e m U n i t
S y s t e m u n i t i m p l e m e n t s s y s t e m c o n t r o l a n d s t a t u s s p e c i a l - p u r p o s e r e g i s t e r s a n d e x e c u t e s a l l l . m t s p r / l . m f s p r i n s t r u c t i o n s .
E x c e p t i o n s
T h e c o r e i m p l e m e n t s a p r e c i s e e x c e p t i o n m o d e l . T h i s m e a n s t h a t w h e n a n e x c e p t i o n i s t a k e n , t h e f o l l o w i n g c o n d i t i o n s a r e m e t :
S u b s e q u e n t i n s t r u c t i o n s i n p r o g r a m f l o w a r e d i s c a r d e d
P r e v i o u s i n s t r u c t i o n s f i n i s h a n d w r i t e b a c k t h e i r r e s u l t s
T h e a d d r e s s o f f a u l t i n g i n s t r u c t i o n i s s a v e d i n E P C R r e g i s t e r s a n d t h e m a c h i n e s t a t e i s s a v e d t o E S R r e g i s t e r s
E x c e p t i o n T y p e V e c t o r O f f s e t c a u s i n g c o n d i t i o n s R e s e t 0 x 1 0 0 C a u s e d b y r e s e t . B u s E r r o r 0 x 2 0 0 C a u s e d b y a n a t t e m p t t o a c c e s s i n v a l i d p h y s i c a l a d d r e s s . D a t a P a g e F a u l t 0 x 3 0 0 G e n e r a t e d a r t i f i c i a l l y b y D T L B m i s s e x c e p t i o n h a n d l e r w h e n n o m a t c h i n g P T E f o u n d i n p a g e t a b l e s o r p a g e p r o t e c t i o n v i o l a t i o n f o r l o a d / s t o r e o p e r a t i o n s . I n s t r u c t i o n P a g e F a u l t 0 x 4 0 0 G e n e r a t e d a r t i f i c i a l l y b y I T L B m i s s e x c e p t i o n h a n d l e r w h e n n o m a t c h i n g P T E f o u n d i n p a g e t a b l e s o r p a g e p r o t e c t i o n v i o l a t i o n f o r i n s t r u c t i o n f e t c h . L o w P r i o r i t y E x t e r n a l I n t e r r u p t 0 x 5 0 0 L o w p r i o r i t y e x t e r n a l i n t e r r u p t a s s e r t e d . A l i g n m e n t 0 x 6 0 0 L o a d / s t o r e a c c e s s t o n a t u r a l l y n o t a l i g n e d l o c a t i o n . I l l e g a l I n s t r u c t i o n 0 x 7 0 0 I l l e g a l i n s t r u c t i o n i n t h e i n s t r u c t i o n s t r e a m . H i g h P r i o r i t y E x t e r n a l I n t e r r u p t 0 x 8 0 0 H i g h p r i o r i t y e x t e r n a l i n t e r r u p t a s s e r t e d . D - T L B M i s s 0 x 9 0 0 N o m a t c h i n g e n t r y i n D T L B ( D T L B m i s s ) . I - T L B M i s s 0 x A 0 0 N o m a t c h i n g e n t r y i n I T L B ( I T L B m i s s ) . S y s t e m C a l l 0 x C 0 0 S y s t e m c a l l i n i t i a t e d b y s o f t w a r e . F l o a t i n g p o i n t e x c e p t i o n 0 x D 0 0 F P o p e r a t i o n c a u s e d f l a g s i n F P C S R t o b e c o m e s e t . T r a p 0 x E 0 0 T r a p i n s t r u c t i o n w a s d e c o d e d T a b l e S E Q " T a b l e " \ * A r a b i c 1 0 . L i s t o f I m p l e m e n t e d E x c e p t i o n s
T h e O R 1 2 0 0 e x c e p t i o n s u p p o r t d o e s n o t i n c l u d e s u p p o r t f o r f a s t c o n t e x t s w i t c h i n g .
D a t a C a c h e O p e r a t i o n
D a t a C a c h e L o a d / S t o r e A c c e s s
L o a d / s t o r e u n i t r e q u e s t s d a t a f r o m t h e d a t a c a c h e a n d s t o r e s t h e m i n t o t h e g e n e r a l - p u r p o s e r e g i s t e r f i l e a n d f o r w a r d s t h e m t o i n t e g e r e x e c u t i o n u n i t s . T h e r e f o r e L S U i s t i g h t l y c o u p l e d w i t h t h e d a t a c a c h e .
I f t h e r e i s n o d a t a c a c h e l i n e m i s s n o r D T L B m i s s , l o a d o p e r a t i o n s t a k e t w o c l o c k c y c l e s t o e x e c u t e a n d s t o r e o p e r a t i o n s t a k e o n e c l o c k c y c l e t o e x e c u t e . L S U d o e s a l l t h e d a t a a l i g n m e n t w o r k .
D a t a c a n b e w r i t t e n t o t h e d a t a c a c h e o n a w o r d , h a l f - w o r d o r b y t e b a s i s . S i n c e d a t a c a c h e o n l y o p e r a t e s i n w r i t e - t h r o u g h m o d e , a l l w r i t e s a r e i m m e d i a t e l y w r i t t e n b a c k t o m a i n m e m o r y o r t o t h e n e x t l e v e l o f c a c h e s .
E M B E D
F i g u r e S E Q " F i g u r e " \ * A r a b i c 6 . W I S H B O N E W r i t e C y c l e
R E F _ R e f 5 1 3 1 9 3 2 4 2 \ h F i g u r e 6 s h o w s h o w a w r i t e - t h r o u g h c y c l e o n d a t a W I S H B O N E i n t e r f a c e i s p e r f o r m e d w h e n a s t o r e i n s t r u c t i o n h i t s i n t h e d a t a c a c h e .
I f d w b _ E R R _ I o r d w b _ R T Y _ I i s a s s e r t e d i n s t e a d o f u s u a l d w b _ A C K _ I , b u s e r r o r e x c e p t i o n i s i n v o k e d .
D a t a C a c h e L i n e F i l l O p e r a t i o n
W h e n e x e c u t i n g l o a d i n s t r u c t i o n a n d a c a c h e m i s s o c c u r s , d e p e n d i n g o n w h e t h e r t h e c a c h e u s e s w r i t e - t h r o u g h o r w r i t e - b a c k s t r a t e g y a n d t h e l i n e i s c l e a n o r i n v a l i d , a 4 b e a t s e q u e n t i a l r e a d b u r s t w i t h c r i t i c a l w o r d f i r s t i s p e r f o r m e d . I f t h e s t r a t e g y i s w r i t e - b a c k a n d t h e l i n e i s d i r t y , t h e l i n e i s f i r s t w r i t t e n b a c k t o m e m o r y . T h e c r i t i c a l w o r d i s f o r w a r d e d t o t h e l o a d / s t o r e u n i t t o m i n i m i z e p e r f o r m a n c e l o s s b e c a u s e o f t h e c a c h e m i s s .
E M B E D
F i g u r e S E Q " F i g u r e " \ * A r a b i c 7 . W I S H B O N E B l o c k R e a d C y c l e
R E F _ R e f 5 1 3 1 9 4 8 2 1 \ h F i g u r e 7 s h o w s h o w a c a c h e l i n e i s r e a d i n W I S H B O N E r e a d b l o c k c y c l e c o m p o s e d o u t o f f o u r r e a d t r a n s f e r s .
I f d w b _ E R R _ I o r d w b _ R T Y _ I i s a s s e r t e d i n s t e a d o f u s u a l d w b _ A C K _ I , b u s e r r o r e x c e p t i o n i s i n v o k e d .
W h e n e x e c u t i n g a s t o r e i n s t r u c t i o n w i t h t h e c a c h e i n w r i t e - t h r o u g h s t r a t e g y , a n d a c a c h e m i s s o c c u r s , t h e w r i t e i s s i m p l y p u t o n t h e b u s a n d n o c a c h i n g o c c u r s . I f i t i s a m i s s a n d t h e c a c h e i s i n w r i t e b a c k s t r a t e g y a n d t h e l i n e i s v a l i d a n d c l e a n o r i n v a l i d , a 4 b e a t s e q u e n t i a l r e a d b u r s t t o f i l l t h e l i n e i s p e r f o r m e d , a n d t h e t h e w r i t e t o c a c h e o c c u r s . I f s t o r i n g a n d a c a c h e m i s s o c c u r s , a n d t h e d e s i r e d l i n e i s v a l i d a n d d i r t y , i t i s f i r s t w r i t t e n b a c k t o m e m o r y b e f o r e t h e d e s i r e d l i n e i s r e a d .
E M B E D
F i g u r e S E Q " F i g u r e " \ * A r a b i c 8 . W I S H B O N E B l o c k R e a d / W r i t e C y c l e
R E F _ R e f 5 1 3 1 9 5 0 7 2 \ h F i g u r e 8 s h o w s h o w a c a c h e l i n e i s r e a d i n W I S H B O N E r e a d b l o c k c y c l e f o l l o w e d b y a w r i t e t r a n s f e r .
I f d w b _ E R R _ I o r d w b _ R T Y _ I i s a s s e r t e d i n s t e a d o f u s u a l d w b _ A C K _ I , b u s e r r o r e x c e p t i o n i s i n v o k e d .
C a c h e / M e m o r y C o h e r e n c y
D a t a c a c h e i n O R 1 2 0 0 o p e r a t e s i n e i t h e r w r i t e - t h r o u g h o r w r i t e - b a c k m o d e , d e f i n a b l e a t s y n t h e s i s t i m e , f o r d e f a u l t u s e , a n d r u n t i m e w h e n D M M U i s u s e d . T h e r e i s c u r r e n t l y n o c o h e r e n c y s u p p o r t b e t w e e n l o c a l d a t a c a c h e a n d c a c h e s o f o t h e r p r o c e s s o r s .
D a t a C a c h e E n a b l i n g / D i s a b l i n g
D a t a c a c h e i s d i s a b l e d a t p o w e r u p . E n t i r e d a t a c a c h e c a n b e e n a b l e d b y s e t t i n g b i t S R [ D C E ] t o o n e . B e f o r e d a t a c a c h e i s e n a b l e d , i t m u s t b e i n v a l i d a t e d .
D a t a C a c h e I n v a l i d a t i o n
D a t a c a c h e i n O R 1 2 0 0 d o e s n o t s u p p o r t i n v a l i d a t i o n o f e n t i r e d a t a c a c h e . N o r m a l p r o c e d u r e t o i n v a l i d a t e e n t i r e d a t a c a c h e i s t o c y c l e t h r o u g h a l l d a t a c a c h e l i n e s a n d i n v a l i d a t e e a c h l i n e s e p a r a t e l y .
D a t a C a c h e L o c k i n g
D a t a c a c h e i m p l e m e n t s w a y l o c k i n g b i t s i n d a t a c a c h e c o n t r o l r e g i s t e r D C C R . B i t s L W x l o c k i n d i v i d u a l w a y s w h e n t h e y a r e s e t t o o n e .
D a t a C a c h e L i n e P r e f e t c h
D a t a c a c h e l i n e p r e f e t c h i s o p t i o n a l i n t h e O p e n R I S C 1 0 0 0 a r c h i t e c t u r e a n d i s n o t i m p l e m e n t e d i n O R 1 2 0 0 .
D a t a C a c h e L i n e F l u s h
O p e r a t i o n i s p e r f o r m e d b y w r i t i n g e f f e c t i v e a d d r e s s t o t h e D C B F R r e g i s t e r .
W h e n a c a c h e l i n e i s v a l i d a n d c l e a n , o r t h e c a c h e i s i n w r i t e - t h r o u g h s t r a t e g y , t h e l i n e i s i n v a l i d a t e d a n d n o w r i t e - b a c k o c c u r s .
D a t a C a c h e L i n e I n v a l i d a t e
D a t a c a c h e l i n e i n v a l i d a t e i n v a l i d a t e s a s i n g l e d a t a c a c h e l i n e . O p e r a t i o n i s p e r f o r m e d b y w r i t i n g e f f e c t i v e a d d r e s s t o t h e D C B I R r e g i s t e r .
I f c a c h e i s i n w r i t e - b a c k s t r a t e g y , i t i s b e s t t o u s e t h e l i n e f l u s h f u n c t i o n .
D a t a C a c h e L i n e W r i t e - b a c k
O p e r a t i o n i s p e r f o r m e d b y w r i t i n g e f f e c t i v e a d d r e s s t o t h e D C B W R r e g i s t e r .
I f c a c h e i s i n w r i t e - t h r o u g h s t r a t e g y , t h i s o p e r a t i o n i s i g n o r e d a s n o l i n e s w i l l b e c a c h e d a n d d i r t y , c a p a b l e o f b e i n g w r i t t e n b a c k .
D a t a C a c h e L i n e L o c k
L o c k i n g o f i n d i v i d u a l d a t a c a c h e l i n e s i s n o t i m p l e m e n t e d i n O R 1 2 0 0 .
D a t a C a c h e i n h i b i t w i t h a d d r e s s b i t 3 1 s e t
I f D M M U i s d i s a b l e d , b y d e f a u l t a l l a d d r e s s e s w i t h b i t 3 1 o f t h e a d d r e s s a s s e r t e d h i g h w i l l c a u s e t h e d a t a c a c h e t o b e i n h i b i t e d , m e a n i n g n o r e a d s o r w r i t e s a r e c a c h e d .
I f t h e D M M U i s e n a b l e d , i t i s p o s s i b l e f o r a n y a d d r e s s t o b e i n h i b i t e d o r n o t , a n d i n t h e s e m o d e s t h e c a c h e b e h a v e s a c c o r d i n g l y .
I n s t r u c t i o n C a c h e O p e r a t i o n
I n s t r u c t i o n C a c h e I n s t r u c t i o n F e t c h A c c e s s
I n s t r u c t i o n u n i t r e q u e s t s i n s t r u c t i o n f r o m t h e i n s t r u c t i o n c a c h e a n d f o r w a r d s t h e m t o t h e i n s t r u c t i o n q u e u e i n s i d e i n s t r u c t i o n u n i t . T h e r e f o r e i n s t r u c t i o n u n i t i s t i g h t l y c o u p l e d w i t h t h e i n s t r u c t i o n c a c h e .
I f t h e r e i s n o i n s t r u c t i o n c a c h e l i n e m i s s n o r I T L B m i s s , i n s t r u c t i o n f e t c h o p e r a t i o n t a k e s o n e c l o c k c y c l e t o e x e c u t e .
I n s t r u c t i o n c a c h e c a n n o t b e e x p l i c i t l y m o d i f i e d l i k e d a t a c a c h e c a n b e w i t h s t o r e i n s t r u c t i o n s .
I n s t r u c t i o n C a c h e L i n e F i l l O p e r a t i o n
O n a c a c h e m i s s , a 4 b e a t s e q u e n t i a l r e a d b u r s t w i t h c r i t i c a l w o r d f i r s t i s p e r f o r m e d . C r i t i c a l w o r d i s f o r w a r d e d t o t h e i n s t r u c t i o n u n i t t o m i n i m i z e p e r f o r m a n c e l o s s b e c a u s e o f t h e c a c h e m i s s .
E M B E D
F i g u r e S E Q " F i g u r e " \ * A r a b i c 9 . W I S H B O N E B l o c k R e a d C y c l e
R E F _ R e f 5 1 3 1 9 7 5 5 2 \ h F i g u r e 9 s h o w s h o w a c a c h e l i n e i s r e a d i n W I S H B O N E r e a d b l o c k c y c l e c o m p o s e d o u t o f f o u r r e a d t r a n s f e r s .
I f i w b _ E R R _ I o r i w b _ R T Y _ I i s a s s e r t e d i n s t e a d o f u s u a l d w b _ A C K _ I , b u s e r r o r e x c e p t i o n i s i n v o k e d .
C a c h e / M e m o r y C o h e r e n c y
O R 1 2 0 0 i s n o t i n t e n d e d f o r u s e i n m u l t i p r o c e s s o r e n v i r o n m e n t s . T h e r e f o r e n o s u p p o r t f o r c o h e r e n c y b e t w e e n l o c a l i n s t r u c t i o n c a c h e a n d c a c h e s o f o t h e r p r o c e s s o r s o r m a i n m e m o r y i s i m p l e m e n t e d .
I n s t r u c t i o n C a c h e E n a b l i n g / D i s a b l i n g
I n s t r u c t i o n c a c h e i s d i s a b l e d a t p o w e r u p . E n t i r e i n s t r u c t i o n c a c h e c a n b e e n a b l e d b y s e t t i n g b i t S R [ I C E ] t o o n e . B e f o r e i n s t r u c t i o n c a c h e i s e n a b l e d , i t m u s t b e i n v a l i d a t e d .
I n s t r u c t i o n C a c h e I n v a l i d a t i o n
I n s t r u c t i o n c a c h e i n O R 1 2 0 0 d o e s n o t s u p p o r t i n v a l i d a t i o n o f e n t i r e i n s t r u c t i o n c a c h e . N o r m a l p r o c e d u r e t o i n v a l i d a t e e n t i r e i n s t r u c t i o n c a c h e i s t o c y c l e t h r o u g h a l l i n s t r u c t i o n c a c h e l i n e s a n d i n v a l i d a t e e a c h l i n e s e p a r a t e l y .
I n s t r u c t i o n C a c h e L o c k i n g
I n s t r u c t i o n c a c h e i m p l e m e n t s w a y l o c k i n g b i t s i n i n s t r u c t i o n c a c h e c o n t r o l r e g i s t e r I C C R . B i t s L W x l o c k i n d i v i d u a l w a y s w h e n t h e y a r e s e t t o o n e .
I n s t r u c t i o n C a c h e L i n e P r e f e t c h
I n s t r u c t i o n c a c h e l i n e p r e f e t c h i s o p t i o n a l i n t h e O p e n R I S C 1 0 0 0 a r c h i t e c t u r e a n d i s n o t i m p l e m e n t e d i n O R 1 2 0 0 .
I n s t r u c t i o n C a c h e L i n e I n v a l i d a t e
I n s t r u c t i o n c a c h e l i n e i n v a l i d a t e i n v a l i d a t e s a s i n g l e i n s t r u c t i o n c a c h e l i n e . O p e r a t i o n i s p e r f o r m e d b y w r i t i n g e f f e c t i v e a d d r e s s t o t h e I C B I R r e g i s t e r .
I n s t r u c t i o n C a c h e L i n e L o c k
L o c k i n g o f i n d i v i d u a l i n s t r u c t i o n c a c h e l i n e s i s n o t i m p l e m e n t e d i n O R 1 2 0 0 .
D a t a M M U
T r a n s l a t i o n D i s a b l e d
L o a d / s t o r e a d d r e s s t r a n s l a t i o n c a n b e d i s a b l e d b y c l e a r i n g b i t S R [ D M E ] . I f t r a n s l a t i o n i s d i s a b l e d , t h e n p h y s i c a l a d d r e s s u s e d t o a c c e s s d a t a c a c h e a n d o p t i o n a l l y p r o v i d e d o n d w b _ A D D R _ O , i s t h e s a m e a s l o a d / s t o r e e f f e c t i v e a d d r e s s .
T r a n s l a t i o n E n a b l e d
L o a d / s t o r e a d d r e s s t r a n s l a t i o n c a n b e e n a b l e d b y s e t t i n g b i t S R [ D M E ] . I f t r a n s l a t i o n i s e n a b l e d , i t p r o v i d e s l o a d / s t o r e e f f e c t i v e a d d r e s s t o p h y s i c a l a d d r e s s t r a n s l a t i o n a n d p a g e p r o t e c t i o n f o r m e m o r y a c c e s s e s .
E M B E D M i c r o s o f t V i s i o D r a w i n g
F i g u r e S E Q " F i g u r e " \ * A r a b i c 1 0 . 3 2 - b i t A d d r e s s T r a n s l a t i o n M e c h a n i s m u s i n g T w o - L e v e l P a g e T a b l e
I n O R 1 2 0 0 c a s e , p a g e t a b l e s m u s t b e m a n a g e d b y o p e r a t i n g s y s t e m s v i r t u a l m e m o r y m a n a g e m e n t s u b s y s t e m . R E F _ R e f 5 1 3 3 4 3 2 2 7 \ h F i g u r e 1 0 s h o w s a d d r e s s t r a n s l a t i o n u s i n g t w o - l e v e l p a g e t a b l e . R e f e r t o O p e n R I S C 1 0 0 0 S y s t e m A r c h i t e c t u r e M a n u a l f o r o n e - l e v e l p a g e t a b l e a d d r e s s t r a n s l a t i o n a s w e l l a s f o r d e t a i l s a b o u t a d d r e s s t r a n s l a t i o n a n d p a g e t a b l e c o n t e n t .
D M M U C R a n d F l u s h o f E n t i r e D T L B
D M M U C R i s n o t i m p l e m e n t e d i n O R 1 2 0 0 . T h e r e f o r e p a g e t a b l e b a s e p o i n t e r ( P T B P ) m u s t b e s t o r e d i n s o f t w a r e v a r i a b l e . F l u s h o f e n t i r e D T L B m u s t b e p e r f o r m e d b y s o f t w a r e f l u s h o f e v e r y D T L B e n t r y s e p a r a t e l y . S o f t w a r e f l u s h i s p e r f o r m e d b y m a n u a l l y w r i t i n g b i t s f r o m t h e T L B e n t r i e s b a c k t o P T E s .
P a g e P r o t e c t i o n
A f t e r a v i r t u a l a d d r e s s i s d e t e r m i n e d t o b e w i t h i n a p a g e c o v e r e d b y t h e v a l i d P T E , t h e a c c e s s i s v a l i d a t e d b y t h e m e m o r y p r o t e c t i o n m e c h a n i s m . I f t h i s p r o t e c t i o n m e c h a n i s m p r o h i b i t s t h e a c c e s s , a d a t a p a g e f a u l t e x c e p t i o n i s g e n e r a t e d .
T h e m e m o r y p r o t e c t i o n m e c h a n i s m a l l o w s s e l e c t i v e l y g r a n t i n g r e a d a c c e s s a n d w r i t e a c c e s s f o r b o t h s u p e r v i s o r a n d u s e r m o d e s . T h e p a g e p r o t e c t i o n m e c h a n i s m p r o v i d e s p r o t e c t i o n a t a l l p a g e l e v e l g r a n u l a r i t i e s .
P r o t e c t i o n a t t r i b u t e M e a n i n g D T L B W y T R [ S R E x ] E n a b l e l o a d o p e r a t i o n s i n s u p e r v i s o r m o d e t o t h e p a g e . D T L B W y T R [ S W E x ] E n a b l e s t o r e o p e r a t i o n s i n s u p e r v i s o r m o d e t o t h e p a g e . D T L B W y T R [ U R E x ] E n a b l e l o a d o p e r a t i o n s i n u s e r m o d e t o t h e p a g e . D T L B W y T R [ U W E x ] E n a b l e s t o r e o p e r a t i o n s i n u s e r m o d e t o t h e p a g e . T a b l e S E Q " T a b l e " \ * A r a b i c 1 1 . P r o t e c t i o n A t t r i b u t e s f o r L o a d / S t o r e A c c e s s e s
R E F _ R e f 5 1 3 3 4 6 0 9 4 \ h T a b l e 1 1 l i s t s p a g e p r o t e c t i o n a t t r i b u t e s d e f i n e d i n D T L B W y T R p r e g i s t e r . F o r t h e i n d i v i d u a l p a g e a p p r o p r i a t e s t r a t e g y o u t o f s e v e n p o s s i b l e s t r a t e g i e s p r o g r a m m e d w i t h t h e P P I f i e l d o f t h e P T E . B e c a u s e O R 1 2 0 0 d o e s n o t i m p l e m e n t D M M U P R , t r a n s l a t i o n o f P T E [ P P I ] i n t o s u i t a b l e s e t o f p r o t e c t i o n b i t s m u s t b e p e r f o r m e d b y s o f t w a r e a n d w r i t t e n i n t o D T L B W y T R .
D T L B E n t r y R e l o a d
O R 1 2 0 0 d o e s n o t i m p l e m e n t D T L B e n t r y r e l o a d s i n h a r d w a r e . I n s t e a d s o f t w a r e r o u t i n e m u s t b e u s e d t o s e a r c h p a g e t a b l e f o r c o r r e c t p a g e t a b l e e n t r y ( P T E ) a n d c o p y i t i n t o t h e D T L B . S o f t w a r e i s r e s p o n s i b l e f o r m a i n t a i n i n g a c c e s s e d a n d d i r t y b i t s i n t h e p a g e t a b l e s .
W h e n L S U c o m p u t e s l o a d / s t o r e e f f e c t i v e a d d r e s s w h o s e p h y s i c a l a d d r e s s i s n o t a l r e a d y c a c h e d b y D T L B , a D T L B m i s s e x c e p t i o n i s i n v o k e d .
D T L B r e l o a d r o u t i n e m u s t l o a d t h e c o r r e c t P T E t o c o r r e c t D T L B W y M R a n d D T L B W y T R r e g i s t e r f r o m o n e o f p o s s i b l e D T L B w a y s .
D T L B E n t r y I n v a l i d a t i o n
S p e c i a l - p u r p o s e r e g i s t e r D T L B E I R m u s t b e w r i t t e n w i t h t h e e f f e c t i v e a d d r e s s a n d c o r r e s p o n d i n g D T L B e n t r y w i l l b e i n v a l i d a t e d i n t h e l o c a l D T L B .
L o c k i n g D T L B E n t r i e s
S i n c e a l l D T L B e n t r y r e l o a d s a r e p e r f o r m e d i n s o f t w a r e , t h e r e i s n o h a r d w a r e l o c k i n g o f D T L B e n t r i e s . I n s t e a d i t i s u p t o t h e s o f t w a r e r e l o a d r o u t i n e t o a v o i d r e p l a c i n g s o m e o f t h e e n t r i e s i f s o d e s i r e d .
P a g e A t t r i b u t e D i r t y ( D )
D i r t y ( D ) a t t r i b u t e i s n o t i m p l e m e n t e d i n O R 1 2 0 0 D T L B . I t i s u p t o t h e o p e r a t i n g s y s t e m t o g e n e r a t e d i r t y a t t r i b u t e b i t w i t h p a g e p r o t e c t i o n m e c h a n i s m .
P a g e A t t r i b u t e A c c e s s e d ( A )
A c c e s s e d ( A ) a t t r i b u t e i s n o t i m p l e m e n t e d i n O R 1 2 0 0 D T L B . I t i s u p t o t h e o p e r a t i n g s y s t e m t o g e n e r a t e a c c e s s e d a t t r i b u t e b i t w i t h p a g e p r o t e c t i o n m e c h a n i s m .
P a g e A t t r i b u t e W e a k l y O r d e r e d M e m o r y ( W O M )
W e a k l y o r d e r e d m e m o r y ( W O M ) a t t r i b u t e i s n o t n e e d e d i n O R 1 2 0 0 b e c a u s e a l l m e m o r y a c c e s s e s a r e s e r i a l i z e d a n d t h e r e f o r e t h i s a t t r i b u t e i s n o t i m p l e m e n t e d .
P a g e A t t r i b u t e W r i t e - B a c k C a c h e ( W B C )
W r i t e - b a c k c a c h e ( W B C ) a t t r i b u t e i s n o t i m p l e m e n t e d a s t h e d a t a c a c h e c a n n o t b e c o n f i g u r e d a t r u n t i m e t o b e w r i t e - b a c k e n a b l e d i f w r i t e - t h r o u g h s t r a t e g y w a s s e l e c t e d a t s y n t h e s i s - t i m e .
P a g e A t t r i b u t e C a c h i n g - I n h i b i t e d ( C I )
C a c h i n g - i n h i b i t e d ( C I ) a t t r i b u t e i s n o t i m p l e m e n t e d i n O R 1 2 0 0 D T L B . C a c h e d a n d u n c a c h e d r e g i o n s a r e d i v i d e d b y b i t 3 0 o f d a t a e f f e c t i v e a d d r e s s .
E f f e c t i v e A d d r e s s R e g i o n 0 x 0 0 0 0 0 0 0 0 - 0 x 3 F F F F F F F C a c h e d 0 x 4 0 0 0 0 0 0 0 - 0 x 7 F F F F F F F U n c a c h e d 0 x 8 0 0 0 0 0 0 0 - 0 x B F F F F F F F C a c h e d 0 x C 0 0 0 0 0 0 0 - 0 x F F F F F F F F U n c a c h e d T a b l e S E Q " T a b l e " \ * A r a b i c 1 2 . C a c h e d a n d u n c a c h e d r e g i o n s
U n c a c h e d a c c e s s e s m u s t b e p e r f o r m e d w h e n I / O r e g i s t e r s a r e m e m o r y m a p p e d a n d a l l r e a d s a n d w r i t e s m u s t b e a l w a y s p e r f o r m e d d i r e c t l y t o t h e e x t e r n a l i n t e r f a c e a n d n o t t o t h e d a t a c a c h e .
P a g e A t t r i b u t e C a c h e C o h e r e n c y ( C C )
C a c h e c o h e r e n c y ( C C ) a t t r i b u t e i s n o t n e e d e d i n O R 1 2 0 0 b e c a u s e i t d o e s n t i m p l e m e n t s u p p o r t f o r m u l t i p r o c e s s o r e n v i r o n m e n t s a n d b e c a u s e d a t a c a c h e o p e r a t e s o n l y i n w r i t e - t h r o u g h m o d e a n d t h e r e f o r e t h i s a t t r i b u t e i s n o t i m p l e m e n t e d .
I n s t r u c t i o n M M U
T r a n s l a t i o n D i s a b l e d
I n s t r u c t i o n f e t c h a d d r e s s t r a n s l a t i o n c a n b e d i s a b l e d b y c l e a r i n g b i t S R [ I M E ] . I f t r a n s l a t i o n i s d i s a b l e d , t h e n p h y s i c a l a d d r e s s u s e d t o a c c e s s i n s t r u c t i o n c a c h e a n d o p t i o n a l l y p r o v i d e d o n i w b _ A D D R _ O , i s t h e s a m e a s i n s t r u c t i o n f e t c h e f f e c t i v e a d d r e s s .
T r a n s l a t i o n E n a b l e d
I n s t r u c t i o n f e t c h a d d r e s s t r a n s l a t i o n c a n b e e n a b l e d b y s e t t i n g b i t S R [ I M E ] . I f t r a n s l a t i o n i s e n a b l e d , i t p r o v i d e s i n s t r u c t i o n f e t c h e f f e c t i v e a d d r e s s t o p h y s i c a l a d d r e s s t r a n s l a t i o n a n d p a g e p r o t e c t i o n f o r i n s t r u c t i o n f e t c h a c c e s s e s .
E M B E D M i c r o s o f t V i s i o D r a w i n g
F i g u r e S E Q " F i g u r e " \ * A r a b i c 1 1 . 3 2 - b i t A d d r e s s T r a n s l a t i o n M e c h a n i s m u s i n g T w o - L e v e l P a g e T a b l e
I n O R 1 2 0 0 c a s e , p a g e t a b l e s m u s t b e m a n a g e d b y o p e r a t i n g s y s t e m s v i r t u a l m e m o r y m a n a g e m e n t s u b s y s t e m . R E F _ R e f 5 1 3 3 4 3 2 2 7 \ h F i g u r e 1 0 s h o w s a d d r e s s t r a n s l a t i o n u s i n g t w o - l e v e l p a g e t a b l e . R e f e r t o O p e n R I S C 1 0 0 0 S y s t e m A r c h i t e c t u r e M a n u a l f o r o n e - l e v e l p a g e t a b l e a d d r e s s t r a n s l a t i o n a s w e l l a s f o r d e t a i l s a b o u t a d d r e s s t r a n s l a t i o n a n d p a g e t a b l e c o n t e n t .
I M M U C R a n d F l u s h o f E n t i r e I T L B
I M M U C R i s n o t i m p l e m e n t e d i n O R 1 2 0 0 . T h e r e f o r e p a g e t a b l e b a s e p o i n t e r ( P T B P ) m u s t b e s t o r e d i n s o f t w a r e v a r i a b l e . F l u s h o f e n t i r e I T L B m u s t b e p e r f o r m e d b y s o f t w a r e f l u s h o f e v e r y I T L B e n t r y s e p a r a t e l y . S o f t w a r e f l u s h i s p e r f o r m e d b y m a n u a l l y w r i t i n g b i t s f r o m t h e T L B e n t r i e s b a c k t o P T E s .
P a g e P r o t e c t i o n
A f t e r a v i r t u a l a d d r e s s i s d e t e r m i n e d t o b e w i t h i n a p a g e c o v e r e d b y t h e v a l i d P T E , t h e a c c e s s i s v a l i d a t e d b y t h e m e m o r y p r o t e c t i o n m e c h a n i s m . I f t h i s p r o t e c t i o n m e c h a n i s m p r o h i b i t s t h e a c c e s s , a n i n s t r u c t i o n p a g e f a u l t e x c e p t i o n i s g e n e r a t e d .
T h e m e m o r y p r o t e c t i o n m e c h a n i s m a l l o w s s e l e c t i v e l y g r a n t i n g e x e c u t e a c c e s s f o r b o t h s u p e r v i s o r a n d u s e r m o d e s . T h e p a g e p r o t e c t i o n m e c h a n i s m p r o v i d e s p r o t e c t i o n a t a l l p a g e l e v e l g r a n u l a r i t i e s .
P r o t e c t i o n a t t r i b u t e M e a n i n g I T L B W y T R [ S X E x ] E n a b l e e x e c u t e o p e r a t i o n s i n s u p e r v i s o r m o d e o f t h e p a g e . I T L B W y T R [ U X E x ] E n a b l e e x e c u t e o p e r a t i o n s i n u s e r m o d e o f t h e p a g e . T a b l e S E Q " T a b l e " \ * A r a b i c 1 3 . P r o t e c t i o n A t t r i b u t e s f o r I n s t r u c t i o n F e t c h A c c e s s e s
R E F _ R e f 5 1 3 3 4 6 0 9 4 \ h T a b l e 1 1 l i s t s p a g e p r o t e c t i o n a t t r i b u t e s d e f i n e d i n I T L B W y T R p r e g i s t e r . F o r t h e i n d i v i d u a l p a g e a p p r o p r i a t e s t r a t e g y o u t o f s e v e n p o s s i b l e s t r a t e g i e s p r o g r a m m e d w i t h P P I f i e l d o f t h e P T E . B e c a u s e O R 1 2 0 0 d o e s n o t i m p l e m e n t I M M U P R , t r a n s l a t i o n o f P T E [ P P I ] i n t o s u i t a b l e s e t o f p r o t e c t i o n b i t s m u s t b e p e r f o r m e d b y s o f t w a r e a n d w r i t t e n i n t o I T L B W y T R .
I T L B E n t r y R e l o a d
O R 1 2 0 0 d o e s n o t i m p l e m e n t I T L B e n t r y r e l o a d s i n h a r d w a r e . I n s t e a d s o f t w a r e r o u t i n e m u s t b e u s e d t o s e a r c h p a g e t a b l e f o r c o r r e c t p a g e t a b l e e n t r y ( P T E ) a n d c o p y i t i n t o t h e I T L B . S o f t w a r e i s r e s p o n s i b l e f o r m a i n t a i n i n g a c c e s s e d b i t i n t h e p a g e t a b l e s .
W h e n L S U c o m p u t e s i n s t r u c t i o n f e t c h e f f e c t i v e a d d r e s s w h o s e p h y s i c a l a d d r e s s i s n o t a l r e a d y c a c h e d b y I T L B , a n I T L B m i s s e x c e p t i o n i s i n v o k e d .
I T L B r e l o a d r o u t i n e m u s t l o a d t h e c o r r e c t P T E t o c o r r e c t I T L B W y M R a n d I T L B W y T R r e g i s t e r f r o m o n e o f p o s s i b l e I T L B w a y s .
I T L B E n t r y I n v a l i d a t i o n
S p e c i a l - p u r p o s e r e g i s t e r I T L B E I R m u s t b e w r i t t e n w i t h t h e e f f e c t i v e a d d r e s s a n d c o r r e s p o n d i n g I T L B e n t r y w i l l b e i n v a l i d a t e d i n t h e l o c a l I T L B .
L o c k i n g I T L B E n t r i e s
S i n c e a l l I T L B e n t r y r e l o a d s a r e p e r f o r m e d i n s o f t w a r e , t h e r e i s n o h a r d w a r e l o c k i n g o f I T L B e n t r i e s . I n s t e a d i t i s u p t o t h e s o f t w a r e r e l o a d r o u t i n e t o a v o i d r e p l a c i n g s o m e o f t h e e n t r i e s i f s o d e s i r e d .
P a g e A t t r i b u t e D i r t y ( D )
D i r t y ( D ) a t t r i b u t e r e s i d e s i n t h e P T E b u t i t i s n o t u s e d b y t h e I M M U .
P a g e A t t r i b u t e A c c e s s e d ( A )
A c c e s s e d ( A ) a t t r i b u t e i s n o t i m p l e m e n t e d i n O R 1 2 0 0 I T L B . I t i s u p t o t h e o p e r a t i n g s y s t e m t o g e n e r a t e a c c e s s e d a t t r i b u t e b i t w i t h p a g e p r o t e c t i o n m e c h a n i s m .
P a g e A t t r i b u t e W e a k l y O r d e r e d M e m o r y ( W O M )
W e a k l y o r d e r e d m e m o r y ( W O M ) a t t r i b u t e i s n o t n e e d e d i n O R 1 2 0 0 b e c a u s e a l l i n s t r u c t i o n f e t c h a c c e s s e s a r e s e r i a l i z e d a n d t h e r e f o r e t h i s a t t r i b u t e i s n o t i m p l e m e n t e d .
P a g e A t t r i b u t e W r i t e - B a c k C a c h e ( W B C )
W r i t e - b a c k c a c h e ( W B C ) a t t r i b u t e r e s i d e s i n t h e P T E b u t i t i s n o t u s e d b y t h e I M M U .
P a g e A t t r i b u t e C a c h i n g - I n h i b i t e d ( C I )
C a c h i n g - i n h i b i t e d ( C I ) a t t r i b u t e i s n o t i m p l e m e n t e d i n O R 1 2 0 0 I T L B . C a c h e d a n d u n c a c h e d r e g i o n s a r e d i v i d e d b y b i t 3 0 o f i n s t r u c t i o n e f f e c t i v e a d d r e s s .
E f f e c t i v e A d d r e s s R e g i o n 0 x 0 0 0 0 0 0 0 0 - 0 x 3 F F F F F F F C a c h e d 0 x 4 0 0 0 0 0 0 0 - 0 x 7 F F F F F F F U n c a c h e d 0 x 8 0 0 0 0 0 0 0 - 0 x B F F F F F F F C a c h e d 0 x C 0 0 0 0 0 0 0 - 0 x F F F F F F F F U n c a c h e d T a b l e S E Q " T a b l e " \ * A r a b i c 1 4 . C a c h e d a n d u n c a c h e d r e g i o n s
P a g e A t t r i b u t e C a c h e C o h e r e n c y ( C C )
C a c h e c o h e r e n c y ( C C ) a t t r i b u t e r e s i d e s i n t h e P T E b u t i t i s n o t u s e d b y t h e I M M U .
P r o g r a m m a b l e I n t e r r u p t C o n t r o l l e r
P I C M R s p e c i a l - p u r p o s e r e g i s t e r i s u s e d t o m a s k o r u n m a s k u p t o 3 0 p r o g r a m m a b l e i n t e r r u p t s o u r c e s . P I C P R s p e c i a l - p u r p o s e r e g i s t e r i s u s e d t o a s s i g n l o w o r h i g h p r i o r i t y t o m a x i m u m o f 3 0 i n t e r r u p t s o u r c e s .
P I C S R s p e c i a l - p u r p o s e r e g i s t e r i s u s e d t o d e t e r m i n e s t a t u s o f e a c h i n t e r r u p t i n p u t . B i t s i n P I C S R r e p r e s e n t s t a t u s o f t h e i n t e r r u p t i n p u t s a n d t h e a c t u a l i n t e r r u p t m u s t b e c l e a r e d i n t h e d e v i c e t h a t i s t h e s o u r c e o f a p e n d i n g i n t e r r u p t .
I n t h e O p e n R I S C 1 2 0 0 , t h e d i f f e r s f r o m t h e a r c h i t e c t u r e s p e c i f i c a t i o n . T h e P I C o f f e r s a l a t c h e d l e v e l - s e n s i t i v e i n t e r r u p t .
O n c e a n i n t e r r u p t l i n e i s l a t c h e d ( i . e . i t s v a l u e a p p e a r s i n P I C S R ) , n o n e w i n t e r r u p t s c a n b e t r i g g e r e d f o r t h a t l i n e u n t i l i t s b i t i n P I C S R i s c l e a r e d . T h e u s u a l s e q u e n c e f o r a n i n t e r r u p t h a n d l e r i s t h e n a s f o l l o w s .
P e r i p h e r a l a s s e r t s i n t e r r u p t , w h i c h i s l a t c h e d a n d t r i g g e r s h a n d l e r .
H a n d l e r p r o c e s s e s i n t e r r u p t .
H a n d l e r n o t i f i e s p e r i p h e r a l t h a t t h e i n t e r r u p t h a s b e e n p r o c e s s e d ( t y p i c a l l y v i a a m e m o r y m a p p e d r e g i s t e r ) .
P e r i p h e r a l d e a s s e r t s i n t e r r u p t .
H a n d l e r c l e a r s c o r r e s p o n d i n g b i t i n P I C S R a n d r e t u r n s .
I t i s a s s u m e d t h a t t h e p e r i p h e r a l w i l l d e - a s s e r t i t s i n t e r r u p t p r o m p t l y ( w i t h i n 1 - 2 c y c l e s ) . O t h e r w i s e o n e x i t i n g t h e i n t e r r u p t h a n d l e r , h a v i n g c l e a r e d P I C S R , t h e l e v e l s e n s i t i v e i n t e r r u p t w i l l i m m e d i a t e l y r e t r i g g e r .
T i c k T i m e r
T i c k t i m e r f a c i l i t y i s e n a b l e d w i t h T T M R [ M ] . T T C R i s i n c r e m e n t e d w i t h e a c h c l o c k c y c l e a n d a h i g h p r i o r i t y i n t e r r u p t c a n b e a s s e r t e d w h e n e v e r l o w e r 2 8 b i t s o f T T C R m a t c h T T M R [ T P ] a n d T T M R [ I E ] i s s e t .
T T C R r e s t a r t s c o u n t i n g f r o m z e r o w h e n m a t c h e v e n t h a p p e n s a n d T T M R [ M ] i s 0 x 1 . I f T T M R [ M ] i s 0 x 2 , T T C R i s s t o p e d w h e n m a t c h e v e n t h a p p e n s a n d T T C R m u s t b e c h a n g e d t o s t a r t c o u n t i n g a g a i n . W h e n T T M R [ M ] i s 0 x 3 , T T C R k e e p s c o u n t i n g e v e n w h e n m a t c h e v e n t h a p p e n s .
P o w e r M a n a g e m e n t
C l o c k G a t i n g a n d F r e q u e n c y C h a n g i n g V e r s u s C P U S t a l l i n g
I f s y s t e m d o e s n t s u p p o r t c l o c k g a t i n g a n d i f c h a n g i n g c l o c k f r e q u e n c y i n s l o w d o w n m o d e i s n o t p o s s i b l e , C P U c a n b e s t a l l e d f o r c e r t a i n n u m b e r o f c l o c k c y c l e s . T h i s i s m u c h l o w e r b e n e f i t o n p o w e r c o n s u m p t i o n h o w e v e r i t s t i l l r e d u c e s p o w e r c o n s u m p t i o n .
S l o w D o w n M o d e
S l o w d o w n m o d e i s s o f t w a r e c o n t r o l l e d w i t h t h e 4 - b i t v a l u e i n P M R [ S D F ] . L o w e r v a l u e s p e c i f i e s h i g h e r e x p e c t e d p e r f o r m a n c e f r o m t h e p r o c e s s o r c o r e . U s u a l l y P M R [ S D F ] i s d y n a m i c a l l y s e t b y t h e o p e r a t i n g s y s t e m s i d l e r o u t i n e , t h a t m o n i t o r s t h e u s a g e o f t h e p r o c e s s o r c o r e .
P M R [ S D F ] i s b r o a d c a s t e d o n p m _ c l k s d . E x t e r n a l c l o c k g e n e r a t o r s h o u l d a d j u s t c l o c k f r e q u e n c y a c c o r d i n g t o t h e v a l u e o f p m _ c l k s d . E x a c t s l o w d o w n f a c t o r s a r e n o t d e f i n e d b u t 0 x F s h o u l d g o a l l t h e w a y d o w n t o 3 2 . 7 6 8 K H z .
W i t h p m _ c l k s d e q u a l t o 0 x F , p m _ l v o l t i s a s s e r t e d . T h i s i s a n i n d i c a t i o n f o r t h e e x t e r n a l p o w e r s u p p l y t o l o w e r t h e v o l t a g e .
D o z e M o d e
T o s w i t c h t o d o z e m o d e , s o f t w a r e s h o u l d s e t t h e P M R [ D M E ] . O n c e a n i n t e r r u p t i s r e c e i v e d b y t h e p r o g r a m m a b l e i n t e r r u p t c o n t r o l l e r ( P I C ) , p m _ w a k e u p i s a s s e r t e d a n d e x t e r n a l c l o c k g e n e r a t i o n c i r c u i t r y s h o u l d e n a b l e a l l c l o c k s . O n c e c l o c k s a r e r u n n i n g R I S C i s s w i t c h e d b a c k a g a i n t o t h e n o r m a l m o d e a n d P M R [ D M E ] i s c l e a r e d .
W h e n d o z e m o d e i s e n a b l e d , p m _ d c _ g a t e , p m _ i c _ g a t e , p m _ d m m u _ g a t e , p m _ i m m u _ g a t e a n d p m _ c p u g a t e a r e a s s e r t e d . A s a r e s u l t a l l c l o c k s e x c e p t c l k _ t t s h o u l d b e g a t e d b y e x t e r n a l c l o c k g e n e r a t i o n c i r c u i t r y .
S l e e p M o d e
T o s w i t c h t o s l e e p m o d e , s o f t w a r e s h o u l d s e t t h e P M R [ S M E ] . O n c e a n i n t e r r u p t i s r e c e i v e d b y t h e p r o g r a m m a b l e i n t e r r u p t c o n t r o l l e r ( P I C ) , p m _ w a k e u p i s a s s e r t e d a n d e x t e r n a l c l o c k g e n e r a t i o n s h o u l d e n a b l e a l l c l o c k s . O n c e c l o c k s a r e r u n n i n g , R I S C i s s w i t c h e d b a c k a g a i n t o t h e n o r m a l m o d e a n d P M R [ S M E ] i s c l e a r e d .
W h e n s l e e p m o d e i s e n a b l e d , p m _ d c _ g a t e , p m _ i c _ g a t e , p m _ d m m u _ g a t e , p m _ i m m u _ g a t e , p m _ c p u _ g a t e a n d p m _ t t _ g a t e a r e a s s e r t e d . A s a r e s u l t a l l c l o c k s i n c l u d i n g c l k _ t t s h o u l d b e g a t e d b y e x t e r n a l c l o c k g e n e r a t i o n c i r c u i t r y .
I n s l e e p m o d e , p m _ l v o l t i s a s s e r t e d . T h i s i s a n i n d i c a t i o n f o r t h e e x t e r n a l p o w e r s u p p l y t o l o w e r t h e v o l t a g e .
C l o c k G a t i n g
C l o c k g a t i n g f e a t u r e i s n o t i m p l e m e n t e d i n O R 1 2 0 0 p o w e r m a n a g e m e n t .
D i s a b l e d U n i t s F o r c e C l o c k G a t i n g
U n i t s t h a t a r e d i s a b l e d i n s p e c i a l - p u r p o s e r e g i s t e r S R , h a v e t h e i r c l o c k g a t e s i g n a l s a s s e r t e d . C l e a r e d b i t s S R [ D C E ] , S R [ I C E ] , S R [ D M E ] a n d S R [ I M E ] d i r e c t l y f o r c e a s s e r t i o n o f p m _ d c _ g a t e , p m _ i c _ g a t e , p m _ d m m u _ g a t e a n d p m _ i m m u _ g a t e .
D e b u g U n i t
D e b u g u n i t c a n b e c o n t r o l l e d t h r o u g h d e v e l o p m e n t i n t e r f a c e o r i t c a n o p e r a t e i n d e p e n d e n t l y p r o g r a m m e d a n d h a n d l e d b y t h e R I S C s r e s i d e n t d e b u g s o f t w a r e .
W a t c h p o i n t s
O R 1 2 0 0 d e b u g u n i t d o e s n o t i m p l e m e n t O R 1 2 0 0 0 a r c h i t e c t u r e w a t c h p o i n t s .
B r e a k p o i n t E x c e p t i o n
W h i c h b r e a k p o i n t D M R 2 [ W G B ] b i t s s p e c i f y w h i c h w a t c h p o i n t s i n v o k e b r e a k p o i n t e x c e p t i o n . B y i n v o k i n g b r e a k p o i n t e x c e p t i o n , t a r g e t r e s i d e n t d e b u g g e r c a n b e b u i l t .
B r e a k p o i n t i s b r o a d c a s t e d o n d e v e l o p m e n t i n t e r f a c e o n d b g _ b p _ o .
D e v e l o p m e n t I n t e r f a c e
N O T E : T h e i n f o r m a t i o n i n t h i s s e c t i o n i s t o b e r e v i e w e d . I t i s t h e a u t h o r ' s o p i n i o n t h a t t h e d e b u g i n t e r f a c e i s n o w l a r g e l y p r o v i d e d b y t h e S P R m a p p i n g s , a n d n o s p e c i a l s i d e b a n d f u n c t i o n s e x i s t a s i d e f r o m s t a l l i n g a n d r e s e t t i n g t h e c o r e .
A n a d d i t i o n a l d e v e l o p m e n t a n d d e b u g i n t e r f a c e I P c o r e m a y b e u s e d t o c o n n e c t O p e n R I S C 1 2 0 0 t o s t a n d a r d d e b u g g e r s u s i n g I E E E . 1 1 4 9 . 1 ( J T A G ) p r o t o c o l .
D e b u g g i n g T h r o u g h D e v e l o p m e n t I n t e r f a c e
T h e D S R s p e c i a l - p u r p o s e r e g i s t e r s p e c i f i e s w h i c h e x c e p t i o n s c a u s e t h e c o r e t o s t o p t h e e x e c u t i o n o f t h e e x c e p t i o n h a n d l e r a n d t u r n o v e r c o n t r o l t o d e v e l o p m e n t i n t e r f a c e . I t c a n b e p r o g r a m m e d b y t h e r e s i d e n t d e b u g s o f t w a r e o r b y t h e d e v e l o p m e n t i n t e r f a c e .
T h e D R R s p e c i a l - p u r p o s e r e g i s t e r i s s p e c i f i e s w h i c h e v e n t c a u s e d t h e c o r e t o s t o p t h e e x e c u t i o n o f p r o g r a m f l o w a n d t u r n e d o v e r c o n t r o l t o t h e d e v e l o p m e n t i n t e r f a c e . I t s h o u l d b e c l e a r e d b y t h e r e s i d e n t d e b u g s o f t w a r e o r b y t h e d e v e l o p m e n t i n t e r f a c e .
T h e D I R s p e c i a l - p u r p o s e r e g i s t e r i s n o t i m p l e m e n t e d .
R e a d i n g P C , L o a d / S t o r e E A , L o a d D a t a , S t o r e D a t a , I n s t r u c t i o n
C r u c i a l i n f o r m a t i o n l i k e p r o g r a m c o u n t e r ( P C ) , l o a d / s t o r e e f f e c t i v e a d d r e s s ( L S E A ) , l o a d d a t a , s t o r e d a t a a n d c u r r e n t i n s t r u c t i o n i n e x e c u t i o n p i p e l i n e c a n b e a s y n c h r o n o u s l y r e a d t h r o u g h t h e d e v e l o p m e n t i n t e r f a c e .
d b g _ o p _ i [ 2 : 0 ] M e a n i n g 0 x 0 R e a d i n g P r o g r a m C o u n t e r ( P C ) 0 x 1 R e a d i n g L o a d / S t o r e E f f e c t i v e A d d r e s s 0 x 2 R e a d i n g L o a d D a t a 0 x 3 R e a d i n g S t o r e D a t a 0 x 4 R e a d i n g S P R 0 x 5 W r i t i n g S P R 0 x 6 R e a d i n g I n s t r u c t i o n i n E x e c u t i o n P i p e l i n e 0 x 7 R e s e r v e d T a b l e S E Q " T a b l e " \ * A r a b i c 1 5 . D e v e l o p m e n t I n t e r f a c e O p e r a t i o n C o m m a n d s
R E F _ R e f 5 1 3 3 2 9 3 0 6 \ h T a b l e 1 5 l i s t s o p e r a t i o n c o m m a n d s t h a t c o n t r o l w h a t i s r e a d o r w r i t t e n t h r o u g h d e v e l o p m e n t i n t e r f a c e . A l l r e a d s e x c e p t r e a d s a n d w r i t e s o f S P R s a r e a s y n c h r o n o u s .
R e a d i n g a n d W r i t i n g S P R s T h r o u g h D e v e l o p m e n t I n t e r f a c e
F o r r e a d s a n d w r i t e t o S P R s d b g _ o p _ i m u s t b e s e t t o 0 x 4 a n d 0 x 5 , r e s p e c t i v e l y .
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R E F _ R e f 5 1 3 3 2 9 8 5 2 \ h F i g u r e 1 2 s h o w s d e v e l o p m e n t i n t e r f a c e c y c l e s . W r i t e s m u s t b e s y n c h r o n o u s t o t h e m a i n R I S C c l o c k p o s i t i v e e d g e a n d s h o u l d t a k e o n e c l o c k c y c l e . R e a d s m u s t t a k e t w o c l o c k c y c l e s b e c a u s e a c c e s s t o s y n c h r o n o u s c a c h e l i n e s o r t o T L B e n t r i e s i n t r o d u c e s o n e c l o c k c y c l e o f d e l a y .
I f r e q u i r e d , e x t e r n a l d e b u g g e r c a n s t o p t h e C P U c o r e b y a s s e r t i n g d b g _ s t a l l _ i . T h i s w a y i t c a n h a v e e n o u g h t i m e t o r e a d a l l i n t e r e s t i n g r e g i s t e r s f r o m t h e R I S C o r g u a r a n t e e t h a t w r i t e s i n t o S P R s a r e p e r f o r m e d w i t h o u t R I S C w r i t i n g t o t h e s a m e r e g i s t e r s .
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A n e x t e r n a l d e b u g g e r c a n m o n i t o r a n d r e c o r d d a t a f l o w i n s i d e t h e R I S C f o r d e b u g g i n g p u r p o s e s a n d p r o f i l i n g a n a l y s i s . T h i s i s a c c o m p l i s h e d b y m o n i t o r i n g s t a t u s o f t h e l o a d / s t o r e u n i t , l o a d / s t o r e e f f e c t i v e a d d r e s s a n d l o a d / s t o r e d a t a , a l l a v a i l a b l e a t t h e d e v e l o p m e n t i n t e r f a c e .
d b g _ l s s _ o [ 3 : 0 ] L o a d / S t o r e I n s t r u c t i o n i n E x e c u t i o n 0 x 0 N o l o a d / s t o r e i n s t r u c t i o n i n e x e c u t i o n 0 x 1 R e s e r v e d f o r l o a d d o u b l e w o r d 0 x 2 L o a d b y t e a n d z e r o e x t e n d 0 x 3 L o a d b y t e a n d s i g n e x t e n d 0 x 4 L o a d h a l f w o r d a n d z e r o e x t e n d 0 x 5 L o a d h a l f w o r d a n d s i g n e x t e n d 0 x 6 L o a d s i n g l e w o r d a n d z e r o e x t e n d 0 x 7 L o a d s i n g l e w o r d a n d s i g n e x t e n d 0 x 8 R e s e r v e d f o r s t o r e d o u b l e w o r d 0 x 9 R e s e r v e d 0 x A S t o r e b y t e 0 x B R e s e r v e d 0 x C S t o r e h a l f w o r d 0 x D R e s e r v e d 0 x E S t o r e s i n g l e w o r d 0 x F R e s e r v e d T a b l e S E Q " T a b l e " \ * A r a b i c 1 6 . S t a t u s o f t h e L o a d / S t o r e U n i t
E x t e r n a l t r a c e b u f f e r c a n c a p t u r e a l l i n t e r e s t i n g d a t a f l o w e v e n t s b y a n a l y z i n g s t a t u s o f t h e l o a d / s t o r e u n i t a v a i l a b l e o n d b g _ l s s _ o . R E F _ R e f 5 1 3 3 2 6 4 8 4 \ h T a b l e 1 6 l i s t s d i f f e r e n t s t a t u s e n c o d i n g f o r t h e l o a d / s t o r e u n i t .
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A n e x t e r n a l d e b u g g e r c a n m o n i t o r a n d r e c o r d p r o g r a m f l o w i n s i d e t h e R I S C f o r d e b u g g i n g p u r p o s e s a n d p r o f i l i n g a n a l y s i s . T h i s i s a c c o m p l i s h e d b y m o n i t o r i n g s t a t u s o f t h e i n s t r u c t i o n u n i t , P C a n d f e t c h e d i n s t r u c t i o n w o r d , a l l a v a i l a b l e a t t h e d e v e l o p m e n t i n t e r f a c e .
d b g _ i s _ o [ 1 : 0 ] I n s t r u c t i o n F e t c h S t a t u s 0 x 0 N o i n s t r u c t i o n f e t c h i n p r o g r e s s 0 x 1 N o r m a l i n s t r u c t i o n f e t c h 0 x 2 E x e c u t i n g b r a n c h i n s t r u c t i o n 0 x 3 F e t c h i n g i n s t r u c t i o n i n d e l a y s l o t T a b l e S E Q " T a b l e " \ * A r a b i c 1 7 . S t a t u s o f t h e I n s t r u c t i o n U n i t
E x t e r n a l t r a c e b u f f e r c a n c a p t u r e a l l i n t e r e s t i n g p r o g r a m f l o w e v e n t s b y a n a l y z i n g s t a t u s o f t h e i n s t r u c t i o n u n i t a v a i l a b l e o n d b g _ i s _ o . R E F _ R e f 5 1 3 3 2 6 2 1 9 \ h T a b l e 1 7 l i s t s d i f f e r e n t s t a t u s e n c o d i n g f o r t h e i n s t r u c t i o n u n i t .
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R E F _ R e f 5 1 3 3 2 4 6 7 0 \ h F i g u r e 1 3 s h o w s h o w d e v e l o p m e n t i n t e r f a c e c a n a s s e r t d b g _ e w t _ I a n d c a u s e w a t c h p o i n t e v e n t . I f p r o g r a m m e d , e x t e r n a l w a t c h p o i n t e v e n t w i l l c a u s e a b r e a k p o i n t e x c e p t i o n .
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F i g u r e S E Q " F i g u r e " \ * A r a b i c 1 3 . A s s e r t i o n o f E x t e r n a l W a t c h p o i n t T r i g g e r
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T h i s s e c t i o n d e s c r i b e s a l l r e g i s t e r s i n s i d e t h e O R 1 2 0 0 c o r e . S h i f t i n g G R P n u m b e r 1 1 b i t s l e f t a n d a d d i n g R E G n u m b e r c o m p u t e s t h e a d d r e s s o f e a c h s p e c i a l - p u r p o s e r e g i s t e r . A l l r e g i s t e r s a r e 3 2 b i t s w i d e f r o m s o f t w a r e p e r s p e c t i v e . U S E R M O D E a n d S U P V M O D E s p e c i f y t h e v a l i d a c c e s s t y p e s f o r e a c h r e g i s t e r i n u s e r m o d e a n d s u p e r v i s o r m o d e o f o p e r a t i o n . R / W s t a n d s f o r r e a d a n d w r i t e a c c e s s a n d R s t a n d s f o r r e a d o n l y a c c e s s .
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M O D E D e s c r i p t i o n 0 0 V R R V e r s i o n R e g i s t e r 0 1 U P R R U n i t P r e s e n t R e g i s t e r 0 2 C P U C F G R R C P U C o n f i g u r a t i o n R e g i s t e r 0 3 D M M U C F G R R D a t a M M U C o n f i g u r a t i o n R e g i s t e r 0 4 I M M U C F G R R I n s t r u c t i o n M M U C o n f i g u r a t i o n R e g i s t e r 0 5 D C C F G R R D a t a C a c h e C o n f i g u r a t i o n R e g i s t e r 0 6 I C C F G R R I n s t r u c t i o n C a c h e C o n f i g u r a t i o n R e g i s t e r 0 7 D C F G R R D e b u g C o n f i g u r a t i o n R e g i s t e r 0 1 6 P C R / W P C m a p p e d t o S P R s p a c e 0 1 7 S R R / W S u p e r v i s i o n R e g i s t e r 0 2 0 F P C S R - R / W F P C o n t r o l S t a t u s R e g i s t e r 0 3 2 E P C R 0 R / W E x c e p t i o n P C R e g i s t e r 0 4 8 E E A R 0 R / W E x c e p t i o n E A R e g i s t e r 0 6 4 E S R 0 R / W E x c e p t i o n S R R e g i s t e r 0 1 0 2 4 - 1 0 5 5 G P R 0 - G P R 3 1 R / W G P R s m a p p e d t o S P R s p a c e 1 2 D T L B E I R W D a t a T L B E n t r y I n v a l i d a t e R e g i s t e r 1 1 0 2 4 - 1 1 5 1 D T L B W 0 M R 0 - D T L B W 0 M R 1 2 7 R / W D a t a T L B M a t c h R e g i s t e r s W a y 0 1 1 5 3 6 - 1 6 6 3 D T L B W 0 T R 0 - D T L B W 0 T R 1 2 7 R / W D a t a T L B T r a n s l a t e R e g i s t e r s W a y 0 2 2 I T L B E I R W I n s t r u c t i o n T L B E n t r y I n v a l i d a t e R e g i s t e r 2 1 0 2 4 - 1 1 5 1 I T L B W 0 M R 0 - I T L B W 0 M R 1 2 7 R / W I n s t r u c t i o n T L B M a t c h R e g i s t e r s W a y 0 2 1 5 3 6 - 1 6 6 3 I T L B W 0 T R 0 - I T L B W 0 T R 1 2 7 R / W I n s t r u c t i o n T L B T r a n s l a t e R e g i s t e r s W a y 0 3 0 D C C R R / W D C C o n t r o l R e g i s t e r 3 2 D C B F R W W D C B l o c k F l u s h R e g i s t e r 3 3 D C B I R W W D C B l o c k I n v a l i d a t e R e g i s t e r 3 4 D C B W R W W D C B l o c k W r i t e - b a c k r e g i s t e r 4 0 I C C R R / W I C C o n t r o l R e g i s t e r 4 2 5 6 I C B I R W W I C B l o c k I n v a l i d a t e R e g i s t e r 5 2 5 6 M A C L O R / W R / W M A C L o w 5 2 5 7 M A C H I R / W R / W M A C H i g h 6 1 6 D M R 1 R / W D e b u g M o d e R e g i s t e r 1 6 1 7 D M R 2 R / W D e b u g M o d e R e g i s t e r 2 6 2 0 D S R R / W D e b u g S t o p R e g i s t e r 6 2 1 D R R R / W D e b u g R e a s o n R e g i s t e r 8 0 P M R R / W P o w e r M a n a g e m e n t R e g i s t e r 9 0 P I C M R R / W P I C M a s k R e g i s t e r 9 2 P I C S R R / W P I C S t a t u s R e g i s t e r 1 0 0 T T M R R / W T i c k T i m e r M o d e R e g i s t e r 1 0 1 T T C R R * R / W T i c k T i m e r C o u n t R e g i s t e r T a b l e S E Q " T a b l e " \ * A r a b i c 1 8 . L i s t o f A l l R e g i s t e r s
R E F _ R e f 5 1 3 3 0 9 4 1 0 \ h T a b l e 1 8 l i s t s a l l O p e n R I S C 1 0 0 0 s p e c i a l - p u r p o s e r e g i s t e r s i m p l e m e n t e d i n O R 1 2 0 0 . R e g i s t e r s V R a n d U P R a r e d e s c r i b e d b e l o w . F o r d e s c r i p t i o n o f o t h e r r e g i s t e r s r e f e r t o O p e n R I S C 1 0 0 0 S y s t e m A r c h i t e c t u r e M a n u a l d o c u m e n t .
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S p e c i a l - p u r p o s e r e g i s t e r V R i d e n t i f i e s t h e v e r s i o n ( m o d e l ) a n d r e v i s i o n l e v e l o f t h e O p e n R I S C 1 0 0 0 p r o c e s s o r . I t a l s o s p e c i f i e s p o s s i b l e s t a n d a r d t e m p l a t e o n w h i c h t h i s i m p l e m e n t a t i o n i s b a s e d .
B i t # A c c e s s R e s e t D e s c r i p t i o n 5 : 0 R R e v i s i o n R E V
R e v i s i o n n u m b e r o f t h i s d o c u m e n t . 1 5 : 6 R 0 x 0 R e s e r v e d 2 3 : 1 6 R 0 x 0 0 C F G
C o n f i g u r a t i o n s h o u l d b e r e a d f r o m U P R a n d c o n f i g u r a t i o n r e g i s t e r s 3 1 : 2 4 R 0 x 1 2 V E R
V e r s i o n n u m b e r f o r O R 1 2 0 0 i s f i x e d a t 0 x 1 2 0 0 . T a b l e S E Q " T a b l e " \ * A r a b i c 1 9 . V R R e g i s t e r
R e g i s t e r U P R d e s c r i p t i o n
S p e c i a l - p u r p o s e r e g i s t e r U P R i d e n t i f i e s t h e u n i t s p r e s e n t i n t h e p r o c e s s o r . I t h a s a b i t f o r e a c h i m p l e m e n t e d u n i t o r f u n c t i o n a l i t y . L o w e r s i x t e e n b i t s i d e n t i f y p r e s e n t u n i t s d e f i n e d i n t h e O p e n R I S C 1 0 0 0 a r c h i t e c t u r e . U p p e r s i x t e e n b i t s d e f i n e p r e s e n t c u s t o m u n i t s .
B i t # A c c e s s R e s e t D e s c r i p t i o n 0 R 1 U P
U P R p r e s e n t 1 R 1 D C P
D a t a c a c h e p r e s e n t * 2 R 1 I C P
I n s t r u c t i o n c a c h e p r e s e n t * 3 R 1 D M P
D a t a M M U p r e s e n t * 4 R 1 I M P
I n s t r u c t i o n M M U p r e s e n t * 5 R 1 M P
M A C p r e s e n t * 6 R 1 D U P
D e b u g u n i t p r e s e n t * 7 R 0 P C U P
P e r f o r m a n c e c o u n t e r s u n i t n o t p r e s e n t * 8 R 1 P M P
P o w e r M a n a g e m e n t P r e s e n t * 9 R 1 P I C P
P r o g r a m m a b l e i n t e r r u p t c o n t r o l l e r p r e s e n t 1 0 R 1 T T P
T i c k t i m e r p r e s e n t 1 1 R 1 F P P
F l o a t i n g p o i n t p r e s e n t * 2 3 : 1 2 R X R e s e r v e d 3 1 : 2 4 R 0 x X X X X C U P
T h e u s e r o f t h e O R 1 2 0 0 c o r e a d d s c u s t o m u n i t s . T a b l e S E Q " T a b l e " \ * A r a b i c 2 0 . U P R R e g i s t e r
* i f e n a b l e d a t s y n t h e s i s t i m e
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S p e c i a l - p u r p o s e r e g i s t e r C P U C F G R i d e n t i f i e s t h e c a p a b i l i t i e s a n d c o n f i g u r a t i o n o f t h e C P U .
B i t # A c c e s s R e s e t D e s c r i p t i o n 3 : 0 R 0 x 0 N S G F
Z e r o n u m b e r o f s h a d o w G P R f i l e s 4 R 0 H G F
N o h a l f G P R f i l e s * 5 R 1 O B 3 2 S
O R B I S 3 2 s u p p o r t e d 6 R 0 O B 6 4 S
O R B I S 6 4 n o t s u p p o r t e d 7 R 1 O F 3 2 S
O R F P X 3 2 s u p p o r t e d * * 8 R 0 O F 6 4 S
O R F P X 6 4 n o t s u p p o r t e d 9 R 0 O V 6 4 S
O R V D X 6 4 n o t s u p p o r t e d T a b l e S E Q " T a b l e " \ * A r a b i c 2 1 . C P U C F G R R e g i s t e r
* I f d i s a b l e d a t s y n t h e s i s t i m e
* * I f F P U e n a b l e d a t s y n t h e s i s t i m e
R e g i s t e r D M M U C F G R d e s c r i p t i o n
S p e c i a l - p u r p o s e r e g i s t e r D M M U C F G R i d e n t i f i e s t h e c a p a b i l i t i e s a n d c o n f i g u r a t i o n o f t h e D M M U .
B i t # A c c e s s R e s e t D e s c r i p t i o n 1 : 0 R 0 x 0 N T W
O n e D T L B w a y 4 : 2 R 0 x 4 0 x 7 N T S
1 6 , 3 2 , 6 4 o r 1 2 8 D T L B s e t s 7 : 5 R 0 x 0 N A E
N o A T B E n t r i e s 8 R 0 C R I
N o D M M U c o n t r o l r e g i s t e r i m p l e m e n t e d 9 R 0 P R I
N o p r o t e c t i o n r e g i s t e r i m p l e m e n t e d 1 0 R 1 T E I R I
D T L B e n t r y i n v a l i d a t e r e g i s t e r i m p l e m e n t e d 1 1 R 0 H T R
N o h a r d w a r e D T L B r e l o a d T a b l e S E Q " T a b l e " \ * A r a b i c 2 2 . D M M U C F G R R e g i s t e r
R e g i s t e r I M M U C F G R d e s c r i p t i o n
S p e c i a l - p u r p o s e r e g i s t e r I M M U C F G R i d e n t i f i e s t h e c a p a b i l i t i e s a n d c o n f i g u r a t i o n o f t h e I M M U .
B i t # A c c e s s R e s e t D e s c r i p t i o n 1 : 0 R 0 x 0 N T W
O n e I T L B w a y 4 : 2 R 0 x 4 0 x 7 N T S
1 6 , 3 2 , 6 4 o r 1 2 8 I T L B s e t s 7 : 5 R 0 x 0 N A E
N o A T B E n t r i e s 8 R 0 C R I
N o I M M U c o n t r o l r e g i s t e r i m p l e m e n t e d 9 R 0 P R I
N o p r o t e c t i o n r e g i s t e r i m p l e m e n t e d 1 0 R 1 T E I R I
I T L B e n t r y i n v a l i d a t e r e g i s t e r i m p l e m e n t e d 1 1 R 0 H T R
N o h a r d w a r e I T L B r e l o a d T a b l e S E Q " T a b l e " \ * A r a b i c 2 3 . I M M U C F G R R e g i s t e r
R e g i s t e r D C C F G R d e s c r i p t i o n
S p e c i a l - p u r p o s e r e g i s t e r D C C F G R i d e n t i f i e s t h e c a p a b i l i t i e s a n d c o n f i g u r a t i o n o f t h e d a t a c a c h e .
B i t # A c c e s s R e s e t D e s c r i p t i o n 2 : 0 R 0 x 0 N C W
O n e D C w a y 6 : 3 R 0 x 4 0 x 7 N C S
1 6 , 3 2 , 6 4 o r 1 2 8 D C s e t s 7 R 0 x 0 C B S
1 6 - b y t e c a c h e b l o c k s i z e 8 R 0 C W S
C a c h e w r i t e - t h r o u g h s t r a t e g y * 9 R 1 C C R I
D C c o n t r o l r e g i s t e r i m p l e m e n t e d 1 0 R 1 C B I R I
D C b l o c k i n v a l i d a t e r e g i s t e r i m p l e m e n t e d 1 1 R 0 C B P R I
D C b l o c k p r e f e t c h r e g i s t e r n o t i m p l e m e n t e d 1 2 R 0 C B L R I
D C b l o c k l o c k r e g i s t e r n o t i m p l e m e n t e d 1 3 R 1 C B F R I
D C b l o c k f l u s h r e g i s t e r i m p l e m e n t e d 1 4 R 1 C B W B R I
D C b l o c k w r i t e - b a c k r e g i s t e r i m p l e m e n t e d * * T a b l e S E Q " T a b l e " \ * A r a b i c 2 4 . D C C F G R R e g i s t e r
* I f W r i t e - t h r o u g h e n a b l e d a t s y n t h e s i s t i m e
* * I f W r i t e - t h r o u g h d i s a b l e d a t s y n t h e s i s t i m e
R e g i s t e r I C C F G R d e s c r i p t i o n
S p e c i a l - p u r p o s e r e g i s t e r I C C F G R i d e n t i f i e s t h e c a p a b i l i t i e s a n d c o n f i g u r a t i o n o f t h e i n s t r u c t i o n c a c h e .
B i t # A c c e s s R e s e t D e s c r i p t i o n 2 : 0 R 0 x 0 N C W
O n e I C w a y 6 : 3 R 0 x 4 0 x 7 N C S
1 6 , 3 2 , 6 4 o r 1 2 8 I C s e t s 7 R 0 x 0 C B S
1 6 - b y t e c a c h e b l o c k s i z e 8 R 0 C W S
C a c h e w r i t e - t h r o u g h s t r a t e g y 9 R 1 C C R I
I C c o n t r o l r e g i s t e r i m p l e m e n t e d 1 0 R 1 C B I R I
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P o r t W i d t h D i r e c t i o n D e s c r i p t i o n R s t 1 I n p u t A s y n c h r o n o u s r e s e t c l k _ c p u 1 I n p u t M a i n c l o c k i n p u t t o t h e R I S C c l k _ d c 1 I n p u t D a t a c a c h e c l o c k c l k _ i c 1 I n p u t I n s t r u c t i o n c a c h e c l o c k c l k _ d m m u 1 I n p u t D a t a M M U c l o c k c l k _ i m m u 1 I n p u t I n s t r u c t i o n M M U c l o c k c l k _ t t 1 I n p u t T i c k t i m e r c l o c k T a b l e S E Q " T a b l e " \ * A r a b i c 2 9 . S y s t e m I n t e r f a c e S i g n a l s
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P o r t W i d t h D i r e c t i o n D e s c r i p t i o n d b g _ d a t _ o 3 2 O u t p u t T r a n s f e r o f d a t a f r o m R I S C t o e x t e r n a l d e v e l o p m e n t i n t e r f a c e d b g _ d a t _ i 3 2 I n p u t T r a n s f e r o f d a t a f r o m e x t e r n a l d e v e l o p m e n t i n t e r f a c e t o R I S C d b g _ a d r _ i 3 2 I n p u t A d d r e s s o f s p e c i a l - p u r p o s e r e g i s t e r t o b e r e a d o r w r i t t e n d b g _ o p _ I 3 I n p u t O p e r a t i o n s e l e c t f o r d e v e l o p m e n t i n t e r f a c e d b g _ l s s _ o 4 O u t p u t S t a t u s o f l o a d / s t o r e u n i t d b g _ i s _ o 2 O u t p u t S t a t u s o f i n s t r u c t i o n f e t c h u n i t d b g _ w p _ o 1 1 O u t p u t S t a t u s o f w a t c h p o i n t s d b g _ b p _ o 1 O u t p u t S t a t u s o f t h e b r e a k p o i n t d b g _ s t a l l _ i 1 I n p u t S t a l l s R I S C C P U c o r e d b g _ e w t _ i 1 I n p u t E x t e r n a l w a t c h p o i n t t r i g g e r T a b l e S E Q " T a b l e " \ * A r a b i c 3 0 . D e v e l o p m e n t I n t e r f a c e
P o w e r M a n a g e m e n t I n t e r f a c e
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P o r t W i d t h D i r e c t i o n G e n e r a t i o n D e s c r i p t i o n p m _ c l k s d 4 O u t p u t S t a t i c ( i n S W ) S l o w d o w n o u t p u t s t h a t c o n t r o l r e d u c t i o n o f R I S C c l o c k f r e q u e n c y p m _ c p u s t a l l 1 I n p u t - S y n c h r o n o u s s t a l l o f t h e R I S C s C P U c o r e p m _ d c _ g a t e 1 O u t p u t D y n a m i c ( i n H W ) G a t i n g o f d a t a c a c h e c l o c k p m _ i c _ g a t e 1 O u t p u t D y n a m i c ( i n H W ) G a t i n g o f i n s t r u c t i o n c a c h e c l o c k p m _ d m m u _ g a t e 1 O u t p u t D y n a m i c ( i n H W ) G a t i n g o f d a t a M M U c l o c k p m _ i m m u _ g a t e 1 O u t p u t D y n a m i c ( i n H W ) G a t i n g o f i n s t r u c t i o n M M U c l o c k p m _ t t _ g a t e 1 O u t p u t D y n a m i c ( i n H W ) G a t i n g o f t i c k t i m e r c l o c k p m _ c p u _ g a t e 1 O u t p u t S t a t i c ( i n S W ) G a t i n g o f m a i n C P U c l o c k p m _ w a k e u p 1 O u t p u t D y n a m i c ( i n H W ) A c t i v a t e a l l c l o c k s p m _ l v o l t 1 O u t p u t S t a t i c ( i n S W ) L o w e r v o l t a g e T a b l e S E Q " T a b l e " \ * A r a b i c 3 1 . P o w e r M a n a g e m e n t I n t e r f a c e
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P o r t W i d t h D i r e c t i o n D e s c r i p t i o n p i c _ i n t s P I C _ I N T S I n p u t E x t e r n a l i n t e r r u p t s T a b l e S E Q " T a b l e " \ * A r a b i c 3 2 . I n t e r r u p t I n t e r f a c e
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Word 1B % % % - 2
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TextGridY 6
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Word IC_SETS-2B % % 0 % - - ) - % 2
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ImportStartTime 0.000000
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ImportEndTime 281474976710656.000000
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- - $
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Visible DELAYS SETUPS HOLDS SAMPLES TEXT HIDDENATTACHMENTS CRITICALPATHS GRIDLINES UNCERTAINTY
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|
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L - -
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ScrollPos 0.000000,0.000000,0.000000
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NoEventOverlap NO
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UseFullPathNames 1
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DMMUH S S H - % L
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|
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- - - $
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PrintSigNames YES
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: log ! Arial ?A?A?A?A?A?A?A?A?A?A?A?A? - 2
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PrintSigNamesOnEachPage YES
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~ 2 2 Arial ?A?A?A?A?A?A?A?A?A?A?A?A? - 2
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(IC_SETS)+4 $ ! ! ! -
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WAY 0 O 9 8 . - - $ HL)L) H HL - -
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DefaultHold 0
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|
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|
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CORGROUP $$CLK_I_BufferRising
|
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Percent 100
|
v@Yd!Y0:R%;\O %U2 ߧȹE*%$U^Q|+|"(9 &)|A2Q !|
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|
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CORGROUP $$CLK_I_BufferFalling
|
j += V h * /۽*k8Co#!2/ / /?!?3?}eAȣY +d ?@M?@UbZuȳxkOvtqa b醴utr[{ wSvw
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Percent 100
|
*2߿U[tcw1 qgy膟~WbvH/Omi%2Mr>17lr b.oooooo -?xPp|(Tfxu(2 1@{N,AS ewя 2+6$K ]ɟz #5Gk}Gৡ_a!$@ͭ>1 m9ODž9D6i@@I?@SC]SBzw8B,(@b_Sƍ_S(A,)3e Xp:_eŃ!@ F1!?pMX !vÔܯC?U?g?y?;&G
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|
8A,VA*OAe L@)3RpA :g kP@z3[Q4b:oLn{#@VgW$onV gmWo??U><+N?¬SAczre?w?????? ??wX.GC>O >iEWOGE<4yl`
|
CORGROUP $$CLK_I_BufferRisingFalling
|
zr?yAM lh ]hMZ R7Yf@DzVtC᪡q-B)F o̕ ?qzI2r q fEI7,X7S@CVQrE5&YxyBqE"4zvP;3M4) kPp` A1I?ǣAu<CY4ԿCjq,w|;@KE}|tS>u7ϐ6͕$ ]f?m۶m|; ݩϻϼVeX`` MO_OqOOOOOOٓ/?@^X_r =_O_a_s__0____?,)A/I?_eO?y%@$ASTԯ,8
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Percent 100
|
yC'TO/FROM CPU
|
!
|
|
|
EXTEN I/F FȁCȁ~d @Ə؏C @@|W=i$E J Tf@l艙l&C ( )o$@ 4b phe&Po/.f'(<{"77
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|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
SELECTS U> U#$%&U*-.0U1234 Ul4,_j @K%@ DC- T7 AU2@$ ZD7 JR H<(
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!
|
U2El D7
R UlL O( D @ ?,% ) R- ) < ;U$
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|
4( U1( UO"D&aU=QJf )h" Ty+Uv' _ Ʌ &aQ-
|
CORGROUP $$CLK_I_BufferFalling
|
- H* 9( TYg EQ /, Guide TheDoc Page-1 Gesture Format Block Normal Visio 10 Block Shadow Visio 12 Block Highlt Visio 11 Connector Visio 90 Dot Connector Connector Arrow Visio 00 Visio 01 Visio 02 Visio 03 Visio 13 Visio 20 Visio 21 Visio 22 Visio 23 Visio 50 Visio 51 Visio 52 Visio 53 Visio 70 Visio 80 Box Box.3 Box.4 Box.5 Dynamic conn?ector Dynamic connector.10 Dynamic connector.23 Box.37 Dynamic connector.40 Dynamic connector.50 Dynamic connector.52 Box.2 Box.9 Box.13 _ 53 E
|
Percent 100
|
E F
-
|
!
|
R - G U0- A- }
Nc
|
|
U, _u
|
CORGROUP $$CLK_I_BufferRisingFalling
|
D lQ
|
Percent 100
|
U\ u
|
!
|
t - U u
|
|
U- U - UUԃ u
|
CORGROUP $$CLK_I_BufferRising
|
}u
|
Percent 100
|
u
|
!
|
7Gv 47ML7 Md7*M|77M7DM7QM7^M7kM7xM M$M<MdcM ATM d7*l7*t7*|I**I*MM UH8)** 'W :* 0>*$ 0B 04 0M:T 0l*\ 0p:| 0: 0 0: 0TE63*(! 0 xfR! T! !"# !%&'()*+T-./U0124 UjU
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|
U
UUU Ul4,_j @K%@ L K UUC-<3 q7 A Ul4, K
|
CORGROUP $$CLK_I_BufferFalling
|
AJ- 3 7 A _ *<N@ wK LRVg q 6uH<(
|
Percent 100
|
H<(
|
!
|
_ *<NE KL
RVg Xq >={ z
|
|
* g"4pFX (r@(ja@2y
|
CORGROUP $$CLK_I_BufferRisingFalling
|
JlO :]R
|
Percent 100
|
TQ U#u &T !B }U ?Q
>4YC O 9B m `O y Nfi$S f'D ON4_ >E)UdG1UW=` 2L H EV
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!
|
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|
w
|
CORGROUP $$CLK_I_BufferRising
|
EMF E X V I S I O D r a w i n g M D ? ? l ( @ ( ʦ Pages Masters Page-1 Box Dynamic connector 8 _VPID_PREVIEWS _VPID_ALTERNATENAMES @ _PID_LINKBASE ÿ A
|
Percent 100
|
F Microsoft Visio Drawing VISIO 6.0 Shapes Visio.Drawing.6 9q _ 1 0 4 8 0 2 5 4 9 1 4 F Q ) O l e
|
!
|
M P R I N T 1 3 ( C o m p O b j N q
|
|
] ^ ! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ A a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~ P&l P
& " WMFC X x x j P &l EMF x l X V I S I O D r a w i n g
|
CORGROUP $$CLK_I_BufferFalling
|
% R L A r i a l % T l ! y
|
Percent 100
|
@
|
!
|
@! y L X S E T 0 - - ) % T l !
|
|
@
|
CORGROUP $$CLK_I_BufferRisingFalling
|
@! L X S E T 1 - - ) % R L A r i a l JSTFm*i Wp LTSH& X OS/2 3 VPC AG ? 6VDMXVp ] cmapܣ 1 cvt ؔ 8 8fpgm Ggasp P glyf~( ިhdmx yhead fY | 6hhea $hmtxR p :kernAON *P Zloca % T ` b 6
|
Percent 100
|
|
!
|
@
|
|
@b L T . . . R L A r i a l F d $ X * n 2 $ f 0 F P B r , > P r R ª % T ` =
S
|
CORGROUP $$CLK_I_BufferRising
|
@
|
Percent 100
|
@=
L T S E T - - ) R L A r i a l Ѱ & b Ҟ 4 d ӊ Ӱ P Ԑ " Z Մ ծ 4 Z ք ֮ B r ע 0 ` ؐ $ ل ٸ P ڰ H ި All Rights ReservedArialBoldMonotype t)% T J
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|
@
|
|
@ J
L d D T L B _ S E T S - 1 TM & % % V 0 9
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% ( R L A r i a l of the last decades of the twentieth century. Th erall treatment of curves is softer and fuller than in most industrial style sans serif faces. Terminal strokes are cut on th diagonal which helps to give the face a less mechanical appear ti% ( R L A r i a l in reports, presentations, magazines etc, and for play use in newspapers, advertising and promotions.http://www.monotype.com/html/mtname/ms_arial.htmlhttp://www.monotype.com/ht /mtname/ms_welcome.htmlNOTIFICATION OF LICENSE AGREEMENT
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
Th ot% ( R L A r i a l reement. You have obtained this typeface software er directly from Monotype or together with software distributed by one of Monotypes licensees.
|
!
|
|
|
This software is a valuable sset of Monotype. Unless you have entered into a specific lice na% ( R L A r i a l own publishing use. You may not copy or distribute s software.
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
If you have any question concerning your rights you should review the license agreement you received with the s tware or contact Monotype for a copy of the license agreement.
|
!
|
% ( R L A r i a l //www.monotype.com/html/type/license.html N e g r a A r i a l N e g r e t a t u
n A r i a l t u
n f e d A r i a l f e d F e t t A r i a l F e t t A i a l T y p e f a c e T h e M o n o t y c % ( R L A r i a l T y p e S o l u t i o n s I n c . 1 9 9 0 - 9 2 . A l l R i g h t s R e s e r v e d A r i a l B o l d M o n o t y p e : A r i a l B o l d : V e r s i o n 2 . 7 ( M i c r o s o f t ) A r i a l B o l d V e r s i o n 2 i % ( R L A r i a l i o n p l c r e g i s t e r e d i n t h e S P a t & T M O f f . a n d e l s e w h e r e . M o n o t y p e T y p o g r a p h y M o n o t y p e T y p e r a w i n g O f f i c e - R o b i n N i c h o l a s , s % ( % R L A r i a l R | Ҧ P \ ך & l 8 > 0 Z , V ( R | & P V
|
|
@ B z ( R % T l [ {
|
CORGROUP $$CLK_RISC_BufferRising
|
@
|
Percent 100
|
@ [ L X V P N 0 - - 0 % T l {
|
!
|
@
|
|
@ L X V P N 1 - - 0 % R L A r i a l 4J 5 5 7 7 8` 8p 8 8 : : :( :8 < = > @
|
CORGROUP $$CLK_RISC_BufferFalling
|
A B C D D E F HX Hh I J L L L L M N N N O O P P R R R R S U> Vj Wd Wt W W Y2 Z [ [ ^0 `z c eh % T ` 7
|
Percent 100
|
|
!
|
@
|
|
@ L T . . . R L A r i a l t t t u u2 u\ u u u v v. vX v v w w* wT w~ w w w x& xP xz x x x y" yL yv z zZ z z {$ {N {x { { { | |J |t | | } }F }p } } } ~ ~B ~l ~ ~ ~ ( \ % ( % T ` ,
M d
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
@
|
Percent 100
|
@ ,
L T V P N ! ! $ T v h
|
!
|
@
|
|
@v h
L d D T L B _ S E T S - 1 $ ! ! ! ! & % % V 0 j M k L L k k L% ( % R L A r i a l 8 p 2 b P p j 8 X s c o v e r e d u n d e r t h e t e r m s o f a l i c e n s e a g r e e m e n t Y o u h a v e o b t a i n e d t h i s t y p e f a c % T ~ b
|
CORGROUP $$CLK_RISC_BufferRising
|
@
|
Percent 100
|
@ L p E F F E C T I V E A D D R E S S b - ) ) - 0 ( - - - 0 0 0 - - - & % % V 0 F 6
G
5
5 GG
% ( R L A r i a l r a n t i n g y o u a d d i t i o n a l r i t s , y o u r u s e o f t h i s s o f t w a r e i s l i m i t e d t o y o u r w o r k s t a t i o n f o y o u r o w n p u b l i s h i n g u s e . Y o u m s % ( R L A r i a l a n y q u e s t i o n c o n c e r n i n g y r r i g h t s y o u s h o u l d r e v i e w t h e l i c e n s e a g r e e m e n t y o u r e c e i v e d w t h t h e s o f t w a r e o r c o n t a c t M o n o f % ( R L & " WMFC 8 x A r i a l n b e c o n t a c t e d a t :
|
!
|
|
|
U S A ( 8 4 7 ) 7 1 8 - 0 4 0 0 U K - 0 1 1 4 4 0 1 7 3 7 7 6 5 9 5 9
|
CORGROUP $$CLK_RISC_BufferFalling
|
h t t p : / / w w w . m o n o t y p e . c m h t t p : / / w w w . m o n o t y p e . c o m / h t m l / t o % ( R L A r i a l r d N o r m a l N o r m a l n y N o r m a l 1K K9 N o r m l n e N o r m a l N o r m a l N a v a d n o t h n g A r r u n t a N o r m a l N o r m a l N o r m a l N o m a l . 1 9 9 0 - 1 9 9 2 . A l l R i g h t s R e s e o % ( R L A r i a l r o s o f t ) A r i a l V e r s i o n 2 . 7 6 A a l M T A r i a l T r a d e m GSUB ' JSTFm*i *\ LTSH! Ud OS/2 2k VPCLT{>C 6VDMXPj Zx cmapܣ .@ cvt pv | 0fpgmw' w gasp P y% ( R L A r i a l Dmaxp name6 ` +postƬ%E 0 epq l
|
Percent 100
|
y" yL yv z zZ z z {$ {N {x { { { | |J |t | | | } }F }p } } ~ ~B ~l ~ ~ ~ ( \ x z J . t ( % ( R L A r i a l * < ( L ^ p 0 6 ` . x H R d r , ` B
|
!
|
P % ( R L A r i a l @ n ( ^ 0 ` > j 8 p 2 b P < p j 8 X rif desi , Arial contains more humanist characteristics than many of it i% ( %
( % R L A r i a l n in most industrial style sans serif faces. Term strokes are cut on the diagonal which helps to give the face a less mechanical appearance. Arial is an extremely versatile f ily of typefaces which can be used with equal success for text , % T l ] o
|
|
@
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
@] o L X P P N 0 om- - 0 % T l ]
|
Percent 100
|
@
|
!
|
@] L X P P N 1 t- - 0 % % T ` ,
|
|
|
CORGROUP $$CLK_I_BufferRising
|
@
|
Percent 100
|
@ L T . . . of R L A r i a l types licensees.
|
!
|
|
|
This software is a valuable a of Monotype. Unless you have entered into a specific license agreement granting you additional rights, your use of this softw e is limited to your workstation for your own publishing use. s % T I
|
CORGROUP $$CLK_I_BufferFalling
|
@
|
Percent 100
|
@ L l P P N D T L B _ S E T S - 2 t- - 0 0 ) % - % - - ) - % T O
|
!
|
@
|
|
@ O
L l P P N D T L B _ S E T S - 1 ty- - 0 0 ) % - % - - ) - % %
( & % % V 0 M L L L% ( %
( %
( & % % V 0 M LL L% ( & % % W , C $ L--% ( & % % W , Z
Y
Y
% ( & % % W , C K
|
CORGROUP $$CLK_I_BufferRisingFalling
|
B LB
|
Percent 100
|
% ( % % V 0 % %% % R L A r i a l o n t a i n s m o r e h u m a n i s t c h a c t e r i s t i c s t h a n m a n y o f i t s p r e d e c e s s o r s a n d a s s u c h i s m o r e i n t u n e w i t h t h e m o o d o f t h e l a s t e % T x k
|
!
|
@
|
|
@ k L \ T L B S E T ) % - - - ) T l
|
CORGROUP $$CLK_RISC_BufferRising
|
@
|
Percent 100
|
@ L X I N D E X 0 0 - + & % W $
|
!
|
a
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
X
|
Percent 100
|
% ( % % V , N =
|
!
|
N
|
|
N=
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
N & % % V 0
% ( % % T d X
|
Percent 100
|
@
|
!
|
@ X L T C O M P 0 4 7 - & % W $ q h% ( % % V , } ^ ^}^^ & % % W $
$ q
h% ( % % V , ^ B B^^B^ & % % V 0 % ( %
( % % T ` ' q
|
|
@
|
CORGROUP $$CLK_I_BufferRising
|
@ ' L T I N V 0 - & % W $ W i @ ``7% ( % % V , 9 . .`9..%
( R L
|
Percent 100
|
|
!
|
A r i a l % ( %
( % % T l 8 #
|
|
@
|
CORGROUP $$CLK_I_BufferFalling
|
@ L X H I T 0 0 ) % %
( R L A r i a l % T X
|
Percent 100
|
@
|
!
|
@ L P 3 1 % % R L A r i a l % T `
|
|
@
|
CORGROUP $$CLK_I_BufferRisingFalling
|
@ L T l o g R L A r i a l & " WMFC x g u s e . Y o u m y n o t c o p y o r d i s t r i b u t e t h i s s u% T T
|
Percent 100
|
@
|
!
|
@ L P 2 R L A r i a l t y o u r e c e i v e d w i t h t h e s t w a r e o r c o n t a c t M o n o t y p e f o r a c o p y o f t h e l i c e n s e a g r e e m e n t .
|
|
M o n o t y p e c a n b e c o n t a c t e d a t : 1% ( % T
|
CORGROUP $$CLK_RISC_BufferRising
|
@
|
Percent 100
|
@ L h ( D T L B _ S E T S ) + 1 3 $ ! ! ! ! %
( R L A r i a l 92. All Rights ReservedArialRegularMonotype:Arial lar:Version 2.76 (Microsoft)ArialVersion 2.76ArialMTArial Trademark of The Monotype Corporation plc registered in the US Pat TM Off. and elsewhere.Monotype TypographyMonotype Type Drawing S% T X I
|
!
|
@
|
|
@I L P 1 3 % % % T T
|
CORGROUP $$CLK_RISC_BufferFalling
|
@
|
Percent 100
|
@ L P 0 er% R L A r i a l serif faces. Terminal strokes are cut on the diag which helps to give the face a less mechanical appearance. Arial is an extremely versatile family of typefaces which can be ed with equal success for text setting in reports, presentatio u% T l
|
!
|
@
|
|
@ L X W A Y 0 :/O 9 8 . & % W $ { % ( % % V , % R L
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
A r i a l e distributed by one of Monotypes licensees.
|
!
|
|
|
T software is a valuable asset of Monotype. Unless you have entered into a specific license agreement granting you additional ri ts, your use of this software is limited to your workstation f y % T m
|
CORGROUP $$CLK_I_BufferRising
|
@
|
Percent 100
|
@ L ` D T L B M I S S t0 ) % - 7 - - T l
|
!
|
@
|
|
@l L ` E X C E P T I O N 7)- + 0 - - ) 4 0 %
( %
( R L A r i a l dL L L L M N N N O P P R R R R R S U> Vj Wd Wt W W Y2 Z [ [ ^0 `z c eh g jb l2 m n n@ nP n` n n n n o( oR ob or o o o p p p p0 p@ % T X
|
CORGROUP $$CLK_I_BufferFalling
|
@
|
Percent 100
|
@ L P 1 2 % % & % W $ % ( % % V , & % % W $ % ( & % % W $
% ( & % % W $ % ( % % V 9
|
!
|
|
|
& % % W $ { % ( % % V , %
( %
( % R L
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
A r i a l r e d i s t r i b u t e d b y o n e o f n o t y p e s l i c e n s e e s .
|
!
|
|
|
T h i s s o f t w a r e i s a v a l u a b l e a s s e t o f M o n t y p e . U n l e s s y o u h a v e e n t e r e d i c % T j
|
CORGROUP $$CLK_RISC_BufferRising
|
@
|
Percent 100
|
@ j L d P A D D R [ 3 1 : 1 3 ] - - 0 0 0 % % % % & % W ( C G L>% ( & % % W $ 5 3 >*% ( % % V , ! !! !R L A r i a l e n t y o u r e c e i v e d w i t h t h e o f t w a r e o r c o n t a c t M o n o t y p e f o r a c o p y o f t h e l i c e n s e a g r e e m e n t
|
!
|
|
|
M o n o t y p e c a n b e c o n t a c t e d a % ( % % T ~ T
|
CORGROUP $$CLK_RISC_BufferFalling
|
@
|
Percent 100
|
@~ L d P A G E O F F S E T o - - 4 - 4 ) ) - - ) T F 1
|
!
|
@
|
|
@ F L d P A D D R [ 1 2 : 0 ] m - - 0 0 0 % % % %
( R L A r i a l a l N o r m a l e r t y o f M o n o t y p e p o g r a p h y a n d i t s u s e b y y o u i s c o v e r e d u n d e r t h e t e r m s o f a l i c n s e a g r e e m e n t . Y o u h a v e o b t a i n e o % ( R L A r i a l r t o g e t h e r w i t h s o f t w a r e s t r i b u t e d b y o n e o f M o n o t y p e s l i c e n s e e s .
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
T h i s s o f t w a r e i s a v a l u a b l e a s s e t o f M o n o t y p e . U n l r % ( %
( R L A r i a l o n a l r i g h t s , y o u r u s e o f i s s o f t w a r e i s l i m i t e d t o y o u r w o r k s t a t i o n f o r y o u r o w n p u b l i s h n g u s e . Y o u m a y n o t c o p y o r d i s % T `
|
!
|
E
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
@
|
Percent 100
|
@
|
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|
L T l o g R L A r i a l racteristics than many of its predecessors and as is more in tune with the mood of the last decades of the twentieth century. The overall treatment of curves is softer and fu er than in most industrial style sans serif faces. Terminal s ch% T T F
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|
W
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
@
|
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|
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|
|
L P 2 il R L A r i a l presentations, magazines etc, and for display use newspapers, advertising and promotions.http://www.monotype.com/html/mtname/ms_arial.htmlhttp://www.monotype.com/html/mtname/ms elcome.htmlNOTIFICATION OF LICENSE AGREEMENT
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
This typeface ap% T X
|
!
|
|
|
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|
CORGROUP $$CLK_RISC_BufferRising
|
@X
|
Percent 100
|
L h ( D T L B _ S E T S ) + 1 2 $ ! ! ! ! & % W $ % ( % & "WMFC x % V 0 z b
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|
!
|
|
|
If you have any q ion concerning your rights you should review the license agreement you received with the software or contact Monotype for a co of the license agreement.
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
Monotype can be contacted at:
|
!
|
01% T Y
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|
|
@
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
@ L l D & A a t t r i b u t e s 0 - - % % % % " & % % V 0 `
|
Percent 100
|
f a
|
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|
e e a
|
|
a
|
CORGROUP $$CLK_RISC_BufferRising
|
e% ( %
( % R L A r i a l p e : A r i a l R e g u l a r : V e r s i o n 7 6 ( M i c r o s o f t ) A r i a l V e r s i o n 2 . 7 6 A r i a l M T A r i a l T r a d e m a r k o f T h e M n o t y p e C o r p o r a t i o n p l c r e g i s t e r & % T
|
Percent 100
|
]
|
!
|
@
|
|
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|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
L ` P A G E F A U L T - - 4 - ) - 0 % ) & % W $ 0 B 9 9% ( % % V , a
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|
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9 ` & % % W $ 0 9 % ( %
( % % V 0 m M mMMmmM % R L A r i a l f c u r v e s i s s o f t e r a n d f u e r t h a n i n m o s t i n d u s t r i a l s t y l e s a n s s e r i f f a c e s . T e r m i n a l s t o k e s a r e c u t o n t h e d i a g o n a l w h % T x v .
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
@
|
Percent 100
|
@v L \ S R [ S U P V - 0 - 0 - - T T 4 ~
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|
@
|
|
@ 4 L P ] u & % W $ % ( % % V , a
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CORGROUP $$CLK_RISC_BufferRising
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a
|
Percent 100
|
& % % W $ % ( %
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( % % V 0 } } }}R L A r i a l R R R R R S U> Vj Wd Wt W W Y2 [ [ ^0 `z c eh g jb l2 m n n@ nP n` n n n n n o( oR ob or o o o p p p p0 p@ pz p p p p q qB ql q q q r r> rh r % ( % R L A r i a l xP xz x x x y" yL yv z zZ z z {$ {x { { { | |J |t | | | } }F }p } } } ~ ~B ~l ~ ~ ~ ( \ x z J . t ( F n ( ^ ` % T p B
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|
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|
|
@ B L X A C C E S S - 0 0 - - - T d g
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CORGROUP $$CLK_RISC_BufferFalling
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|
Percent 100
|
@ L T T Y P E ) - - - & % W $
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|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
L ` P R O T E C T I O N - 0 4 ) - 0 ) 4 0 T
& 2
|
Percent 100
|
@
|
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|
@
|
|
L ` A T T R I B U T E S - ) ) 0 - 0 ) - - & % W $ \ e % ( % % V , f f R L
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
A r i a l e c i f i c l i c e n s e a g r e e m e n t a n t i n g y o u a d d i t i o n a l r i g h t s , y o u r u s e o f t h i s s o f t w a r e i s l i m i e d t o y o u r w o r k s t a t i o n f o r y o u r s % ( % R L
|
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|
|
|
A r i a l
|
CORGROUP $$CLK_RISC_BufferFalling
|
I f y o u h a v e a n y q u e s t i o c o n c e r n i n g y o u r r i g h t s y o u s h o u l d r e v i e w t h e l i c e n s e a g r e e m e n t o u r e c e i v e d w i t h t h e s o f t w a r e o e % T
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|
Percent 100
|
@
|
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|
@ L ` D M M U P A G E 0 7 7 0 - - 4 - T l Q L $
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|
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|
CORGROUP $$CLK_RISC_BufferRisingFalling
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@Q L L X F A U L T / ) - 0 % ) T ?
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Percent 100
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|
!
|
@ L ` E X C E P T I O N o - + 0 - - ) 4 0 & % W ( % ( % % V 9
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|
|
CORGROUP $$CLK_RISC_BufferRising
|
. - C Arial ? ? ?? ? ? ? - 2
|
Percent 100
|
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|
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|
! SET 1 - - ) % C Arial ?????? ????? ? ????? ? ?? - 2
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|
b ... C Arial ????????????????????????? - 2
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CORGROUP $$CLK_RISC_BufferFalling
|
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|
Percent 100
|
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DTLB_SETS-1 - - $ :
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|
[ VPN 0 - - 0 % 2
|
|
VPN 1 - - 0 % C Arial ????????????????????????? - 2
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
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|
Percent 100
|
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VPN ! ! $ 2
|
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|
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|
EFFECTIVE ADDRESS(- ) ) - 0 ( - - - 0 0 0 - - - -
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CORGROUP $$CLK_RISC_BufferRising
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|
Percent 100
|
C Arial ranting you additional ri -
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|
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|
|
CORGROUP $$CLK_RISC_BufferFalling
|
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Percent 100
|
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|
"System c pXρ / - - C Arial ????4??????????????????? - 2
|
|
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|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
] PPN 1 - - 0 % - 2
|
Percent 100
|
... C Arial ????????????????????????? - 2
|
!
|
PPN DTLB_SETS-2 - - 0 0 ) % - % - - ) - % 2
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|
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CORGROUP $$CLK_RISC_BufferRising
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Percent 100
|
k TLB SET ) % - - - ) 2
|
!
|
INDEX 0 0 - + - %
|
|
X
|
CORGROUP $$CLK_RISC_BufferFalling
|
- - - $ N
|
Percent 100
|
N=
|
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|
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|
|
X COMP0 4 7 - - % h - - - $ ^}^^ - - %
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|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
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|
Percent 100
|
C
|
!
|
|
|
Arial - - - - 2
|
CORGROUP $$clk_risc_BufferRising
|
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|
Percent 100
|
2
|
!
|
31% % 2 Arial - 2
|
|
log ! Arial - 2
|
CORGROUP $$clk_risc_BufferFalling
|
2 2 Arial ? ??? ???????? ???? ??? ? -
|
Percent 100
|
-
|
!
|
2
|
|
(DTLB_SETS)+13 $ ! ! ! ! - C Arial ????????????????????????? -
|
CORGROUP $$clk_risc_BufferRisingFalling
|
2
|
Percent 100
|
I 13% % - 2
|
!
|
0% S Arial ???????????????????????? - 2
|
|
WAY 0 O 9 8 . - % - - - $ - C
|
CORGROUP $$clk_risc_BufferRising
|
|
Percent 100
|
Arial ????????????????????????? - 2
|
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|
DTLB MISS0 ) % - 7 - - 2
|
|
l EXCEPTION- + 0 - - ) 4 0 - - C Arial ??a?????????????????????? -
|
CORGROUP $$clk_risc_BufferFalling
|
2
|
Percent 100
|
12% % - % - - - $ - - % - - - %
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|
!
|
|
|
- - % - - - $ -
|
CORGROUP $$clk_risc_BufferRisingFalling
|
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|
Percent 100
|
|
!
|
Arial re distributed by one of - 2
|
|
j PADDR[31:13]- - 0 0 0 % % % % -
|
CORGROUP $$clk_risc_BufferRising
|
% L> - - - % >* - - - $ !! ! C Arial ent you received with the - - - 2
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Percent 100
|
~ PAGE OFFSET - - 4 - 4 ) ) - - ) 2
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!
|
F PADDR[12:0] - - 0 0 0 % % % - 2 Arial alNormalerty of Monotype - ! Arial r together with software - - 2 Arial onal rights, your use of - 2
|
|
|
CORGROUP $$clk_risc_BufferFalling
|
log ! Arial ????????????????????????? - 2
|
Percent 100
|
F
|
!
|
2 2 Arial ????????????????????????? -
|
|
2
|
CORGROUP $$clk_risc_BufferRisingFalling
|
X
|
Percent 100
|
(DTLB_SETS)+12 $ ! ! ! ! - % - - - $ z b
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|
D & A attributes0 - - % % % % " - - $ a
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|
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CLOCK clk_risc
|
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|
PERIODE 1
|
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DUTY 50
|
|
OFFSETE 0
|
|
INITIAL LOW
|
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|
MAXUNCERTRISE 0
|
9 ` - - % 9 - - - - $ mMMmmM - C Arial f curves is softer and fu - 2
|
MAXUNCERTFALL 0
|
v SR[SUPV - 0 - 0 - - 2
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MINUNCERTRISE 0
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MINUNCERTFALL 0
|
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JRISEE 0
|
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|
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|
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|
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|
ENDGRID -1
|
Hz
|
DIRECTION input
|
PROTECTION- 0 4 ) - 0 ) 4 0 2
|
MASTERCLOCK None
|
|
Clock Unclocked
|
ATTRIBUTES- ) ) 0 - 0 ) - - - % e - - - $ f C
|
EdgeLevel neg
|
|
Set Not Used
|
Arial ecific license agreement - - C
|
Clear Not Used
|
|
ClockEnable Not Used
|
Arial
|
ActiveLowSetClear True
|
If you have any questio - 2
|
AsyncSetClear True
|
DMMU PAGE0 7 7 0 - - 4 - 2
|
ActiveLowClockEnable True
|
LQ FAULT ) - 0 % ) 2
|
VhdlType std_logic
|
EXCEPTION- + 0 - - ) 4 0 -
|
VerilogType wire
|
% - - - v $9
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SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
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O b j I n f o 2 6 P V i s i o D o c u m e n t N V i s i o I n f o r m a t i o n " 5 7 Q S u m m a r y I n f o r m a t i o n ( 8 9 F ՜. +,D ՜. +," @ H P \ h t
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StateEquation Hex(Inc(0,2,5))
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N TH GM R l ! fff MMM 333 $
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HighVoltageThreshold 5
|
$
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LowVoltageThreshold 0
|
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|
SIGNAL dbg_wp_o[11]
|
<h b
261
|
DIRECTION output
|
g,s724?`b?M1^%Y? r? 91M1E; 6==5(2?;zrA
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RADIX hex
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ENDGRID -1
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H<(
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Clock Unclocked
|
U~EC '
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EdgeLevel neg
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AsyncSetClear True
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2r q ?@I k?$%?
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ActiveLowClockEnable True
|
@ "V *5L -b r/ ^vԜv"(2u &."q28iv"uh 9Bd &< O/M {
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VhdlType std_logic
|
#145 `Vis_SBl.chm!#22474 `7Copyright 1999 @io Corporation. All $AUd3 CE \^ 4
|
VerilogType wire
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*L 1$b 24R(^[w[D ZQi a59 93O ' 2"q?/g;2GHls ' $ ! Oya GEӧF t # B 7 B
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SystemCType sc_logic
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ahj TqUIߴ< @%@??I?*? Q c `2 @ ? qu `&u o <Q w! w! ` Connector
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
`W "
|
StateEquation Hex(Inc(0,2,5))
|
*eU0'$P !a ! J6$ !"#$%&$()*+,-.
|
HighVoltageThreshold 5
|
/
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LowVoltageThreshold 0
|
̿
|
SignalActionType 0
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|
MSB 0
|
E#UT mǟٟ"/W{
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
ض.@R !Q,l4Gdì?[m? 9A|0T ůׯ. +=OsZ ɿb ,>Pb i/ύ/4/ /Q ?;?@_?|?ߠ5;ۿVPN 0
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DrawAnalog 0
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11
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BooleanEquation
|
F...G2DTLB_SETS-1=H*'" H.{U8kU oB EOJ1G]5 1KU7R G8cRZ!z[儻U?a `kIP_b_
1
_fa{ *]59K]o@[vkvHZ~Tia ' 9 K o v // ,/>/P/?%x/?/#z// k ?(?L? R${r?x?
|
NegTolerance 0
|
ץJ;P21O<1!G2R+GooYOpoOOOO U)ƿ ؿOOH_oo~_ ______Zl o2oDd^aESlEէ poognӤoon\"9N'@@|=%$
~(u'v1C`U03w.1Zړ̓ pT|^a(: L^p0mʏ u);M _q!|*џ |w%? ;/ 1N ǯ r x ;S
|
PosTolerance 0
|
߀I[/ 0 )q-AX`$/6,_< ^a SaOSlSS|ߎߔgS
|
UserSpecifiedSizeRatio 1
|
"4FXj42FuS E;1(: L^ (_6U_ +__-?Q c 8 :;G;H3o' _ ^oo = -8 J S_Ay1_cE7? +um9Pa$!IE4@E{CEu9p\8"/{ 6:u PkRAu0`u^`Agӂu
ہ YA1 nhDsN%rtږR@ p5%E` @z3Z`r5"&5"
|
VerilogCode
|
җhSYV2r
?@I?V?ČBu@`m@CDuy0`
|
VHDLCode
|
ףp=+
|
PROPS!
|
W8&H9-kx0 Qe#"(
H @`0 AO{-pOTIKE AISB_8OOZ Yo|D X nYLRؿ$ϸWYL˧cR eϫ_n Ajo]5q5//H9*
|
E0 0 1750 1750 1 0 DR 0
|
Սv4U
W0ɐ=5"] Aa5ooβ GYLp !DOa 14 d4V$6HZloq:?=I)⨅4ӏ \* F4@ GV I; ð"*<` ?_A=/mǫ߀ؠaܯ $NAT `rC5E ϱ
|
E1 1 3750 3750 1 0 DR 0
|
1DiI wI''??{/')O;O uC6ԹqM, +sq EOi \"9N'
|
E2 0 4750 4750 1 0 DR 0
|
_ _._@_R_R'b d ԀU6T U__;@u
Qfp@US`ܦ jjZ e$@/@ )pup5 fp@z3Q/5G֧Dif!ZoU@OOi糘oo` F]tE ƏouId"04FXj +~RQT ,߾OݢY5H o 1ˑ#5G`k0 ;jD{8\ Utp߉TLB SET? INDEXROÕl? oa7 p? ]1s]Y#֒V }-b ŨvF@"Z1)ŨY RRFʢŢo[0mSRfiT #q27F XP X~8ŵϜ
\0 qqI}SY1H߾*"$ @J+ /C8! HCSZœ%5|Ŗq]_U## U
|
!
|
UԓUVρ S F(~eNBD ŵ
|
|
/b8!LQZG#27 q@?OFcD?ǐup!%H}uԀ n9Hqf* ߆/ߪ&-6 ~_]<__4g hm^$o_Hmq_|ooT߁ŵ:-0
|
SIGNAL dbg_bp_o
|
-1
|
DIRECTION output
|
v... w-D)_-S-1 iDˑq |ߐgN9Qo8m:' D r>LƠ ]tI
|
RADIX hex
|
{rB{6Uw /AadOs ڛ?]a`kȤo8
% Cqˑ/
5AQ? ғ;e5QS55Q3aZ,zuŵ9E:?@E_$Q * ?Ql_U^S T{n9D?ҟqe__*_<_NX [Y^qo³)e IŲiŋe q6qHZlUo8*'wn ᖉ_U߄phϲhħĨUfϿ4 as߈jejq COMP BeCɟg2?V?h?$TP-DT!/ASe@w?
O0 "
41Z2DyE
/ /0/B/T/ f/x/o//* '1CUgy@DsN@3
|
GRID 0 1 0 1 0 16711680 0 0
|
]#5GYk}!$I6/@'" )Vp%7 C@z3A2?>, 6
|
ENDGRID -1
|
*'ՄAߚ, mןhg RQ INV/q 8o/'/D)ˏPt,Ӆ/ /// ??$?6?H?Z?l?~? /Kƫ?U
|
Clock Unclocked
|
^A 7EO &OZKJOK= ZGOOOO _!v+SdG2 q?涓lt?$O`a_! ;_M___q_____ _pc HIT 0 ao߯TPrewqD%rt?@|=I%%u\
?P
a+τ;BD9ju!lt rL
|
EdgeLevel neg
|
AN | brT W n e @ gcW /{ 3/P/ t/ հ31 Io\n U>qNt1Ug\"9NW@
1CU^@O8F
|
Set Not Used
|
@ ODs1 2 D /// / M6_&/ _ :__:/!o^/_Wo@/{o_o/log2(DTLB_SETS)+12 i-^X0' 2UrB ~rVL{~ܧxCpj5B
9Ey^XGHm 7 !3 Q?D/İ ? `,k!);b^X^XJ
? ?1?C?U?g?y????@DsN
????O #Og $OPQOcOuO OOOOOOO_ _)_;_M___q_oo o__Boƿo oϮomooV¿oϥ !3x3 ?Qcu M _qˏGY ,C Se`rVş5' (
1+J<
|
Clear Not Used
|
z q )/M/ q/ 7U,==, [k}h˟ݐ)! '#5G EAT.F}
1 C /// _92_ / h_:__4/_X& _D_/o'_2oDo%|*
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
k0Grp J\+ؐdã>7 @@ٓ|{P-DT!]k-u{`u`b uq
fP+
Kp,2I{H
v _eO/? )p> @z3 {%'zz//A%{m'9-w/A v]/"/GSչ Qbi{ӏBبXd 6G 2,rq?G?Y6KVb?Ty ](Alǿ{ύіU *gy ];OihDTLB MISS
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
EXCE_PTIONGr% );M_qu! { $ 6 H Z ܑA1>fI RXsRW>fg=gC$on>fgmMgoA ///)P?ذ4?F??q???? ????>OO/$OWO 軘B&OO *v́ ȏڏOO__%_7_t[:Fd^v______`__oƟ؟0Fe6WoHU(~lf677d?>6$G=7.O BTx?Ou 0BTf,-ύb
|
VhdlType std_logic
|
(_ ) //= ʱ3 Wu/'})!.:P-DT!///?? ,?>?P?b?ܝ
|
VerilogType wire
|
avd?n`| @5@v w4 v S w]dOvOOO O_*_<_N_`_r__ __
|
SystemCType sc_logic
|
hjaq q -?߯9ٓdv ߚ߬߾q ? -q'X=*aj|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
﨏 0Of _Tq @q !3W&%/r տߥ QM!XACCESS TYPE ? Q c u . o/oAo /2/`D/V/h/o'g5.h?. o "4FXj|y%@@"'@@54 ' \( f >Ϸ$ ŀaɏ Ot/!_ oߥQu//_ [PROTECTION
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
ATTRIBUTES/"4 FXj|nXo "4FXj|@wX1yV
|
LowVoltageThreshold 0
|
M6AH
|
SignalActionType 0
|
cpq!}i^W r@'@z3A
|
MSB 0
|
b^_p^VWW2_^ VW]Wo + "V|f /o//A/S/e/ w///////*H ?FaaDMMU PAGE
|
LSB 0
|
|
isFallingEdgeSensitive False
|
FAULT EXCEPC1_2`? r???x93шS?"/{ @@ F ruكGOYOkO}OO OOOOO 0ĉts@
2% eAy[%:oLo8 t,>P tَqK1$6HZl~@D/sN
|
isRisingEdgeSensitive False
|
΄RKQ_,> Pbt
ʱ s _}@
XRpBUt_ߙ_Ys r2 0se1o loᯐgʱ2r2 -? QcuȖ2Y?ݷ1"P@ǧ9ᱷ5047 4PUHSu h͑ئ v$?P;t*ɀ`@ҠC3?'ԙFᝪ^!Bq~2rb_?@IϾE
S]݄G&G5/ PTŴXjͣi
ۨ
|
DrawAnalog 0
|
`ӡuۯ95ؕ
|
BooleanEquation
|
V $gW;%o7nVlg@8mWvof/
˯ /.?8Jd?n?@fyNxsTVADDR[31:13]
|
NegTolerance 0
|
*B Z'O9DZ74FXj|'vg@@|=i$UFUjT3Xp+?@΄րRЂ)o$@ p.ՙ9(NbR
|
PosTolerance 0
|
pu v3O /0/B/T/ ox(ϒ//)Ppe/Tp /p$9CrO M?TqDV?q 1y;߈FO ?3ΗV56O HOZON~OO迴OO~ H _-_?_Q_c_u___ _\ Y_օ d Bd 2g3q onoM -?cuϙi~!}GE OFFSET
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
~s12:0] UF U #$%U&(+-U.01235 Ul4,< @%@ F _]D ;C-_TC 7 AU2@lB D7 JR H<(
|
VHDLCode
|
U2}EB
R UlL ( 4 LD @ ?% ) R ) t E ?U$
|
PROPS!
|
4( U1( UO"D&aU=QJf )h" Ty+Uv' _ Ʌ &aQ-
|
E0 0 2750 2750 1 0 DR 0
|
- H* 9( TYg EQ /, Guide TheDoc Page-1 Gesture Format Block Normal Visio 10 Block Shadow Visio 12 Block Highlt Visio 11 Connector Visio 90 Dot Connector Connector Arrow Visio 00 Visio 01 Visio 02 Visio 03 Visio 13 Visio 20 Visio 21 Visio 22 Visio 23 Visio 50 Visio 51 Visio 52 Visio 53 Visio 70 Visio 80 Box Dynamic connector.8 Box.3 Box.4 Box.5 Dynamic conn?ector Dynamic connector.10 Box.2 Box.24 Box.33 Dynamic connector.39 Dynamic connector.50 Dynamic connector.52 Dynamic connector.9 Dynamic connector.45 Box.13 _ 63T AF
|
E1 1 4750 4750 If Enabled 1 0 DR 0
|
Ed K L V-
|
!
|
\R; a Gt; Uy ; U
; c
|
|
; Uu
|
SIGNAL dbg_ewt_i
|
; Q
|
DIRECTION input
|
; }u
|
RADIX hex
|
U u
|
GRID 0 1 0 1 0 16711680 0 0
|
4 UL GW Ud %x| 2 ? L Y f s $<Tl̑^c/ U
H I A[* [* { #I* { -I*,J{ 7I { RI U Ul{ q[*|{ UuI*{ [*{ [*{ I 0̪{ [*{ !: *$S0[*DS0*dS0Z*S0I8)S0) 0'S0>0^'ES0B00(! 0Q xfB! :! !!"#%&'()J*+!-U./01245 UjU
|
ENDGRID -1
|
U
UUU Ul4,< @%@ K UC-\3 L A Ul4, \B SL
|
Clock Unclocked
|
AJ-T3 ]7 A _ *<N@D
|
EdgeLevel neg
|
L IRVg _q 6uH<(
|
Set Not Used
|
H<(
|
Clear Not Used
|
_ *<NED L
RVg q k{ z
|
ClockEnable Not Used
|
* g"4pFX (4
@(?a@2y
|
ActiveLowSetClear True
|
JO :]R P
|
AsyncSetClear True
|
4du &S !B T ?Q
>C F C m `s Ĭ Hfk$O f'}2E U>ND U)tU1=%` 2, MI XV
|
ActiveLowClockEnable True
|
O? LtDl#+ 5 C=S8MJ! AY
@ Oh +'0 @ H h t Valued Sony Customer G (E x w
|
VhdlType std_logic
|
w
|
VerilogType wire
|
EMF E X V I S I O D r a w i n g M D ? ? l ( @ ( ʦ D o c u m e n t S u m m a r y I n f o r m a t i o n 8 R _ 1 0 4 8 0 2 5 9 1 1 J = F ) 9 O l e
|
SystemCType sc_logic
|
Z P R I N T : < l _VPID_PREVIEWS @ _PID_LINKBASE A
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
F Microsoft Visio Drawing VISIO 6.0 Shapes Visio.Drawing.6 9q ՜. +,D ՜. +, UMZ c@mUBE,E"dHM
|
StateEquation Hex(Inc(0,2,5))
|
m|7﮻Ks̜sf~ )`Ri1zcْJQ"*6[9m)2sUo!yT
Xjf!T-^DV:{1YtNըJWЈhF=ݟEa:cYΰلi[W . ԺbؔB!c>erq=F|7*p-g0]!c䡄X%&.q\T[qKÐdj;1Nۃ)awEֻ) `#˒nɕ2CWܪd,|A wjNI6gs\UeFMG7Ŋ~(?5E VQu ~x E,l29oܲ\s7X-E}i'D?q5eUk87=ц}84)w~]%ֻ(eMJzwv´wv{i\2Nj F}V<{F4WdٻVF\vܑ#zp#*?#֪LN[f"óLs5n{##jt =߯9;ms^ca~{~$9IIO Nvs}J%bq^}f'h e+&mxYeL:ɗ2t\%2y*0S/qEpғ'өI/ @QX Q
|
HighVoltageThreshold 5
|
_NRb)l&XZoBI< pLjo"=
'[LNz<&'cqAO=ZUm|
|
LowVoltageThreshold 0
|
9)4ȗ%cه#v>dCxյsC_oԻM0 ^?^+ 'd 'N!A"Dd @P C zqB#<@yʃ 3@m磶wr>ѸEzޛ3iLl^y?Ǎ|KROI @'}IzL%x$U5Zi
|
SignalActionType 0
|
|
MSB 0
|
C A ? " 2 &]_)%ݢ4 a `! &]_)%ݢ4L \ k x2F J* m x\]h\>sv]E' iR*nH+)l܍7F6:Y'yi!
`ȃ5% y*i
|
LSB 0
|
?\\0$Vϙ?i̝;93> >x` AFR}0@gT 2 cy09% *9KX6tHnX` g GGp^}-lH_FV<)*MC1+:hg: L 7h|y]ig.ϟb-" ) ~5jyt?0q8x*SÓv FWznp'kXHK{h[kH_9Nꃈ@: g`{c &9;e'A0&5HdN:s[}>mp~ I$oaɈn|)ma\C~w7ؽm? ςm[b#Xvl| ЀE>z S:vU~t@u"ph]
|
isFallingEdgeSensitive False
|
-
|
isRisingEdgeSensitive False
|
^C].TeN>g? \FsFҟ+N`ũ&8eh.Fsqvnodjdnl|
|
DrawAnalog 0
|
UeI>qu?*?(|#7ْ|2&Q -ς|
|
BooleanEquation
|
|3C|3/q e ;茑U #YG:⛠U+kZ = "p\0pܔ8
|
NegTolerance 0
|
Ǘ1OtฐDž,~+lG Ы $x}COiU_#o̪Mg1V]gP{ E`3ZX]y
|
PosTolerance 0
|
+<v}Ę\)Ywg`X%5 ,q\$iX ψc/Ǟccf5<2扚n| .0F[@ =}ۚOX>7OPeI>=]sAk9t1\zsAi} |U/Z|2*|_ku7¤E?5 ~t^D{XmPC_ m#&bOTY|[Mη)LGңH?d4筲D8 += AEmmFWmKLS`MA;tS"OCF5in@1^1
|
UserSpecifiedSizeRatio 1
|
_z^0=X|P_d,bnsA@ xu@XKݏ *K[/
bla\#,LMpjba6Pl~?~29_ V||<}|ak#|K5C+cLTeV?' jOx 0'ai| _DqBۃbajSYc? }Tm>db/1d >gC/:9/c2_cVSܰ{
8U}R~P3*K
sSYgST7D>An&R4w!~$Wf7#}Kvks%V7y* /ē\!d'M>Thz ]vYQm}o_ @!-ά|6_ܹmEyF`s?J;eh+v؆>tz8סCp+-Zm,oBn:f
]jǐ#vELF65S=zJ;K;pظg?4j&i{vfr}˭a]g1JM\@ְe
|
VerilogCode
|
J}QGuGT҂&ivIV$iLV? B>{PKNqn٤/Jiw[n`H | Ѥ.B3ӋH7/^&ovy=C^_w\1zd[οfܝ5+m- IoLzYG(jlxF+jޯse|Cs oe9[j-XK/nrᒦ=d..h{lqKj
;r/8FSJW6]ʄm;p5Q$ج/vt__z龾m}+jIծ] :oإa֏R`b:j>05QH승Z쵨x { }d;5ѹ )zA<՛8L MX&ʬ51945 Ini#doϱko:5lK
##B4,F 8ШY1B ܹg϶H&Qc\ M75x 7OBcQ!9fSƨz(tEazOϥ~mq Zz@TP-q-zEz'} D y K _ R e f 5 1 1 2 0 8 7 3 0 2
D d M
\ J
|
VHDLCode
|
|
PROPS!
|
C A ? " 2 DZ~"rcHW=i p n `!h DZ~"rcHW=ij: \ k x2F J* 6 xZ}TW?y3;;0[V llI |eŪacwRE!jBJ II Q&61~TmM,VJiA~}{3N={ι{%ۯ#j߅4/6Wp jC?Y6Tjv.iEx~TUͺ U\lFL:Om1_"BAgqHf?L1 B
0c_ʎ[,ZoiSh
\&suJ5B7́g8#ˍfAPq;=H$3:y9(dG,yg >s;*w E7}%x*/hǃ)^ø'=ǫö.3a=A)4>
|
E0 0 1250 1250 1 0 DR 0
|
x
֥^4e!:A
|
E1 1 3750 3750 1 0 DR 0
|
`G3)MY:_V!:cN_LY,03͘+ُJ|t ವ?EC
|
E2 0 4750 4750 1 0 DR 0
|
Xr+w/"Ͱ2 ՏJr ], p*g>6eQr+L #uH\
|
!
|
wBx[\.yΩ
k)Y5|< 4;0Znsu |wukC72o
Wxj/Cn
.AxP:2&K-z=h,*i!h{zYB `wXdaVL\L/' [ZFsXlr|U4ءrxΈMX^AyB=WBr}![u]"|lrH! 'K6Za G0M> ̔5E`}$ Kyr ͚k/
|
|
oL roO@<)4_?LT{:@Yp嫝:xǮg_ gN3eQsmGvp JFǦ6jx=4/ įP W o~!;|/]8|c ) V`[C}5j$g4 Nߩwi <'gP5[D8sK ~. =tT?*8MWlіHl>|Fӟ}pzY6y`` j
\\2f!B_
|
MARKER MARK10
|
sc1uW`Q{W@=r'#|ϫf8|XE ڜm7i{EC XLY/6 .ډm k9MU\}B#K>52 $Wۻ́<{BݿϔE-W"9>щZd?qIˈ,ӕTgs#H%j$BY͑SջE^{!})K+i D]пCggi~Ixtc'Ms5>ϞNY9ew~i Zd~|x]^ (?6eQ^aqd]lks _ O l?}"U#Ff|=F)X!(j
v{c<) yhMYd k2 BK;֔sz]QTBbo;7UK: t[Q?vynm]h`Sr>~L5w @g2Ң:.mQ16A7JiaWe[(Q ͖:?:10926ꀧRr*]6Y :ktdrrOCD vGqo* AO'wیj)h
|
ATTACH dbg_wp_o[11] NULL S1
|
$.w2'Z@9~.RU%R:xzfL^r7wS\ ~;Ro}s_;o䲴XٍK(EVF- }?ߞuFDx7 % Db;wgb R[.c3<7YRbr81'b`MɪZ\f{7\S)IN5opdqǔ֑<
|
TIME 1610.903040
|
8zT1wQ;+N96k,& nFJ5pH
|
RELATIVETIME 0.000000
|
Q~ܗZ!ҺE<"mXjuH Zh>۹J%ԳzJsfNwJ锊3M-=_ϘoNONCoN7oN+N NoN*Wld;h?:dΡ;AY!xv:G})i5A[NiqH8p`dgqh6 #]F}R˨b4🥘|`Dy3WAAZ
xat 5wic7u
N PSxebIN=pӼbٚ3Oc3ݽY a8]97;*Tf${lҝu?L} D y K _ R e f 5 1 2 0 9 8 4 9 1 2 D d Z.P= J
|
DISPLAYAS 5
|
|
MARKERTYPE Timebreak(Curved)
|
C A ? " 2 y1 2mBFYX_@ U1 { `!M1 2mBFYX_@V F r p 1 x} xUN!("K@4I$醀8; "8 &. 2n({k9>Nw>?yNnV[Tݺ(!,G /~
z{^"NoagbąS[k^qJ^hyNU?> 28D!خHo}E6$ =EpJQ$JEv+V,?B&<ST [_snO[dK `?Zly*7WSd6m6K?_Ѷc K~ n[ж2OoKSBjOEƛ:E__X<ӅX!~Bx_w{\mN'q(?i5amv
=M. ]3hUѢnjHHcCaksO0 V1NmZT2 cʭbۆKVn,<7ԽQ?,/u-|C>{B~-d + ` Uͷ 2#ᐿ@
C((c z=d䯐g! %6VH#BȁLӪ\*wB c 3iG#QՅB(AV-|طB _zo'nj h!.ѳBF| o\(q||PZv PZ J
|
WHILERETURN
|
:Hǹ^ڡۣG(7nBtfH/ܜ ! iv.H#xt+h(WhR Z + u2n
Df}) ! _>$k! C76 +C/@y'84FG@Gʝ;((hۅ@]:~]뻐n 1u<z?q
|
REPEATNUMBER
|
^P= %v_6*ABcգ- Uu<zmÐ2e:Q(ӠC M L1Գ0GG~ʣG'@Mf۟f"Y#FƱsZ@e.2yY( `[ pBBBY롲.E]. +
|
SNAPTO 0
|
J{%[C( ?.U} hUBcG [!fu뿄
zlSd;tawwBC ?]w {/ E˗V/]_ v}
}{/} =߇ݏc#7Qozvq q @`7Pz DZ' D B~ Bq:mt q{6t?B{v;enCe3 #*-q_|D #Q'<SCDžj cB
[/)Ԩۄ}A1H֭B'
|
COMPRESSTIME 0.000000
|
5v}xS ?j"Ϋ#$2PuZ9& P yOg;ڠ>+F}jBqm^_ EMmep/Q6 V+"[ FB>jBME R 5 Ϳ__ >Mhd l|D GTC#B/^#P(4A!jgP w uXҺz{Kw@ 7Z2* + 2j
b AYʗAd = =jE =+
|
COMMENT aaa
|
XnՅx]h/tr|&Tw-4;Bk6p!¾̧0@*tNk#/@ҋr-ee2jO4c> ;|252~|Ր 'Y-V<}_gϬ,uDžD85 tIAON| ԧOAWGհ : 64q
6 AĿƱ&[&@7=MnoFzvliy[ֺlEu l]nm;(gaϢ,{=`;n_B>.U9ȷ8! ]Λ\B
: W-;'`;vާeIDΔ6 Xj ?\돋r1p)@cxׅ\!~t.\ sO ƏǸ`#0f rd 0N
t |>g;a̖) c|~"BK 1+_c῎X>c1/1.Q)|2qeckr!} )7ƞ L@ܕ&b,9IOxrI&ǽc}+_X}&4 ; y e{
_p6=\>1>
|
!
|
=; -Da0._]?id%ʽ?vXv]
g5|ը5u`
;Y[6\1 {
|
|
~zoD:smB>|oF[nߌ'z qUMUu}{;(A B C7;wQw }z ~h?@| H88D
|
MARKER MARK20
|
~ yyv#IǪPNS))q
|
ATTACH dbg_bp_o NULL S2
|
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( % R L T i m e s N e w R o m a n (R 9 Times New Roman Times New Roman % T ) X A A A ) L ` D V R 0 / D C R 0 & % % V 0 6 X X X 6 6 X % ( %
( % R L T i m e s N e w R o m a n % T J y b A A J L ` D V R 7 / D C R 7 & % W $ . p p . % ( & % % W $ > > % ( & % % W $ W W % ( & % % W $ > W > > >W % ( & % % V 0 . . . % ( & % % V 0 . O . OO . . % ( & % % V 0 ( ( ( % ( % R L T i m e s N e w R o m a n ,UE ^? T? > % T X A A L P W P %
( R L T i m e s N e w R o m a n V I S I O D r a n g
|
!
|
d & % % V 0 7 7 7 7 % % T T
|
|
A A
|
CORGROUP $$CLK_I_BufferFalling
|
L P / %
( %
( R L T i m e s N e w R o m a n % T ` Q ~ 7 A AQ L T C P U % T X A A L P B P %
( & % W $ % ( %
( %
( % R L T i m e s N e w R o m a n % T / A A L I n s t r u c t i o n C a c h e % T 6 A A6 L d B r e a k p o i n t s
|
Percent 100
|
|
!
|
|
|
& % W $ & } & } % ( % % V , { { { { & % % V 0 6 9 X X 9X 96 6 X % ( %
( % R L T i m e s N e w R o m a n % T ` J b A A J L T D M R & % W $ W W % ( %
( % R L T i m e s N e w R o m a n D % T 6 A A6 L d W a t c h p o i n t s
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
%
( & % W $ & } & } % ( % % V , { { { { & % % W $ x x x x % ( & % % W $ x x % ( & % % W $ > > % ( & % % W $ % ( % R L T i m e s N e w R o m a n % T x A A L \ M a t c h 0 %
( R L T i m e s N e w R o m a n h
% T x A A L \ M a t c h 7 & % % V 0 q q q q % ( % R L T i m e s N e w R o m a n % T T { A A{ L P ? %
( & % % V 0 % ( % R L T i m e s N e w R o m a n % T T A A L P ? %
( & % W $ % ( & % % V 0 ` 4 V `VV4`4`V% ( % R L T i m e s N e w R o m a n '
x x 9 # (R 9 Times New Roman Times New Roman % T ` | I a A A| I L T D S R x %
( & % % V 0 4 9 V V9V944V% ( %
( % R L T i m e s N e w R o m a n # (R 9 Times New Roman Times New Roman x % T ` I a A A I L T D R R & % % V 0 H 4 V HVV4H4HV% ( %
( % R L T i m e s N e w R o m a n 9 Times N oman Times New Roman '
x x 9 % T ` f I a A Af I L T D I R %
( ՜. +,D ՜. +, @ H P \ h t
Pages Page-1 8 _VPID_ALTERNATENAMES _VPID_PREVIEWS _PID_LINKBASE A Yrp^ JsZrNȵq"O8q"8r,' !jWl- ma!=
|
CORGROUP $$CLK_I_BufferRising
|
xk
Sivʃ Sh&u(O&U8P0R孨sz ^Vп0/[C:%1y|Y/Q<`>2yIyxK˩d*)}_?4~ L~iF亚Fc_1ViSp#p
~xͫ4TӊoADrfp'NE)V *ѣg(bZ=l9~?t\ǁ_yUcvc6UnY V}bh3(Xh~W"*# i#H';B`8 +.2#mXPexթ: u&:U`>=zŕ<" hjsOz7 b& [O`WL#!K #I* D )!:2aEL]g-J[Ov2^{dk\qM ~!$wC,OB)Ȓ ])Fm\ΌM0QVxj st>( e?
hiGCi7,8LOVQGqԑc k[ЋFeܻI
ص8^;oD"LN?Vn'%Kp"4l$ʀz` ).C)Dn0DhzbO?x fi~- o a:Opp"\v>6p= 7a`7]~L+~Ey3 % _'h 25 r##CB=u (VG}#R HC ɑȼC x3e;^P}
|
Percent 100
|
}1W] m&tfan1"<\\@> >FD`=6 "¦%D|:p?-
|
!
|
|
|
9|."<& =Oo ˝С_Dxr > 3"CORGROUP $$CLK_I_BufferFalling
|
9 7qr}0^!
|
Percent 100
|
'\utum-JR9bRIrB= L8݉ESE?n(\V4 r/aRZzrSBEKZiFQ.(KFdaawpU" vXܟu6g7r`O4P]|ZHU^ JE]9ɶHLNJ`8r,2c4|%0&d=G;=l=OQUCVT1X3JlO$su&X߁cSA}+gRfߪ[/ge UVzT4oҒ3V$cc(<=܅D-j
ڀQa2sf>wV:\GiLe]=Tds8 Sŏϡy.zn4 rnkf4~=~y$1XW "ˀ "0
|
!
|
\ <0;4ء G0 &¿C4xGQ\ \S)y?Ü3>xc9懟c9~.a^yl: sc&qiO0'=1
|
|
sٯ.0
|
CORGROUP $$CLK_I_BufferRisingFalling
|
sۯPWP RԮ'5/Y׳2uGM4A-0C<$ү? c8.q:kOkv uj;>5q罩v
|
Percent 100
|
f .3eSM3Q.t*qk:?3ff7%㳈̓ODH7qZkp ;O g6?YJ^>z7
|
!
|
Mt<~d\M CYf+3Ѷu{x&VLlmb^Wc쎟]ne\Z;s@ Ÿ"1mRϒ ~֮ 4n Ⴥ}X%琳87q1nџd4~JzfD%kN;;rf;Qɴ^W*5HE3,^_HfO~ vm\=MT~I5͓j<6 |f aA }_kQuS#.ؑ667YM3)͎侎 >=liF}vI扙{=}´J?D~'=j\j&yDUb+Myδ9K1A}lwқ;-9|Alkq}fO~Uk4etz,S~4g {I- VSOcnjQݨe6iR~=w}#[I#WL(N;{cѵNWӕw/8*g{&^wnC7\cvw
|
|
oUp̾;=My y c8./;}sī:Iz[ ?E z8/xv#'S Rz/xNW(; >^ @/=|ۻu_ox=Ϟ {Q;GC !Vui!Rv)[ :2YԳC
|
CORGROUP $$CLK_I_BufferRising
|
hmq*npD%vqw{;+jb ![4vVl_)e?kg39B'^i뜛Y)HʸCU"yW]X6 =<ZcJ8Mn֙%Yan +yB
+qJ\X_?x \':ֺ6 px#?^⺸~* ]Y=ـ
= ==V (gr\ :7C7C7f}#лG_, p.-kU/lo nmC h>m
|
Percent 100
|
&c b h0c 5Ȅ.^vLcazf[rim VL =K=xYO5BAm 9`0_8zfgv>D}^ 4.{]Tc 3sj)]g6ӕOSӌiqS4+;v'8W<]TOqgǭrE#:^J7J7ϤHfes<+ oxP){0JV1^'\Nr
|
!
|
&ⅳ`?m e몚{ZMӴг:k4Xݲ=}sL<" < q~Iq|7]%Em} 2? HFy)^t¢,Gy<*>&Qv/H?mdgH4}S,Drpag?b
|
|
C\w;/~1 r)S1i>FUia}n7IBs,O+WF&]3}9c:>2n~Wl{1Ž.`YF:M'Z5}ƚO"d%RRZNJ|S?W2 jf4j>QK%ӗ#RAB]O&*kNǸϜJ"C[RJe \d :KJq :Wߥ}lEĂ:1]r,l x⮲BƁ'&7Sǚ' k&2~F J(|-":Ί5;ʁ(iF,Df@kVh|w-{xځ6 bGĴ8>QGKs} jG G7 )罩^`gsE} Q:E߯vIqjźVk4L5ҿK3Ɠ.M+ A Z0 h'Bh G+S"/!ggD>ЫW# >o"?VOe t y.ܿ ]+toH\{5) {5CӍjZ+G-<ܬ4c[x:/LUj56~ףQ3P NM3ւ:6[X+?҂NsQۊREEhۊ?zKQ Aˋ pb9s/.
KC9< 4orX=b ,Cj4cf /Hx@ +P8ni@#4CNj~
|
CORGROUP $$CLK_I_BufferFalling
|
41u&JQ)HM jQjjvMD+si-u >dԾ0OQ柧zQ}Oht+y)$~BOJ<Ƅ 4IķL|%KIrn[~ۥJiw7̷- 6 }mAmxQ< P% kԪ튄`J~NqK ?FsJ['YC.? Q3*VG֥Γ;Ucj$֩͡H. i#CX~ }$1#Ϟ(t
|
Percent 100
|
Qފ YtmZi9Z ca έI+K>ݛ).({4x 8'v+?b _IW6О}ɸ;iZcSfics0A
|
!
|
ɶUBKZFԖPʲJW
,s\M+j UUZ
Sg0ٮ0)שW%e
߈-m\\ViU{Tr+/l7:dlc)n@נpk0&'Q_Cnb< S]fn&5i솻Ƀn,:03, u"@0$' ./8/+Z ;f<ǝ=jO$GʛISbYcfg^w3d8Նb1OةG ]Ck LLsfN3#b]ip'uyf6 ϓ ՞RַʜRnlhnU%me 6dݬIuM-
ӦڨZ1y߮θcM O?Lx ݳjDO;vPt>+>Q{O{:ʐvxr6A c&=²B A]=z|95j '6 /ul9ն#OQjweCQ k*Ϻ /\+b}A<^]Ce}j7(SnUCW#s.$Fb2F;d/[ړ|R+ѥo_巫XpA(Zor=1g^iv&zW-iH,>ӏͷLIZ 5˕eoXr8m_Aɽbgl5u<{ d|
|
|
Y4Y2"+Jw\>OdJKJ:r.KBqRԈw*6㴑F}ݬG7 M4P(eSث+&B |otu%W^Yw!]3j>jbyjځA$d-&TfL=-8SstSЋ h%1uk8hЄIꚛ+rxP(]v ,Ҧ9rQhUozޘ7җ\XZ[jTjJ?kğ=Xz={vBK5sO*#-3ٞj4ZhFy_#/eȳUfȴ.¬u&_2":g z~L(ʘusj)Ҙm}uN#%GAM& D d -P= J
|
CORGROUP $$CLK_I_BufferRisingFalling
|
$
|
Percent 100
|
C A
? " 2 % 楮\:g0_j % `!% 楮\:g0_jR ȶq p Q% x} xU$I?HH A- $$AvVyC C" :I'iMcw|쀣DE| KȌ~ u;8숳UJp|ns=s=8F\Ey >,HU=m@ }LȰ*@>'d!c 7> W;TVOo<"!Gl y> IH=0n Aޟķ7^ =xO =Xr \ +gϞM@Gb$ oq9}'Wʶ P,B>,wϕ4;AT7I%ɤ %
|
!
|
(Te+jH[
|
|
٩4er4%^Q_!,@Yp=\ONv (i7m%z
|
CORGROUP $$CLK_I_BufferRising
|
^/Q|@#{4ոs&VM2Ȗ)e\*Sd/S Jrݔj~s]R< \]Tӌ*۩ W !CʈP<
|
Percent 100
|
LjPc. 1fUe qiD70 p9y^"G$(D0!OAM`5BC#O5M O 6!Cj7&>"B×D%v x4""\:_ +z76}o! \h!"̛ 8A ?H x;Im96O3:F""9n|;dBЧۉ<\H Ðy"D u] / P [=X`MvE~?`jd93p>5L&?Vf=e99y! W
|
!
|
)W<_ұjm&O1>}m봝iD.5oOi[fY-_8MMhsaS6o"/zm z"ta;~ `/.nz
D@?_Oa/^n^^sNuD=DtWЩ׀u( x
z:6lЭuz\/ FهQaðP;- ;] C2+{ r nj_7̂oI٨
-PnU-<"
|
|
QZ"ږ %Y"fMĜ ":!16& oNf1?@ % _
|
CORGROUP $$CLK_I_BufferFalling
|
S"5qN" /D :(8 ۈxDmD Oċ=0x"?j%Mn =/E~NĒ L'h0 wKT+;9 8 -4hŷ̱zsLQQyeD5[$
Dl{ _ryv' kh8` Ba xnt" PV'puW' Ⱦn 0`?grCo / `/ r od" ~Ev>#b400ߚ5
|
Percent 100
|
]z> tiؠoOg@Wu8E lxv ?w1 69ص6q#ml@ {nD{ mef<|Qfhg[ We% x]n
ߊ6 i"nC܆lóm
EѾ^Z{Qv;`C! ,A ($뭚/N@WᯒL*JsT}=ΞUh#ክTÂ4J QȌt^LӲ8 ZA,
|
!
|
c:Z4mi5c q,iCfٿ!ό1O;Z[+zYFK觧-Rk`ojA{I" 3. 8ϮE{< },p,[qV
|t` d:q+p+v ;K!4'd?2=>q%|Y m%h_~v
|
|
uX
|
CORGROUP $$CLK_I_BufferRisingFalling
|
<\5~d vkրB7 Xa-_ ay q'O@D :h_OBo ~=iO˷N{R^ͅ BP pfU7UZΫ
|
Percent 100
|
T^@C\>סOw ufcɖ6 H%=i()TC
'DZp
ai
|
!
|
<\;+ϋ5stZd}8ti} r:W\{?מ}v/vt\'oVbkF{v:y|b{ze}Gy^EtKa'Nգ5[CJ_BS}ٚx [`taD
|
|
іSh_|\s59ik"ծ9&WA.!:ys so (9ӕ6;zr߀ztFX Q8*JCy`v> as}/`osWƬ `O'! (V&ʬ OioДV m3Qy(8ߝq<A:%3
|
CORGROUP $$CLK_I_BufferRising
|
ƓqL
|
Percent 100
|
#DH)^Zɍ_B>;d;eg?9Ɋ
%5 X zdz4#
|
!
|
|
|
Zf;8ƥhڷ4mmȅyh-귝,mǦ Fkҟ 6Z#wV`;q~ )-Q
|
CORGROUP $$CLK_I_BufferFalling
|
[/Yj/BjcubU}/ /z[/ٳ^j 9/y{ y׃ϋq_kY ?w~N`j`Id{.7'mٯuUuOv
|
Percent 100
|
ODaia_uVRldUӌRFTα
ϣp?7߶|Bt x\JϷ=\2't»/ Ljx6"$HğO g 'Oqߏwx;ك/0 pdZUɱZ~_b-Vc{j0r0{ɺW}%Γ-\ > z{D!* " l].~feI}&2 #ԗl=a166> R"Y+Ǜ~ZhQO 1jHl4`&Ǹ9
|
!
|
͛u_XKT7}w3MkySRpmC !ӄ4d( |}=/X )1 N}Pӌv[!S4[U H}> UL os?íصI5$.FK2S1G;Fe ? ;$JX-̶PZ#O5h
gxhM4bVӵNbD:n >x'2X@qZ2#er? k<5\8l"nWBu)# )o[:8 7:Rۤ 66 k98Oof-ڴuc)zn'> 1P 3"6b%N/%Uy_~ /Vӌl*>I5Mui`w!ꄌzf+ߢw{d[/!&
^.T9iF̤ߕa }syʫUpn({l41,؎9Zf0S;2 c7@ͅ@miۣӭ2߀ +?qxĖ3h̼Q_d_u̿,?%믚07RW:Jl z@m< tMM3F໎mc|cF}¿#95EԾiQm3t&ΣY~v#NE۹x^:vn;m?:mߙu~8 B@4 9}_{ǸMpz m4@]7m_lsQ+
|
|
/*Wʴc xsOݼo?p_1o= {>vGϧ N3H'ݢ}ߝ=vx 8 x K<߇xo߅|;E
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|[w3oB9P& o Aе:w]{ߋzC}~ xMw.u,T>Bkb pK#Crh,5 Mbi-iBDƨ c wҏLM3'U]r=SȢsܕi֫B{#(};թ}n*%{3 +R] ecy˳b׆~ΏCjh?4!tkw1jsV‡ְ: E{:rurmKK/3B\hj Z狆M\
|
Percent 100
|
6|SB3{/#pEnGQp.7-_ _n "r#Z@4"w&$e w5(vrw چ~<
5݇2bLą8 ݛ4 RrMήZK9+ǧ 㴱^f_Q: -ӐXd:մ\ a撦&>33 mюhsݥ 6:FӴ Ѡ?#n{چiUS&5TȵUS*k+IWͨip9]Ά6( CPp 2MlOJc:K+{PZfhGŃ6H|r;_Z~?- [o_5fQj0tӨswi& V E sQ\ FU57P$ hmFFa[G}a&@G Jyu7F>Bn PwPjlDh9!N
0Q@cWy JjT0 a5Aanr-, nnM336:S 49Ȩ BъKjϜ6CVRKp};-(Yy2&(ϤHHK$'<;ia!u6n ;S։9&[njTz?Yq zq H> bfֲ/䌍|Q[Zۢ\
|
!
|
gl l}o\`ƵA~G7>>#p.O x߄qD:3&_Ɓ_A 1?÷ӱ3o# eڕ._ig(=|q%=uᅛ>FUgݷIٗ}YKZLj!5kgC
|
|
iwutPKQ_'}N
|
CORGROUP $$CLK_I_BufferRising
|
"+ab`%ދsҝ۰%طs̬%v-! t$3B+ 4k43i61C6*Zh=MVՎ qL(<c/7:\_: } _:{+g=䤩oN椉uuw ҫ{ZB n :
|
Percent 100
|
fm6l
|
!
|
pwĩNDF'"SqDnZk/&10^Lc;JZ[n/
θBҮ5hUV['k>?[_:{
_xc vnTk "( |] ldt4OSL)ce:)v7d*ee-UB^3ݍ @Y#
j>2LW_+0LYF
|
|
5WmW|W]Ps{-=x0xKQF+um,ܓ5ާ[ hd/_W2_3
S&UjqkT
AŠB3ǧ7 @c 4< 91Ι] sk瞛-|ځ+.Ԃ+H8Kn0u~g`-4w-_ ;ΗcK]ݗi%nHK>Ӿ4g`1g`=w30^JX h_`*4f>s*zjX9iF+PY3:DHC? 4
C4uR|C叀r@4W}Zje?8mct;z~At#ϵ'3 -ʠ t!]#3L"e].ٽJ9ޟKN˻Bx y 5R1Rw=s<`3ҷx'B=rg
|
CORGROUP $$CLK_I_BufferFalling
|
~M6_`
|
Percent 100
|
gOP\_ ӑS 4 e1o%]dbOڒ>IqD9;%(e.Gr+` ar^p}Z)u/" 'Sʱ_ťX;M #Ĩ;O%8%5LcԦ<2 ) !ܸז;K?vki6m ?یyr0&lB
jhY/h3j].ˠ.vf]BK t:i*8rFrP+2Rksnkt^*2 iKn~:J+ ? D}vd&Sﻷ)eіN.p
|
!
|
$:O]9mZ唆SgT V`3 :T~%I܋Sjb
|
|
7γN榶,Iۦm7I2rIj<ܖ<^"nm9 9+#Ϯ؍P\z3ee^Mx;Q5O {x2}Ag8Eb^9DG.n *bt@q_%gRij]z-:C=3lK37eM,[,|2\,RΗLk txўW߸$>##pGRa ?szjK|ɔRlK~2)M+cgs-4<;'Y-W{"]owY̧t:Փݬ@{b[̹iǷ)71O*:-c='2F2(b~&1i gekgS|5wl }`}{OxݼiI8_4kſ[ E/(7&&!Q QjC5xqi~c3456 ߥr e%q*<*1f5)VװTg]
|
CORGROUP $$CLK_I_BufferRisingFalling
|
)e)\O6xiֲ/^bNFTZʭU̚4-L c<_j b@=
" tލ9`Tk)d~(PƪruU} ֛Wzt-xλm4g)utDž8=SrL)#ͮ Wq8OP>ڝFiJuw\ ܽͯ6[&vZ[%=mU=>_N~ev$rdb= o(Қѐc'[P/8mf=쒔wTLW+%u/~4{
|
Percent 100
|
,rUKŋ,FRj"3\nVu:;mҵ⭗ǵuڮwٷ]jg
Rl>tc>Z +|.cX-Ȧ1_[7S( V.ܖ @rhqs0ۣc RWM'snBrɫJF]Wֺk{L[v1ߔP 2vv7fghf;.$V n@0/wuL/I3D呹a=ϩ t}uͥU D23kFʹk
|
!
|
%
|
|
C A ? " 2 < 5U0T -" `! 5U0Tǰ5 i -
|
CORGROUP $$CLK_RISC_BufferRising
|
x[}lW?{{oǔ )l]BYtkF+- t@`s)턅d7YL&KC J`(?#&.ef 1d$&~ ssoߏޚE9y|"#Dw 1C̭xwIjX()KHq~rB O)_@.;D?kbskۛ6Gy9fz?G++PEM
HIķ.[|gAU)}|^Fق1l-=ҳ قeטTXLBH!tڶG ry#I{xln
t ZyN!$ĿgeynyC+<2f]" !e^v.EwU J>šޢPء
|
Percent 100
|
aɄF 1a6KGtUٞb;z(oylϖU7@>ы!I x]ǻ
|
!
|
l3 it Uk 0c"?a~ws)?;Lxvֱ$R?@種4s?s: kQZ Dج&|B }t:JRba,;HxjTܩ@KJ).';yp y8x`ak%۱A>Q-d=;ơy#Ho'7ơyrl䣵A1 3
7 a{9֘/ r./zNRKv@sq^3@L>Ϝd˲!sWA-riCcݺ4$ӎx'bIhMv P&-ΫrT}O^WG=W MՆp5uF?[WU~gNc q/8
|
|
׀q (0^+3
`c0z Uկ=5*Wćꇨ7e# wPtb `#xQ`cx
G*0^7o.s~ľ-_TD
|
CORGROUP $$CLK_RISC_BufferFalling
|
qQ8dz=h!h=MqAT,B4\mr
k'cz QZ2>cד"7{E[V^{ŌkXWVboew
/1WzbQZ'YOD1 /zC#K]LfGw;nItנ̾aUl@HRҴ"WY^GG f;x] @a 9zf3 eQ>f ˘wƳ(Q[xetۃGBQYit"QC9Yd]>ͺe3(&J>m| m_Y 궟"TlBnnmYEnw
:α^~? -c[Y{n.ɶzۄ:xQ3~^껌l>X0}ӯkA k_K9|y08g *wӾk4O>mu|I
}ᰎGZ*nx|1uѮ4#}~Cs2?Exc<~4/۴},L gCl8 |증!$Q Dtt}-~Yo&
|
Percent 100
|
q>0{b6Xy#tvZYز0CtG-J]߸M wX
|
!
|
~r~>Ji|+e虶H~|?D8)
|
|
^˟BBgXw ZJ%c,KC^ J )^*Yz9pҋ^l?@w JCw jIqo$.W*t<0ʒ&\oJ=zT'|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
2>Z6J}',Ӄ_zRyg\´O}#ƶY Br~_LxO]˾7מ=x)NcI_282)s|kn.3~X(LϩIz,U4o/ xyٯ|퓓n8}-|>+i7r tЉB}(L~- sOX^_ם M Xe9[Xҁ}Y=8,V>%Jzz 'ғ L,;{U(:U3{KRF{?F] {[h{{7).n{_*(d 1GMhZ&vL\pS@k:a>#o+}+akƖ
9,'^Yt=hOO6L2y͙~|yg1g ŧgmE=ki^ge'5+keCǟ2
|
Percent 100
|
Y&3{6Y&Rg3ׂtv#?*w!JJkd>d'7~'ynMd7e ʕM~%_իԢM}ĖUM2/uD
|
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|
FDY[D`;8n~oor{F% n:w߯<%nX}3g oT D d < J
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|
9
|
CORGROUP $$CLK_RISC_BufferRising
|
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Percent 100
|
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|
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|
B
|
|
G2>~
|
CORGROUP $$CLK_RISC_BufferFalling
|
:r?>n@?`#_>'ss
|
Percent 100
|
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|
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|
)7s9E A}ɳf}^Ԩ=!ϭ!ϭūx;LHKju]>RSu9%i
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|
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|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
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|
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|
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|
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CORGROUP $$CLK_I_BufferRising
|
s G/PNG
|
Percent 100
|
|
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|
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|
|$tu
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CORGROUP $$CLK_I_BufferFalling
|
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|
Percent 100
|
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|
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|
|
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|
CORGROUP $$CLK_I_BufferRisingFalling
|
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|
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|
8}Bӆh.H@јW
|
CORGROUP $$CLK_RISC_BufferRising
|
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|
Percent 100
|
m(sLwy7GꆥuXqk$cnL;X[@#Ɛ?% &PON )rhXhauwu͉ꆭuPh D}H^^&UHz_C ҹ/ s, }R:- j W|y~# #hx̫e, E^D@%2e>ißU 24H)<;(ޙBͧX/QH~f
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|
T\նF]|`I <5 Cn*\5i'"T
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|
Imui2Ns Si:f ˳Kl1IIPd) dc e"269QP2c7Oč!5
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CORGROUP $$CLK_RISC_BufferFalling
|
0KWՐBsw @4ഌ
|
Percent 100
|
4!&t
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|
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|
˾Z0,(4pY͓dZp he0ˊ,dztH{%ئ9M
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
V7j(}~ /!&na`L衙
|
Percent 100
|
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|
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|
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|
j;injpp]Rj'px$(E8c;L^ltxΖ ϝgmYG%Շ(7 D F) B!^C熈[E^2WPqPp_.=v&dy .Ł.qZ9R$r6S ;,*&`
|
CORGROUP $$CLK_I_BufferRising
|
!(fBJN֤mK~D
|
Percent 100
|
]J\ZI,\D[**G-gPml ,EWZVi?f-K P50&3QԠќq9A"lfm LVv-\*{Hir&-IZXtOYhѓI
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|
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|
rM帏+{I3 A0n:Q9̀ijdI 5:±=YލM_fAoF;HDR&j?^n JkUqlp-JM=,2Cz9>?=& "sj՝bKWma
|
CORGROUP $$CLK_I_BufferFalling
|
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|
Percent 100
|
0 zjD0r39Y4IԷ֘i
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|
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|
|
BZGB Y~ܻ8HhG$29] T
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CORGROUP $$CLK_I_BufferRisingFalling
|
(lu B @/ԌFbxRJHB쾲ұ3QY6O
|
Percent 100
|
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|
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|
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|
CORGROUP $$CLK_RISC_BufferRising
|
'3 v?mOR̞{ (یѹk̏5aAXQV_ C\zEpg<MWnWu/XGq\ex% #
|
Percent 100
|
Ys")cJP z#qu¹S=o?4\r'uZ MqO՜v
|
!
|
^MTI+"CO »_%MzCBWґ@ _?="fRi*7߽OEUe{Ƕ%E_qٽ.. |sw7 7'WZڳZL:(Ǔ2ښI h7Xf64kt'7YDq>oCTUlzAzFYx7p;XgIB]gxo5| QL% Fͬ;yhj9L`bۯYGXAssv>M)?+vNMW-]4v qh Zew$,
|
|
c@Gw1.Z ^U}DD AK
<ŕ Åw0%KJ' r/&=Kzv Lt0 .$ G6r{b+zOy{Ҩ 6$Ő
|
CORGROUP $$CLK_RISC_BufferFalling
|
Y5b,G=Ybc4$8 C43JWgI4oMH}r 1sEAӟUM ~sŏu5e& :qI,Pm
|
Percent 100
|
&:
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|
!
|
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|
|
w~
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|H/ۦMMK'[NIwON@]u
|
Percent 100
|
+PW@]u
|
!
|
+PW {4 IENDB` D d t% 0
|
|
:
|
CORGROUP $$CLK_I_BufferRising
|
# A
|
Percent 100
|
2 + q&13E S|@ 8Y `! q&13E S|@ \ xڽXO\E>3ˏBR]5bT"5`ki wF5 O l e
|
!
|
C o m p O b j T V i O b j I n f o W C O N T E N T S }0
|
|
Q<= Kuy Timing Diagram Timing.Document.1 9q Timing Diagram
|
CORGROUP $$CLK_I_BufferFalling
|
Q<= Kuy Timing Diagram Timing.Document.1 9q Timing Diagram
|
Percent 100
|
! " # $ % & ' ( ) * + , - . 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n p q r s t u v w x y z { | } ~ Timing Diagram Editor v7.1g - Output File
|
!
|
|
|
PROJECT
|
CORGROUP $$CLK_I_BufferRisingFalling
|
BaseTimeUnit 1
|
Percent 100
|
DisplayTimeUnit 2
|
!
|
TextGridX 250.000000
|
|
TextGridY 6
|
CORGROUP $$CLK_RISC_BufferRising
|
EdgeGridX 250.000000
|
Percent 100
|
ImportStartTime 0.000000
|
!
|
ImportEndTime 281474976710656.000000
|
|
TimePerPixel 6.497175
|
CORGROUP $$CLK_RISC_BufferFalling
|
Visible DELAYS SETUPS HOLDS SAMPLES TEXT HIDDENATTACHMENTS CRITICALPATHS GRIDLINES UNCERTAINTY
|
Percent 100
|
ColWidths 144,216,288,423,488
|
!
|
ScrollPos 0.000000,0.000009,0.000000
|
|
DefDelayRule 1
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
NoEventOverlap NO
|
Percent 100
|
SigLabelFontHeight 10
|
!
|
LabelHeight 12
|
|
LoadLibsToMem 1
|
CORGROUP $$CLK_I_BufferRising
|
UseFullPathNames 1
|
Percent 100
|
LibPath
|
!
|
EntireTime YES
|
|
PrintTimeSpecified NO
|
CORGROUP $$CLK_I_BufferFalling
|
FromTime 0
|
Percent 100
|
ToTime 5.75
|
!
|
AllSignals YES
|
|
CurrSelSigs NO
|
CORGROUP $$CLK_I_BufferRisingFalling
|
PrintTo 2
|
Percent 100
|
PrintFileName C:\DOCS\reset.wmf
|
!
|
PreviewInterchange YES
|
|
PreviewTIFF5 NO
|
CORGROUP $$CLK_RISC_BufferRising
|
UseMargins NO
|
Percent 100
|
PrintTimeLine NO
|
!
|
PrintBorderBox YES
|
|
PrintSigNames YES
|
CORGROUP $$CLK_RISC_BufferFalling
|
PrintSigNamesOnEachPage YES
|
Percent 100
|
AddPreviewToEPS NO
|
!
|
PreviewRes 150
|
|
MarginLR 1.25
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
MifImageWidth 6.00
|
Percent 100
|
MarginTB Auto
|
!
|
Header %d %t;%f;%p
|
|
Footer
|
CORGROUP $$CLK_I_BufferRising
|
ScaleHorz 100
|
Percent 100
|
ScaleVert 100
|
!
|
ScaleHPage 1
|
|
PrintImage DIAGRAM
|
CORGROUP $$CLK_I_BufferFalling
|
DefaultTimingModel minmax
|
Percent 100
|
DefaultClock Unclocked
|
!
|
DefaultEdgeLevel neg
|
|
DefaultSet Not Used
|
CORGROUP $$CLK_I_BufferRisingFalling
|
DefaultClear Not Used
|
Percent 100
|
DefaultClockEnable Not Used
|
!
|
DefaultClockToOutLH 0
|
|
DefaultClockToOutHL 0
|
CORGROUP $$CLK_RISC_BufferRising
|
DefaultSetup 0
|
Percent 100
|
DefaultHold 0
|
!
|
DefaultRegStartupState unknown
|
|
DefaultPodSize 8
|
CORGROUP $$CLK_RISC_BufferFalling
|
DefaultActiveLowSetClear True
|
Percent 100
|
DefaultAsyncSetClear True
|
!
|
DefaultActiveLowClockEnable True
|
|
SigLabelFontHeight 10
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
PROPS!
|
Percent 100
|
!
|
!
|
|
|
STYLE
|
CORGROUP $$CLK_I_BufferRising
|
DefaultFont USER {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
|
Percent 100
|
DrawWndFont DEFAULT
|
!
|
DrawWndColor DEFAULT
|
|
GridWndFont DEFAULT
|
CORGROUP $$CLK_I_BufferFalling
|
GridWndColor DEFAULT
|
Percent 100
|
LabelWndFont USER {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
|
!
|
LabelWndColor DEFAULT
|
|
ParamDispPref 0
|
CORGROUP $$CLK_I_BufferRisingFalling
|
ParamWndCellDisplay 0
|
Percent 100
|
CustDispString %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
|
!
|
CustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
|
|
MarkerDispPref 4
|
CORGROUP $$CLK_RISC_BufferRising
|
MarkerCustDispString %n v=%mv,%Mv d=%md %t
|
Percent 100
|
MarkerCustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
|
!
|
SignalColor 2
|
|
LabelOffset 4
|
CORGROUP $$CLK_RISC_BufferFalling
|
BusDisplay 0
|
Percent 100
|
WaveFormWidth 0.500000
|
!
|
WaveFormColor 0
|
|
InputWaveFormColor 16711680
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
SlantedEdges 1
|
Percent 100
|
SlantAngle 75
|
!
|
RightJustifySigNames 1
|
|
AutosplitEnabled 1
|
CORGROUP $$CLK_I_BufferRising
|
AutosplitChar _
|
Percent 100
|
DynamSizedSignals 1
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
DIAGRAMTESTBENCHSETTINGS
|
Percent 100
|
FilesBeforeDiagramModel
|
!
|
FilesInsideDiagramModelDeclarationSection
|
|
AbortHdlCodeEnabled 1
|
CORGROUP $$CLK_I_BufferRisingFalling
|
DelayHdlCodeEnabled 1
|
Percent 100
|
SampleHdlCodeEnabled 1
|
!
|
MarkerHdlCodeEnabled 1
|
|
VerboseSamples 0
|
CORGROUP $$CLK_RISC_BufferRising
|
VerboseDelays 0
|
Percent 100
|
VerboseFileInput 0
|
!
|
VerboseSequenceVerification 0
|
|
IncludeDelayTime 1
|
CORGROUP $$CLK_RISC_BufferFalling
|
ExecuteFromTopLevel 1
|
Percent 100
|
TimeOutInDiagramLengths 0
|
!
|
DefaultCycleClock Unclocked
|
|
DefaultCycleEdge neg
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
!
|
Percent 100
|
|
!
|
MACROS
|
|
!
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
CORGROUP $$CLK_I_BufferRising
|
!
|
Percent 100
|
|
!
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
CORGROUP $$CLK_I_BufferFalling
|
!
|
Percent 100
|
|
!
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
CORGROUP $$CLK_I_BufferRisingFalling
|
!
|
Percent 100
|
|
!
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
CORGROUP $$CLK_I_BufferRising
|
!
|
Percent 100
|
|
!
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
CORGROUP $$CLK_I_BufferFalling
|
!
|
Percent 100
|
|
!
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
CORGROUP $$CLK_I_BufferRisingFalling
|
!
|
Percent 100
|
|
!
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
CORGROUP $$CLK_I_BufferRising
|
!
|
Percent 100
|
|
!
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
CORGROUP $$CLK_I_BufferFalling
|
!
|
Percent 100
|
|
!
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
CORGROUP $$CLK_I_BufferRisingFalling
|
!
|
Percent 100
|
|
!
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
CORGROUP $$CLK_I_BufferRising
|
!
|
Percent 100
|
|
!
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
CORGROUP $$CLK_I_BufferFalling
|
!
|
Percent 100
|
|
!
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
CORGROUP $$CLK_I_BufferRisingFalling
|
!
|
Percent 100
|
|
!
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
CORGROUP $$CLK_I_BufferRising
|
!
|
Percent 100
|
|
!
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
CORGROUP $$CLK_I_BufferFalling
|
!
|
Percent 100
|
|
!
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
CORGROUP $$CLK_I_BufferRisingFalling
|
!
|
Percent 100
|
|
!
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
CORGROUP $$CLK_I_BufferRising
|
!
|
Percent 100
|
|
!
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
CORGROUP $$CLK_I_BufferFalling
|
!
|
Percent 100
|
|
!
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
CORGROUP $$CLK_I_BufferRisingFalling
|
!
|
Percent 100
|
|
!
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
CORGROUP $$CLK_RISC_BufferRising
|
!
|
Percent 100
|
|
!
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
CORGROUP $$CLK_RISC_BufferFalling
|
!
|
Percent 100
|
|
!
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
!
|
Percent 100
|
|
!
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
|
Percent 100
|
CORGROUP $$CLK_RISC_BufferRising
|
!
|
Percent 100
|
|
!
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
|
Percent 100
|
CORGROUP $$CLK_RISC_BufferFalling
|
!
|
Percent 100
|
|
!
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
!
|
Percent 100
|
|
!
|
CORGROUP $$dwb_CLK_I_BufferRising
|
|
Percent 100
|
CORGROUP $$CLK_I_BufferRising
|
!
|
Percent 100
|
|
!
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
|
Percent 100
|
CORGROUP $$CLK_I_BufferFalling
|
!
|
Percent 100
|
|
!
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
|
Percent 100
|
CORGROUP $$CLK_I_BufferRisingFalling
|
!
|
Percent 100
|
|
!
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
|
Percent 100
|
CORGROUP $$CLK_RISC_BufferRising
|
!
|
Percent 100
|
|
!
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
|
Percent 100
|
CORGROUP $$CLK_RISC_BufferFalling
|
!
|
Percent 100
|
|
!
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
!
|
Percent 100
|
|
!
|
CORGROUP $$dwb_CLK_I_BufferRising
|
|
Percent 100
|
CORGROUP $$CLK_I_BufferRising
|
!
|
Percent 100
|
|
!
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
|
Percent 100
|
CORGROUP $$CLK_I_BufferFalling
|
!
|
Percent 100
|
|
!
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
|
Percent 100
|
CORGROUP $$CLK_I_BufferRisingFalling
|
!
|
Percent 100
|
|
!
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
|
Percent 100
|
CORGROUP $$CLK_RISC_BufferRising
|
!
|
Percent 100
|
|
!
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
|
Percent 100
|
CORGROUP $$CLK_RISC_BufferFalling
|
!
|
Percent 100
|
|
!
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
!
|
Percent 100
|
|
!
|
CORGROUP $$dwb_CLK_I_BufferRising
|
|
Percent 100
|
CORGROUP $$CLK_I_BufferRising
|
!
|
Percent 100
|
|
!
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
|
Percent 100
|
CORGROUP $$CLK_I_BufferFalling
|
!
|
Percent 100
|
|
!
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
|
Percent 100
|
CORGROUP $$CLK_I_BufferRisingFalling
|
!
|
Percent 100
|
|
!
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
|
Percent 100
|
CORGROUP $$CLK_RISC_BufferRising
|
!
|
Percent 100
|
|
!
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
|
Percent 100
|
CORGROUP $$CLK_RISC_BufferFalling
|
!
|
Percent 100
|
|
!
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
!
|
Percent 100
|
|
!
|
CORGROUP $$dwb_CLK_I_BufferRising
|
|
Percent 100
|
CORGROUP $$CLK_RISC_BufferRising
|
!
|
Percent 100
|
|
!
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
|
Percent 100
|
CORGROUP $$CLK_RISC_BufferFalling
|
!
|
Percent 100
|
|
!
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
|
Percent 100
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
!
|
Percent 100
|
|
!
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
|
Percent 100
|
CORGROUP $$CLK_RISC_BufferRising
|
!
|
Percent 100
|
|
!
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
|
Percent 100
|
CORGROUP $$CLK_RISC_BufferFalling
|
!
|
Percent 100
|
|
!
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
!
|
Percent 100
|
|
!
|
CORGROUP $$dwb_CLK_I_BufferRising
|
|
Percent 100
|
CORGROUP $$CLK_RISC_BufferRising
|
!
|
Percent 100
|
|
!
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
|
Percent 100
|
CORGROUP $$CLK_RISC_BufferFalling
|
!
|
Percent 100
|
|
!
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
|
Percent 100
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
!
|
Percent 100
|
|
!
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
CORGROUP $$CLK_RISC_BufferRising
|
!
|
Percent 100
|
|
!
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
CORGROUP $$CLK_RISC_BufferFalling
|
!
|
Percent 100
|
|
!
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
!
|
Percent 100
|
|
!
|
CORGROUP $$iwb_CLK_I_BufferRising
|
|
Percent 100
|
CORGROUP $$CLK_RISC_BufferRising
|
!
|
Percent 100
|
|
!
|
CORGROUP $$iwb_CLK_I_BufferFalling
|
|
Percent 100
|
CORGROUP $$CLK_RISC_BufferFalling
|
!
|
Percent 100
|
|
!
|
CORGROUP $$iwb_CLK_I_BufferRisingFalling
|
|
Percent 100
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
!
|
Percent 100
|
|
!
|
CLOCK CLK_RISC
|
|
PERIODE 2.5
|
CORGROUP $$CLK_RISC_BufferRising
|
DUTY 50
|
Percent 100
|
OFFSETE 0
|
!
|
INITIAL HIGH
|
|
MAXUNCERTRISE 0
|
CORGROUP $$CLK_RISC_BufferFalling
|
MAXUNCERTFALL 0
|
Percent 100
|
MINUNCERTRISE 0
|
!
|
MINUNCERTFALL 0
|
|
JRISEE 0
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
JFALLE 0
|
Percent 100
|
GRID 0 1 0 2 0 16711680 0 0
|
!
|
ENDGRID -1
|
|
DIRECTION internal
|
CORGROUP $$CLK_RISC_BufferRising
|
MASTERCLOCK None
|
Percent 100
|
Clock Unclocked
|
!
|
EdgeLevel neg
|
|
Set Not Used
|
CORGROUP $$CLK_RISC_BufferFalling
|
Clear Not Used
|
Percent 100
|
ClockEnable Not Used
|
!
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
ActiveLowClockEnable True
|
Percent 100
|
VhdlType std_logic
|
!
|
VerilogType wire
|
|
SystemCType sc_logic
|
CORGROUP $$CLK_RISC_BufferRising
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
Percent 100
|
StateEquation Hex(Inc(0,2,5))
|
!
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
CORGROUP $$CLK_RISC_BufferFalling
|
MSB 0
|
Percent 100
|
LSB 0
|
!
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
DrawAnalog 0
|
Percent 100
|
BooleanEquation
|
!
|
NegTolerance 0
|
|
PosTolerance 0
|
CORGROUP $$CLK_RISC_BufferRising
|
UserSpecifiedSizeRatio 1
|
Percent 100
|
VerilogCode
|
!
|
VHDLCode
|
|
PROPS!
|
CORGROUP $$CLK_RISC_BufferFalling
|
!
|
Percent 100
|
|
!
|
CLOCK iwb_CLK_I
|
|
PERIODE 5
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
DUTY 50
|
Percent 100
|
OFFSETE 0
|
!
|
INITIAL LOW
|
|
MAXUNCERTRISE 0
|
CORGROUP $$CLK_RISC_BufferRising
|
MAXUNCERTFALL 0
|
Percent 100
|
MINUNCERTRISE 0
|
!
|
MINUNCERTFALL 0
|
|
JRISEE 0
|
CORGROUP $$CLK_RISC_BufferFalling
|
JFALLE 0
|
Percent 100
|
GRID 1 1 1 2 2 16711680 0 0
|
!
|
ENDGRID -1
|
|
DIRECTION input
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
MASTERCLOCK None
|
Percent 100
|
Clock Unclocked
|
!
|
EdgeLevel neg
|
|
Set Not Used
|
CORGROUP $$clk_risc_BufferRising
|
Clear Not Used
|
Percent 100
|
ClockEnable Not Used
|
!
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
CORGROUP $$clk_risc_BufferFalling
|
ActiveLowClockEnable True
|
Percent 100
|
VhdlType std_logic
|
!
|
VerilogType wire
|
|
SystemCType sc_logic
|
CORGROUP $$clk_risc_BufferRisingFalling
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
Percent 100
|
StateEquation Hex(Inc(0,2,5))
|
!
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
CORGROUP $$clk_risc_BufferRising
|
MSB 0
|
Percent 100
|
LSB 0
|
!
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive True
|
CORGROUP $$clk_risc_BufferFalling
|
DrawAnalog 0
|
Percent 100
|
BooleanEquation
|
!
|
NegTolerance 0
|
|
PosTolerance 0
|
CORGROUP $$clk_risc_BufferRisingFalling
|
UserSpecifiedSizeRatio 1
|
Percent 100
|
VerilogCode
|
!
|
VHDLCode
|
|
PROPS!
|
CORGROUP $$clk_risc_BufferRising
|
!
|
Percent 100
|
|
!
|
SIGNAL iwb_ADR_O
|
|
DIRECTION output
|
CORGROUP $$clk_risc_BufferFalling
|
RADIX hex
|
Percent 100
|
GRID 0 1 0 1 0 16711680 0 0
|
!
|
ENDGRID -1
|
|
Clock
|
CORGROUP $$clk_risc_BufferRisingFalling
|
EdgeLevel neg
|
Percent 100
|
Set Not Used
|
!
|
Clear Not Used
|
|
ClockEnable Not Used
|
CORGROUP $$clk_risc_BufferRising
|
ActiveLowSetClear True
|
Percent 100
|
AsyncSetClear True
|
!
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
CORGROUP $$clk_risc_BufferFalling
|
VerilogType wire
|
Percent 100
|
SystemCType sc_logic
|
!
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
CORGROUP $$clk_risc_BufferRisingFalling
|
HighVoltageThreshold 5
|
Percent 100
|
LowVoltageThreshold 0
|
!
|
LSB 0
|
|
MSB 31
|
CORGROUP $$clk_risc_BufferRising
|
SignalActionType 0
|
Percent 100
|
isFallingEdgeSensitive False
|
!
|
isRisingEdgeSensitive True
|
|
DrawAnalog 0
|
CORGROUP $$clk_risc_BufferFalling
|
BooleanEquation
|
Percent 100
|
NegTolerance 0
|
!
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
CORGROUP $$clk_risc_BufferRisingFalling
|
VerilogCode
|
Percent 100
|
VHDLCode
|
!
|
VhdlMapping DefaultVhdlMapping
|
|
PROPS!
|
CLOCK clk_risc
|
E0 V -1 -1 1 0 DR 0
|
PERIODE 1
|
E1 X 3125 3125 1 0 DR 0
|
DUTY 50
|
E2 V 3126 3126 A0 1 0 DR 0
|
OFFSETE 0
|
E3 X 3750 3750 1 0 DR 0
|
INITIAL LOW
|
E4 V 13125 13125 A0 1 0 DR 0
|
MAXUNCERTRISE 0
|
E5 X 13625 13625 1 0 DR 0
|
MAXUNCERTFALL 0
|
E6 V 23125 23125 A4 1 0 DR 0
|
MINUNCERTRISE 0
|
E7 X 23625 23625 1 0 DR 0
|
MINUNCERTFALL 0
|
E8 V 33125 33125 A8 1 0 DR 0
|
JRISEE 0
|
E9 X 33625 33625 1 0 DR 0
|
JFALLE 0
|
E10 V 43125 43125 A12 1 0 DR 0
|
GRID 1 1 1 2 2 16711680 0 0
|
E11 X 43750 43750 1 0 DR 0
|
ENDGRID -1
|
!
|
DIRECTION input
|
|
MASTERCLOCK None
|
SIGNAL iwb_DAT_I
|
Clock Unclocked
|
DIRECTION input
|
EdgeLevel neg
|
RADIX hex
|
Set Not Used
|
GRID 0 1 0 1 0 16711680 0 0
|
Clear Not Used
|
ENDGRID -1
|
ClockEnable Not Used
|
Clock
|
ActiveLowSetClear True
|
EdgeLevel neg
|
AsyncSetClear True
|
Set Not Used
|
ActiveLowClockEnable True
|
Clear Not Used
|
VhdlType std_logic
|
ClockEnable Not Used
|
VerilogType wire
|
ActiveLowSetClear True
|
SystemCType sc_logic
|
AsyncSetClear True
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
ActiveLowClockEnable True
|
StateEquation Hex(Inc(0,2,5))
|
VhdlType std_logic
|
HighVoltageThreshold 5
|
VerilogType wire
|
LowVoltageThreshold 0
|
SystemCType sc_logic
|
MSB 0
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
LSB 0
|
StateEquation Hex(Inc(0,2,5))
|
isFallingEdgeSensitive False
|
HighVoltageThreshold 5
|
isRisingEdgeSensitive True
|
LowVoltageThreshold 0
|
DrawAnalog 0
|
LSB 0
|
BooleanEquation
|
MSB 31
|
NegTolerance 0
|
SignalActionType 0
|
PosTolerance 0
|
isFallingEdgeSensitive False
|
UserSpecifiedSizeRatio 1
|
isRisingEdgeSensitive False
|
VerilogCode
|
DrawAnalog 0
|
VHDLCode
|
BooleanEquation
|
PROPS!
|
NegTolerance 0
|
E5 1 2500 2500 1 0 DR 0
|
PosTolerance 0
|
E6 0 3000 3000 1 0 DR 0
|
UserSpecifiedSizeRatio 1
|
E7 0 3500 3500 1 0 DR 0
|
VerilogCode
|
E9 1 4500 4500 1 0 DR 0
|
VHDLCode
|
!
|
VhdlMapping DefaultVhdlMapping
|
|
PROPS!
|
SIGNAL rst
|
E0 X 11250 11250 1 0 DR 0
|
DIRECTION input
|
E1 V 13125 13125 D0 1 0 DR 0
|
RADIX hex
|
E2 X 21250 21250 1 0 DR 0
|
GRID 0 1 0 1 0 16711680 0 0
|
E3 V 23125 23125 D4 1 0 DR 0
|
ENDGRID -1
|
E4 X 31250 31250 1 0 DR 0
|
Clock Unclocked
|
E5 V 33125 33125 D8 1 0 DR 0
|
EdgeLevel neg
|
E6 X 41250 41250 1 0 DR 0
|
Set Not Used
|
E7 V 43125 43125 D12 1 0 DR 0
|
Clear Not Used
|
E8 X 43750 43750 1 0 DR 0
|
ClockEnable Not Used
|
!
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
SIGNAL iwb_DAT_O
|
ActiveLowClockEnable True
|
DIRECTION output
|
VhdlType std_logic
|
RADIX hex
|
VerilogType wire
|
GRID 0 1 0 1 0 16711680 0 0
|
SystemCType sc_logic
|
ENDGRID -1
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
Clock Unclocked
|
StateEquation Hex(Inc(0,2,5))
|
EdgeLevel neg
|
HighVoltageThreshold 5
|
Set Not Used
|
LowVoltageThreshold 0
|
Clear Not Used
|
SignalActionType 0
|
ClockEnable Not Used
|
MSB 0
|
ActiveLowSetClear True
|
LSB 0
|
AsyncSetClear True
|
isFallingEdgeSensitive False
|
ActiveLowClockEnable True
|
isRisingEdgeSensitive False
|
VhdlType std_logic
|
DrawAnalog 0
|
VerilogType wire
|
BooleanEquation
|
SystemCType sc_logic
|
NegTolerance 0
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
PosTolerance 0
|
StateEquation Hex(Inc(0,2,5))
|
UserSpecifiedSizeRatio 1
|
HighVoltageThreshold 5
|
VerilogCode
|
LowVoltageThreshold 0
|
VHDLCode
|
LSB 0
|
PROPS!
|
MSB 31
|
E0 0 1750 1750 1 0 DR 0
|
SignalActionType 0
|
E1 1 3750 3750 1 0 DR 0
|
isFallingEdgeSensitive False
|
E2 0 5750 5750 1 0 DR 0
|
isRisingEdgeSensitive False
|
!
|
DrawAnalog 0
|
|
BooleanEquation
|
SIGNAL dbg_dat_o
|
NegTolerance 0
|
DIRECTION output
|
PosTolerance 0
|
RADIX hex
|
UserSpecifiedSizeRatio 1
|
GRID 0 1 0 1 0 16711680 0 0
|
VerilogCode
|
ENDGRID -1
|
VHDLCode
|
Clock
|
PROPS!
|
EdgeLevel neg
|
E0 X 43750 43750 1 0 DR 0
|
Set Not Used
|
!
|
Clear Not Used
|
|
ClockEnable Not Used
|
SIGNAL iwb_WE_O
|
ActiveLowSetClear True
|
DIRECTION output
|
AsyncSetClear True
|
RADIX hex
|
ActiveLowClockEnable True
|
GRID 0 1 0 1 0 16711680 0 0
|
VhdlType std_logic
|
ENDGRID -1
|
VerilogType wire
|
Clock Unclocked
|
SystemCType sc_logic
|
EdgeLevel neg
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
Set Not Used
|
StateEquation Hex(Inc(0,2,5))
|
Clear Not Used
|
HighVoltageThreshold 5
|
ClockEnable Not Used
|
LowVoltageThreshold 0
|
ActiveLowSetClear True
|
LSB 0
|
AsyncSetClear True
|
MSB 31
|
ActiveLowClockEnable True
|
SignalActionType 0
|
VhdlType std_logic
|
isFallingEdgeSensitive False
|
VerilogType wire
|
isRisingEdgeSensitive True
|
SystemCType sc_logic
|
DrawAnalog 0
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
BooleanEquation
|
StateEquation Hex(Inc(0,2,5))
|
NegTolerance 0
|
HighVoltageThreshold 5
|
PosTolerance 0
|
LowVoltageThreshold 0
|
UserSpecifiedSizeRatio 1
|
SignalActionType 0
|
VerilogCode
|
MSB 0
|
VHDLCode
|
LSB 0
|
VhdlMapping DefaultVhdlMapping
|
isFallingEdgeSensitive False
|
PROPS!
|
isRisingEdgeSensitive False
|
E0 X 1750 1750 1 0 DR 0
|
DrawAnalog 0
|
E1 V 4750 4750 0x0 1 0 DR 0
|
BooleanEquation
|
E2 V 5750 5750 0x4 1 0 DR 0
|
NegTolerance 0
|
!
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
SIGNAL dbg_op_i
|
VerilogCode
|
DIRECTION input
|
VHDLCode
|
RADIX hex
|
PROPS!
|
GRID 0 1 0 1 0 16711680 0 0
|
E0 X 3125 3125 1 0 DR 0
|
ENDGRID -1
|
E1 1 3126 3126 1 0 DR 0
|
Clock Unclocked
|
E2 0 13125 13125 1 0 DR 0
|
EdgeLevel neg
|
E3 X 13625 13625 1 0 DR 0
|
Set Not Used
|
E4 0 23125 23125 1 0 DR 0
|
Clear Not Used
|
E5 X 23625 23625 1 0 DR 0
|
ClockEnable Not Used
|
E6 0 33125 33125 1 0 DR 0
|
ActiveLowSetClear True
|
E7 X 33625 33625 1 0 DR 0
|
AsyncSetClear True
|
E8 0 43125 43125 1 0 DR 0
|
ActiveLowClockEnable True
|
E9 X 43625 43625 1 0 DR 0
|
VhdlType std_logic
|
!
|
VerilogType wire
|
|
SystemCType sc_logic
|
SIGNAL iwb_SEL_O
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
DIRECTION output
|
StateEquation Hex(Inc(0,2,5))
|
RADIX hex
|
HighVoltageThreshold 5
|
GRID 0 1 0 1 0 16711680 0 0
|
LowVoltageThreshold 0
|
ENDGRID -1
|
SignalActionType 0
|
Clock Unclocked
|
MSB 3
|
EdgeLevel neg
|
LSB 0
|
Set Not Used
|
isFallingEdgeSensitive False
|
Clear Not Used
|
isRisingEdgeSensitive False
|
ClockEnable Not Used
|
DrawAnalog 0
|
ActiveLowSetClear True
|
BooleanEquation
|
AsyncSetClear True
|
NegTolerance 0
|
ActiveLowClockEnable True
|
PosTolerance 0
|
VhdlType std_logic
|
UserSpecifiedSizeRatio 1
|
VerilogType wire
|
VerilogCode
|
SystemCType sc_logic
|
VHDLCode
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
PROPS!
|
StateEquation Hex(Inc(0,2,5))
|
E0 V 5750 5750 READ PC 0x0 1 0 DR 0
|
HighVoltageThreshold 5
|
!
|
LowVoltageThreshold 0
|
|
LSB 0
|
PARM Trs
|
MSB 3
|
MIN NULL
|
SignalActionType 0
|
MAX NULL
|
isFallingEdgeSensitive False
|
COMMENT Reset Setup Time
|
isRisingEdgeSensitive False
|
NameRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont Trs}
|
DrawAnalog 0
|
MinRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont}
|
BooleanEquation
|
MaxRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont}
|
NegTolerance 0
|
CommentRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont Reset Setup Time}
|
PosTolerance 0
|
CLOCKNAME Unclocked
|
UserSpecifiedSizeRatio 1
|
CLOCKEDGE neg
|
VerilogCode
|
IsApplyInput False
|
VHDLCode
|
PROPS!
|
PROPS!
|
!
|
E0 V 0 0 Valid 1 0 DR 0
|
|
E1 X 3750 3750 1 0 DR 0
|
PARM Trh
|
E2 V 13125 13125 Valid 1 0 DR 0
|
MIN NULL
|
E3 X 13625 13625 1 0 DR 0
|
MAX NULL
|
E4 V 23125 23125 Valid 1 0 DR 0
|
COMMENT Reset Hold Time
|
E5 X 23625 23625 1 0 DR 0
|
NameRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont Trh}
|
E6 V 33125 33125 Valid 1 0 DR 0
|
MinRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont}
|
E7 X 33625 33625 1 0 DR 0
|
MaxRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont}
|
E8 V 43125 43125 Valid 1 0 DR 0
|
CommentRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont Reset Hold Time}
|
E9 X 43750 43750 1 0 DR 0
|
CLOCKNAME Unclocked
|
!
|
CLOCKEDGE neg
|
|
IsApplyInput False
|
SIGNAL iwb_STB_O
|
PROPS!
|
DIRECTION output
|
!
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
SETUP Trs
|
ENDGRID -1
|
FROM clk_risc E9 S0
|
Clock Unclocked
|
TO rst E1 S1
|
EdgeLevel neg
|
OUTARROWS 0
|
Set Not Used
|
USERPLACED 0
|
Clear Not Used
|
DISPLAYAS 6
|
ClockEnable Not Used
|
CUSTDISPSTRING %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
|
ActiveLowSetClear True
|
CustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
|
AsyncSetClear True
|
EnableHdlCodeGeneration False
|
ActiveLowClockEnable True
|
OrderIndex 1
|
VhdlType std_logic
|
PROPS!
|
VerilogType wire
|
!
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
HOLD Trh
|
StateEquation Hex(Inc(0,2,5))
|
FROM clk_risc E7 S0
|
HighVoltageThreshold 5
|
TO rst E1 S1
|
LowVoltageThreshold 0
|
OUTARROWS 0
|
SignalActionType 0
|
USERPLACED 0
|
MSB 0
|
DISPLAYAS 6
|
LSB 0
|
CUSTDISPSTRING %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
|
isFallingEdgeSensitive False
|
CustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
|
isRisingEdgeSensitive False
|
EnableHdlCodeGeneration False
|
DrawAnalog 0
|
OrderIndex 2
|
BooleanEquation
|
PROPS!
|
NegTolerance 0
|
!
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
MARKER MARK0
|
VerilogCode
|
ATTACH rst NULL S1
|
VHDLCode
|
TIME 2750.000000
|
PROPS!
|
RELATIVETIME 0.000000
|
E0 0 3750 3750 1 0 DR 0
|
DISPLAYAS 5
|
E1 1 13125 13125 1 0 DR 0
|
MARKERTYPE Timebreak(Curved)
|
E2 0 13625 13625 1 0 DR 0
|
WHILERETURN
|
E3 1 23125 23125 1 0 DR 0
|
REPEATNUMBER
|
E4 0 23625 23625 1 0 DR 0
|
SNAPTO 0
|
E5 1 33125 33125 1 0 DR 0
|
COMPRESSTIME 0.000000
|
E6 0 33625 33625 1 0 DR 0
|
COMMENT
|
E7 1 43125 43125 1 0 DR 0
|
!
|
E8 X 43750 43750 1 0 DR 0
|
|
!
|
_ 1 0 5 0 0 7 8 8 3 7 Z Q<= Kuy `} `} O l e
|
|
C o m p O b j Y [ i O b j I n f o \ C O N T E N T S ?( _ 1 0 5 0 0 6 4 4 0 9 l _ Q<= Kuy `} @9 O l e
|
SIGNAL iwb_ACK_I
|
C o m p O b j ^ ` i Timing Diagram Editor v7.1g - Output File
|
DIRECTION input
|
|
RADIX hex
|
PROJECT
|
GRID 0 1 0 1 0 16711680 0 0
|
BaseTimeUnit 1
|
ENDGRID -1
|
DisplayTimeUnit 2
|
Clock Unclocked
|
TextGridX 250.000000
|
EdgeLevel neg
|
TextGridY 6
|
Set Not Used
|
EdgeGridX 250.000000
|
Clear Not Used
|
ImportStartTime 0.000000
|
ClockEnable Not Used
|
ImportEndTime 281474976710656.000000
|
ActiveLowSetClear True
|
TimePerPixel 6.497175
|
AsyncSetClear True
|
Visible DELAYS SETUPS HOLDS SAMPLES TEXT HIDDENATTACHMENTS CRITICALPATHS GRIDLINES UNCERTAINTY
|
ActiveLowClockEnable True
|
ColWidths 144,216,288,423,488
|
VhdlType std_logic
|
ScrollPos 0.000000,0.000000,0.000000
|
VerilogType wire
|
DefDelayRule 1
|
SystemCType sc_logic
|
NoEventOverlap NO
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
SigLabelFontHeight 10
|
StateEquation Hex(Inc(0,2,5))
|
LabelHeight 12
|
HighVoltageThreshold 5
|
LoadLibsToMem 1
|
LowVoltageThreshold 0
|
UseFullPathNames 1
|
SignalActionType 0
|
LibPath
|
MSB 0
|
EntireTime YES
|
LSB 0
|
PrintTimeSpecified NO
|
isFallingEdgeSensitive False
|
FromTime 0
|
isRisingEdgeSensitive False
|
ToTime 5.75
|
DrawAnalog 0
|
AllSignals YES
|
BooleanEquation
|
CurrSelSigs NO
|
NegTolerance 0
|
PrintTo 2
|
PosTolerance 0
|
PrintFileName C:\DOCS\reset_gated.wmf
|
UserSpecifiedSizeRatio 1
|
PreviewInterchange YES
|
VerilogCode
|
PreviewTIFF5 NO
|
VHDLCode
|
UseMargins NO
|
PROPS!
|
PrintTimeLine NO
|
E0 0 11250 11250 1 0 DR 0
|
PrintBorderBox YES
|
E1 1 13125 13125 1 0 DR 0
|
PrintSigNames YES
|
E2 0 21250 21250 1 0 DR 0
|
PrintSigNamesOnEachPage YES
|
E3 1 23125 23125 1 0 DR 0
|
AddPreviewToEPS NO
|
E4 0 31250 31250 1 0 DR 0
|
PreviewRes 150
|
E5 1 33125 33125 1 0 DR 0
|
MarginLR 1.25
|
E6 0 41250 41250 1 0 DR 0
|
MifImageWidth 6.00
|
E7 1 43125 43125 1 0 DR 0
|
MarginTB Auto
|
E8 X 43750 43750 1 0 DR 0
|
Header %d %t;%f;%p
|
!
|
Footer
|
|
ScaleHorz 100
|
SIGNAL iwb_CYC_O
|
ScaleVert 100
|
DIRECTION output
|
ScaleHPage 1
|
RADIX hex
|
PrintImage DIAGRAM
|
GRID 0 1 0 1 0 16711680 0 0
|
DefaultTimingModel minmax
|
ENDGRID -1
|
DefaultClock Unclocked
|
Clock Unclocked
|
DefaultEdgeLevel neg
|
EdgeLevel neg
|
DefaultSet Not Used
|
Set Not Used
|
DefaultClear Not Used
|
Clear Not Used
|
DefaultClockEnable Not Used
|
ClockEnable Not Used
|
DefaultClockToOutLH 0
|
ActiveLowSetClear True
|
DefaultClockToOutHL 0
|
AsyncSetClear True
|
DefaultSetup 0
|
ActiveLowClockEnable True
|
DefaultHold 0
|
VhdlType std_logic
|
DefaultRegStartupState unknown
|
VerilogType wire
|
DefaultPodSize 8
|
SystemCType sc_logic
|
DefaultActiveLowSetClear True
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
DefaultAsyncSetClear True
|
StateEquation Hex(Inc(0,2,5))
|
DefaultActiveLowClockEnable True
|
HighVoltageThreshold 5
|
SigLabelFontHeight 10
|
LowVoltageThreshold 0
|
PROPS!
|
SignalActionType 0
|
!
|
MSB 0
|
|
LSB 0
|
STYLE
|
isFallingEdgeSensitive False
|
DefaultFont USER {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
|
isRisingEdgeSensitive False
|
DrawWndFont DEFAULT
|
DrawAnalog 0
|
DrawWndColor DEFAULT
|
BooleanEquation
|
GridWndFont DEFAULT
|
NegTolerance 0
|
GridWndColor DEFAULT
|
PosTolerance 0
|
LabelWndFont USER {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
|
UserSpecifiedSizeRatio 1
|
LabelWndColor DEFAULT
|
VerilogCode
|
ParamDispPref 0
|
VHDLCode
|
ParamWndCellDisplay 0
|
PROPS!
|
CustDispString %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
|
E0 0 3125 3125 1 0 DR 0
|
CustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
|
E1 1 43125 43125 1 0 DR 0
|
MarkerDispPref 4
|
E2 0 43750 43750 1 0 DR 0
|
MarkerCustDispString %n v=%mv,%Mv d=%md %t
|
!
|
MarkerCustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
|
|
SignalColor 2
|
SIGNAL iwb_ERR_I
|
LabelOffset 4
|
DIRECTION input
|
BusDisplay 0
|
RADIX hex
|
WaveFormWidth 0.500000
|
GRID 0 1 0 1 0 16711680 0 0
|
WaveFormColor 0
|
ENDGRID -1
|
InputWaveFormColor 16711680
|
Clock Unclocked
|
SlantedEdges 1
|
EdgeLevel neg
|
SlantAngle 75
|
Set Not Used
|
RightJustifySigNames 1
|
Clear Not Used
|
AutosplitEnabled 1
|
ClockEnable Not Used
|
AutosplitChar _
|
ActiveLowSetClear True
|
DynamSizedSignals 1
|
AsyncSetClear True
|
!
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
DIAGRAMTESTBENCHSETTINGS
|
VerilogType wire
|
FilesBeforeDiagramModel
|
SystemCType sc_logic
|
FilesInsideDiagramModelDeclarationSection
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
AbortHdlCodeEnabled 1
|
StateEquation Hex(Inc(0,2,5))
|
DelayHdlCodeEnabled 1
|
HighVoltageThreshold 5
|
SampleHdlCodeEnabled 1
|
LowVoltageThreshold 0
|
MarkerHdlCodeEnabled 1
|
SignalActionType 0
|
VerboseSamples 0
|
MSB 0
|
VerboseDelays 0
|
LSB 0
|
VerboseFileInput 0
|
isFallingEdgeSensitive False
|
VerboseSequenceVerification 0
|
isRisingEdgeSensitive False
|
IncludeDelayTime 1
|
DrawAnalog 0
|
ExecuteFromTopLevel 1
|
BooleanEquation
|
TimeOutInDiagramLengths 0
|
NegTolerance 0
|
DefaultCycleClock Unclocked
|
PosTolerance 0
|
DefaultCycleEdge neg
|
UserSpecifiedSizeRatio 1
|
!
|
VerilogCode
|
|
VHDLCode
|
MACROS
|
PROPS!
|
!
|
E0 0 43125 43125 1 0 DR 0
|
|
E1 X 43750 43750 1 0 DR 0
|
CORGROUP $$CLK_I_BufferRising
|
!
|
Percent 100
|
|
!
|
SIGNAL iwb_RTY_I
|
|
DIRECTION input
|
CORGROUP $$CLK_I_BufferFalling
|
RADIX hex
|
Percent 100
|
GRID 0 1 0 1 0 16711680 0 0
|
!
|
ENDGRID -1
|
|
Clock Unclocked
|
CORGROUP $$CLK_I_BufferRisingFalling
|
EdgeLevel neg
|
Percent 100
|
Set Not Used
|
!
|
Clear Not Used
|
|
ClockEnable Not Used
|
CORGROUP $$CLK_I_BufferRising
|
ActiveLowSetClear True
|
Percent 100
|
AsyncSetClear True
|
!
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
CORGROUP $$CLK_I_BufferFalling
|
VerilogType wire
|
Percent 100
|
SystemCType sc_logic
|
!
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
CORGROUP $$CLK_I_BufferRisingFalling
|
HighVoltageThreshold 5
|
Percent 100
|
LowVoltageThreshold 0
|
!
|
SignalActionType 0
|
|
MSB 0
|
CORGROUP $$CLK_I_BufferRising
|
LSB 0
|
Percent 100
|
isFallingEdgeSensitive False
|
!
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
CORGROUP $$CLK_I_BufferFalling
|
BooleanEquation
|
Percent 100
|
NegTolerance 0
|
!
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
CORGROUP $$CLK_I_BufferRisingFalling
|
VerilogCode
|
Percent 100
|
VHDLCode
|
!
|
PROPS!
|
|
E0 0 43125 43125 1 0 DR 0
|
CORGROUP $$CLK_I_BufferRising
|
E1 X 43750 43750 1 0 DR 0
|
Percent 100
|
!
|
!
|
|
|
MARKER MARK1
|
CORGROUP $$CLK_I_BufferFalling
|
ATTACH iwb_SEL_O NULL S6
|
Percent 100
|
TIME 17500.000000
|
!
|
RELATIVETIME 0.000000
|
|
DISPLAYAS 5
|
CORGROUP $$CLK_I_BufferRisingFalling
|
MARKERTYPE Timebreak(Curved)
|
Percent 100
|
WHILERETURN
|
!
|
REPEATNUMBER
|
|
SNAPTO 0
|
CORGROUP $$CLK_I_BufferRising
|
COMPRESSTIME 0.000000
|
Percent 100
|
COMMENT
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
MARKER MARK2
|
Percent 100
|
ATTACH iwb_STB_O NULL S7
|
!
|
TIME 27500.000000
|
|
RELATIVETIME 0.000000
|
CORGROUP $$CLK_I_BufferRisingFalling
|
DISPLAYAS 5
|
Percent 100
|
MARKERTYPE Timebreak(Curved)
|
!
|
WHILERETURN
|
|
REPEATNUMBER
|
CORGROUP $$CLK_I_BufferRising
|
SNAPTO 0
|
Percent 100
|
COMPRESSTIME 0.000000
|
!
|
COMMENT
|
|
!
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
MARKER MARK3
|
!
|
ATTACH iwb_STB_O NULL S7
|
|
TIME 37500.000000
|
CORGROUP $$CLK_I_BufferRisingFalling
|
RELATIVETIME 0.000000
|
Percent 100
|
DISPLAYAS 5
|
!
|
MARKERTYPE Timebreak(Curved)
|
|
WHILERETURN
|
CORGROUP $$CLK_RISC_BufferRising
|
REPEATNUMBER
|
Percent 100
|
SNAPTO 0
|
!
|
COMPRESSTIME 0.000000
|
|
COMMENT
|
CORGROUP $$CLK_RISC_BufferFalling
|
!
|
Percent 100
|
|
!
|
MARKER MARK0
|
|
ATTACH iwb_CLK_I NULL S1
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
TIME 7494.285714
|
Percent 100
|
RELATIVETIME 0.000000
|
!
|
DISPLAYAS 5
|
|
MARKERTYPE Timebreak(Curved)
|
CORGROUP $$CLK_RISC_BufferRising
|
WHILERETURN
|
Percent 100
|
REPEATNUMBER
|
!
|
SNAPTO 0
|
|
COMPRESSTIME 0.000000
|
CORGROUP $$CLK_RISC_BufferFalling
|
COMMENT
|
Percent 100
|
!
|
!
|
|
|
Timing Diagram Editor v7.1g - Output File
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
PROJECT
|
!
|
BaseTimeUnit 1
|
|
DisplayTimeUnit 2
|
CORGROUP $$CLK_I_BufferRising
|
TextGridX 625.000000
|
Percent 100
|
TextGridY 6
|
!
|
EdgeGridX 625.000000
|
|
ImportStartTime 0.000000
|
CORGROUP $$CLK_I_BufferFalling
|
ImportEndTime 281474976710656.000000
|
Percent 100
|
TimePerPixel 61.428571
|
!
|
Visible DELAYS SETUPS HOLDS SAMPLES TEXT HIDDENATTACHMENTS CRITICALPATHS GRIDLINES UNCERTAINTY
|
|
ColWidths 144,216,288,423,488
|
CORGROUP $$CLK_I_BufferRisingFalling
|
ScrollPos 0.000000,0.000000,0.000000
|
Percent 100
|
DefDelayRule 1
|
!
|
NoEventOverlap NO
|
|
SigLabelFontHeight 10
|
CORGROUP $$CLK_RISC_BufferRising
|
LabelHeight 12
|
Percent 100
|
LoadLibsToMem 1
|
!
|
UseFullPathNames 1
|
|
LibPath
|
CORGROUP $$CLK_RISC_BufferFalling
|
EntireTime YES
|
Percent 100
|
PrintTimeSpecified NO
|
!
|
FromTime 0
|
|
ToTime 53.75
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
AllSignals YES
|
Percent 100
|
CurrSelSigs NO
|
!
|
PrintTo 2
|
|
PrintFileName C:\DOCS\wb_writeblock_typ.wmf
|
CORGROUP $$CLK_I_BufferRising
|
PreviewInterchange YES
|
Percent 100
|
PreviewTIFF5 NO
|
!
|
UseMargins NO
|
|
PrintTimeLine NO
|
CORGROUP $$CLK_I_BufferFalling
|
PrintBorderBox YES
|
Percent 100
|
PrintSigNames YES
|
!
|
PrintSigNamesOnEachPage YES
|
|
AddPreviewToEPS NO
|
CORGROUP $$CLK_I_BufferRisingFalling
|
PreviewRes 150
|
Percent 100
|
MarginLR 1.25
|
!
|
MifImageWidth 6.00
|
|
MarginTB Auto
|
CORGROUP $$CLK_RISC_BufferRising
|
Header %d %t;%f;%p
|
Percent 100
|
Footer
|
!
|
ScaleHorz 100
|
|
ScaleVert 100
|
CORGROUP $$CLK_RISC_BufferFalling
|
ScaleHPage 1
|
Percent 100
|
PrintImage DIAGRAM
|
!
|
DefaultTimingModel minmax
|
|
DefaultClock Unclocked
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
DefaultEdgeLevel neg
|
Percent 100
|
DefaultSet Not Used
|
!
|
DefaultClear Not Used
|
|
DefaultClockEnable Not Used
|
CORGROUP $$CLK_I_BufferRising
|
DefaultClockToOutLH 0
|
Percent 100
|
DefaultClockToOutHL 0
|
!
|
DefaultSetup 0
|
|
DefaultHold 0
|
CORGROUP $$CLK_I_BufferFalling
|
DefaultRegStartupState unknown
|
Percent 100
|
DefaultPodSize 8
|
!
|
DefaultActiveLowSetClear True
|
|
DefaultAsyncSetClear True
|
CORGROUP $$CLK_I_BufferRisingFalling
|
DefaultActiveLowClockEnable True
|
Percent 100
|
SigLabelFontHeight 10
|
!
|
PROPS!
|
|
!
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
STYLE
|
!
|
DefaultFont USER {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
|
|
DrawWndFont DEFAULT
|
CORGROUP $$CLK_RISC_BufferFalling
|
DrawWndColor DEFAULT
|
Percent 100
|
GridWndFont DEFAULT
|
!
|
GridWndColor DEFAULT
|
|
LabelWndFont USER {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
LabelWndColor DEFAULT
|
Percent 100
|
ParamDispPref 0
|
!
|
ParamWndCellDisplay 0
|
|
CustDispString %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
|
CORGROUP $$CLK_RISC_BufferRising
|
CustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
|
Percent 100
|
MarkerDispPref 4
|
!
|
MarkerCustDispString %n v=%mv,%Mv d=%md %t
|
|
MarkerCustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
|
CORGROUP $$CLK_RISC_BufferFalling
|
SignalColor 2
|
Percent 100
|
LabelOffset 2
|
!
|
BusDisplay 0
|
|
WaveFormWidth 0.500000
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
WaveFormColor 0
|
Percent 100
|
InputWaveFormColor 16711680
|
!
|
SlantedEdges 1
|
|
SlantAngle 75
|
CORGROUP $$CLK_RISC_BufferRising
|
RightJustifySigNames 1
|
Percent 100
|
AutosplitEnabled 1
|
!
|
AutosplitChar _
|
|
DynamSizedSignals 1
|
CORGROUP $$CLK_RISC_BufferFalling
|
!
|
Percent 100
|
|
!
|
DIAGRAMTESTBENCHSETTINGS
|
|
FilesBeforeDiagramModel
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
FilesInsideDiagramModelDeclarationSection
|
Percent 100
|
AbortHdlCodeEnabled 1
|
!
|
DelayHdlCodeEnabled 1
|
|
SampleHdlCodeEnabled 1
|
CORGROUP $$CLK_RISC_BufferRising
|
MarkerHdlCodeEnabled 1
|
Percent 100
|
VerboseSamples 0
|
!
|
VerboseDelays 0
|
|
VerboseFileInput 0
|
CORGROUP $$CLK_RISC_BufferFalling
|
VerboseSequenceVerification 0
|
Percent 100
|
IncludeDelayTime 1
|
!
|
ExecuteFromTopLevel 1
|
|
TimeOutInDiagramLengths 0
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
DefaultCycleClock Unclocked
|
Percent 100
|
DefaultCycleEdge neg
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
MACROS
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRising
|
CORGROUP $$CLK_RISC_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
CORGROUP $$CLK_RISC_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRising
|
CORGROUP $$CLK_RISC_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
CORGROUP $$CLK_RISC_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRising
|
CORGROUP $$CLK_RISC_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
CORGROUP $$CLK_RISC_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRising
|
CORGROUP $$CLK_RISC_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
CORGROUP $$CLK_RISC_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRising
|
CORGROUP $$CLK_RISC_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
CORGROUP $$CLK_RISC_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRising
|
CORGROUP $$CLK_RISC_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
CORGROUP $$CLK_RISC_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
CORGROUP $$CLK_RISC_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CORGROUP $$clk_risc_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
CORGROUP $$clk_risc_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
CORGROUP $$clk_risc_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CORGROUP $$clk_risc_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRising
|
CORGROUP $$clk_risc_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
CORGROUP $$clk_risc_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
CORGROUP $$clk_risc_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
CORGROUP $$clk_risc_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
CORGROUP $$clk_risc_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CORGROUP $$clk_risc_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRising
|
CORGROUP $$clk_risc_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
CORGROUP $$clk_risc_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
CORGROUP $$clk_risc_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
CORGROUP $$clk_risc_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
CORGROUP $$clk_risc_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CORGROUP $$clk_risc_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRising
|
CORGROUP $$clk_risc_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
CORGROUP $$clk_risc_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
CLOCK clk_risc
|
Percent 100
|
PERIODE 1
|
!
|
DUTY 50
|
|
OFFSETE 4.5
|
CORGROUP $$CLK_RISC_BufferRising
|
INITIAL HIGH
|
Percent 100
|
MAXUNCERTRISE 0
|
!
|
MAXUNCERTFALL 0
|
|
MINUNCERTRISE 0
|
CORGROUP $$CLK_RISC_BufferFalling
|
MINUNCERTFALL 0
|
Percent 100
|
JRISEE 0
|
!
|
JFALLE 0
|
|
GRID 1 1 0 2 2 16711680 0 0
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
ENDGRID -1
|
Percent 100
|
DIRECTION input
|
!
|
MASTERCLOCK None
|
|
Clock Unclocked
|
CORGROUP $$CLK_I_BufferRising
|
EdgeLevel neg
|
Percent 100
|
Set Not Used
|
!
|
Clear Not Used
|
|
ClockEnable Not Used
|
CORGROUP $$CLK_I_BufferFalling
|
ActiveLowSetClear True
|
Percent 100
|
AsyncSetClear True
|
!
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
CORGROUP $$CLK_I_BufferRisingFalling
|
VerilogType wire
|
Percent 100
|
SystemCType sc_logic
|
!
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
CORGROUP $$CLK_RISC_BufferRising
|
HighVoltageThreshold 5
|
Percent 100
|
LowVoltageThreshold 0
|
!
|
MSB 0
|
|
LSB 0
|
CORGROUP $$CLK_RISC_BufferFalling
|
isFallingEdgeSensitive False
|
Percent 100
|
isRisingEdgeSensitive True
|
!
|
DrawAnalog 0
|
|
BooleanEquation
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
NegTolerance 0
|
Percent 100
|
PosTolerance 0
|
!
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
CORGROUP $$CLK_I_BufferRising
|
VHDLCode
|
Percent 100
|
PROPS!
|
!
|
E5 1 7000 7000 1 0 DR 0
|
|
E6 0 7500 7500 1 0 DR 0
|
CORGROUP $$CLK_I_BufferFalling
|
E7 1 8000 8000 1 0 DR 0
|
Percent 100
|
E9 1 9000 9000 1 0 DR 0
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
SIGNAL rst
|
Percent 100
|
DIRECTION input
|
!
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
CORGROUP $$CLK_RISC_BufferRising
|
ENDGRID -1
|
Percent 100
|
Clock Unclocked
|
!
|
EdgeLevel neg
|
|
Set Not Used
|
CORGROUP $$CLK_RISC_BufferFalling
|
Clear Not Used
|
Percent 100
|
ClockEnable Not Used
|
!
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
ActiveLowClockEnable True
|
Percent 100
|
VhdlType std_logic
|
!
|
VerilogType wire
|
|
SystemCType sc_logic
|
CORGROUP $$CLK_I_BufferRising
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
Percent 100
|
StateEquation Hex(Inc(0,2,5))
|
!
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
CORGROUP $$CLK_I_BufferFalling
|
SignalActionType 0
|
Percent 100
|
MSB 0
|
!
|
LSB 0
|
|
isFallingEdgeSensitive False
|
CORGROUP $$CLK_I_BufferRisingFalling
|
isRisingEdgeSensitive False
|
Percent 100
|
DrawAnalog 0
|
!
|
BooleanEquation
|
|
NegTolerance 0
|
CORGROUP $$CLK_RISC_BufferRising
|
PosTolerance 0
|
Percent 100
|
UserSpecifiedSizeRatio 1
|
!
|
VerilogCode
|
|
VHDLCode
|
CORGROUP $$CLK_RISC_BufferFalling
|
PROPS!
|
Percent 100
|
E0 0 1750 1750 1 0 DR 0
|
!
|
E1 1 3750 3750 1 0 DR 0
|
|
E2 0 5750 5750 1 0 DR 0
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
!
|
Percent 100
|
|
!
|
SIGNAL dbg_dat_o
|
|
DIRECTION output
|
CORGROUP $$CLK_I_BufferRising
|
RADIX hex
|
Percent 100
|
GRID 0 1 0 1 0 16711680 0 0
|
!
|
ENDGRID -1
|
|
Clock
|
CORGROUP $$CLK_I_BufferFalling
|
EdgeLevel neg
|
Percent 100
|
Set Not Used
|
!
|
Clear Not Used
|
|
ClockEnable Not Used
|
CORGROUP $$CLK_I_BufferRisingFalling
|
ActiveLowSetClear True
|
Percent 100
|
AsyncSetClear True
|
!
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
CORGROUP $$CLK_RISC_BufferRising
|
VerilogType wire
|
Percent 100
|
SystemCType sc_logic
|
!
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
CORGROUP $$CLK_RISC_BufferFalling
|
HighVoltageThreshold 5
|
Percent 100
|
LowVoltageThreshold 0
|
!
|
LSB 0
|
|
MSB 31
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
SignalActionType 0
|
Percent 100
|
isFallingEdgeSensitive False
|
!
|
isRisingEdgeSensitive True
|
|
DrawAnalog 0
|
CORGROUP $$CLK_I_BufferRising
|
BooleanEquation
|
Percent 100
|
NegTolerance 0
|
!
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
CORGROUP $$CLK_I_BufferFalling
|
VerilogCode
|
Percent 100
|
VHDLCode
|
!
|
VhdlMapping DefaultVhdlMapping
|
|
PROPS!
|
CORGROUP $$CLK_I_BufferRisingFalling
|
E0 X 1750 1750 1 0 DR 0
|
Percent 100
|
E1 V 4750 4750 0x0 1 0 DR 0
|
!
|
E2 V 5750 5750 0x4 1 0 DR 0
|
|
!
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
SIGNAL dbg_op_i
|
!
|
DIRECTION input
|
|
RADIX hex
|
CORGROUP $$CLK_RISC_BufferFalling
|
GRID 0 1 0 1 0 16711680 0 0
|
Percent 100
|
ENDGRID -1
|
!
|
Clock Unclocked
|
|
EdgeLevel neg
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
Set Not Used
|
Percent 100
|
Clear Not Used
|
!
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
CORGROUP $$CLK_I_BufferRising
|
AsyncSetClear True
|
Percent 100
|
ActiveLowClockEnable True
|
!
|
VhdlType std_logic
|
|
VerilogType wire
|
CORGROUP $$CLK_I_BufferFalling
|
SystemCType sc_logic
|
Percent 100
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
!
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
CORGROUP $$CLK_I_BufferRisingFalling
|
LowVoltageThreshold 0
|
Percent 100
|
SignalActionType 0
|
!
|
MSB 3
|
|
LSB 0
|
CORGROUP $$CLK_RISC_BufferRising
|
isFallingEdgeSensitive False
|
Percent 100
|
isRisingEdgeSensitive False
|
!
|
DrawAnalog 0
|
|
BooleanEquation
|
CORGROUP $$CLK_RISC_BufferFalling
|
NegTolerance 0
|
Percent 100
|
PosTolerance 0
|
!
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
VHDLCode
|
Percent 100
|
PROPS!
|
!
|
E0 V 5750 5750 READ PC 0x0 1 0 DR 0
|
|
!
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
MARKER MARK0
|
!
|
ATTACH rst NULL S1
|
|
TIME 2750.000000
|
CORGROUP $$CLK_I_BufferFalling
|
RELATIVETIME 0.000000
|
Percent 100
|
DISPLAYAS 5
|
!
|
MARKERTYPE Timebreak(Curved)
|
|
WHILERETURN
|
CORGROUP $$CLK_I_BufferRisingFalling
|
REPEATNUMBER
|
Percent 100
|
SNAPTO 0
|
!
|
COMPRESSTIME 0.000000
|
|
COMMENT
|
CORGROUP $$CLK_RISC_BufferRising
|
!
|
Percent 100
|
|
!
|
*ibi*
JP"M^465Ysٽ5$';s̝ʈU~RE0)D ??%_CfDPɠ?)]]s: uq- Ф* :`{\
|
|
>iuP*PH "ܻ_/{{
N/Fi2N.a*e5QV11˕T^L1ڥ9Bl
Yg&]}~]Hh=T AΝ=1'QfiRs
?7؟;sH{ee^ ̢
|
CORGROUP $$CLK_RISC_BufferFalling
|
]CMؙvblZsD魯L7L7.
|
Percent 100
|
}x^L6.˚} "Lag 0陀btJ5Tqs tW'.-nqֵ ]k5t}GmFk s_]2z
|
!
|
9Hem&I9[W033/L!k5
|
|
H\0hB*nU4#ܣ;7~g3'hǧE>Z;$)w"gm*K3g:JX߃8y4Q4&}Q_oB*WٰRnr얅_4~nh2LE`fnr2r )!m[eV Bt ]A} 2cYy Zo/a'v猗S jw.5S\3E+͝B@+rN9{WV׆Z19̙ɩ"s&EqBn[Hy+F]Ԩ˙7Ajf,FgdIJ鲎3qA!?-F;J
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
. Oo xAtO" k;Ѿkz{2kUhVkx<+}xxULkj 闙kA! 3kO[(^= ;篞~߇i̷{| u
.BjpOj cԎ7N;| #N1ʢQEO'"wSf?Eu^Yt5s.W1 ;CmQ("G?_}>.l=\]wU[8,>Ca ֿl/î-
|
Percent 100
|
E\q(_> zH®"%maఘG9XRg0]G"%mQ("G?_}{Myלwm/uCo
|
!
|
/^\Uot dnq.']z:} D y K _ R e f 5 1 3 2 0 6 8 1 0 g D d t%@ 0
|
|
;
|
CORGROUP $$CLK_I_BufferRising
|
# A 2 kZx<aK m]* d` `! kZx<aK m]*D p \ 8
xڽWNG>3 & iLZ&AS*е"F4IȂq zoP_
|
Percent 100
|
Hk+z=\svy?]1R b-kSrA#x%KlevlW!*z /iS貎iK+Ge^ ڈbHp]ZׁJh9N4EO܃.s BZ-KXujFE";ؘxm0wzJ!mW6C+\H{ќ[/(Q[X {681 ?GO;KԿ\S?u ÷Bϟm?8\{2dK. i.{/O.-Bg5
HY=llD(F4]
9u.c /
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|
!
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a $$If T xZ Vz !
|
CORGROUP $$CLK_I_BufferFalling
|
t 0
"6$ $ $ $ 4 a w$$If T !x^D*
|
Percent 100
|
t Z @
& pVJz < 6 f!!
|
!
|
t 0
"6ք ք ք ք 4 a $$If T xZ Vz !
|
|
t 0
"6$ $ $ $ 4 a w$$If T !x^D*
|
CORGROUP $$CLK_I_BufferRisingFalling
|
t Z @
& pVJz < 6 f!!
|
Percent 100
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
!
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a $$If T xZ Vz !
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
t 0
"6$ $ $ $ 4 a w$$If T !x^D*
|
Percent 100
|
t Z @
& pVJz < 6 f!!
|
!
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
Percent 100
|
t Z @
& pVJz < 6 f!!
|
!
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
Percent 100
|
t Z @
& pVJz < 6 f!!
|
!
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
CORGROUP $$dwb_CLK_I_BufferRising
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
Percent 100
|
t Z @
& pVJz < 6 f!!
|
!
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
Percent 100
|
t Z @
& pVJz < 6 f!!
|
!
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
Percent 100
|
t Z @
& pVJz < 6 f!!
|
!
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
Percent 100
|
t Z @
& pVJz < 6 f!!
|
!
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
Percent 100
|
t Z @
& pVJz < 6 f!!
|
!
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
Percent 100
|
t Z @
& pVJz < 6 f!! !
|
!
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
CORGROUP $$dwb_CLK_I_BufferRising
|
t 0
"6ք ք ք ք 4 a $$If T xZ Vz !
|
Percent 100
|
t 0
"6$ $ $ $ 4 a w$$If T !x^D*
|
!
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
t Z @
& pVJz < 6 f!!
|
Percent 100
|
t 0
"6ք ք ք ք 4 a $$If T xZ Vz !
|
!
|
t 0
"6$ $ $ $ 4 a w$$If T !x^D*
|
|
t Z @
& pVJz < 6 f!!
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
Percent 100
|
t Z @
& pVJz < 6 f!!
|
!
|
t 0
"6ք ք ք ք 4 a $$If T xZ Vz !
|
|
t 0
"6$ $ $ $ 4 a w$$If T !x^D*
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
t Z @
& pVJz < 6 f!!
|
Percent 100
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
!
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
t Z @
& pVJz < 6 f!!
|
Percent 100
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
!
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
t Z @
& pVJz < 6 f!!
|
Percent 100
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
!
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
CORGROUP $$dwb_CLK_I_BufferRising
|
t Z @
& pVJz < 6 f!!
|
Percent 100
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
!
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
t Z @
& pVJz < 6 f!!
|
Percent 100
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
!
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
t Z @
& pVJz < 6 f!!
|
Percent 100
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
!
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
t Z @
& pVJz < 6 f!!
|
Percent 100
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
!
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
t Z @
& pVJz < 6 f!!
|
Percent 100
|
t 0
"6ք ք ք ք 4 a w$$If T !x^D*
|
!
|
t Z @
& pVJz < 6 f!!
|
|
t 0
"6ք ք ք ք 4 a $$If T xZ V !
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
t 0
"6$ $ $ $ 4 a w$$If T !x^D*
|
Percent 100
|
t Z @
& pVJz < 6 f!!
|
!
|
Q<= Kuy Timing Diagram Timing.Document.1 9q Timing Diagram
|
|
Q<= Kuy Timing Diagram Timing.Document.1 9q Timing Diagram O b j I n f o a C O N T E N T S ~7 _ 1 0 5 0 0 6 8 8 9 7 z d Q<= Kuy @9 O l e
|
CORGROUP $$dwb_CLK_I_BufferRising
|
Timing Diagram Editor v7.1g - Output File
|
Percent 100
|
|
!
|
PROJECT
|
|
BaseTimeUnit 1
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
DisplayTimeUnit 2
|
Percent 100
|
TextGridX 625.000000
|
!
|
TextGridY 6
|
|
EdgeGridX 625.000000
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
ImportStartTime 0.000000
|
Percent 100
|
ImportEndTime 281474976710656.000000
|
!
|
TimePerPixel 17.543860
|
|
Visible DELAYS SETUPS HOLDS SAMPLES TEXT HIDDENATTACHMENTS CRITICALPATHS GRIDLINES UNCERTAINTY
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
ColWidths 144,216,288,423,488
|
Percent 100
|
ScrollPos 0.000000,0.000000,0.000000
|
!
|
DefDelayRule 1
|
|
NoEventOverlap NO
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
SigLabelFontHeight 8
|
Percent 100
|
LabelHeight 10
|
!
|
LoadLibsToMem 1
|
|
UseFullPathNames 1
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
LibPath
|
Percent 100
|
EntireTime YES
|
!
|
PrintTimeSpecified NO
|
|
FromTime 0
|
CORGROUP $$dwb_CLK_I_BufferRising
|
ToTime 15.625
|
Percent 100
|
AllSignals YES
|
!
|
CurrSelSigs NO
|
|
PrintTo 2
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
PrintFileName C:\DOCS\wb_writesingle.wmf
|
Percent 100
|
PreviewInterchange YES
|
!
|
PreviewTIFF5 NO
|
|
UseMargins NO
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
PrintTimeLine NO
|
Percent 100
|
PrintBorderBox YES
|
!
|
PrintSigNames YES
|
|
PrintSigNamesOnEachPage YES
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
AddPreviewToEPS NO
|
Percent 100
|
PreviewRes 150
|
!
|
MarginLR 1
|
|
MifImageWidth 6.00
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
MarginTB Auto
|
Percent 100
|
Header %d %t;%f;%p
|
!
|
Footer
|
|
ScaleHorz 100
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
ScaleVert 100
|
Percent 100
|
ScaleHPage 1
|
!
|
PrintImage DIAGRAM
|
|
DefaultTimingModel minmax
|
CORGROUP $$dwb_CLK_I_BufferRising
|
DefaultClock Unclocked
|
Percent 100
|
DefaultEdgeLevel neg
|
!
|
DefaultSet Not Used
|
|
DefaultClear Not Used
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
DefaultClockEnable Not Used
|
Percent 100
|
DefaultClockToOutLH 0
|
!
|
DefaultClockToOutHL 0
|
|
DefaultSetup 0
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
DefaultHold 0
|
Percent 100
|
DefaultRegStartupState unknown
|
!
|
DefaultPodSize 8
|
|
DefaultActiveLowSetClear True
|
CORGROUP $$CLK_RISC_BufferRising
|
DefaultAsyncSetClear True
|
Percent 100
|
DefaultActiveLowClockEnable True
|
!
|
SigLabelFontHeight 10
|
|
PROPS!
|
CORGROUP $$CLK_RISC_BufferFalling
|
!
|
Percent 100
|
|
!
|
STYLE
|
|
DefaultFont USER {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
DrawWndFont DEFAULT
|
Percent 100
|
DrawWndColor DEFAULT
|
!
|
GridWndFont DEFAULT
|
|
GridWndColor DEFAULT
|
CORGROUP $$dwb_CLK_I_BufferRising
|
LabelWndFont USER {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
|
Percent 100
|
LabelWndColor DEFAULT
|
!
|
ParamDispPref 0
|
|
ParamWndCellDisplay 0
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
CustDispString %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
|
Percent 100
|
CustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
|
!
|
MarkerDispPref 4
|
|
MarkerCustDispString %n v=%mv,%Mv d=%md %t
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
MarkerCustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
|
Percent 100
|
SignalColor 2
|
!
|
LabelOffset 2
|
|
BusDisplay 0
|
CLOCK CLK_RISC
|
WaveFormWidth 0.500000
|
PERIODE 2.5
|
WaveFormColor 0
|
DUTY 50
|
InputWaveFormColor 16711680
|
OFFSETE 0
|
SlantedEdges 1
|
INITIAL HIGH
|
SlantAngle 75
|
MAXUNCERTRISE 0
|
RightJustifySigNames 1
|
MAXUNCERTFALL 0
|
AutosplitEnabled 1
|
MINUNCERTRISE 0
|
AutosplitChar _
|
MINUNCERTFALL 0
|
DynamSizedSignals 1
|
JRISEE 0
|
!
|
JFALLE 0
|
|
GRID 0 1 0 2 0 16711680 0 0
|
DIAGRAMTESTBENCHSETTINGS
|
ENDGRID -1
|
FilesBeforeDiagramModel
|
DIRECTION internal
|
FilesInsideDiagramModelDeclarationSection
|
MASTERCLOCK None
|
AbortHdlCodeEnabled 1
|
Clock Unclocked
|
DelayHdlCodeEnabled 1
|
EdgeLevel neg
|
SampleHdlCodeEnabled 1
|
Set Not Used
|
MarkerHdlCodeEnabled 1
|
Clear Not Used
|
VerboseSamples 0
|
ClockEnable Not Used
|
VerboseDelays 0
|
ActiveLowSetClear True
|
VerboseFileInput 0
|
AsyncSetClear True
|
VerboseSequenceVerification 0
|
ActiveLowClockEnable True
|
IncludeDelayTime 1
|
VhdlType std_logic
|
ExecuteFromTopLevel 1
|
VerilogType wire
|
TimeOutInDiagramLengths 0
|
SystemCType sc_logic
|
DefaultCycleClock Unclocked
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
DefaultCycleEdge neg
|
StateEquation Hex(Inc(0,2,5))
|
!
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
MACROS
|
MSB 0
|
!
|
LSB 0
|
|
isFallingEdgeSensitive False
|
CORGROUP $$CLK_I_BufferRising
|
isRisingEdgeSensitive False
|
Percent 100
|
DrawAnalog 0
|
!
|
BooleanEquation
|
|
NegTolerance 0
|
CORGROUP $$CLK_I_BufferFalling
|
PosTolerance 0
|
Percent 100
|
UserSpecifiedSizeRatio 1
|
!
|
VerilogCode
|
|
VHDLCode
|
CORGROUP $$CLK_I_BufferRisingFalling
|
PROPS!
|
Percent 100
|
!
|
!
|
|
|
CLOCK dwb_CLK_I
|
CORGROUP $$CLK_I_BufferRising
|
PERIODE 5
|
Percent 100
|
DUTY 50
|
!
|
OFFSETE 0
|
|
INITIAL LOW
|
CORGROUP $$CLK_I_BufferFalling
|
MAXUNCERTRISE 0
|
Percent 100
|
MAXUNCERTFALL 0
|
!
|
MINUNCERTRISE 0
|
|
MINUNCERTFALL 0
|
CORGROUP $$CLK_I_BufferRisingFalling
|
JRISEE 0
|
Percent 100
|
JFALLE 0
|
!
|
GRID 1 1 1 2 2 16711680 0 0
|
|
ENDGRID -1
|
CORGROUP $$CLK_I_BufferRising
|
DIRECTION input
|
Percent 100
|
MASTERCLOCK None
|
!
|
Clock Unclocked
|
|
EdgeLevel neg
|
CORGROUP $$CLK_I_BufferFalling
|
Set Not Used
|
Percent 100
|
Clear Not Used
|
!
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
CORGROUP $$CLK_I_BufferRisingFalling
|
AsyncSetClear True
|
Percent 100
|
ActiveLowClockEnable True
|
!
|
VhdlType std_logic
|
|
VerilogType wire
|
CORGROUP $$CLK_I_BufferRising
|
SystemCType sc_logic
|
Percent 100
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
!
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
CORGROUP $$CLK_I_BufferFalling
|
LowVoltageThreshold 0
|
Percent 100
|
MSB 0
|
!
|
LSB 0
|
|
isFallingEdgeSensitive False
|
CORGROUP $$CLK_I_BufferRisingFalling
|
isRisingEdgeSensitive True
|
Percent 100
|
DrawAnalog 0
|
!
|
BooleanEquation
|
|
NegTolerance 0
|
CORGROUP $$CLK_I_BufferRising
|
PosTolerance 0
|
Percent 100
|
UserSpecifiedSizeRatio 1
|
!
|
VerilogCode
|
|
VHDLCode
|
CORGROUP $$CLK_I_BufferFalling
|
PROPS!
|
Percent 100
|
!
|
!
|
|
|
SIGNAL dwb_ADR_O
|
CORGROUP $$CLK_I_BufferRisingFalling
|
DIRECTION output
|
Percent 100
|
RADIX hex
|
!
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
CORGROUP $$CLK_I_BufferRising
|
Clock
|
Percent 100
|
EdgeLevel neg
|
!
|
Set Not Used
|
|
Clear Not Used
|
CORGROUP $$CLK_I_BufferFalling
|
ClockEnable Not Used
|
Percent 100
|
ActiveLowSetClear True
|
!
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
CORGROUP $$CLK_I_BufferRisingFalling
|
VhdlType std_logic
|
Percent 100
|
VerilogType wire
|
!
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
CORGROUP $$CLK_RISC_BufferRising
|
StateEquation Hex(Inc(0,2,5))
|
Percent 100
|
HighVoltageThreshold 5
|
!
|
LowVoltageThreshold 0
|
|
LSB 0
|
CORGROUP $$CLK_RISC_BufferFalling
|
MSB 31
|
Percent 100
|
SignalActionType 0
|
!
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive True
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
DrawAnalog 0
|
Percent 100
|
BooleanEquation
|
!
|
NegTolerance 0
|
|
PosTolerance 0
|
CORGROUP $$CLK_RISC_BufferRising
|
UserSpecifiedSizeRatio 1
|
Percent 100
|
VerilogCode
|
!
|
VHDLCode
|
|
VhdlMapping DefaultVhdlMapping
|
CORGROUP $$CLK_RISC_BufferFalling
|
PROPS!
|
Percent 100
|
E0 V -1 -1 1 0 DR 0
|
!
|
E1 X 3123 3123 1 0 DR 0
|
|
E2 V 13125 13125 A0 1 0 DR 0
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
E3 X 13625 13625 1 0 DR 0
|
Percent 100
|
E4 V 23125 23125 A4 1 0 DR 0
|
!
|
E5 X 23625 23625 1 0 DR 0
|
|
E6 V 33125 33125 A8 1 0 DR 0
|
CORGROUP $$CLK_I_BufferRising
|
E7 X 33625 33625 1 0 DR 0
|
Percent 100
|
E8 V 43125 43125 A12 1 0 DR 0
|
!
|
E9 X 43750 43750 1 0 DR 0
|
|
E10 V 53125 53125 A0 1 0 DR 0
|
CORGROUP $$CLK_I_BufferFalling
|
E11 X 53750 53750 1 0 DR 0
|
Percent 100
|
!
|
!
|
|
|
SIGNAL dwb_DAT_I
|
CORGROUP $$CLK_I_BufferRisingFalling
|
DIRECTION input
|
Percent 100
|
RADIX hex
|
!
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
CORGROUP $$CLK_RISC_BufferRising
|
Clock
|
Percent 100
|
EdgeLevel neg
|
!
|
Set Not Used
|
|
Clear Not Used
|
CORGROUP $$CLK_RISC_BufferFalling
|
ClockEnable Not Used
|
Percent 100
|
ActiveLowSetClear True
|
!
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
VhdlType std_logic
|
Percent 100
|
VerilogType wire
|
!
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
CORGROUP $$CLK_I_BufferRising
|
StateEquation Hex(Inc(0,2,5))
|
Percent 100
|
HighVoltageThreshold 5
|
!
|
LowVoltageThreshold 0
|
|
LSB 0
|
CORGROUP $$CLK_I_BufferFalling
|
MSB 31
|
Percent 100
|
SignalActionType 0
|
!
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
CORGROUP $$CLK_I_BufferRisingFalling
|
DrawAnalog 0
|
Percent 100
|
BooleanEquation
|
!
|
NegTolerance 0
|
|
PosTolerance 0
|
CORGROUP $$CLK_RISC_BufferRising
|
UserSpecifiedSizeRatio 1
|
Percent 100
|
VerilogCode
|
!
|
VHDLCode
|
|
VhdlMapping DefaultVhdlMapping
|
CORGROUP $$CLK_RISC_BufferFalling
|
PROPS!
|
Percent 100
|
E0 X 11250 11250 1 0 DR 0
|
!
|
E1 V 13125 13125 D0 1 0 DR 0
|
|
E2 X 21250 21250 1 0 DR 0
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
E3 V 23125 23125 D4 1 0 DR 0
|
Percent 100
|
E4 X 31250 31250 1 0 DR 0
|
!
|
E5 V 33125 33125 D8 1 0 DR 0
|
|
E6 X 41250 41250 1 0 DR 0
|
CORGROUP $$CLK_I_BufferRising
|
E7 V 43125 43125 D12 1 0 DR 0
|
Percent 100
|
E8 X 53750 53750 1 0 DR 0
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
SIGNAL dwb_DAT_O
|
Percent 100
|
DIRECTION output
|
!
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
CORGROUP $$CLK_I_BufferRisingFalling
|
ENDGRID -1
|
Percent 100
|
Clock Unclocked
|
!
|
EdgeLevel neg
|
|
Set Not Used
|
CORGROUP $$CLK_RISC_BufferRising
|
Clear Not Used
|
Percent 100
|
ClockEnable Not Used
|
!
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
CORGROUP $$CLK_RISC_BufferFalling
|
ActiveLowClockEnable True
|
Percent 100
|
VhdlType std_logic
|
!
|
VerilogType wire
|
|
SystemCType sc_logic
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
Percent 100
|
StateEquation Hex(Inc(0,2,5))
|
!
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
CORGROUP $$CLK_I_BufferRising
|
LSB 0
|
Percent 100
|
MSB 31
|
!
|
SignalActionType 0
|
|
isFallingEdgeSensitive False
|
CORGROUP $$CLK_I_BufferFalling
|
isRisingEdgeSensitive False
|
Percent 100
|
DrawAnalog 0
|
!
|
BooleanEquation
|
|
NegTolerance 0
|
CORGROUP $$CLK_I_BufferRisingFalling
|
PosTolerance 0
|
Percent 100
|
UserSpecifiedSizeRatio 1
|
!
|
VerilogCode
|
|
VHDLCode
|
CORGROUP $$CLK_RISC_BufferRising
|
PROPS!
|
Percent 100
|
E0 X 3125 3125 1 0 DR 0
|
!
|
E1 V 3126 3126 D0 1 0 DR 0
|
|
E2 X 43125 43125 1 0 DR 0
|
CORGROUP $$CLK_RISC_BufferFalling
|
E3 V 53124 53124 D0 1 0 DR 0
|
Percent 100
|
E4 X 53750 53750 1
|
!
|
O ! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~ 0 DR 0
|
|
!
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
SIGNAL dwb_WE_O
|
!
|
DIRECTION output
|
|
RADIX hex
|
CORGROUP $$CLK_I_BufferRising
|
GRID 0 1 0 1 0 16711680 0 0
|
Percent 100
|
ENDGRID -1
|
!
|
Clock Unclocked
|
|
EdgeLevel neg
|
CORGROUP $$CLK_I_BufferFalling
|
Set Not Used
|
Percent 100
|
Clear Not Used
|
!
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
CORGROUP $$CLK_I_BufferRisingFalling
|
AsyncSetClear True
|
Percent 100
|
ActiveLowClockEnable True
|
!
|
VhdlType std_logic
|
|
VerilogType wire
|
CORGROUP $$CLK_RISC_BufferRising
|
SystemCType sc_logic
|
Percent 100
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
!
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
CORGROUP $$CLK_RISC_BufferFalling
|
LowVoltageThreshold 0
|
Percent 100
|
SignalActionType 0
|
!
|
MSB 0
|
|
LSB 0
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
isFallingEdgeSensitive False
|
Percent 100
|
isRisingEdgeSensitive False
|
!
|
DrawAnalog 0
|
|
BooleanEquation
|
CORGROUP $$dwb_CLK_I_BufferRising
|
NegTolerance 0
|
Percent 100
|
PosTolerance 0
|
!
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
VHDLCode
|
Percent 100
|
PROPS!
|
!
|
E0 X 3126 3126 1 0 DR 0
|
|
E1 0 13125 13125 1 0 DR 0
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
E2 X 13625 13625 1 0 DR 0
|
Percent 100
|
E3 0 23125 23125 1 0 DR 0
|
!
|
E4 X 23625 23625 1 0 DR 0
|
|
E5 0 33125 33125 1 0 DR 0
|
CLOCK CLK_RISC
|
E6 X 33750 33750 1 0 DR 0
|
PERIODE 2.5
|
E7 0 43125 43125 1 0 DR 0
|
DUTY 50
|
E8 1 53125 53125 1 0 DR 0
|
OFFSETE 0
|
E9 0 53750 53750 1 0 DR 0
|
INITIAL HIGH
|
!
|
MAXUNCERTRISE 0
|
|
MAXUNCERTFALL 0
|
SIGNAL dwb_SEL_O
|
MINUNCERTRISE 0
|
DIRECTION output
|
MINUNCERTFALL 0
|
RADIX hex
|
JRISEE 0
|
GRID 0 1 0 1 0 16711680 0 0
|
JFALLE 0
|
ENDGRID -1
|
GRID 0 1 0 2 0 16711680 0 0
|
Clock Unclocked
|
ENDGRID -1
|
EdgeLevel neg
|
DIRECTION internal
|
Set Not Used
|
MASTERCLOCK None
|
Clear Not Used
|
Clock Unclocked
|
ClockEnable Not Used
|
EdgeLevel neg
|
ActiveLowSetClear True
|
Set Not Used
|
AsyncSetClear True
|
Clear Not Used
|
ActiveLowClockEnable True
|
ClockEnable Not Used
|
VhdlType std_logic
|
ActiveLowSetClear True
|
VerilogType wire
|
AsyncSetClear True
|
SystemCType sc_logic
|
ActiveLowClockEnable True
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
VhdlType std_logic
|
StateEquation Hex(Inc(0,2,5))
|
VerilogType wire
|
HighVoltageThreshold 5
|
SystemCType sc_logic
|
LowVoltageThreshold 0
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
LSB 0
|
StateEquation Hex(Inc(0,2,5))
|
MSB 3
|
HighVoltageThreshold 5
|
SignalActionType 0
|
LowVoltageThreshold 0
|
isFallingEdgeSensitive False
|
MSB 0
|
isRisingEdgeSensitive False
|
LSB 0
|
DrawAnalog 0
|
isFallingEdgeSensitive False
|
BooleanEquation
|
isRisingEdgeSensitive False
|
NegTolerance 0
|
DrawAnalog 0
|
PosTolerance 0
|
BooleanEquation
|
UserSpecifiedSizeRatio 1
|
NegTolerance 0
|
VerilogCode
|
PosTolerance 0
|
VHDLCode
|
UserSpecifiedSizeRatio 1
|
PROPS!
|
VerilogCode
|
E0 X 3123 3123 1 0 DR 0
|
VHDLCode
|
E1 V 13125 13125 Valid 1 0 DR 0
|
PROPS!
|
E2 X 13625 13625 1 0 DR 0
|
!
|
E3 V 23125 23125 Valid 1 0 DR 0
|
|
E4 X 23625 23625 1 0 DR 0
|
CLOCK dwb_CLK_I
|
E5 V 33125 33125 Valid 1 0 DR 0
|
PERIODE 5
|
E6 X 33625 33625 1 0 DR 0
|
DUTY 50
|
E7 V 43125 43125 Valid 1 0 DR 0
|
OFFSETE 0
|
E8 X 43750 43750 1 0 DR 0
|
INITIAL LOW
|
E9 V 53124 53124 Valid 1 0 DR 0
|
MAXUNCERTRISE 0
|
E10 X 53750 53750 1 0 DR 0
|
MAXUNCERTFALL 0
|
!
|
MINUNCERTRISE 0
|
|
MINUNCERTFALL 0
|
SIGNAL dwb_STB_O
|
JRISEE 0
|
DIRECTION output
|
JFALLE 0
|
RADIX hex
|
GRID 1 1 1 2 2 16711680 0 0
|
GRID 0 1 0 1 0 16711680 0 0
|
ENDGRID -1
|
ENDGRID -1
|
DIRECTION input
|
Clock Unclocked
|
MASTERCLOCK None
|
EdgeLevel neg
|
Clock Unclocked
|
Set Not Used
|
EdgeLevel neg
|
Clear Not Used
|
Set Not Used
|
ClockEnable Not Used
|
Clear Not Used
|
ActiveLowSetClear True
|
ClockEnable Not Used
|
AsyncSetClear True
|
ActiveLowSetClear True
|
ActiveLowClockEnable True
|
AsyncSetClear True
|
VhdlType std_logic
|
ActiveLowClockEnable True
|
VerilogType wire
|
VhdlType std_logic
|
SystemCType sc_logic
|
VerilogType wire
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
SystemCType sc_logic
|
StateEquation Hex(Inc(0,2,5))
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
HighVoltageThreshold 5
|
StateEquation Hex(Inc(0,2,5))
|
LowVoltageThreshold 0
|
HighVoltageThreshold 5
|
SignalActionType 0
|
LowVoltageThreshold 0
|
MSB 0
|
MSB 0
|
LSB 0
|
LSB 0
|
isFallingEdgeSensitive False
|
isFallingEdgeSensitive False
|
isRisingEdgeSensitive False
|
isRisingEdgeSensitive True
|
DrawAnalog 0
|
DrawAnalog 0
|
BooleanEquation
|
BooleanEquation
|
NegTolerance 0
|
NegTolerance 0
|
PosTolerance 0
|
PosTolerance 0
|
UserSpecifiedSizeRatio 1
|
UserSpecifiedSizeRatio 1
|
VerilogCode
|
VerilogCode
|
VHDLCode
|
VHDLCode
|
PROPS!
|
PROPS!
|
E0 0 3750 3750 1 0 DR 0
|
!
|
E1 1 13125 13125 1 0 DR 0
|
|
E2 0 13625 13625 1 0 DR 0
|
SIGNAL dwb_ADR_O
|
E3 1 23125 23125 1 0 DR 0
|
DIRECTION output
|
E4 0 23625 23625 1 0 DR 0
|
RADIX hex
|
E5 1 33125 33125 1 0 DR 0
|
GRID 0 1 0 1 0 16711680 0 0
|
E6 0 33625 33625 1 0 DR 0
|
ENDGRID -1
|
E7 1 43124 43124 1 0 DR 0
|
Clock
|
E8 0 44466 44466 1 0 DR 0
|
EdgeLevel neg
|
E9 1 53124 53124 1 0 DR 0
|
Set Not Used
|
E10 X 53750 53750 1 0 DR 0
|
Clear Not Used
|
!
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
SIGNAL dwb_ACK_I
|
AsyncSetClear True
|
DIRECTION input
|
ActiveLowClockEnable True
|
RADIX hex
|
VhdlType std_logic
|
GRID 0 1 0 1 0 16711680 0 0
|
VerilogType wire
|
ENDGRID -1
|
SystemCType sc_logic
|
Clock Unclocked
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
EdgeLevel neg
|
StateEquation Hex(Inc(0,2,5))
|
Set Not Used
|
HighVoltageThreshold 5
|
Clear Not Used
|
LowVoltageThreshold 0
|
ClockEnable Not Used
|
LSB 0
|
ActiveLowSetClear True
|
MSB 31
|
AsyncSetClear True
|
SignalActionType 0
|
ActiveLowClockEnable True
|
isFallingEdgeSensitive False
|
VhdlType std_logic
|
isRisingEdgeSensitive True
|
VerilogType wire
|
DrawAnalog 0
|
SystemCType sc_logic
|
BooleanEquation
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
NegTolerance 0
|
StateEquation Hex(Inc(0,2,5))
|
PosTolerance 0
|
HighVoltageThreshold 5
|
UserSpecifiedSizeRatio 1
|
LowVoltageThreshold 0
|
VerilogCode
|
SignalActionType 0
|
VHDLCode
|
MSB 0
|
VhdlMapping DefaultVhdlMapping
|
LSB 0
|
PROPS!
|
isFallingEdgeSensitive False
|
E0 V -1 -1 1 0 DR 0
|
isRisingEdgeSensitive False
|
E1 X 3125 3125 1 0 DR 0
|
DrawAnalog 0
|
E2 V 13125 13125 Valid 1 0 DR 0
|
BooleanEquation
|
E3 X 15625 15625 1 0 DR 0
|
NegTolerance 0
|
!
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
SIGNAL dwb_DAT_I
|
VerilogCode
|
DIRECTION input
|
VHDLCode
|
RADIX hex
|
PROPS!
|
GRID 0 1 0 1 0 16711680 0 0
|
E0 0 11250 11250 1 0 DR 0
|
ENDGRID -1
|
E1 1 13125 13125 1 0 DR 0
|
Clock
|
E2 0 21250 21250 1 0 DR 0
|
EdgeLevel neg
|
E3 1 23125 23125 1 0 DR 0
|
Set Not Used
|
E4 0 31250 31250 1 0 DR 0
|
Clear Not Used
|
E5 1 33125 33125 1 0 DR 0
|
ClockEnable Not Used
|
E6 0 41250 41250 1 0 DR 0
|
ActiveLowSetClear True
|
E7 1 43124 43124 1 0 DR 0
|
AsyncSetClear True
|
E8 0 51875 51875 1 0 DR 0
|
ActiveLowClockEnable True
|
E9 1 53124 53124 1 0 DR 0
|
VhdlType std_logic
|
E10 X 53750 53750 1 0 DR 0
|
VerilogType wire
|
!
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
SIGNAL dwb_CYC_O
|
StateEquation Hex(Inc(0,2,5))
|
DIRECTION output
|
HighVoltageThreshold 5
|
RADIX hex
|
LowVoltageThreshold 0
|
GRID 0 1 0 1 0 16711680 0 0
|
LSB 0
|
ENDGRID -1
|
MSB 31
|
Clock Unclocked
|
SignalActionType 0
|
EdgeLevel neg
|
isFallingEdgeSensitive False
|
Set Not Used
|
isRisingEdgeSensitive False
|
Clear Not Used
|
DrawAnalog 0
|
ClockEnable Not Used
|
BooleanEquation
|
ActiveLowSetClear True
|
NegTolerance 0
|
AsyncSetClear True
|
PosTolerance 0
|
ActiveLowClockEnable True
|
UserSpecifiedSizeRatio 1
|
VhdlType std_logic
|
VerilogCode
|
VerilogType wire
|
VHDLCode
|
SystemCType sc_logic
|
VhdlMapping DefaultVhdlMapping
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
PROPS!
|
StateEquation Hex(Inc(0,2,5))
|
E0 X 13125 13125 1 0 DR 0
|
HighVoltageThreshold 5
|
E1 V 13126 13126 Valid 1 0 DR 0
|
LowVoltageThreshold 0
|
E2 X 15625 15625 1 0 DR 0
|
SignalActionType 0
|
!
|
MSB 0
|
|
LSB 0
|
SIGNAL dwb_DAT_O
|
isFallingEdgeSensitive False
|
DIRECTION output
|
isRisingEdgeSensitive False
|
RADIX hex
|
DrawAnalog 0
|
GRID 0 1 0 1 0 16711680 0 0
|
BooleanEquation
|
ENDGRID -1
|
NegTolerance 0
|
Clock Unclocked
|
PosTolerance 0
|
EdgeLevel neg
|
UserSpecifiedSizeRatio 1
|
Set Not Used
|
VerilogCode
|
Clear Not Used
|
VHDLCode
|
ClockEnable Not Used
|
PROPS!
|
ActiveLowSetClear True
|
E0 0 3125 3125 1 0 DR 0
|
AsyncSetClear True
|
E1 1 43125 43125 1 0 DR 0
|
ActiveLowClockEnable True
|
E2 0 44375 44375 1 0 DR 0
|
VhdlType std_logic
|
E3 1 53125 53125 1 0 DR 0
|
VerilogType wire
|
E4 0 53750 53750 1 0 DR 0
|
SystemCType sc_logic
|
!
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
SIGNAL dwb_ERR_I
|
HighVoltageThreshold 5
|
DIRECTION input
|
LowVoltageThreshold 0
|
RADIX hex
|
LSB 0
|
GRID 0 1 0 1 0 16711680 0 0
|
MSB 31
|
ENDGRID -1
|
SignalActionType 0
|
Clock Unclocked
|
isFallingEdgeSensitive False
|
EdgeLevel neg
|
isRisingEdgeSensitive False
|
Set Not Used
|
DrawAnalog 0
|
Clear Not Used
|
BooleanEquation
|
ClockEnable Not Used
|
NegTolerance 0
|
ActiveLowSetClear True
|
PosTolerance 0
|
AsyncSetClear True
|
UserSpecifiedSizeRatio 1
|
ActiveLowClockEnable True
|
VerilogCode
|
VhdlType std_logic
|
VHDLCode
|
VerilogType wire
|
PROPS!
|
SystemCType sc_logic
|
E0 X 3125 3125 1 0 DR 0
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
E1 V 13125 13125 Valid 1 0 DR 0
|
StateEquation Hex(Inc(0,2,5))
|
E2 X 15625 15625 1 0 DR 0
|
HighVoltageThreshold 5
|
!
|
LowVoltageThreshold 0
|
|
SignalActionType 0
|
SIGNAL dwb_WE_O
|
MSB 0
|
DIRECTION output
|
LSB 0
|
RADIX hex
|
isFallingEdgeSensitive False
|
GRID 0 1 0 1 0 16711680 0 0
|
isRisingEdgeSensitive False
|
ENDGRID -1
|
DrawAnalog 0
|
Clock Unclocked
|
BooleanEquation
|
EdgeLevel neg
|
NegTolerance 0
|
Set Not Used
|
PosTolerance 0
|
Clear Not Used
|
UserSpecifiedSizeRatio 1
|
ClockEnable Not Used
|
VerilogCode
|
ActiveLowSetClear True
|
VHDLCode
|
AsyncSetClear True
|
PROPS!
|
ActiveLowClockEnable True
|
E0 0 53125 53125 1 0 DR 0
|
VhdlType std_logic
|
E1 X 53750 53750 1 0 DR 0
|
VerilogType wire
|
!
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
SIGNAL dwb_RTY_I
|
StateEquation Hex(Inc(0,2,5))
|
DIRECTION input
|
HighVoltageThreshold 5
|
RADIX hex
|
LowVoltageThreshold 0
|
GRID 0 1 0 1 0 16711680 0 0
|
SignalActionType 0
|
ENDGRID -1
|
MSB 0
|
Clock Unclocked
|
LSB 0
|
EdgeLevel neg
|
isFallingEdgeSensitive False
|
Set Not Used
|
isRisingEdgeSensitive False
|
Clear Not Used
|
DrawAnalog 0
|
ClockEnable Not Used
|
BooleanEquation
|
ActiveLowSetClear True
|
NegTolerance 0
|
AsyncSetClear True
|
PosTolerance 0
|
ActiveLowClockEnable True
|
UserSpecifiedSizeRatio 1
|
VhdlType std_logic
|
VerilogCode
|
VerilogType wire
|
VHDLCode
|
SystemCType sc_logic
|
PROPS!
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
E0 X 3125 3125 1 0 DR 0
|
StateEquation Hex(Inc(0,2,5))
|
E1 0 3467 3467 1 0 DR 0
|
HighVoltageThreshold 5
|
E2 1 13125 13125 1 0 DR 0
|
LowVoltageThreshold 0
|
E3 0 13126 13126 1 0 DR 0
|
SignalActionType 0
|
E4 X 15625 15625 1 0 DR 0
|
MSB 0
|
!
|
LSB 0
|
|
isFallingEdgeSensitive False
|
SIGNAL dwb_SEL_O
|
isRisingEdgeSensitive False
|
DIRECTION output
|
DrawAnalog 0
|
RADIX hex
|
BooleanEquation
|
GRID 0 1 0 1 0 16711680 0 0
|
NegTolerance 0
|
ENDGRID -1
|
PosTolerance 0
|
Clock Unclocked
|
UserSpecifiedSizeRatio 1
|
EdgeLevel neg
|
VerilogCode
|
Set Not Used
|
VHDLCode
|
Clear Not Used
|
PROPS!
|
ClockEnable Not Used
|
E0 0 53125 53125 1 0 DR 0
|
ActiveLowSetClear True
|
E1 X 53750 53750 1 0 DR 0
|
AsyncSetClear True
|
!
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
MARKER MARK1
|
VerilogType wire
|
ATTACH dwb_SEL_O NULL S6
|
SystemCType sc_logic
|
TIME 17500.000000
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
RELATIVETIME 0.000000
|
StateEquation Hex(Inc(0,2,5))
|
DISPLAYAS 5
|
HighVoltageThreshold 5
|
MARKERTYPE Timebreak(Curved)
|
LowVoltageThreshold 0
|
WHILERETURN
|
LSB 0
|
REPEATNUMBER
|
MSB 3
|
SNAPTO 0
|
SignalActionType 0
|
COMPRESSTIME 0.000000
|
isFallingEdgeSensitive False
|
COMMENT
|
isRisingEdgeSensitive False
|
!
|
DrawAnalog 0
|
|
BooleanEquation
|
MARKER MARK2
|
NegTolerance 0
|
ATTACH dwb_STB_O NULL S7
|
PosTolerance 0
|
TIME 27500.000000
|
UserSpecifiedSizeRatio 1
|
RELATIVETIME 0.000000
|
VerilogCode
|
DISPLAYAS 5
|
VHDLCode
|
MARKERTYPE Timebreak(Curved)
|
PROPS!
|
WHILERETURN
|
E0 X 3125 3125 1 0 DR 0
|
REPEATNUMBER
|
E1 V 13125 13125 Valid 1 0 DR 0
|
SNAPTO 0
|
E2 X 15625 15625 1 0 DR 0
|
COMPRESSTIME 0.000000
|
!
|
COMMENT
|
|
!
|
SIGNAL dwb_STB_O
|
|
DIRECTION output
|
MARKER MARK3
|
RADIX hex
|
ATTACH dwb_STB_O NULL S7
|
GRID 0 1 0 1 0 16711680 0 0
|
TIME 37500.000000
|
ENDGRID -1
|
RELATIVETIME 0.000000
|
Clock Unclocked
|
DISPLAYAS 5
|
EdgeLevel neg
|
MARKERTYPE Timebreak(Curved)
|
Set Not Used
|
WHILERETURN
|
Clear Not Used
|
REPEATNUMBER
|
ClockEnable Not Used
|
SNAPTO 0
|
ActiveLowSetClear True
|
COMPRESSTIME 0.000000
|
AsyncSetClear True
|
COMMENT
|
ActiveLowClockEnable True
|
!
|
VhdlType std_logic
|
|
VerilogType wire
|
MARKER MARK0
|
SystemCType sc_logic
|
ATTACH dwb_CLK_I NULL S1
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
TIME 7500.000000
|
StateEquation Hex(Inc(0,2,5))
|
RELATIVETIME 0.000000
|
HighVoltageThreshold 5
|
DISPLAYAS 5
|
LowVoltageThreshold 0
|
MARKERTYPE Timebreak(Curved)
|
SignalActionType 0
|
WHILERETURN
|
MSB 0
|
REPEATNUMBER
|
LSB 0
|
SNAPTO 0
|
isFallingEdgeSensitive False
|
COMPRESSTIME 0.000000
|
isRisingEdgeSensitive False
|
COMMENT
|
DrawAnalog 0
|
!
|
BooleanEquation
|
|
NegTolerance 0
|
MARKER MARK4
|
PosTolerance 0
|
ATTACH dwb_ADR_O NULL S2
|
UserSpecifiedSizeRatio 1
|
TIME 47500.000000
|
VerilogCode
|
RELATIVETIME 0.000000
|
VHDLCode
|
DISPLAYAS 5
|
PROPS!
|
MARKERTYPE Timebreak(Curved)
|
E0 0 3125 3125 1 0 DR 0
|
WHILERETURN
|
E1 1 13125 13125 1 0 DR 0
|
REPEATNUMBER
|
E2 0 15625 15625 1 0 DR 0
|
SNAPTO 0
|
!
|
COMPRESSTIME 0.000000
|
|
COMMENT
|
SIGNAL dwb_ACK_I
|
!
|
DIRECTION input
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
Q<= Kuy Timing Diagram Timing.Document.1 9q Timing Diagram
|
ENDGRID -1
|
Q<= Kuy Timing Diagram Timing.Document.1 9q Timing Diagram Timing Diagram Editor v7.1g - Output File
|
Clock Unclocked
|
|
EdgeLevel neg
|
PROJECT
|
Set Not Used
|
BaseTimeUnit 1
|
Clear Not Used
|
DisplayTimeUnit 2
|
ClockEnable Not Used
|
TextGridX 625.000000
|
ActiveLowSetClear True
|
TextGridY 6
|
AsyncSetClear True
|
EdgeGridX 625.000000
|
ActiveLowClockEnable True
|
ImportStartTime 0.000000
|
VhdlType std_logic
|
ImportEndTime 281474976710656.000000
|
VerilogType wire
|
TimePerPixel 50.000000
|
SystemCType sc_logic
|
Visible DELAYS SETUPS HOLDS SAMPLES TEXT HIDDENATTACHMENTS CRITICALPATHS GRIDLINES UNCERTAINTY
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
ColWidths 144,216,288,423,488
|
StateEquation Hex(Inc(0,2,5))
|
ScrollPos 0.000000,0.000000,0.000000
|
HighVoltageThreshold 5
|
DefDelayRule 1
|
LowVoltageThreshold 0
|
NoEventOverlap NO
|
SignalActionType 0
|
SigLabelFontHeight 10
|
MSB 0
|
LabelHeight 12
|
LSB 0
|
LoadLibsToMem 1
|
isFallingEdgeSensitive False
|
UseFullPathNames 1
|
isRisingEdgeSensitive False
|
LibPath
|
DrawAnalog 0
|
EntireTime YES
|
BooleanEquation
|
PrintTimeSpecified NO
|
NegTolerance 0
|
FromTime 0
|
PosTolerance 0
|
ToTime 43.75
|
UserSpecifiedSizeRatio 1
|
AllSignals YES
|
VerilogCode
|
CurrSelSigs NO
|
VHDLCode
|
PrintTo 2
|
PROPS!
|
PrintFileName C:\DOCS\wb_readblock_typ.wmf
|
E0 0 11250 11250 1 0 DR 0
|
PreviewInterchange YES
|
E1 1 13125 13125 1 0 DR 0
|
PreviewTIFF5 NO
|
E2 0 15625 15625 1 0 DR 0
|
UseMargins NO
|
!
|
PrintTimeLine NO
|
|
PrintBorderBox YES
|
SIGNAL dwb_CYC_O
|
PrintSigNames YES
|
DIRECTION output
|
PrintSigNamesOnEachPage YES
|
RADIX hex
|
AddPreviewToEPS NO
|
GRID 0 1 0 1 0 16711680 0 0
|
PreviewRes 150
|
ENDGRID -1
|
MarginLR 1.25
|
Clock Unclocked
|
MifImageWidth 6.00
|
EdgeLevel neg
|
MarginTB Auto
|
Set Not Used
|
Header %d %t;%f;%p
|
Clear Not Used
|
Footer
|
ClockEnable Not Used
|
ScaleHorz 100
|
ActiveLowSetClear True
|
ScaleVert 100
|
AsyncSetClear True
|
ScaleHPage 1
|
ActiveLowClockEnable True
|
PrintImage DIAGRAM
|
VhdlType std_logic
|
DefaultTimingModel minmax
|
VerilogType wire
|
DefaultClock Unclocked
|
SystemCType sc_logic
|
DefaultEdgeLevel neg
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
DefaultSet Not Used
|
StateEquation Hex(Inc(0,2,5))
|
DefaultClear Not Used
|
HighVoltageThreshold 5
|
DefaultClockEnable Not Used
|
LowVoltageThreshold 0
|
DefaultClockToOutLH 0
|
SignalActionType 0
|
DefaultClockToOutHL 0
|
MSB 0
|
DefaultSetup 0
|
LSB 0
|
DefaultHold 0
|
isFallingEdgeSensitive False
|
DefaultRegStartupState unknown
|
isRisingEdgeSensitive False
|
DefaultPodSize 8
|
DrawAnalog 0
|
DefaultActiveLowSetClear True
|
BooleanEquation
|
DefaultAsyncSetClear True
|
NegTolerance 0
|
DefaultActiveLowClockEnable True
|
PosTolerance 0
|
SigLabelFontHeight 10
|
UserSpecifiedSizeRatio 1
|
PROPS!
|
VerilogCode
|
!
|
VHDLCode
|
|
PROPS!
|
STYLE
|
E0 0 3125 3125 1 0 DR 0
|
DefaultFont USER {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
|
E1 1 13125 13125 1 0 DR 0
|
DrawWndFont DEFAULT
|
E2 0 15625 15625 1 0 DR 0
|
DrawWndColor DEFAULT
|
!
|
GridWndFont DEFAULT
|
|
GridWndColor DEFAULT
|
SIGNAL dwb_ERR_I
|
LabelWndFont USER {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
|
DIRECTION input
|
LabelWndColor DEFAULT
|
RADIX hex
|
ParamDispPref 0
|
GRID 0 1 0 1 0 16711680 0 0
|
ParamWndCellDisplay 0
|
ENDGRID -1
|
CustDispString %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
|
Clock Unclocked
|
CustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
|
EdgeLevel neg
|
MarkerDispPref 4
|
Set Not Used
|
MarkerCustDispString %n v=%mv,%Mv d=%md %t
|
Clear Not Used
|
MarkerCustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
|
ClockEnable Not Used
|
SignalColor 2
|
ActiveLowSetClear True
|
LabelOffset 2
|
AsyncSetClear True
|
BusDisplay 0
|
ActiveLowClockEnable True
|
WaveFormWidth 0.500000
|
VhdlType std_logic
|
WaveFormColor 0
|
VerilogType wire
|
InputWaveFormColor 16711680
|
SystemCType sc_logic
|
SlantedEdges 1
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
SlantAngle 75
|
StateEquation Hex(Inc(0,2,5))
|
RightJustifySigNames 1
|
HighVoltageThreshold 5
|
AutosplitEnabled 1
|
LowVoltageThreshold 0
|
AutosplitChar _
|
SignalActionType 0
|
DynamSizedSignals 1
|
MSB 0
|
!
|
LSB 0
|
|
isFallingEdgeSensitive False
|
DIAGRAMTESTBENCHSETTINGS
|
isRisingEdgeSensitive False
|
FilesBeforeDiagramModel
|
DrawAnalog 0
|
FilesInsideDiagramModelDeclarationSection
|
BooleanEquation
|
AbortHdlCodeEnabled 1
|
NegTolerance 0
|
DelayHdlCodeEnabled 1
|
PosTolerance 0
|
SampleHdlCodeEnabled 1
|
UserSpecifiedSizeRatio 1
|
MarkerHdlCodeEnabled 1
|
VerilogCode
|
VerboseSamples 0
|
VHDLCode
|
VerboseDelays 0
|
PROPS!
|
VerboseFileInput 0
|
E0 0 15625 15625 1 0 DR 0
|
VerboseSequenceVerification 0
|
!
|
IncludeDelayTime 1
|
|
ExecuteFromTopLevel 1
|
SIGNAL dwb_RTY_I
|
TimeOutInDiagramLengths 0
|
DIRECTION input
|
DefaultCycleClock Unclocked
|
RADIX hex
|
DefaultCycleEdge neg
|
GRID 0 1 0 1 0 16711680 0 0
|
!
|
ENDGRID -1
|
|
Clock Unclocked
|
MACROS
|
EdgeLevel neg
|
!
|
Set Not Used
|
|
Clear Not Used
|
CORGROUP $$CLK_I_BufferRising
|
ClockEnable Not Used
|
Percent 100
|
ActiveLowSetClear True
|
!
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
CORGROUP $$CLK_I_BufferFalling
|
VhdlType std_logic
|
Percent 100
|
VerilogType wire
|
!
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
CORGROUP $$CLK_I_BufferRisingFalling
|
StateEquation Hex(Inc(0,2,5))
|
Percent 100
|
HighVoltageThreshold 5
|
!
|
LowVoltageThreshold 0
|
|
SignalActionType 0
|
CORGROUP $$CLK_I_BufferRising
|
MSB 0
|
Percent 100
|
LSB 0
|
!
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
CORGROUP $$CLK_I_BufferFalling
|
DrawAnalog 0
|
Percent 100
|
BooleanEquation
|
!
|
NegTolerance 0
|
|
PosTolerance 0
|
CORGROUP $$CLK_I_BufferRisingFalling
|
UserSpecifiedSizeRatio 1
|
Percent 100
|
VerilogCode
|
!
|
VHDLCode
|
|
PROPS!
|
CORGROUP $$CLK_I_BufferRising
|
E0 0 15625 15625 1 0 DR 0
|
Percent 100
|
!
|
!
|
|
|
MARKER MARK0
|
CORGROUP $$CLK_I_BufferFalling
|
ATTACH dwb_DAT_O NULL S4
|
Percent 100
|
TIME 7500.000000
|
!
|
RELATIVETIME 0.000000
|
|
DISPLAYAS 5
|
CORGROUP $$CLK_I_BufferRisingFalling
|
MARKERTYPE Timebreak(Curved)
|
Percent 100
|
WHILERETURN
|
!
|
REPEATNUMBER
|
|
SNAPTO 0
|
CORGROUP $$CLK_I_BufferRising
|
COMPRESSTIME 0.000000
|
Percent 100
|
COMMENT
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
C o m p O b j c e i O b j I n f o f C O N T E N T S K _ 1 0 5 0 0 6 8 8 1 9 ] b i Q<= Kuy Timing Diagram Editor v7.1g - Output File
|
Percent 100
|
|
!
|
PROJECT
|
|
BaseTimeUnit 1
|
CORGROUP $$CLK_I_BufferRisingFalling
|
DisplayTimeUnit 2
|
Percent 100
|
TextGridX 625.000000
|
!
|
TextGridY 6
|
|
EdgeGridX 625.000000
|
CORGROUP $$CLK_I_BufferRising
|
ImportStartTime 0.000000
|
Percent 100
|
ImportEndTime 281474976710656.000000
|
!
|
TimePerPixel 50.000000
|
|
Visible DELAYS SETUPS HOLDS SAMPLES TEXT HIDDENATTACHMENTS CRITICALPATHS GRIDLINES UNCERTAINTY
|
CORGROUP $$CLK_I_BufferFalling
|
ColWidths 144,216,288,423,488
|
Percent 100
|
ScrollPos 0.000000,0.000000,0.000000
|
!
|
DefDelayRule 1
|
|
NoEventOverlap NO
|
CORGROUP $$CLK_I_BufferRisingFalling
|
SigLabelFontHeight 10
|
Percent 100
|
LabelHeight 12
|
!
|
LoadLibsToMem 1
|
|
UseFullPathNames 1
|
CORGROUP $$CLK_I_BufferRising
|
LibPath
|
Percent 100
|
EntireTime YES
|
!
|
PrintTimeSpecified NO
|
|
FromTime 0
|
CORGROUP $$CLK_I_BufferFalling
|
ToTime 43.75
|
Percent 100
|
AllSignals YES
|
!
|
CurrSelSigs NO
|
|
PrintTo 2
|
CORGROUP $$CLK_I_BufferRisingFalling
|
PrintFileName C:\DOCS\wb_readblock_typ.wmf
|
Percent 100
|
PreviewInterchange YES
|
!
|
PreviewTIFF5 NO
|
|
UseMargins NO
|
CORGROUP $$CLK_RISC_BufferRising
|
PrintTimeLine NO
|
Percent 100
|
PrintBorderBox YES
|
!
|
PrintSigNames YES
|
|
PrintSigNamesOnEachPage YES
|
CORGROUP $$CLK_RISC_BufferFalling
|
AddPreviewToEPS NO
|
Percent 100
|
PreviewRes 150
|
!
|
MarginLR 1.25
|
|
MifImageWidth 6.00
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
MarginTB Auto
|
Percent 100
|
Header %d %t;%f;%p
|
!
|
Footer
|
|
ScaleHorz 100
|
CORGROUP $$CLK_RISC_BufferRising
|
ScaleVert 100
|
Percent 100
|
ScaleHPage 1
|
!
|
PrintImage DIAGRAM
|
|
DefaultTimingModel minmax
|
CORGROUP $$CLK_RISC_BufferFalling
|
DefaultClock Unclocked
|
Percent 100
|
DefaultEdgeLevel neg
|
!
|
DefaultSet Not Used
|
|
DefaultClear Not Used
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
DefaultClockEnable Not Used
|
Percent 100
|
DefaultClockToOutLH 0
|
!
|
DefaultClockToOutHL 0
|
|
DefaultSetup 0
|
CORGROUP $$CLK_I_BufferRising
|
DefaultHold 0
|
Percent 100
|
DefaultRegStartupState unknown
|
!
|
DefaultPodSize 8
|
|
DefaultActiveLowSetClear True
|
CORGROUP $$CLK_I_BufferFalling
|
DefaultAsyncSetClear True
|
Percent 100
|
DefaultActiveLowClockEnable True
|
!
|
SigLabelFontHeight 10
|
|
PROPS!
|
CORGROUP $$CLK_I_BufferRisingFalling
|
!
|
Percent 100
|
|
!
|
STYLE
|
|
DefaultFont USER {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
|
CORGROUP $$CLK_RISC_BufferRising
|
DrawWndFont DEFAULT
|
Percent 100
|
DrawWndColor DEFAULT
|
!
|
GridWndFont DEFAULT
|
|
GridWndColor DEFAULT
|
CORGROUP $$CLK_RISC_BufferFalling
|
LabelWndFont USER {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
|
Percent 100
|
LabelWndColor DEFAULT
|
!
|
ParamDispPref 0
|
|
ParamWndCellDisplay 0
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CustDispString %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
|
Percent 100
|
CustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
|
!
|
MarkerDispPref 4
|
|
MarkerCustDispString %n v=%mv,%Mv d=%md %t
|
CORGROUP $$CLK_I_BufferRising
|
MarkerCustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
|
Percent 100
|
SignalColor 2
|
!
|
LabelOffset 2
|
|
BusDisplay 0
|
CORGROUP $$CLK_I_BufferFalling
|
WaveFormWidth 0.500000
|
Percent 100
|
WaveFormColor 0
|
!
|
InputWaveFormColor 16711680
|
|
SlantedEdges 1
|
CORGROUP $$CLK_I_BufferRisingFalling
|
SlantAngle 75
|
Percent 100
|
RightJustifySigNames 1
|
!
|
AutosplitEnabled 1
|
|
AutosplitChar _
|
CORGROUP $$CLK_RISC_BufferRising
|
DynamSizedSignals 1
|
Percent 100
|
!
|
!
|
|
|
DIAGRAMTESTBENCHSETTINGS
|
CORGROUP $$CLK_RISC_BufferFalling
|
FilesBeforeDiagramModel
|
Percent 100
|
FilesInsideDiagramModelDeclarationSection
|
!
|
AbortHdlCodeEnabled 1
|
|
DelayHdlCodeEnabled 1
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
SampleHdlCodeEnabled 1
|
Percent 100
|
MarkerHdlCodeEnabled 1
|
!
|
VerboseSamples 0
|
|
VerboseDelays 0
|
CORGROUP $$CLK_I_BufferRising
|
VerboseFileInput 0
|
Percent 100
|
VerboseSequenceVerification 0
|
!
|
IncludeDelayTime 1
|
|
ExecuteFromTopLevel 1
|
CORGROUP $$CLK_I_BufferFalling
|
TimeOutInDiagramLengths 0
|
Percent 100
|
DefaultCycleClock Unclocked
|
!
|
DefaultCycleEdge neg
|
|
!
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
MACROS
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
CORGROUP $$CLK_I_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
CORGROUP $$CLK_I_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRising
|
CORGROUP $$CLK_I_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
CORGROUP $$CLK_I_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
CORGROUP $$CLK_I_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
CORGROUP $$CLK_I_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRising
|
CORGROUP $$CLK_I_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
CORGROUP $$CLK_I_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
CORGROUP $$CLK_I_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
CORGROUP $$CLK_I_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRising
|
CORGROUP $$CLK_I_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
CORGROUP $$CLK_I_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
CORGROUP $$CLK_RISC_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
CORGROUP $$CLK_RISC_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRising
|
CORGROUP $$CLK_RISC_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
CORGROUP $$CLK_RISC_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
CORGROUP $$CLK_I_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
CORGROUP $$CLK_I_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRising
|
CORGROUP $$CLK_RISC_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
CORGROUP $$CLK_RISC_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
CORGROUP $$CLK_I_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
CORGROUP $$CLK_I_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRising
|
CORGROUP $$CLK_RISC_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
CORGROUP $$CLK_RISC_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
CORGROUP $$CLK_I_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
CORGROUP $$CLK_I_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRising
|
CORGROUP $$CLK_RISC_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
CORGROUP $$CLK_RISC_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
CORGROUP $$CLK_I_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
CORGROUP $$CLK_I_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRising
|
CORGROUP $$CLK_RISC_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
CORGROUP $$CLK_RISC_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
CORGROUP $$CLK_I_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
CORGROUP $$CLK_I_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$dwb_CLK_I_BufferRising
|
CORGROUP $$CLK_RISC_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
CORGROUP $$CLK_RISC_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
CORGROUP $$CLK_I_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
CORGROUP $$CLK_I_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$dwb_CLK_I_BufferRising
|
CORGROUP $$CLK_RISC_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
CORGROUP $$CLK_RISC_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
CORGROUP $$CLK_I_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
CORGROUP $$CLK_I_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$dwb_CLK_I_BufferRising
|
CORGROUP $$CLK_RISC_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
CORGROUP $$CLK_RISC_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
CORGROUP $$CLK_I_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
CORGROUP $$CLK_I_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$dwb_CLK_I_BufferRising
|
CORGROUP $$CLK_RISC_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
CORGROUP $$CLK_RISC_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
CORGROUP $$CLK_I_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
CORGROUP $$CLK_I_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$dwb_CLK_I_BufferRising
|
CORGROUP $$CLK_RISC_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
CORGROUP $$CLK_RISC_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
CORGROUP $$CLK_I_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
CORGROUP $$CLK_I_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$dwb_CLK_I_BufferRising
|
CORGROUP $$CLK_RISC_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
CORGROUP $$CLK_RISC_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CLOCK CLK_RISC
|
CORGROUP $$CLK_I_BufferRising
|
PERIODE 2.5
|
Percent 100
|
DUTY 50
|
!
|
OFFSETE 0
|
|
INITIAL HIGH
|
CORGROUP $$CLK_I_BufferFalling
|
MAXUNCERTRISE 0
|
Percent 100
|
MAXUNCERTFALL 0
|
!
|
MINUNCERTRISE 0
|
|
MINUNCERTFALL 0
|
CORGROUP $$CLK_I_BufferRisingFalling
|
JRISEE 0
|
Percent 100
|
JFALLE 0
|
!
|
GRID 0 1 0 2 0 16711680 0 0
|
|
ENDGRID -1
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
DIRECTION internal
|
Percent 100
|
MASTERCLOCK None
|
!
|
Clock Unclocked
|
|
EdgeLevel neg
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
Set Not Used
|
Percent 100
|
Clear Not Used
|
!
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
AsyncSetClear True
|
Percent 100
|
ActiveLowClockEnable True
|
!
|
VhdlType std_logic
|
|
VerilogType wire
|
CORGROUP $$dwb_CLK_I_BufferRising
|
SystemCType sc_logic
|
Percent 100
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
!
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
LowVoltageThreshold 0
|
Percent 100
|
MSB 0
|
!
|
LSB 0
|
|
isFallingEdgeSensitive False
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
isRisingEdgeSensitive False
|
Percent 100
|
DrawAnalog 0
|
!
|
BooleanEquation
|
|
NegTolerance 0
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
PosTolerance 0
|
Percent 100
|
UserSpecifiedSizeRatio 1
|
!
|
VerilogCode
|
|
VHDLCode
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
PROPS!
|
Percent 100
|
!
|
!
|
|
|
CLOCK dwb_CLK_I
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
PERIODE 5
|
Percent 100
|
DUTY 50
|
!
|
OFFSETE 0
|
|
INITIAL LOW
|
CORGROUP $$dwb_CLK_I_BufferRising
|
MAXUNCERTRISE 0
|
Percent 100
|
MAXUNCERTFALL 0
|
!
|
MINUNCERTRISE 0
|
|
MINUNCERTFALL 0
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
JRISEE 0
|
Percent 100
|
JFALLE 0
|
!
|
GRID 1 1 1 2 2 16711680 0 0
|
|
ENDGRID -1
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
DIRECTION input
|
Percent 100
|
MASTERCLOCK None
|
!
|
Clock Unclocked
|
|
EdgeLevel neg
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
Set Not Used
|
Percent 100
|
Clear Not Used
|
!
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
AsyncSetClear True
|
Percent 100
|
ActiveLowClockEnable True
|
!
|
VhdlType std_logic
|
|
VerilogType wire
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
SystemCType sc_logic
|
Percent 100
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
!
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
CORGROUP $$dwb_CLK_I_BufferRising
|
LowVoltageThreshold 0
|
Percent 100
|
MSB 0
|
!
|
LSB 0
|
|
isFallingEdgeSensitive False
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
isRisingEdgeSensitive True
|
Percent 100
|
DrawAnalog 0
|
!
|
BooleanEquation
|
|
NegTolerance 0
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
PosTolerance 0
|
Percent 100
|
UserSpecifiedSizeRatio 1
|
!
|
VerilogCode
|
|
VHDLCode
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
PROPS!
|
Percent 100
|
!
|
!
|
|
|
SIGNAL dwb_ADR_O
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
DIRECTION output
|
Percent 100
|
RADIX hex
|
!
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
Clock
|
Percent 100
|
EdgeLevel neg
|
!
|
Set Not Used
|
|
Clear Not Used
|
CORGROUP $$dwb_CLK_I_BufferRising
|
ClockEnable Not Used
|
Percent 100
|
ActiveLowSetClear True
|
!
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
VhdlType std_logic
|
Percent 100
|
VerilogType wire
|
!
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
StateEquation Hex(Inc(0,2,5))
|
Percent 100
|
HighVoltageThreshold 5
|
!
|
LowVoltageThreshold 0
|
|
LSB 0
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
MSB 31
|
Percent 100
|
SignalActionType 0
|
!
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive True
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
DrawAnalog 0
|
Percent 100
|
BooleanEquation
|
!
|
NegTolerance 0
|
|
PosTolerance 0
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
UserSpecifiedSizeRatio 1
|
Percent 100
|
VerilogCode
|
!
|
VHDLCode
|
|
VhdlMapping DefaultVhdlMapping
|
CORGROUP $$dwb_CLK_I_BufferRising
|
PROPS!
|
Percent 100
|
E0 V -1 -1 1 0 DR 0
|
!
|
E1 X 3125 3125 1 0 DR 0
|
|
E2 V 3126 3126 A0 1 0 DR 0
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
E3 X 3750 3750 1 0 DR 0
|
Percent 100
|
E4 V 13125 13125 A0 1 0 DR 0
|
!
|
E5 X 13625 13625 1 0 DR 0
|
|
E6 V 23125 23125 A4 1 0 DR 0
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
E7 X 23625 23625 1 0 DR 0
|
Percent 100
|
E8 V 33125 33125 A8 1 0 DR 0
|
!
|
E9 X 33625 33625 1 0 DR 0
|
|
E10 V 43125 43125 A12 1 0 DR 0
|
CORGROUP $$CLK_RISC_BufferRising
|
E11 X 43750 43750 1 0 DR 0
|
Percent 100
|
!
|
!
|
|
|
SIGNAL dwb_DAT_I
|
CORGROUP $$CLK_RISC_BufferFalling
|
DIRECTION input
|
Percent 100
|
RADIX hex
|
!
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
Clock
|
Percent 100
|
EdgeLevel neg
|
!
|
Set Not Used
|
|
Clear Not Used
|
CORGROUP $$dwb_CLK_I_BufferRising
|
ClockEnable Not Used
|
Percent 100
|
ActiveLowSetClear True
|
!
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
VhdlType std_logic
|
Percent 100
|
VerilogType wire
|
!
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
StateEquation Hex(Inc(0,2,5))
|
Percent 100
|
HighVoltageThreshold 5
|
!
|
LowVoltageThreshold 0
|
|
LSB 0
|
CLOCK CLK_RISC
|
MSB 31
|
PERIODE 2.5
|
SignalActionType 0
|
DUTY 50
|
isFallingEdgeSensitive False
|
OFFSETE 0
|
isRisingEdgeSensitive False
|
INITIAL HIGH
|
DrawAnalog 0
|
MAXUNCERTRISE 0
|
BooleanEquation
|
MAXUNCERTFALL 0
|
NegTolerance 0
|
MINUNCERTRISE 0
|
PosTolerance 0
|
MINUNCERTFALL 0
|
UserSpecifiedSizeRatio 1
|
JRISEE 0
|
VerilogCode
|
JFALLE 0
|
VHDLCode
|
GRID 0 1 0 2 0 16711680 0 0
|
VhdlMapping DefaultVhdlMapping
|
ENDGRID -1
|
PROPS!
|
DIRECTION internal
|
E0 X 11250 11250 1 0 DR 0
|
MASTERCLOCK None
|
E1 V 13125 13125 D0 1 0 DR 0
|
Clock Unclocked
|
E2 X 21250 21250 1 0 DR 0
|
EdgeLevel neg
|
E3 V 23125 23125 D4 1 0 DR 0
|
Set Not Used
|
E4 X 31250 31250 1 0 DR 0
|
Clear Not Used
|
E5 V 33125 33125 D8 1 0 DR 0
|
ClockEnable Not Used
|
E6 X 41250 41250 1 0 DR 0
|
ActiveLowSetClear True
|
E7 V 43125 43125 D12 1 0 DR 0
|
AsyncSetClear True
|
E8 X 43750 43750 1 0 DR 0
|
ActiveLowClockEnable True
|
!
|
VhdlType std_logic
|
|
VerilogType wire
|
SIGNAL dwb_DAT_O
|
SystemCType sc_logic
|
DIRECTION output
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
RADIX hex
|
StateEquation Hex(Inc(0,2,5))
|
GRID 0 1 0 1 0 16711680 0 0
|
HighVoltageThreshold 5
|
ENDGRID -1
|
LowVoltageThreshold 0
|
Clock Unclocked
|
MSB 0
|
EdgeLevel neg
|
LSB 0
|
Set Not Used
|
isFallingEdgeSensitive False
|
Clear Not Used
|
isRisingEdgeSensitive False
|
ClockEnable Not Used
|
DrawAnalog 0
|
ActiveLowSetClear True
|
BooleanEquation
|
AsyncSetClear True
|
NegTolerance 0
|
ActiveLowClockEnable True
|
PosTolerance 0
|
VhdlType std_logic
|
UserSpecifiedSizeRatio 1
|
VerilogType wire
|
VerilogCode
|
SystemCType sc_logic
|
VHDLCode
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
PROPS!
|
StateEquation Hex(Inc(0,2,5))
|
!
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
CLOCK dwb_CLK_I
|
LSB 0
|
PERIODE 5
|
MSB 31
|
DUTY 50
|
SignalActionType 0
|
OFFSETE 0
|
isFallingEdgeSensitive False
|
INITIAL LOW
|
isRisingEdgeSensitive False
|
MAXUNCERTRISE 0
|
DrawAnalog 0
|
MAXUNCERTFALL 0
|
BooleanEquation
|
MINUNCERTRISE 0
|
NegTolerance 0
|
MINUNCERTFALL 0
|
PosTolerance 0
|
JRISEE 0
|
UserSpecifiedSizeRatio 1
|
JFALLE 0
|
VerilogCode
|
GRID 1 1 1 2 2 16711680 0 0
|
VHDLCode
|
ENDGRID -1
|
PROPS!
|
DIRECTION input
|
E0 X 43750 43750 1 0 DR 0
|
MASTERCLOCK None
|
!
|
Clock Unclocked
|
|
EdgeLevel neg
|
SIGNAL dwb_WE_O
|
Set Not Used
|
DIRECTION output
|
Clear Not Used
|
RADIX hex
|
ClockEnable Not Used
|
GRID 0 1 0 1 0 16711680 0 0
|
ActiveLowSetClear True
|
ENDGRID -1
|
AsyncSetClear True
|
Clock Unclocked
|
ActiveLowClockEnable True
|
EdgeLevel neg
|
VhdlType std_logic
|
Set Not Used
|
VerilogType wire
|
Clear Not Used
|
SystemCType sc_logic
|
ClockEnable Not Used
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
ActiveLowSetClear True
|
StateEquation Hex(Inc(0,2,5))
|
AsyncSetClear True
|
HighVoltageThreshold 5
|
ActiveLowClockEnable True
|
LowVoltageThreshold 0
|
VhdlType std_logic
|
MSB 0
|
VerilogType wire
|
LSB 0
|
SystemCType sc_logic
|
isFallingEdgeSensitive False
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
isRisingEdgeSensitive True
|
StateEquation Hex(Inc(0,2,5))
|
DrawAnalog 0
|
HighVoltageThreshold 5
|
BooleanEquation
|
LowVoltageThreshold 0
|
NegTolerance 0
|
SignalActionType 0
|
PosTolerance 0
|
MSB 0
|
UserSpecifiedSizeRatio 1
|
LSB 0
|
VerilogCode
|
isFallingEdgeSensitive False
|
VHDLCode
|
isRisingEdgeSensitive False
|
PROPS!
|
DrawAnalog 0
|
!
|
BooleanEquation
|
|
NegTolerance 0
|
SIGNAL dwb_ADR_O
|
PosTolerance 0
|
DIRECTION output
|
UserSpecifiedSizeRatio 1
|
RADIX hex
|
VerilogCode
|
GRID 0 1 0 1 0 16711680 0 0
|
VHDLCode
|
ENDGRID -1
|
PROPS!
|
Clock
|
E0 X 3125 3125 1 0 DR 0
|
EdgeLevel neg
|
E1 1 3126 3126 1 0 DR 0
|
Set Not Used
|
E2 0 13125 13125 1 0 DR 0
|
Clear Not Used
|
E3 X 13625 13625 1 0 DR 0
|
ClockEnable Not Used
|
E4 0 23125 23125 1 0 DR 0
|
ActiveLowSetClear True
|
E5 X 23625 23625 1 0 DR 0
|
AsyncSetClear True
|
E6 0 33125 33125 1 0 DR 0
|
ActiveLowClockEnable True
|
E7 X 33625 33625 1 0 DR 0
|
VhdlType std_logic
|
E8 0 43125 43125 1 0 DR 0
|
VerilogType wire
|
E9 X 43625 43625 1 0 DR 0
|
SystemCType sc_logic
|
!
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
SIGNAL dwb_SEL_O
|
HighVoltageThreshold 5
|
DIRECTION output
|
LowVoltageThreshold 0
|
RADIX hex
|
LSB 0
|
GRID 0 1 0 1 0 16711680 0 0
|
MSB 31
|
ENDGRID -1
|
SignalActionType 0
|
Clock Unclocked
|
isFallingEdgeSensitive False
|
EdgeLevel neg
|
isRisingEdgeSensitive True
|
Set Not Used
|
DrawAnalog 0
|
Clear Not Used
|
BooleanEquation
|
ClockEnable Not Used
|
NegTolerance 0
|
ActiveLowSetClear True
|
PosTolerance 0
|
AsyncSetClear True
|
UserSpecifiedSizeRatio 1
|
ActiveLowClockEnable True
|
VerilogCode
|
VhdlType std_logic
|
VHDLCode
|
VerilogType wire
|
VhdlMapping DefaultVhdlMapping
|
SystemCType sc_logic
|
PROPS!
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
E0 V -1 -1 1 0 DR 0
|
StateEquation Hex(Inc(0,2,5))
|
E1 X 3125 3125 1 0 DR 0
|
HighVoltageThreshold 5
|
E2 V 3126 3126 A0 1 0 DR 0
|
LowVoltageThreshold 0
|
E3 X 3750 3750 1 0 DR 0
|
LSB 0
|
E4 V 13125 13125 A0 1 0 DR 0
|
MSB 3
|
E5 X 13625 13625 1 0 DR 0
|
SignalActionType 0
|
E6 V 23125 23125 A4 1 0 DR 0
|
isFallingEdgeSensitive False
|
E7 X 23625 23625 1 0 DR 0
|
isRisingEdgeSensitive False
|
E8 V 33125 33125 A8 1 0 DR 0
|
DrawAnalog 0
|
E9 X 33625 33625 1 0 DR 0
|
BooleanEquation
|
E10 V 43125 43125 A12 1 0 DR 0
|
NegTolerance 0
|
E11 X 43750 43750 1 0 DR 0
|
PosTolerance 0
|
!
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
SIGNAL dwb_DAT_I
|
VHDLCode
|
DIRECTION input
|
PROPS!
|
RADIX hex
|
E0 V 0 0 Valid 1 0 DR 0
|
GRID 0 1 0 1 0 16711680 0 0
|
E1 X 3750 3750 1 0 DR 0
|
ENDGRID -1
|
E2 V 13125 13125 Valid 1 0 DR 0
|
Clock
|
E3 X 13625 13625 1 0 DR 0
|
EdgeLevel neg
|
E4 V 23125 23125 Valid 1 0 DR 0
|
Set Not Used
|
E5 X 23625 23625 1 0 DR 0
|
Clear Not Used
|
E6 V 33125 33125 Valid 1 0 DR 0
|
ClockEnable Not Used
|
E7 X 33625 33625 1 0 DR 0
|
ActiveLowSetClear True
|
E8 V 43125 43125 Valid 1 0 DR 0
|
AsyncSetClear True
|
E9 X 43750 43750 1 0 DR 0
|
ActiveLowClockEnable True
|
!
|
VhdlType std_logic
|
|
VerilogType wire
|
SIGNAL dwb_STB_O
|
SystemCType sc_logic
|
DIRECTION output
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
RADIX hex
|
StateEquation Hex(Inc(0,2,5))
|
GRID 0 1 0 1 0 16711680 0 0
|
HighVoltageThreshold 5
|
ENDGRID -1
|
LowVoltageThreshold 0
|
Clock Unclocked
|
LSB 0
|
EdgeLevel neg
|
MSB 31
|
Set Not Used
|
SignalActionType 0
|
Clear Not Used
|
isFallingEdgeSensitive False
|
ClockEnable Not Used
|
isRisingEdgeSensitive False
|
ActiveLowSetClear True
|
DrawAnalog 0
|
AsyncSetClear True
|
BooleanEquation
|
ActiveLowClockEnable True
|
NegTolerance 0
|
VhdlType std_logic
|
PosTolerance 0
|
VerilogType wire
|
UserSpecifiedSizeRatio 1
|
SystemCType sc_logic
|
VerilogCode
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
VHDLCode
|
StateEquation Hex(Inc(0,2,5))
|
VhdlMapping DefaultVhdlMapping
|
HighVoltageThreshold 5
|
PROPS!
|
LowVoltageThreshold 0
|
E0 X 11250 11250 1 0 DR 0
|
SignalActionType 0
|
E1 V 13125 13125 D0 1 0 DR 0
|
MSB 0
|
E2 X 21250 21250 1 0 DR 0
|
LSB 0
|
E3 V 23125 23125 D4 1 0 DR 0
|
isFallingEdgeSensitive False
|
E4 X 31250 31250 1 0 DR 0
|
isRisingEdgeSensitive False
|
E5 V 33125 33125 D8 1 0 DR 0
|
DrawAnalog 0
|
E6 X 41250 41250 1 0 DR 0
|
BooleanEquation
|
E7 V 43125 43125 D12 1 0 DR 0
|
NegTolerance 0
|
E8 X 43750 43750 1 0 DR 0
|
PosTolerance 0
|
!
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
SIGNAL dwb_DAT_O
|
VHDLCode
|
DIRECTION output
|
PROPS!
|
RADIX hex
|
E0 0 3750 3750 1 0 DR 0
|
GRID 0 1 0 1 0 16711680 0 0
|
E1 1 13125 13125 1 0 DR 0
|
ENDGRID -1
|
E2 0 13625 13625 1 0 DR 0
|
Clock Unclocked
|
E3 1 23125 23125 1 0 DR 0
|
EdgeLevel neg
|
E4 0 23625 23625 1 0 DR 0
|
Set Not Used
|
E5 1 33125 33125 1 0 DR 0
|
Clear Not Used
|
E6 0 33625 33625 1 0 DR 0
|
ClockEnable Not Used
|
E7 1 43125 43125 1 0 DR 0
|
ActiveLowSetClear True
|
E8 X 43750 43750 1 0 DR 0
|
AsyncSetClear True
|
!
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
SIGNAL dwb_ACK_I
|
VerilogType wire
|
DIRECTION input
|
SystemCType sc_logic
|
RADIX hex
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
GRID 0 1 0 1 0 16711680 0 0
|
StateEquation Hex(Inc(0,2,5))
|
ENDGRID -1
|
HighVoltageThreshold 5
|
Clock Unclocked
|
LowVoltageThreshold 0
|
EdgeLevel neg
|
LSB 0
|
Set Not Used
|
MSB 31
|
Clear Not Used
|
SignalActionType 0
|
ClockEnable Not Used
|
isFallingEdgeSensitive False
|
ActiveLowSetClear True
|
isRisingEdgeSensitive False
|
AsyncSetClear True
|
DrawAnalog 0
|
ActiveLowClockEnable True
|
BooleanEquation
|
VhdlType std_logic
|
NegTolerance 0
|
VerilogType wire
|
PosTolerance 0
|
SystemCType sc_logic
|
UserSpecifiedSizeRatio 1
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
VerilogCode
|
StateEquation Hex(Inc(0,2,5))
|
VHDLCode
|
HighVoltageThreshold 5
|
PROPS!
|
LowVoltageThreshold 0
|
E0 X 43750 43750 1 0 DR 0
|
SignalActionType 0
|
!
|
MSB 0
|
|
LSB 0
|
SIGNAL dwb_WE_O
|
isFallingEdgeSensitive False
|
DIRECTION output
|
isRisingEdgeSensitive False
|
RADIX hex
|
DrawAnalog 0
|
GRID 0 1 0 1 0 16711680 0 0
|
BooleanEquation
|
ENDGRID -1
|
NegTolerance 0
|
Clock Unclocked
|
PosTolerance 0
|
EdgeLevel neg
|
UserSpecifiedSizeRatio 1
|
Set Not Used
|
VerilogCode
|
Clear Not Used
|
VHDLCode
|
ClockEnable Not Used
|
PROPS!
|
ActiveLowSetClear True
|
E0 0 11250 11250 1 0 DR 0
|
AsyncSetClear True
|
E1 1 13125 13125 1 0 DR 0
|
ActiveLowClockEnable True
|
E2 0 21250 21250 1 0 DR 0
|
VhdlType std_logic
|
E3 1 23125 23125 1 0 DR 0
|
VerilogType wire
|
E4 0 31250 31250 1 0 DR 0
|
SystemCType sc_logic
|
E5 1 33125 33125 1 0 DR 0
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
E6 0 41250 41250 1 0 DR 0
|
StateEquation Hex(Inc(0,2,5))
|
E7 1 43125 43125 1 0 DR 0
|
HighVoltageThreshold 5
|
E8 X 43750 43750 1 0 DR 0
|
LowVoltageThreshold 0
|
!
|
SignalActionType 0
|
|
MSB 0
|
SIGNAL dwb_CYC_O
|
LSB 0
|
DIRECTION output
|
isFallingEdgeSensitive False
|
RADIX hex
|
isRisingEdgeSensitive False
|
GRID 0 1 0 1 0 16711680 0 0
|
DrawAnalog 0
|
ENDGRID -1
|
BooleanEquation
|
Clock Unclocked
|
NegTolerance 0
|
EdgeLevel neg
|
PosTolerance 0
|
Set Not Used
|
UserSpecifiedSizeRatio 1
|
Clear Not Used
|
VerilogCode
|
ClockEnable Not Used
|
VHDLCode
|
ActiveLowSetClear True
|
PROPS!
|
AsyncSetClear True
|
E0 X 3125 3125 1 0 DR 0
|
ActiveLowClockEnable True
|
E1 1 3126 3126 1 0 DR 0
|
VhdlType std_logic
|
E2 0 13125 13125 1 0 DR 0
|
VerilogType wire
|
E3 X 13625 13625 1 0 DR 0
|
SystemCType sc_logic
|
E4 0 23125 23125 1 0 DR 0
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
E5 X 23625 23625 1 0 DR 0
|
StateEquation Hex(Inc(0,2,5))
|
E6 0 33125 33125 1 0 DR 0
|
HighVoltageThreshold 5
|
E7 X 33625 33625 1 0 DR 0
|
LowVoltageThreshold 0
|
E8 0 43125 43125 1 0 DR 0
|
SignalActionType 0
|
E9 X 43625 43625 1 0 DR 0
|
MSB 0
|
!
|
LSB 0
|
|
isFallingEdgeSensitive False
|
SIGNAL dwb_SEL_O
|
isRisingEdgeSensitive False
|
DIRECTION output
|
DrawAnalog 0
|
RADIX hex
|
BooleanEquation
|
GRID 0 1 0 1 0 16711680 0 0
|
NegTolerance 0
|
ENDGRID -1
|
PosTolerance 0
|
Clock Unclocked
|
UserSpecifiedSizeRatio 1
|
EdgeLevel neg
|
VerilogCode
|
Set Not Used
|
VHDLCode
|
Clear Not Used
|
PROPS!
|
ClockEnable Not Used
|
E0 0 3125 3125 1 0 DR 0
|
ActiveLowSetClear True
|
E1 1 43125 43125 1 0 DR 0
|
AsyncSetClear True
|
E2 0 43750 43750 1 0 DR 0
|
ActiveLowClockEnable True
|
!
|
VhdlType std_logic
|
|
VerilogType wire
|
SIGNAL dwb_ERR_I
|
SystemCType sc_logic
|
DIRECTION input
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
RADIX hex
|
StateEquation Hex(Inc(0,2,5))
|
GRID 0 1 0 1 0 16711680 0 0
|
HighVoltageThreshold 5
|
ENDGRID -1
|
LowVoltageThreshold 0
|
Clock Unclocked
|
LSB 0
|
EdgeLevel neg
|
MSB 3
|
Set Not Used
|
SignalActionType 0
|
Clear Not Used
|
isFallingEdgeSensitive False
|
ClockEnable Not Used
|
isRisingEdgeSensitive False
|
ActiveLowSetClear True
|
DrawAnalog 0
|
AsyncSetClear True
|
BooleanEquation
|
ActiveLowClockEnable True
|
NegTolerance 0
|
VhdlType std_logic
|
PosTolerance 0
|
VerilogType wire
|
UserSpecifiedSizeRatio 1
|
SystemCType sc_logic
|
VerilogCode
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
VHDLCode
|
StateEquation Hex(Inc(0,2,5))
|
PROPS!
|
HighVoltageThreshold 5
|
E0 V 0 0 Valid 1 0 DR 0
|
LowVoltageThreshold 0
|
E1 X 3750 3750 1 0 DR 0
|
SignalActionType 0
|
E2 V 13125 13125 Valid 1 0 DR 0
|
MSB 0
|
E3 X 13625 13625 1 0 DR 0
|
LSB 0
|
E4 V 23125 23125 Valid 1 0 DR 0
|
isFallingEdgeSensitive False
|
E5 X 23625 23625 1 0 DR 0
|
isRisingEdgeSensitive False
|
E6 V 33125 33125 Valid 1 0 DR 0
|
DrawAnalog 0
|
E7 X 33625 33625 1 0 DR 0
|
BooleanEquation
|
E8 V 43125 43125 Valid 1 0 DR 0
|
NegTolerance 0
|
E9 X 43750 43750 1 0 DR 0
|
PosTolerance 0
|
!
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
SIGNAL dwb_STB_O
|
VHDLCode
|
DIRECTION output
|
PROPS!
|
RADIX hex
|
E0 0 43125 43125 1 0 DR 0
|
GRID 0 1 0 1 0 16711680 0 0
|
E1 X 43750 43750 1 0 DR 0
|
ENDGRID -1
|
!
|
Clock Unclocked
|
|
EdgeLevel neg
|
SIGNAL dwb_RTY_I
|
Set Not Used
|
DIRECTION input
|
Clear Not Used
|
RADIX hex
|
ClockEnable Not Used
|
GRID 0 1 0 1 0 16711680 0 0
|
ActiveLowSetClear True
|
ENDGRID -1
|
AsyncSetClear True
|
Clock Unclocked
|
ActiveLowClockEnable True
|
EdgeLevel neg
|
VhdlType std_logic
|
Set Not Used
|
VerilogType wire
|
Clear Not Used
|
SystemCType sc_logic
|
ClockEnable Not Used
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
ActiveLowSetClear True
|
StateEquation Hex(Inc(0,2,5))
|
AsyncSetClear True
|
HighVoltageThreshold 5
|
ActiveLowClockEnable True
|
LowVoltageThreshold 0
|
VhdlType std_logic
|
SignalActionType 0
|
VerilogType wire
|
MSB 0
|
SystemCType sc_logic
|
LSB 0
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
isFallingEdgeSensitive False
|
StateEquation Hex(Inc(0,2,5))
|
isRisingEdgeSensitive False
|
HighVoltageThreshold 5
|
DrawAnalog 0
|
LowVoltageThreshold 0
|
BooleanEquation
|
SignalActionType 0
|
NegTolerance 0
|
MSB 0
|
PosTolerance 0
|
LSB 0
|
UserSpecifiedSizeRatio 1
|
isFallingEdgeSensitive False
|
VerilogCode
|
isRisingEdgeSensitive False
|
VHDLCode
|
DrawAnalog 0
|
PROPS!
|
BooleanEquation
|
E0 0 3750 3750 1 0 DR 0
|
NegTolerance 0
|
E1 1 13125 13125 1 0 DR 0
|
PosTolerance 0
|
E2 0 13625 13625 1 0 DR 0
|
UserSpecifiedSizeRatio 1
|
E3 1 23125 23125 1 0 DR 0
|
VerilogCode
|
E4 0 23625 23625 1 0 DR 0
|
VHDLCode
|
E5 1 33125 33125 1 0 DR 0
|
PROPS!
|
E6 0 33625 33625 1 0 DR 0
|
E0 0 43125 43125 1 0 DR 0
|
E7 1 43125 43125 1 0 DR 0
|
E1 X 43750 43750 1 0 DR 0
|
E8 X 43750 43750 1 0 DR 0
|
!
|
!
|
|
|
MARKER MARK1
|
SIGNAL dwb_ACK_I
|
ATTACH dwb_SEL_O NULL S6
|
DIRECTION input
|
TIME 17500.000000
|
RADIX hex
|
RELATIVETIME 0.000000
|
GRID 0 1 0 1 0 16711680 0 0
|
DISPLAYAS 5
|
ENDGRID -1
|
MARKERTYPE Timebreak(Curved)
|
Clock Unclocked
|
WHILERETURN
|
EdgeLevel neg
|
REPEATNUMBER
|
Set Not Used
|
SNAPTO 0
|
Clear Not Used
|
COMPRESSTIME 0.000000
|
ClockEnable Not Used
|
COMMENT
|
ActiveLowSetClear True
|
!
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
MARKER MARK2
|
VhdlType std_logic
|
ATTACH dwb_STB_O NULL S7
|
VerilogType wire
|
TIME 27500.000000
|
SystemCType sc_logic
|
RELATIVETIME 0.000000
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
DISPLAYAS 5
|
StateEquation Hex(Inc(0,2,5))
|
MARKERTYPE Timebreak(Curved)
|
HighVoltageThreshold 5
|
WHILERETURN
|
LowVoltageThreshold 0
|
REPEATNUMBER
|
SignalActionType 0
|
SNAPTO 0
|
MSB 0
|
COMPRESSTIME 0.000000
|
LSB 0
|
COMMENT
|
isFallingEdgeSensitive False
|
!
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
MARKER MARK3
|
BooleanEquation
|
ATTACH dwb_STB_O NULL S7
|
NegTolerance 0
|
TIME 37500.000000
|
PosTolerance 0
|
RELATIVETIME 0.000000
|
UserSpecifiedSizeRatio 1
|
DISPLAYAS 5
|
VerilogCode
|
MARKERTYPE Timebreak(Curved)
|
VHDLCode
|
WHILERETURN
|
PROPS!
|
REPEATNUMBER
|
E0 0 11250 11250 1 0 DR 0
|
SNAPTO 0
|
E1 1 13125 13125 1 0 DR 0
|
COMPRESSTIME 0.000000
|
E2 0 21250 21250 1 0 DR 0
|
COMMENT
|
E3 1 23125 23125 1 0 DR 0
|
!
|
E4 0 31250 31250 1 0 DR 0
|
|
E5 1 33125 33125 1 0 DR 0
|
MARKER MARK0
|
E6 0 41250 41250 1 0 DR 0
|
ATTACH dwb_CLK_I NULL S1
|
E7 1 43125 43125 1 0 DR 0
|
TIME 7494.285714
|
E8 X 43750 43750 1 0 DR 0
|
RELATIVETIME 0.000000
|
!
|
DISPLAYAS 5
|
|
MARKERTYPE Timebreak(Curved)
|
SIGNAL dwb_CYC_O
|
WHILERETURN
|
DIRECTION output
|
REPEATNUMBER
|
RADIX hex
|
SNAPTO 0
|
GRID 0 1 0 1 0 16711680 0 0
|
COMPRESSTIME 0.000000
|
ENDGRID -1
|
COMMENT
|
Clock Unclocked
|
!
|
EdgeLevel neg
|
|
Set Not Used
|
Timing Diagram Editor v7.1g - Output File
|
Clear Not Used
|
|
ClockEnable Not Used
|
PROJECT
|
ActiveLowSetClear True
|
BaseTimeUnit 1
|
AsyncSetClear True
|
DisplayTimeUnit 2
|
ActiveLowClockEnable True
|
TextGridX 250.000000
|
VhdlType std_logic
|
TextGridY 6
|
VerilogType wire
|
EdgeGridX 250.000000
|
SystemCType sc_logic
|
ImportStartTime 0.000000
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
ImportEndTime 281474976710656.000000
|
StateEquation Hex(Inc(0,2,5))
|
TimePerPixel 6.497175
|
HighVoltageThreshold 5
|
Visible DELAYS SETUPS HOLDS SAMPLES TEXT HIDDENATTACHMENTS CRITICALPATHS GRIDLINES UNCERTAINTY
|
LowVoltageThreshold 0
|
ColWidths 144,216,288,423,488
|
SignalActionType 0
|
ScrollPos 0.000000,0.000009,0.000000
|
MSB 0
|
DefDelayRule 1
|
LSB 0
|
NoEventOverlap NO
|
isFallingEdgeSensitive False
|
SigLabelFontHeight 10
|
isRisingEdgeSensitive False
|
LabelHeight 12
|
DrawAnalog 0
|
LoadLibsToMem 1
|
BooleanEquation
|
UseFullPathNames 1
|
NegTolerance 0
|
LibPath
|
PosTolerance 0
|
EntireTime YES
|
UserSpecifiedSizeRatio 1
|
PrintTimeSpecified NO
|
VerilogCode
|
FromTime 0
|
VHDLCode
|
ToTime 5.75
|
PROPS!
|
AllSignals YES
|
E0 0 3125 3125 1 0 DR 0
|
CurrSelSigs NO
|
E1 1 43125 43125 1 0 DR 0
|
PrintTo 2
|
E2 0 43750 43750 1 0 DR 0
|
PrintFileName C:\DOCS\reset.wmf
|
!
|
PreviewInterchange YES
|
|
PreviewTIFF5 NO
|
SIGNAL dwb_ERR_I
|
UseMargins NO
|
DIRECTION input
|
PrintTimeLine NO
|
RADIX hex
|
PrintBorderBox YES
|
GRID 0 1 0 1 0 16711680 0 0
|
PrintSigNames YES
|
ENDGRID -1
|
PrintSigNamesOnEachPage YES
|
Clock Unclocked
|
AddPreviewToEPS NO
|
EdgeLevel neg
|
PreviewRes 150
|
Set Not Used
|
MarginLR 1.25
|
Clear Not Used
|
MifImageWidth 6.00
|
ClockEnable Not Used
|
MarginTB Auto
|
ActiveLowSetClear True
|
Header %d %t;%f;%p
|
AsyncSetClear True
|
Footer
|
ActiveLowClockEnable True
|
ScaleHorz 100
|
VhdlType std_logic
|
ScaleVert 100
|
VerilogType wire
|
ScaleHPage 1
|
SystemCType sc_logic
|
PrintImage DIAGRAM
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
DefaultTimingModel minmax
|
StateEquation Hex(Inc(0,2,5))
|
DefaultClock Unclocked
|
HighVoltageThreshold 5
|
DefaultEdgeLevel neg
|
LowVoltageThreshold 0
|
DefaultSet Not Used
|
SignalActionType 0
|
DefaultClear Not Used
|
MSB 0
|
DefaultClockEnable Not Used
|
LSB 0
|
DefaultClockToOutLH 0
|
isFallingEdgeSensitive False
|
DefaultClockToOutHL 0
|
isRisingEdgeSensitive False
|
DefaultSetup 0
|
DrawAnalog 0
|
DefaultHold 0
|
BooleanEquation
|
DefaultRegStartupState unknown
|
NegTolerance 0
|
DefaultPodSize 8
|
PosTolerance 0
|
DefaultActiveLowSetClear True
|
UserSpecifiedSizeRatio 1
|
DefaultAsyncSetClear True
|
VerilogCode
|
DefaultActiveLowClockEnable True
|
VHDLCode
|
SigLabelFontHeight 10
|
PROPS!
|
PROPS!
|
E0 0 43125 43125 1 0 DR 0
|
!
|
E1 X 43750 43750 1 0 DR 0
|
|
!
|
STYLE
|
|
DefaultFont USER {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
|
SIGNAL dwb_RTY_I
|
DrawWndFont DEFAULT
|
DIRECTION input
|
DrawWndColor DEFAULT
|
RADIX hex
|
GridWndFont DEFAULT
|
GRID 0 1 0 1 0 16711680 0 0
|
GridWndColor DEFAULT
|
ENDGRID -1
|
LabelWndFont USER {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
|
Clock Unclocked
|
LabelWndColor DEFAULT
|
EdgeLevel neg
|
ParamDispPref 0
|
Set Not Used
|
ParamWndCellDisplay 0
|
Clear Not Used
|
CustDispString %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
|
ClockEnable Not Used
|
CustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
|
ActiveLowSetClear True
|
MarkerDispPref 4
|
AsyncSetClear True
|
MarkerCustDispString %n v=%mv,%Mv d=%md %t
|
ActiveLowClockEnable True
|
MarkerCustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
|
VhdlType std_logic
|
SignalColor 2
|
VerilogType wire
|
LabelOffset 4
|
SystemCType sc_logic
|
BusDisplay 0
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
WaveFormWidth 0.500000
|
StateEquation Hex(Inc(0,2,5))
|
WaveFormColor 0
|
HighVoltageThreshold 5
|
InputWaveFormColor 16711680
|
LowVoltageThreshold 0
|
SlantedEdges 1
|
SignalActionType 0
|
SlantAngle 75
|
MSB 0
|
RightJustifySigNames 1
|
LSB 0
|
AutosplitEnabled 1
|
isFallingEdgeSensitive False
|
AutosplitChar _
|
isRisingEdgeSensitive False
|
DynamSizedSignals 1
|
DrawAnalog 0
|
!
|
BooleanEquation
|
|
NegTolerance 0
|
DIAGRAMTESTBENCHSETTINGS
|
PosTolerance 0
|
FilesBeforeDiagramModel
|
UserSpecifiedSizeRatio 1
|
FilesInsideDiagramModelDeclarationSection
|
VerilogCode
|
AbortHdlCodeEnabled 1
|
VHDLCode
|
DelayHdlCodeEnabled 1
|
PROPS!
|
SampleHdlCodeEnabled 1
|
E0 0 43125 43125 1 0 DR 0
|
MarkerHdlCodeEnabled 1
|
E1 X 43750 43750 1 0 DR 0
|
VerboseSamples 0
|
!
|
VerboseDelays 0
|
|
VerboseFileInput 0
|
MARKER MARK1
|
VerboseSequenceVerification 0
|
ATTACH dwb_SEL_O NULL S6
|
IncludeDelayTime 1
|
TIME 17500.000000
|
ExecuteFromTopLevel 1
|
RELATIVETIME 0.000000
|
TimeOutInDiagramLengths 0
|
DISPLAYAS 5
|
DefaultCycleClock Unclocked
|
MARKERTYPE Timebreak(Curved)
|
DefaultCycleEdge neg
|
WHILERETURN
|
!
|
REPEATNUMBER
|
|
SNAPTO 0
|
MACROS
|
COMPRESSTIME 0.000000
|
!
|
COMMENT
|
|
!
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
MARKER MARK2
|
!
|
ATTACH dwb_STB_O NULL S7
|
|
TIME 27500.000000
|
CORGROUP $$CLK_I_BufferFalling
|
RELATIVETIME 0.000000
|
Percent 100
|
DISPLAYAS 5
|
!
|
MARKERTYPE Timebreak(Curved)
|
|
WHILERETURN
|
CORGROUP $$CLK_I_BufferRisingFalling
|
REPEATNUMBER
|
Percent 100
|
SNAPTO 0
|
!
|
COMPRESSTIME 0.000000
|
|
COMMENT
|
CORGROUP $$CLK_I_BufferRising
|
!
|
Percent 100
|
|
!
|
MARKER MARK3
|
|
ATTACH dwb_STB_O NULL S7
|
CORGROUP $$CLK_I_BufferFalling
|
TIME 37500.000000
|
Percent 100
|
RELATIVETIME 0.000000
|
!
|
DISPLAYAS 5
|
|
MARKERTYPE Timebreak(Curved)
|
CORGROUP $$CLK_I_BufferRisingFalling
|
WHILERETURN
|
Percent 100
|
REPEATNUMBER
|
!
|
SNAPTO 0
|
|
COMPRESSTIME 0.000000
|
CORGROUP $$CLK_I_BufferRising
|
COMMENT
|
Percent 100
|
!
|
!
|
|
|
MARKER MARK0
|
CORGROUP $$CLK_I_BufferFalling
|
ATTACH dwb_CLK_I NULL S1
|
Percent 100
|
TIME 7494.285714
|
!
|
RELATIVETIME 0.000000
|
|
DISPLAYAS 5
|
CORGROUP $$CLK_I_BufferRisingFalling
|
MARKERTYPE Timebreak(Curved)
|
Percent 100
|
WHILERETURN
|
!
|
REPEATNUMBER
|
|
SNAPTO 0
|
CORGROUP $$CLK_I_BufferRising
|
COMPRESSTIME 0.000000
|
Percent 100
|
COMMENT
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
O l e
|
Percent 100
|
C o m p O b j h j i O b j I n f o k C O N T E N T S AN
|
!
|
Q<= Kuy Timing Diagram Timing.Document.1 9q Timing Diagram
|
|
Q<= Kuy Timing Diagram Timing.Document.1 9q Timing Diagram
|
CORGROUP $$CLK_I_BufferRisingFalling
|
a " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` d e f g h i j k l m n o p q r s t u v w x y z { | } ~ Timing Diagram Editor v7.1g - Output File
|
Percent 100
|
|
!
|
PROJECT
|
|
BaseTimeUnit 1
|
CORGROUP $$CLK_I_BufferRising
|
DisplayTimeUnit 2
|
Percent 100
|
TextGridX 625.000000
|
!
|
TextGridY 6
|
|
EdgeGridX 625.000000
|
CORGROUP $$CLK_I_BufferFalling
|
ImportStartTime 0.000000
|
Percent 100
|
ImportEndTime 281474976710656.000000
|
!
|
TimePerPixel 61.428571
|
|
Visible DELAYS SETUPS HOLDS SAMPLES TEXT HIDDENATTACHMENTS CRITICALPATHS GRIDLINES UNCERTAINTY
|
CORGROUP $$CLK_I_BufferRisingFalling
|
ColWidths 144,216,288,423,488
|
Percent 100
|
ScrollPos 0.000000,0.000000,0.000000
|
!
|
DefDelayRule 1
|
|
NoEventOverlap NO
|
CORGROUP $$CLK_I_BufferRising
|
SigLabelFontHeight 10
|
Percent 100
|
LabelHeight 12
|
!
|
LoadLibsToMem 1
|
|
UseFullPathNames 1
|
CORGROUP $$CLK_I_BufferFalling
|
LibPath
|
Percent 100
|
EntireTime YES
|
!
|
PrintTimeSpecified NO
|
|
FromTime 0
|
CORGROUP $$CLK_I_BufferRisingFalling
|
ToTime 53.75
|
Percent 100
|
AllSignals YES
|
!
|
CurrSelSigs NO
|
|
PrintTo 2
|
CORGROUP $$CLK_RISC_BufferRising
|
PrintFileName C:\DOCS\wb_writeblock_typ.wmf
|
Percent 100
|
PreviewInterchange YES
|
!
|
PreviewTIFF5 NO
|
|
UseMargins NO
|
CORGROUP $$CLK_RISC_BufferFalling
|
PrintTimeLine NO
|
Percent 100
|
PrintBorderBox YES
|
!
|
PrintSigNames YES
|
|
PrintSigNamesOnEachPage YES
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
AddPreviewToEPS NO
|
Percent 100
|
PreviewRes 150
|
!
|
MarginLR 1.25
|
|
MifImageWidth 6.00
|
CORGROUP $$CLK_RISC_BufferRising
|
MarginTB Auto
|
Percent 100
|
Header %d %t;%f;%p
|
!
|
Footer
|
|
ScaleHorz 100
|
CORGROUP $$CLK_RISC_BufferFalling
|
ScaleVert 100
|
Percent 100
|
ScaleHPage 1
|
!
|
PrintImage DIAGRAM
|
|
DefaultTimingModel minmax
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
DefaultClock Unclocked
|
Percent 100
|
DefaultEdgeLevel neg
|
!
|
DefaultSet Not Used
|
|
DefaultClear Not Used
|
CORGROUP $$CLK_I_BufferRising
|
DefaultClockEnable Not Used
|
Percent 100
|
DefaultClockToOutLH 0
|
!
|
DefaultClockToOutHL 0
|
|
DefaultSetup 0
|
CORGROUP $$CLK_I_BufferFalling
|
DefaultHold 0
|
Percent 100
|
DefaultRegStartupState unknown
|
!
|
DefaultPodSize 8
|
|
DefaultActiveLowSetClear True
|
CORGROUP $$CLK_I_BufferRisingFalling
|
DefaultAsyncSetClear True
|
Percent 100
|
DefaultActiveLowClockEnable True
|
!
|
SigLabelFontHeight 10
|
|
PROPS!
|
CORGROUP $$CLK_RISC_BufferRising
|
!
|
Percent 100
|
|
!
|
STYLE
|
|
DefaultFont USER {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
|
CORGROUP $$CLK_RISC_BufferFalling
|
DrawWndFont DEFAULT
|
Percent 100
|
DrawWndColor DEFAULT
|
!
|
GridWndFont DEFAULT
|
|
GridWndColor DEFAULT
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
LabelWndFont USER {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
|
Percent 100
|
LabelWndColor DEFAULT
|
!
|
ParamDispPref 0
|
|
ParamWndCellDisplay 0
|
CORGROUP $$CLK_I_BufferRising
|
CustDispString %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
|
Percent 100
|
CustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
|
!
|
MarkerDispPref 4
|
|
MarkerCustDispString %n v=%mv,%Mv d=%md %t
|
CORGROUP $$CLK_I_BufferFalling
|
MarkerCustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
|
Percent 100
|
SignalColor 2
|
!
|
LabelOffset 2
|
|
BusDisplay 0
|
CORGROUP $$CLK_I_BufferRisingFalling
|
WaveFormWidth 0.500000
|
Percent 100
|
WaveFormColor 0
|
!
|
InputWaveFormColor 16711680
|
|
SlantedEdges 1
|
CORGROUP $$CLK_RISC_BufferRising
|
SlantAngle 75
|
Percent 100
|
RightJustifySigNames 1
|
!
|
AutosplitEnabled 1
|
|
AutosplitChar _
|
CORGROUP $$CLK_RISC_BufferFalling
|
DynamSizedSignals 1
|
Percent 100
|
!
|
!
|
|
|
DIAGRAMTESTBENCHSETTINGS
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
FilesBeforeDiagramModel
|
Percent 100
|
FilesInsideDiagramModelDeclarationSection
|
!
|
AbortHdlCodeEnabled 1
|
|
DelayHdlCodeEnabled 1
|
CORGROUP $$CLK_I_BufferRising
|
SampleHdlCodeEnabled 1
|
Percent 100
|
MarkerHdlCodeEnabled 1
|
!
|
VerboseSamples 0
|
|
VerboseDelays 0
|
CORGROUP $$CLK_I_BufferFalling
|
VerboseFileInput 0
|
Percent 100
|
VerboseSequenceVerification 0
|
!
|
IncludeDelayTime 1
|
|
ExecuteFromTopLevel 1
|
CORGROUP $$CLK_I_BufferRisingFalling
|
TimeOutInDiagramLengths 0
|
Percent 100
|
DefaultCycleClock Unclocked
|
!
|
DefaultCycleEdge neg
|
|
!
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
MACROS
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
CORGROUP $$CLK_I_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CORGROUP $$CLK_I_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
CORGROUP $$CLK_I_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CORGROUP $$CLK_I_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
CORGROUP $$CLK_I_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CORGROUP $$CLK_I_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
CORGROUP $$CLK_I_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CORGROUP $$CLK_I_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
CORGROUP $$CLK_I_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CORGROUP $$CLK_I_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
CORGROUP $$CLK_I_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CORGROUP $$CLK_I_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
CORGROUP $$CLK_RISC_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CORGROUP $$CLK_RISC_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
CORGROUP $$CLK_RISC_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CORGROUP $$CLK_RISC_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
CORGROUP $$CLK_I_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CORGROUP $$CLK_I_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
CORGROUP $$CLK_RISC_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CORGROUP $$CLK_RISC_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
CORGROUP $$CLK_I_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CORGROUP $$CLK_I_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$clk_risc_BufferRising
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$clk_risc_BufferFalling
|
CORGROUP $$CLK_RISC_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$clk_risc_BufferRisingFalling
|
CORGROUP $$CLK_RISC_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$clk_risc_BufferRising
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$clk_risc_BufferFalling
|
CORGROUP $$CLK_I_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$clk_risc_BufferRisingFalling
|
CORGROUP $$CLK_I_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$clk_risc_BufferRising
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$clk_risc_BufferFalling
|
CORGROUP $$CLK_RISC_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$clk_risc_BufferRisingFalling
|
CORGROUP $$CLK_RISC_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$clk_risc_BufferRising
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$clk_risc_BufferFalling
|
CORGROUP $$CLK_I_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$clk_risc_BufferRisingFalling
|
CORGROUP $$CLK_I_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$clk_risc_BufferRising
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$clk_risc_BufferFalling
|
CORGROUP $$CLK_RISC_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$clk_risc_BufferRisingFalling
|
CORGROUP $$CLK_RISC_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CLOCK clk_risc
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
PERIODE 1
|
Percent 100
|
DUTY 50
|
!
|
OFFSETE 0
|
|
INITIAL LOW
|
CORGROUP $$CLK_I_BufferRising
|
MAXUNCERTRISE 0
|
Percent 100
|
MAXUNCERTFALL 0
|
!
|
MINUNCERTRISE 0
|
|
MINUNCERTFALL 0
|
CORGROUP $$CLK_I_BufferFalling
|
JRISEE 0
|
Percent 100
|
JFALLE 0
|
!
|
GRID 1 1 1 2 2 16711680 0 0
|
|
ENDGRID -1
|
CORGROUP $$CLK_I_BufferRisingFalling
|
DIRECTION input
|
Percent 100
|
MASTERCLOCK None
|
!
|
Clock Unclocked
|
|
EdgeLevel neg
|
CORGROUP $$CLK_RISC_BufferRising
|
Set Not Used
|
Percent 100
|
Clear Not Used
|
!
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
CORGROUP $$CLK_RISC_BufferFalling
|
AsyncSetClear True
|
Percent 100
|
ActiveLowClockEnable True
|
!
|
VhdlType std_logic
|
|
VerilogType wire
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
SystemCType sc_logic
|
Percent 100
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
!
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
CORGROUP $$CLK_I_BufferRising
|
LowVoltageThreshold 0
|
Percent 100
|
MSB 0
|
!
|
LSB 0
|
|
isFallingEdgeSensitive False
|
CORGROUP $$CLK_I_BufferFalling
|
isRisingEdgeSensitive True
|
Percent 100
|
DrawAnalog 0
|
!
|
BooleanEquation
|
|
NegTolerance 0
|
CORGROUP $$CLK_I_BufferRisingFalling
|
PosTolerance 0
|
Percent 100
|
UserSpecifiedSizeRatio 1
|
!
|
VerilogCode
|
|
VHDLCode
|
CORGROUP $$CLK_RISC_BufferRising
|
PROPS!
|
Percent 100
|
E5 1 2500 2500 1 0 DR 0
|
!
|
E6 0 3000 3000 1 0 DR 0
|
|
E7 0 3500 3500 1 0 DR 0
|
CORGROUP $$CLK_RISC_BufferFalling
|
E9 1 4500 4500 1 0 DR 0
|
Percent 100
|
!
|
!
|
|
|
SIGNAL rst
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
DIRECTION input
|
Percent 100
|
RADIX hex
|
!
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
CORGROUP $$CLK_I_BufferRising
|
Clock Unclocked
|
Percent 100
|
EdgeLevel neg
|
!
|
Set Not Used
|
|
Clear Not Used
|
CORGROUP $$CLK_I_BufferFalling
|
ClockEnable Not Used
|
Percent 100
|
ActiveLowSetClear True
|
!
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
CORGROUP $$CLK_I_BufferRisingFalling
|
VhdlType std_logic
|
Percent 100
|
VerilogType wire
|
!
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
CORGROUP $$CLK_RISC_BufferRising
|
StateEquation Hex(Inc(0,2,5))
|
Percent 100
|
HighVoltageThreshold 5
|
!
|
LowVoltageThreshold 0
|
|
SignalActionType 0
|
CORGROUP $$CLK_RISC_BufferFalling
|
MSB 0
|
Percent 100
|
LSB 0
|
!
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
DrawAnalog 0
|
Percent 100
|
BooleanEquation
|
!
|
NegTolerance 0
|
|
PosTolerance 0
|
CORGROUP $$CLK_I_BufferRising
|
UserSpecifiedSizeRatio 1
|
Percent 100
|
VerilogCode
|
!
|
VHDLCode
|
|
PROPS!
|
CORGROUP $$CLK_I_BufferFalling
|
E0 0 1750 1750 1 0 DR 0
|
Percent 100
|
E1 1 3750 3750 1 0 DR 0
|
!
|
E2 0 5750 5750 1 0 DR 0
|
|
!
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
SIGNAL dbg_dat_o
|
!
|
DIRECTION output
|
|
RADIX hex
|
CORGROUP $$CLK_RISC_BufferRising
|
GRID 0 1 0 1 0 16711680 0 0
|
Percent 100
|
ENDGRID -1
|
!
|
Clock
|
|
EdgeLevel neg
|
CORGROUP $$CLK_RISC_BufferFalling
|
Set Not Used
|
Percent 100
|
Clear Not Used
|
!
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
AsyncSetClear True
|
Percent 100
|
ActiveLowClockEnable True
|
!
|
VhdlType std_logic
|
|
VerilogType wire
|
CORGROUP $$CLK_I_BufferRising
|
SystemCType sc_logic
|
Percent 100
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
!
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
CORGROUP $$CLK_I_BufferFalling
|
LowVoltageThreshold 0
|
Percent 100
|
LSB 0
|
!
|
MSB 31
|
|
SignalActionType 0
|
CORGROUP $$CLK_I_BufferRisingFalling
|
isFallingEdgeSensitive False
|
Percent 100
|
isRisingEdgeSensitive True
|
!
|
DrawAnalog 0
|
|
BooleanEquation
|
CORGROUP $$CLK_RISC_BufferRising
|
NegTolerance 0
|
Percent 100
|
PosTolerance 0
|
!
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
CORGROUP $$CLK_RISC_BufferFalling
|
VHDLCode
|
Percent 100
|
VhdlMapping DefaultVhdlMapping
|
!
|
PROPS!
|
|
E0 X 1750 1750 1 0 DR 0
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
E1 V 4750 4750 0x0 1 0 DR 0
|
Percent 100
|
E2 V 5750 5750 0x4 1 0 DR 0
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRising
|
SIGNAL dbg_op_i
|
Percent 100
|
DIRECTION input
|
!
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
CORGROUP $$CLK_I_BufferFalling
|
ENDGRID -1
|
Percent 100
|
Clock Unclocked
|
!
|
EdgeLevel neg
|
|
Set Not Used
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Clear Not Used
|
Percent 100
|
ClockEnable Not Used
|
!
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
CORGROUP $$CLK_RISC_BufferRising
|
ActiveLowClockEnable True
|
Percent 100
|
VhdlType std_logic
|
!
|
VerilogType wire
|
|
SystemCType sc_logic
|
CORGROUP $$CLK_RISC_BufferFalling
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
Percent 100
|
StateEquation Hex(Inc(0,2,5))
|
!
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
SignalActionType 0
|
Percent 100
|
MSB 3
|
!
|
LSB 0
|
|
isFallingEdgeSensitive False
|
CORGROUP $$CLK_I_BufferRising
|
isRisingEdgeSensitive False
|
Percent 100
|
DrawAnalog 0
|
!
|
BooleanEquation
|
|
NegTolerance 0
|
CORGROUP $$CLK_I_BufferFalling
|
PosTolerance 0
|
Percent 100
|
UserSpecifiedSizeRatio 1
|
!
|
VerilogCode
|
|
VHDLCode
|
CORGROUP $$CLK_I_BufferRisingFalling
|
PROPS!
|
Percent 100
|
E0 V 5750 5750 READ PC 0x0 1 0 DR 0
|
!
|
!
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
PARM Trs
|
Percent 100
|
MIN NULL
|
!
|
MAX NULL
|
|
COMMENT Reset Setup Time
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
NameRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont Trs}
|
Percent 100
|
MinRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont}
|
!
|
MaxRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont}
|
|
CommentRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont Reset Setup Time}
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
CLOCKNAME Unclocked
|
Percent 100
|
CLOCKEDGE neg
|
!
|
IsApplyInput False
|
|
PROPS!
|
CORGROUP $$dwb_CLK_I_BufferRising
|
!
|
Percent 100
|
|
!
|
PARM Trh
|
|
MIN NULL
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
MAX NULL
|
Percent 100
|
COMMENT Reset Hold Time
|
!
|
NameRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont Trh}
|
|
MinRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont}
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
MaxRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont}
|
Percent 100
|
CommentRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont Reset Hold Time}
|
!
|
CLOCKNAME Unclocked
|
|
CLOCKEDGE neg
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
IsApplyInput False
|
Percent 100
|
PROPS!
|
!
|
!
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
SETUP Trs
|
Percent 100
|
FROM clk_risc E9 S0
|
!
|
TO rst E1 S1
|
|
OUTARROWS 0
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
USERPLACED 0
|
Percent 100
|
DISPLAYAS 6
|
!
|
CUSTDISPSTRING %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
|
|
CustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
|
CORGROUP $$dwb_CLK_I_BufferRising
|
EnableHdlCodeGeneration False
|
Percent 100
|
OrderIndex 1
|
!
|
PROPS!
|
|
!
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
|
Percent 100
|
HOLD Trh
|
!
|
FROM clk_risc E7 S0
|
|
TO rst E1 S1
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
OUTARROWS 0
|
Percent 100
|
USERPLACED 0
|
!
|
DISPLAYAS 6
|
|
CUSTDISPSTRING %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
CustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
|
Percent 100
|
EnableHdlCodeGeneration False
|
!
|
OrderIndex 2
|
|
PROPS!
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
!
|
Percent 100
|
|
!
|
MARKER MARK0
|
|
ATTACH rst NULL S1
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
TIME 2750.000000
|
Percent 100
|
RELATIVETIME 0.000000
|
!
|
DISPLAYAS 5
|
|
MARKERTYPE Timebreak(Curved)
|
CORGROUP $$dwb_CLK_I_BufferRising
|
WHILERETURN
|
Percent 100
|
REPEATNUMBER
|
!
|
SNAPTO 0
|
|
COMPRESSTIME 0.000000
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
COMMENT
|
Percent 100
|
!
|
!
|
|
|
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
F Microsoft Visio Drawing VISIO 6.0 Shapes Visio.Drawing.6 9q ՜. +,D ՜. +," @ H P \ h t
P&l 1Q
& " WMFC Y y x j P &l EMF y s X V I S I O D r a w i n g
|
Percent 100
|
% R L A r i a l % T l ! y
|
!
|
@
|
|
@! y L X S E T 0 - - ) % T l !
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
@
|
Percent 100
|
@! L X S E T 1 - - ) % R L A r i a l ^ 0 ` > j 8 p 2 b P < p j 8 X rif design, Arial contains more huma st characteristics than many of its predecessors and as such i e % T ` b 6
|
!
|
|
|
@
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
@b L T . . . ha R L A r i a l hich helps to give the face a less mechanical appe ce. Arial is an extremely versatile family of typefaces which can be used with equal success for text setting in reports, pre ntations, magazines etc, and for display use in newspapers, ad w.% T ` =
S
|
Percent 100
|
@
|
!
|
@=
L T S E T IC- - ) R L A r i a l ts use by you is covered under the terms of a lice agreement. You have obtained this typeface software either directly from Monotype or together with software distributed by one f Monotypes licensees.
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
This software is a valuable asset o d % T T J
|
Percent 100
|
@
|
!
|
@ J
L P I e R L A r i a l distribute this software.
|
|
|
CORGROUP $$dwb_CLK_I_BufferRising
|
If you have any quest concerning your rights you should review the license agreement you received with the software or contact Monotype for a copy o the license agreement.
|
Percent 100
|
|
!
|
Monotype can be contacted at:
|
|
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
USA 7 % T
|
Percent 100
|
J
x
|
!
|
@
|
|
@
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
J
|
Percent 100
|
L ` T L B _ S E T S - 1 & % % V 0 9
:
::
% ( R L A r i a l 2 . A l l R i g h t s R e s e r v e d A r i R e g u l a r M o n o t y p e : A r i a l R e g u l a r : V e r s i o n 2 . 7 6 ( M i c r o s o f t ) A r i a l V e r s o n 2 . 7 6 A r i a l M T A r i a l T r a d e m a r k o % ( R L A r i a l & T M O f f . a n d e l s e w h e r e . n o t y p e T y p o g r a p h y M o n o t y p e T y p e D r a w i n g O f f i c e - R o b i n N i c h o l a s , P a t r i c i a S a u n d e r s 1 9 8 2 C o n t e m p o r s % ( R L A r i a l a c t e r i s t i c s t h a n m a n y o f s p r e d e c e s s o r s a n d a s s u c h i s m o r e i n t u n e w i t h t h e m o o d o f t h e l a s t d e c a d e s o f t h e t w e n t i e t h c a % ( R L A r i a l u l l e r t h a n i n m o s t i n d u s t a l s t y l e s a n s s e r i f f a c e s . T e r m i n a l s t r o k e s a r e c u t o n t h e d i a o n a l w h i c h h e l p s t o g i v e t h e f a c % ( R L A r i a l v e r s a t i l e f a m i l y o f t y p e f e s w h i c h c a n b e u s e d w i t h e q u a l s u c c e s s f o r t e x t s e t t i n g i n r e p r t s , p r e s e n t a t i o n s , m a g a z i n e s e a % ( R L A r i a l r o m o t i o n s . h t t p : / / w w w . m o n o p * ! #0 %` ' )< ) ** *: * ,r -P .. . / 1 3 3 3 4 4 5 5 5& 56 6 6( 68 6 6 70 7@ 8* 8: 8J 8Z 9f : : ;
|
!
|
% ( R L A r i a l L0 M ML Np N N N N O P Q Q R* R S S T T T W Xl X Y" Z@ Z Z Z [ [ [ [ [ \ ] ] ^B ^ _ `V a a b b c d e& fR f gX gh iz j k k m m o o o % ( R L A r i a l H : x 2
|
|
N v B v > ~ h ( ^ < ` p B p 2 ~ H % ( %
( % R L A r i a l z $ b z B j t <
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
H æ ( Ɔ ư ǒ Ǽ B l ˖ @ j ͔ ; < f ΐ B м ( R | Ҧ % T l [ {
|
Percent 100
|
@
|
!
|
@ [ L X V P N 0 - - 0 % T l {
|
|
@
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
@ L X V P N 1 - - 0 % R L A r i a l J
|
Percent 100
|
B
V n ~ > N d J Z n ~ H ! "l " # $2 % &z & '" '2 ' ( ( ( * + + -< -L / / 1 1 3: 3J 4: 4J 5 5 % T ` 7
|
!
|
|
|
@
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
@ L T . . . R L A r i a l [ [ ^0 `z c eh g jb l2 m n n@ nP n n n n n o( oR ob or o o o p p p p0 p@ pP pz p p p p q qB ql q q q r r> r r r s s: sd s s s t t6 t` t t t % ( % T ` ,
M d
|
Percent 100
|
@
|
!
|
@ ,
L T V P N ! ! $ T h
|
|
@
|
CORGROUP $$dwb_CLK_I_BufferRising
|
@ h
L d I T L B _ S E T S - 1 ! ! ! ! & % % V 0 j M k L L k k L% ( % R L A r i a l B
|
Percent 100
|
P Z & L ~ f " v & N 4 f @ n ( ^ 0 ` > j 8 p % T ~ b
|
!
|
@
|
|
@ L p E F F E C T I V E A D D R E S S a- ) ) - 0 ( - - - 0 0 0 - - - & % & " WMFC 9 y % V 0 F 6
G
5
5 GG
% ( R L A r i a l pearance. Arial is an extremely versatile family ypefaces which can be used with equal success for text setting in reports, presentations, magazines etc, and for display use i newspapers, advertising and promotions.http://www.monotype.com ww% ( R L A r i a l
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
This typeface is the property of Monotype Typogr and its use by you is covered under the terms of a li 6 " B b J r & P | > h * n % ( R L A r i a l h p v x p 4 > . ^ " R B r T
|
Percent 100
|
0
|
!
|
`
|
|
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
|
Percent 100
|
D t % ( R L A r i a l 4 d 4 d * ! #0 %` ' )< ) ** *: * ,r -P .. . / 1 3 3 3 4 4 5 5 5& 56 5F 6 6( 68 6 70 7@ 8* 8: 8J 8Z 9f : : ;
|
!
|
;@ ;p ; ; < % ( R L A r i a l N N N O P Q Q R* R R S S T T W Xl X Y" Z@ Z Z Z [ [ [ [ [ \ ] ] ^B ^ _ `V a a b b c c d e& fR f gh iz j k k m m o o o pR pb pr p p % ( R L A r i a l x 2
|
|
N v B v > ~ h ( ^ < ` p B 2 ~ H L % ( R L A r i a l * h z $ b z B j t <
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
H æ ( Ɔ ư ǒ Ǽ B l @ j ͔ ; < f ΐ B м % ( %
( % R L A r i a l & P P V
|
Percent 100
|
@ B z ( R | $ N x J t F p B l ^ t ~ J % T l ] o
|
!
|
@
|
|
@] o L X P P N 0 - - 0 % T l ]
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
@
|
Percent 100
|
@] L X P P N 1 - - 0 % % T ` ,
|
!
|
|
|
@
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
@ L T . . . R L A r i a l n n n n n o( oR ob or o o o p p p0 p@ pP pz p p p p q qB ql q q q r r> rh r r r s s: sd s s s t t6 t` t t u u2 u\ u u u v v. vX v v v w w* % T I
|
Percent 100
|
@
|
!
|
@ L l P P N I T L B _ S E T S - 2 - - 0 ) % - % - - ) - % T O
|
|
@
|
CORGROUP $$dwb_CLK_I_BufferRising
|
@ O
L l P P N I T L B _ S E T S - 1 - - 0 ) % - % - - ) - % %
( & % % V 0 M L L L% ( %
( %
( & % % V 0 M LL L% ( %
( & % % W , C $ L--% ( & % % W , Z
Y
Y
% ( & % % W , C K
|
Percent 100
|
B LB
|
!
|
% ( % % V 0 % %% % R L A r i a l % T x k
|
|
@
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
@ k L \ T L B S E T ) % - - - ) T l
|
Percent 100
|
@
|
!
|
@ L X I N D E X 0 0 - + & % W $
|
|
a
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
|
Percent 100
|
X
|
!
|
% ( % % V , N =
|
|
N
|
CORGROUP $$CLK_RISC_BufferRising
|
N=
|
Percent 100
|
N & % % V 0
% ( % % T d X
|
!
|
@
|
|
@ X L T C O M P 0 4 7 - & % W $ q h% ( % % V , } ^ ^}^^ & % % W $
$ q
h% ( % % V , ^ B B^^B^ & % % V 0 % ( %
( % % T ` ' q
|
CORGROUP $$CLK_RISC_BufferFalling
|
@
|
Percent 100
|
@ ' L T I N V 0 - & % W $ W i @ ``7% ( % % V , 9 . .`9..R L
|
!
|
|
|
A r i a l % ( %
( % % T l 8 #
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
@
|
Percent 100
|
@ L X H I T 0 0 ) % %
( R L A r i a l % T X
|
!
|
@
|
|
@ L P 3 1 % % R L A r i a l & " WMFC y p
|
CORGROUP $$dwb_CLK_I_BufferRising
|
|
Percent 100
|
% T `
|
!
|
@
|
|
@ L T l o g R L A r i a l ( ) * + , - / 0 1 2 3 4 5 6 7 8 9 : ; < = ? @ A B C D E % T T
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
|
Percent 100
|
@
|
!
|
@ L P 2 , R L A r i a l essors and as such is more in tune with the mood o e last decades of the twentieth century. The overall treatment of curves is softer and fuller than in most industrial style s s serif faces. Terminal strokes are cut on the diagonal which ha% ( % T
|
|
@
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
@ L h ( I T L B _ S E T S ) + 1 3 ! ! ! ! %
( R L A r i a l tname/ms_welcome.htmlNOTIFICATION OF LICENSE AGREE
|
Percent 100
|
|
!
|
This typeface is the property of Monotype Typography and its use by you is covered under the terms of a license agreement. ou have obtained this typeface software either directly from M di% T X I
|
|
@
|
CLOCK CLK_RISC
|
@I L P 1 3 % % % T T
|
PERIODE 2.5
|
@
|
DUTY 50
|
@ L P 0 it% R L A r i a l te this software.
|
OFFSETE 0
|
|
INITIAL HIGH
|
If you have any question conc ng your rights you should review the license agreement you received with the software or contact Monotype for a copy of the li nse agreement.
|
MAXUNCERTRISE 0
|
|
MAXUNCERTFALL 0
|
Monotype can be contacted at:
|
MINUNCERTRISE 0
|
|
MINUNCERTFALL 0
|
USA - (847)
|
JRISEE 0
|
% T l
|
JFALLE 0
|
@
|
GRID 0 1 0 2 0 16711680 0 0
|
@ L X W A Y 0 n O 9 8 . & % W $ { % ( % % V , % R L
|
ENDGRID -1
|
|
DIRECTION internal
|
A r i a l i a l R e g u l a r M o n o t y p e : A r i a l g u l a r : V e r s i o n 2 . 7 6 ( M i c r o s o f t ) A r i a l V e r s i o n 2 . 7 6 A r i a l M T A r i a l T r d e m a r k o f T h e M o n o t y p e C o r p o r a t d % T P
|
MASTERCLOCK None
|
@
|
Clock Unclocked
|
@ L ` I T L B M I S S r ) % - 7 - - T l
|
EdgeLevel neg
|
@
|
Set Not Used
|
@l L ` E X C E P T I O N e - + 0 - - ) 4 0 %
( %
( R L A r i a l y o f i t s p r e d e c e s s o r s a n d s s u c h i s m o r e i n t u n e w i t h t h e m o o d o f t h e l a s t d e c a d e s o f t h e t w e n t i e t h c e n t u r y . T h e o v e r a l l v % T X
|
Clear Not Used
|
@
|
ClockEnable Not Used
|
@ L P 1 2 % % & % W $ % ( % % V , & % % W $ % ( & % % W $
% ( & % % W $ % ( % % V 9
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
& % % W $ { % ( % % V , %
( %
( % R L
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
A r i a l
|
VerilogType wire
|
`
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
D t D . @ x B ^ , \ & V 4 4 d * ! #0 %` % T j
|
HighVoltageThreshold 5
|
@
|
LowVoltageThreshold 0
|
@ j L d P A D D R [ 3 1 : 1 3 ] - - 0 0 0 % % % % & % W ( C G L>% ( & % % W $ 5 3 >*% ( % % V , ! !! !R L A r i a l z zT { { | | | } } ~ ~ : x 2
|
MSB 0
|
N v B v > ~ h ^ < ` p B % ( % % T ~ T
|
LSB 0
|
@
|
isFallingEdgeSensitive False
|
@~ L d P A G E O F F S E T - - 4 - 4 ) ) - - ) T F 1
|
isRisingEdgeSensitive False
|
@
|
DrawAnalog 0
|
@ F L d P A D D R [ 1 2 : 0 ] - - 0 0 0 % % % %
( R L A r i a l 0 Z , V ( R | & P P V
|
BooleanEquation
|
@ B z R | $ N x J t % ( R L A r i a l n ~ > N d J Z n ~ H ! "l " # $2 % &z & '" '2 ' ( ( ( ) * + + -< -L / / 1 3: 3J 4: 4J 5 5 7 7 8` 8p 8 8 : : :( % ( %
( R L A r i a l Wd Wt W W Y2 Z [ [ ^0 `z c eh g l2 m n n@ nP n` n n n n n o( oR ob or o o o p p p p0 p@ pP pz p p p p q qB q q q r r> rh r r r s s: sd s s s % T `
|
NegTolerance 0
|
P
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
@
|
VerilogCode
|
@
|
VHDLCode
|
L T l o g R L A r i a l } ~ ~B ~l ~ ~ ~ ( \ x z J . ( F n ( ^ ` T j b r * * < ( : L ^ p % T T Q
|
PROPS!
|
b
|
!
|
|
|
@
|
CLOCK dwb_CLK_I
|
@Q
|
PERIODE 5
|
L P 2 R L B A r i a l ~ f " v & N 4 f @ n ( ^
& WMFC y 0 ` > j 8 p 2 b P < p j 8 X m% T c
|
DUTY 50
|
|
OFFSETE 0
|
@
|
INITIAL LOW
|
@c
|
MAXUNCERTRISE 0
|
L h ( I T L B _ S E T S ) + 1 2 ! ! ! ! & % W $ % ( % % V 0 z b
z b
b
z z % R L A r i a l p v x p 4 > . ^ " R B r T
|
MAXUNCERTFALL 0
|
|
MINUNCERTRISE 0
|
0
|
MINUNCERTFALL 0
|
`
|
JRISEE 0
|
|
JFALLE 0
|
D t D . @ % T Y
.
|
GRID 1 1 1 2 2 16711680 0 0
|
@
|
ENDGRID -1
|
@ L l D & A a t t r i b u t e s 0 - - % % % % " & % % V 0 `
|
DIRECTION input
|
f a
|
MASTERCLOCK None
|
e e a
|
Clock Unclocked
|
a
|
EdgeLevel neg
|
e% ( %
( % R L A r i a l Q R* R R S S T T T W Xl X Y" Z Z Z [ [ [ [ [ \ ] ] ^B ^ _ `V a a b b c c d e& fR f gX gh iz j k k m o o o pR pb pr p p rr r s s tp u^ % T
|
Set Not Used
|
]
|
Clear Not Used
|
@
|
ClockEnable Not Used
|
@
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
L ` P A G E F A U L T - - 4 - ) - 0 % ) & % W $ 0 B 9 9% ( % % V , a
|
ActiveLowClockEnable True
|
` a
|
VhdlType std_logic
|
9 ` & % % W $ 0 9 % ( %
( % % V 0 m M mMMmmM % R L A r i a l ( R | Ҧ P \ ך & l 8 ^ 0 Z , V ( R | & P P V
|
VerilogType wire
|
@ B z % T x v .
|
SystemCType sc_logic
|
@
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
@v L \ S R [ S U P V - 0 - 0 - - T T 4 ~
|
StateEquation Hex(Inc(0,2,5))
|
@
|
HighVoltageThreshold 5
|
@ 4 L P ] & % W $ % ( % % V , a
|
LowVoltageThreshold 0
|
a
|
MSB 0
|
& % % W $ % ( %
( %
( %
( % % V 0 } } }}R L A r i a l t t6 t` t t t u u2 u\ u u u v vX v v v w w* wT w~ w w w x& xP xz x x x y" yL yv z zZ z z {$ {N {x { { { | |t | | | } }F }p } } } ~ ~B ~l ~ ~ % ( % R L A r i a l r * * < ( : L ^ p 0 6 ` . x H R d r f , ` B % T p B
|
LSB 0
|
@
|
isFallingEdgeSensitive False
|
@ B L X A C C E S S - 0 0 - - - T d g
|
isRisingEdgeSensitive True
|
@
|
DrawAnalog 0
|
@ L T T Y P E ) - - - & % W $
{ %
% ( % % V , ] .
.
.
].
%
( %
( % % T z
H 0
|
BooleanEquation
|
@
|
NegTolerance 0
|
@z
H
|
PosTolerance 0
|
L ` P R O T E C T I O N - 0 4 ) - 0 ) 4 0 T
& 2
|
UserSpecifiedSizeRatio 1
|
@
|
VerilogCode
|
@
|
VHDLCode
|
L ` A T T R I B U T E S - ) ) 0 - 0 ) - - & % W $ \ e % ( % % V , f f R L
|
PROPS!
|
|
!
|
A r i a l # XX> C ' ,f (Q Arial Arial % ( % R L
|
|
|
SIGNAL dwb_ADR_O
|
A r i a l E - C hQ Arial Arial C C M T316eafa793t % T
2
|
DIRECTION output
|
@
|
RADIX hex
|
@ L ` D M M U P A G E X0 7 7 0 - - 4 - T l Q L $
|
GRID 0 1 0 1 0 16711680 0 0
|
@
|
ENDGRID -1
|
@Q L L X F A U L T ) - 0 % ) T ?
|
Clock
|
@
|
EdgeLevel neg
|
@ L ` E X C E P T I O N - + 0 - - ) 4 0 & % W ( % ( % % V 9
|
Set Not Used
|
|
Clear Not Used
|
. - C Arial ? ? ?? ? ? ? - 2
|
ClockEnable Not Used
|
y! SET 0 - - ) % 2
|
ActiveLowSetClear True
|
! SET 1 - - ) % C Arial ????????????????????????? - 2
|
AsyncSetClear True
|
b ... C Arial ????????????????????????? - 2
|
ActiveLowClockEnable True
|
= SET - - ) 2 Arial ??????5?????????????????? - 2
|
VhdlType std_logic
|
J
I * Arial ?????????????????5??????? - 2
|
VerilogType wire
|
J
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
TLB_SETS-1 - - $ :
::
- C Arial 2. All Rights ReservedAri - C Arial & TM Off. and elsewhere. - C Arial acteristics than many of - C Arial uller than in most indust - C Arial versatile family of typef - 2 Arial romotions.http://www.mono - 2 Arial ?A?A?A?A?A?A?A?A?A?A?A?A? - 2 Arial ?A?A?A?A?A?A?A?A?A?A?A?A? - "System c pxρ / - - C Arial ?A?A?A?A?A?A?A?A?A?A?A?A? - 2
|
StateEquation Hex(Inc(0,2,5))
|
[ VPN 0 - - 0 % 2
|
HighVoltageThreshold 5
|
VPN 1 - - 0 % C Arial ???????? ??????????????? - 2
|
LowVoltageThreshold 0
|
... C Arial ????????c???????????????? -
|
LSB 0
|
- 2
|
MSB 31
|
,
VPN ! ! $ 2
|
SignalActionType 0
|
h
ITLB_SETS-1 ! ! ! ! - - $ k L L k k L - - C Arial ????????????????????????? - ! 2
|
isFallingEdgeSensitive False
|
EFFECTIVE ADDRESS- ) ) - 0 ( - - - 0 0 0 - - - - - $ G
5
5 GG
- C Arial ????????????????????????? - C Arial ????????????????????????? - C Arial ? ? ? ? ? ? ? ? ? ? ? ? ? - C Arial ?A?A?A?A?A?A?A?A?A?A?A?A? - C Arial ?A?A?A?A?A?A?A?A?A?A?A?A? -
|
isRisingEdgeSensitive True
|
C Arial ?A?A?A?A?A?A?A?A?A?A?A?A? -
|
DrawAnalog 0
|
C Arial ?A?A?A?A?A?A?A?A?A?A?A?A? - - - C Arial ?A?A?A?A?A?A?A?AA?A?A?A? - 2
|
BooleanEquation
|
o] PPN 0 - - 0 % 2
|
NegTolerance 0
|
] PPN 1 - - 0 % - 2
|
PosTolerance 0
|
... C Arial ????????????????????????p - 2
|
UserSpecifiedSizeRatio 1
|
PPN ITLB_SETS-2 - - 0 ) % - % - - ) - % 2
|
VerilogCode
|
O
PPN ITLB_SETS-1 - - 0 ) % - % - - ) - % - - - $ L L L - - - - - $ LL L - -
|
VHDLCode
|
- - % L-- - - - % Y
Y
- - - % B LB
|
VhdlMapping DefaultVhdlMapping
|
- - - $ %% - C Arial - 2
|
PROPS!
|
k TLB SET ) % - - - ) 2
|
E0 V -1 -1 1 0 DR 0
|
INDEX 0 0 - + - %
|
E1 X 3123 3123 1 0 DR 0
|
X
|
E2 V 13125 13125 A0 1 0 DR 0
|
- - - $ N
|
E3 X 13625 13625 1 0 DR 0
|
N=
|
E4 V 23125 23125 A4 1 0 DR 0
|
N - - $ - - -
2
|
E5 X 23625 23625 1 0 DR 0
|
X COMP0 4 7 - - % h - - - $ ^}^^ - - %
h - - - $ B^^B^ - - $ - - - - 2
|
E6 V 33125 33125 A8 1 0 DR 0
|
' INV 0 - - % ``7 - - - $ .`9.. C
|
E7 X 33625 33625 1 0 DR 0
|
|
E8 V 43125 43125 A12 1 0 DR 0
|
Arial - - - - 2
|
E9 X 43750 43750 1 0 DR 0
|
HIT 0 0 ) % - C Arial -
|
E10 V 53125 53125 A0 1 0 DR 0
|
2
|
E11 X 53750 53750 1 0 DR 0
|
31% % 2 Arial - 2
|
!
|
log ! Arial ( ) * + , - - 2
|
|
2 2 Arial ????????????????????????? -
|
SIGNAL dwb_DAT_I
|
-
|
DIRECTION input
|
2
|
RADIX hex
|
(ITLB_SETS)+13 ! ! ! ! - C Arial ????????????????????????? -
|
GRID 0 1 0 1 0 16711680 0 0
|
2
|
ENDGRID -1
|
I 13% % - 2
|
Clock
|
0% S Arial ?????????????5??????????? - 2
|
EdgeLevel neg
|
WAY 0 O 9 8 . - % - - - $ - C
|
Set Not Used
|
|
Clear Not Used
|
Arial ialRegularMonotype:Arial - 2
|
ClockEnable Not Used
|
ITLB MISS ) % - 7 - - 2
|
ActiveLowSetClear True
|
l EXCEPTION- + 0 - - ) 4 0 - - C Arial y of its predecessors and -
|
AsyncSetClear True
|
2
|
ActiveLowClockEnable True
|
12% % - % - - - $ - - % - - - %
- - - % - - - v $9
|
VhdlType std_logic
|
|
VerilogType wire
|
- - % - - - $ -
|
SystemCType sc_logic
|
- - C
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
Arial ?A?A?A?A?A?A?A?A?A?A?A?A? - 2
|
HighVoltageThreshold 5
|
j PADDR[31:13]- - 0 0 0 % % % % -
|
LowVoltageThreshold 0
|
% L> - - - % >* - - - $ !! ! C Arial ?A?A?A?A?A?A?A?A?A?A?A?A? - - - 2
|
LSB 0
|
~ PAGE OFFSET - - 4 - 4 ) ) - - ) 2
|
MSB 31
|
F PADDR[12:0] - - 0 0 0 % % % - 2 Arial ?A?A?A?A?A?A?A?A?A?A?A?A? - ! Arial ???????????????????????? - - 2 Arial ????????????????????c???? - 2
|
SignalActionType 0
|
|
isFallingEdgeSensitive False
|
log ! Arial ????????????????????????? - 2
|
isRisingEdgeSensitive False
|
Q
|
DrawAnalog 0
|
2 2 Arial ???????????????????????? -
|
BooleanEquation
|
2
|
NegTolerance 0
|
c
|
PosTolerance 0
|
(ITLB_SETS)+12 ! ! ! ! - % - - - $ z b
b
z z - C Arial ? ? ? ? ? ? ? ? ? ? ? ? ? - 2
|
UserSpecifiedSizeRatio 1
|
D & A attributes0 - - % % % % " - - $ a
|
VerilogCode
|
e e a
|
VHDLCode
|
a
|
VhdlMapping DefaultVhdlMapping
|
e - - - C Arial ?A?A?A?A?A?A?A?A?A?A?A?A? - 2
|
PROPS!
|
|
E0 X 11250 11250 1 0 DR 0
|
|
E1 V 13125 13125 D0 1 0 DR 0
|
PAGE FAULT- - 4 - ) - 0 % ) - % 9 9 - - - $ a
|
E2 X 21250 21250 1 0 DR 0
|
9 ` - - % 9 - - - - $ mMMmmM - C Arial ?A?A?A?A?A?A?A?A?A?A?A?A? - 2
|
E3 V 23125 23125 D4 1 0 DR 0
|
v SR[SUPV - 0 - 0 - - 2
|
E4 X 31250 31250 1 0 DR 0
|
4 ] - % - - - $ a
|
E5 V 33125 33125 D8 1 0 DR 0
|
- - % - - - - - - $ } }} C Arial ????????????????????????? -
|
E6 X 41250 41250 1 0 DR 0
|
- C Arial ????????????????????????? - 2
|
E7 V 43125 43125 D12 1 0 DR 0
|
B ACCESS- 0 0 - - -
2
|
E8 X 53750 53750 1 0 DR 0
|
TYPE) - - - - % %
- - - $ .
.
].
- - - - 2
|
!
|
Hz
|
|
PROTECTION- 0 4 ) - 0 ) 4 0 2
|
SIGNAL dwb_DAT_O
|
|
DIRECTION output
|
ATTRIBUTES- ) ) 0 - 0 ) - - - % e - - - $ f C
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
Arial ?#???C ? ?? - - C
|
ENDGRID -1
|
|
Clock Unclocked
|
Arial E-?? ? AC ?A?? - 2
|
EdgeLevel neg
|
DMMU PAGE0 7 7 0 - - 4 - 2
|
Set Not Used
|
LQ FAULT ) - 0 % ) 2
|
Clear Not Used
|
EXCEPTION- + 0 - - ) 4 0 -
|
ClockEnable Not Used
|
% - - - v $9
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
Visio (TM) Drawing
|
ActiveLowClockEnable True
|
N TH 2M R l ! fff MMM 333 $
|
VhdlType std_logic
|
$
|
VerilogType wire
|
U38@ Td Arial@N Wingdz s@N@tMonotype Sort+
N tSymbol 5T?? Y@ - 1 U J:D T1EW-hT T< *
|
SystemCType sc_logic
|
/U b
bO 0zGz?@8@H2!kWb*U
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
+$ PL/^&9^$? { Ak^&,,'%/v&& *
|
StateEquation Hex(Inc(0,2,5))
|
1y
) P? 2
U
U12?k9 a BBHEHEHEHEHEHEH@?>?:`T2BBHEHEHEUHEHEHEHE%H@%O9 F 7AOY@;P
AsVsVA!gLTkY W_W__ !`# k4l b6u`kW *4l
|
HighVoltageThreshold 5
|
4l %Y?P:?-\
#!+|QtKf2|2|2|I2wGQ A UoTMeE$ttA%_ 8BOTOfOxOO??HO?7ܻ XuW?YsU42
|
LowVoltageThreshold 0
|
T*
|
LSB 0
|
x x x
|
MSB 31
|
0jPvȲl^/!3jBj6D///$Q 0p?Mdj^cj4Ak[~ϐ$YkU1% 1F-(kp
ٻ A. $5-B i`# 9)F/Pv// ߾/u?2trߜKS52 7xߢ#6@h$MuLh Ճ %ԊՑ ) <OU # 5 G ::U2 q ?/&w&
|
SignalActionType 0
|
<<7H 1O QjP SH QywH At///Y OG$_ p4b%F! 8q/#P?C/N^qhE! @d)n{r1P1 @ /Oqt}Q!n =k@Ʊ셩{B'ɂXVP_0TNJg21 1R5P"QQ[O" P!q[rr qqӂqq¢ӁӁP¡¡Waa7$VW7P$q"$qP1q1qP>q">qPKqKqPXq Xq2eqeqZ2Sob ZZdSTQcd PQQ P1H[<k?ta}Y M/OO*Dd3qO/NkS\O 9E/ / _ ? ?-??=___ѷ'sϖdI,O 0R 7nO&ګa ̗ѫaW?O // ?*
|
isFallingEdgeSensitive False
|
K ϥϷϾCNa \ "4FXj ߲K߳ BTf_/q/ //, ڭaRdv *<+/`bbiA nFUj?|?~/ "C??Va]? Ia(G
|
isRisingEdgeSensitive False
|
rpl/YDE@a1LO pO #Q/I SGQۍBQfQaIq_Uyj ( ȄBb_(_:_/^_ //Q__a1 _ OO-OF ZO Qo~MA %o C AOOMgy N_r_O7 Zg @ :o,Ko -XyCŮbddpddp A͟ߟ'@9K]vAB(Onl=# ??6HZl Ǝ' ;M_q 2DV hzόϞϰ
|
DrawAnalog 0
|
.@Rdv ߚ߬߾#} (:L^p Uɑۏ"4FXj@|X *<N`r & 8 J \ n Y / ///A/S/e/w///F/L// ? ?$?6?H?Z?l?~?? ?????? O"O4OFOXOjO|O OOOOO _ _ 0_B_T_f___ _____oo'o 9oKo]oFxoOoo oooo,>PPfx ,> nBsgcEf Ώ (ٴJ\n ȟڟ" OeOj|@į֯ ( :L^pʿܿ B#vXT+Sb b z @v 6M_Toρ6 ϱi -?Qcu ߙ߽߫ ϭ, /-?eY[Ưy +=Oas 1ńR Z sc<Ɠ`Zl~ sb6-1R# # 5 G Y k } x;6/ F%/jI/[/m////) ////
|
BooleanEquation
|
? ?.?@?R?d?v??? YTV
|?bO 2ODOVOzOaq OOOOOO_ !_3_E_W_i_{___ _____ o o/o Ao}x^oK Acrobat Distiller o d 7X X6 $)/@o .0 ²r
|
NegTolerance 0
|
dt ' 9 K ] o Custom ?page 0 ,/FBN#/#1>//?/Q/
*2////
*3/.?//d:h # winspool Acrobat Distiller c:\Program Files\Adobe\4.0\PDF Output\*.pdfUFDf P
h> / T6DUmA@
?ۿI? Y{O1@3 EE b O e Z
|
PosTolerance 0
|
Hu P (: { W_q QGeneric box with text and connection points. Can be stretched to y dimwens s. mb?贁No ? k? 4
HDD
$# =h-(>TTE=UA??Q6 u ` 6u mB> 00 0 (2s@sJs&T> 5
L @{5 `7Copyright 1999 Visio Corporation. All "s reserved. ` _SBl.chm!#22448 d 9 l>#0>Udd#3 T
|
UserSpecifiedSizeRatio 1
|
<h b
261
|
VerilogCode
|
g,s724?`b?M1^%Y? r? 91M1E; 6==5(2?;zrA
|
VHDLCode
|
IB=OCq ,^35/rV:?@F AC MAOMOO@ _2A#[ 6OMZM"3A^%\ $___Z__B#[@ o_9Bo[(
^text Hl& ' ! Oya GEF # o JB
|
PROPS!
|
j] \a\k _ @ +dk 3ak I k % Ul4,< @.%@ ]W A-3 c7 "A % Ul4,< @.%@ W A-3 7U~}@T eBR0BTf*
?H<(
|
E0 X 3125 3125 1 0 DR 0
|
H<(
|
E1 V 3126 3126 D0 1 0 DR 0
|
U~E %
R0BTf
4 2 UFDf
h - TUU [U@@??I?`d
buoqYkQhu23u` Connector
|
E2 X 43125 43125 1 0 DR 0
|
`
|
E3 V 53124 53124 D0 1 0 DR 0
|
e1 C rw
|
E4 X 53750 53750 1 0 DR 0
|
UH ^ -}|5 p`I` V ?}`xa 833 ސ ] 3σ3 u 33?, ? Gxpx ^ &
CThis connector automatically routes between the shap i
ts.b?贁N ? HD
@# =h8T YY9 BF U@?
ۿP6
|
!
|
u
|
|
`u# `b A @u
J .Q# DB # ։u `h?U\hr|Su Za { @-?bHl;'b E-ho' y(
|
SIGNAL dwb_WE_O
|
2r q ?@I k?$%?
|
DIRECTION output
|
@ "V *5L -b r/ ^vԜv"(2u &."q28iv"uh 9Bd &< O/M {
|
RADIX hex
|
#145 `Vis_SBl.chm!#22474 `7Copyright 1999 @io Corporation. All $AUd3 CE \^ 4
|
GRID 0 1 0 1 0 16711680 0 0
|
*L 1$b 24R(^[w[D ZQi a59 93O ' 2"q?/g;2GHls ' $ ! Oya GEӧF r # @ 7 B
|
ENDGRID -1
|
L w$ dro @ +Ik "sk 5o ( S J + B ?9 = 3R D ?Pi{" / | UPx P4FD Tey
ahj TqUIߴ< @%@??I?*? Q c `2 @ ? qu `&u o <Q w! w! ` Connector
|
Clock Unclocked
|
`W "
|
EdgeLevel neg
|
*eU0'$P !a ! J6$ !"#$%&$()*+,-.
|
Set Not Used
|
/
!+1H<47 47 "7 !7 4a718171 8171817 4!7 18'17! 817'18/17+18:187/1 87318G17 89!78 :?18 :8[17G1 87K18c179! 8k17S18w17W1 8!7[181:_1"82:c183:g1"84:k185:! 8S17s18 17w1 8W17{18g171 8!718s171 817181718138/ C PS1S1s1Ds1QQ !_1D_1ac1c11g1Dg11QQaDa 1k1k1!aDa1111D1W111!aDa1!!aaaap 0 2uEiafC< 1|fE ! c1E !5)EDsN@@|=$@
|
Clear Not Used
|
̿
|
ClockEnable Not Used
|
?p! a1H- "d1a2l(?1N<s1<<< -?{l1!>SU1IE/R
3ÞP by5 {bº,Eq4111 ,E( !@q`dm@ bqqbC`l̤ 5l8J_°i ߒ/1b FFECTIVE ADDRESSC j 45/G/*N\ 3z&&i4*_1N ' 2 q
|
ActiveLowSetClear True
|
E#UT mǟٟ"/W{
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
ض.@R !Q,l4Gdì?[m? 9A|0T ůׯ. +=OsZ ɿb ,>Pb i/ύ/4/ /Q ?;?@_?|?ߠ5;ۿVPN 0
|
VerilogType wire
|
11
|
SystemCType sc_logic
|
F...G2ITLB_SETS-1=H*'" H.{U8kU oB EOJ1G]5 1KU7R G8cRZ!z[儻U?a `kIP_b_
1
_fa{ *]59K]o@[vkvHZ~Tia ' 9 K o v // ,/>/P/?%x/?/#z// k ?(?L? R${r?x?
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
ץJ;P21O<1!G2R+GooYOpoOOOO U)ƿ ؿOOH_oo~_ ______Zl o2oDd^aESlEէ poognӤoon\"9N'@@|=%$
~(u'v1C`U03w.1Zړ̓ pT|^a(: L^p0mʏ u);M _q!|*џ |w%? ;/ 1N ǯ r x ;S
|
StateEquation Hex(Inc(0,2,5))
|
߀I[/ 0 )q-AX`$/6,_< ^a SaOSlSS|ߎߔgS
|
HighVoltageThreshold 5
|
"4FXj42FuS E;1(: L^ (_6U_ +__-?Q c 8 :;G;H3o' _ ^oo = -8 J S_Ay1_cE7? +um9Pa$!IE4@E{CEu9p\8"/{ 6:u PkRAu0`u^`Agӂu
ہ YA1 nhDsN%rtږR@ p5%E` @z3Z`r5"&5"
|
LowVoltageThreshold 0
|
җhSYV2r
?@I?V?ČBu@`m@CDuy0`
|
SignalActionType 0
|
ףp=+
|
MSB 0
|
W8&H9-kx0 Qe#"(
H @`0 AO{-pOTIKE AISB_8OOZ Yo|D X nYLRؿ$ϸWYL˧cR eϫ_n Ajo]5q5//H9*
|
LSB 0
|
Սv4U
W0ɐ=5"] Aa5ooβ GYLp !DOa 14 d4V$6HZloq:?=I)⨅4ӏ \* F4@ GV I; ð"*<` ?_A=/mǫ߀ؠaܯ $NAT `rC5E ϱ
|
isFallingEdgeSensitive False
|
1DiI wI''??{/')O;O uC6ԹqM, +sq EOi \"9N'
|
isRisingEdgeSensitive False
|
_ _._@_R_R'b d ԀU6T U__;@u
Qfp@US`ܦ jjZ e$@/@ )pup5 fp@z3Q/5G֧Dif!ZoU@OOi糘oo` F]tE ƏouId"04FXj +~RQT ,߾OݢY5H o 1ˑ#5G`k0 ;jD{8\ Utp߉TLB SET? INDEXROÕl? oa7 p? ]1s]Y#֒V }-b ŨvF@"Z1)ŨY RRFʢŢo[0mSRfiT #q27F XP X~8ŵϜ
\0 qqI}SY1H߾*"$ @J+ /C8! HCSZœ%5|Ŗq]_U## U
|
DrawAnalog 0
|
UԓUVρ S F(~eNBD ŵ
|
BooleanEquation
|
/b8!LQZG#27 q@?OFcD?ǐup!%H}uԀ n9Hqf* ߆/ߪ&-6 ~_]<__4g hm^$o_Hmq_|ooT߁ŵ:-0
|
NegTolerance 0
|
-1
|
PosTolerance 0
|
v... w-)_-S-1 iDˑq |ߩgHN9Qo8m:' D r>LƠ ]tI)rB{ŵwUw /Ad0Os ?.a`kԤdo8
%C qˑ/
5AQ?ғ ;e5QS55Q3aZ,zuyR9E:?@E_$ * ?Ql_U^Sb T{jn9D?ҟqe__*_<_NX [Y^qo³)e IŲiŋ뺫e q6qHZlU@o8*'wn _U߄phϲħ4ĨUfϿ4a s߈jexjq COMPB eCɟg2?V?h?P$TP-DT!/ASew ?
O0 "
41Z2DyE
/ /0/B/T/f/ x/o//* '1CUgy@DsoN@3]#5GYk}$I6/Y@'" )Vp%܍7 0@z 3A2?>,6
|
UserSpecifiedSizeRatio 1
|
* 'ՄAߚ,m ןhgRQ INV/q 8o/'/D)ˏt,Ӆ/ /// ??$?`6?H?Z?l?~?/ѐKƫ?U
|
VerilogCode
|
^ 7EO&OZKJO K= ZGOOOO _!v+SzdG2 qì?涓lt?
|
VHDLCode
|
$O`a_!;_ M___q______ pc _HIT 0 ao߯TPrewqD%rt?@|=I%%к\
?Pa+τ;B9jult rL
|
PROPS!
|
AN | brT W n e @ g cW /{ 3/P/ `t/ հ31I o\n U>qNt1Ug\"9N+@
1 CU^@O8F
|
E0 X 3126 3126 1 0 DR 0
|
@ ODs1 2 D //// M6_&/ _: __:/!o^/_Wo/{o_o/log2(ITLB_SETS)+12 i-^X0' 2UrB ~rVL{~ܧxCpj5B
9Ey^XGHm !3 Q?D/İ ? `,k!);^X^XJ
? ?1?C?U?g?y????@DsN
????O#O g $OPQOcOuOO OOOOOO__ )_;_M___q_ooo __Boƿo꿊o ϮomooV¿o@ !3x3? Qcu M_ qˏGY ,CS e`rVş5' (
1 +J<
|
E1 0 13125 13125 1 0 DR 0
|
z q )/M/ q/ 7U,==, [k}˟ݐ)!'#5GE AT.F}
1 C / // _92_ / h_:__4/_X&_ D_/o'_2oDo%*>
|
E2 X 13625 13625 1 0 DR 0
|
k0Grp J\+dã>7 @@ٓ|{P-DT!]-u{`u`b u
8 3р +
Kp2I{H
v _eO? )p> @z 3 {%'zz//A% {m'9-w/A GсSչ Qbi{ӏBبd6G2,rq?7?I6Kb+?Ty] (Alǿ{ύKU *gy ];?iѾhITLB MISS
|
E3 0 23125 23125 1 0 DR 0
|
|
E4 X 23625 23625 1 0 DR 0
|
EXCEP/TIONGr% );M_q
|
E5 0 33125 33125 1 0 DR 0
|
u! { $ 6 H Z ܁A1.f BXsBW.fg-gC$on.fgm=go// /,P/ذ$?6??a?s????? ??.OO ?GO 軈B&OO*
|
E6 X 33750 33750 1 0 DR 0
|
>~Eӏ7PE
ŗM8 U c#]^\lSV~vpZ Qv(TX֓L~* !F=FTU֒-qs@ق--?@I\?RZ忚G0 >Y, /zN#' kq
w5u0xɧSth`0 ,$O(,ϓ vdЋKy]HSR[SUPV] jX
ŕQI| !3h~ @.v ʏO OO__L'_dK*FT^f_x______0__ȟ6et6Go8U(nl~ft67s7d?> t6G=7 O2 Dh/Oe 2DV }R
|
E7 0 43125 43125 1 0 DR 0
|
(_ ) /- #Ge/w'Zm)!v.*P-DT!////
|
E8 1 53125 53125 1 0 DR 0
|
? ? .?@?R?̝Qv?2n`| @5v ww4vC wMTOfOxOOO __,_>_P_b_t__ _
|
E9 0 53750 53750 1 0 DR 0
|
hZaa
|
!
|
a /ߟ9WٓTfx ߜ߮aߟ? aH-QZl~ OpVOzTa
0a #G% bp ſ
|
|
ߕ Q=!XACCESS TYPE/ A S e w .
o o1o/"/4/F/X/o|'g5.h . o $6HZl~y~%@@"'@@54 L V .ϧ aϮO d/
|
SIGNAL dwb_SEL_O
|
! __ ߕAe//_ [PROTECTION
|
DIRECTION output
|
|
RADIX hex
|
ATTRIBUT ES/ $6HZl~
|
GRID 0 1 0 1 0 16711680 0 0
|
nXo $6HZl~ wH1yF
|
ENDGRID -1
|
=&A8 Sp!mYNW b@@z3oARN_`^@FWG"_^F W]W_ + " Vlf o /1/C/U/g/ y//////Hr ?6aQDMMU PAGE
|
Clock Unclocked
|
|
EdgeLevel neg
|
FAULT EXCEP31O2P?b? t??x9#xC?"/{ @@? 6bu Ƀ7OIO[OmOOO OOOO ds@ "e 1iK*o
|
Set Not Used
|
.@ dvɎa; 1&8J\n@DsN
|
Clear Not Used
|
R;QO⏿
|
ClockEnable Not Used
|
.@ Rdv
c_mp@HRp2|Ud_ ߉_Ic
b" cU!r_ \oѯg2b2 /ASewqȆ2 I?ͷ뵯1ٿ0Ǩ9ѱ5 47 $PE8CeXeњؖ ;$?P;:ɀ`@ғC#/ęFѝNA}B}qn2rb?@IϮ"
CMB7&7% DŤHj4˨ а`xáe˯)%ȕ< 3/st 5*DTK]qq AӞ7 u;?u?C Ͽ*
'9K]϶_?@2BC`+=OAVßB_ eOVgW+o'nV\g(m WfoV/
/ ߯ ?(:T?^x? VyNsxsTFADDR[3?1:13]
|
ActiveLowSetClear True
|
BJ O)DJ '$6HZl~vљg@@|=iU$EE#ZT#X P`/0њɩƀRސ)$7@ p )tڜ>bR `uAЇ v3x?/ /2/D/o h(}//)(`U/T` /`9~C rO=? Dq4Fs?q 1y;ψ6?Ǽ?#·F5&O8O JO>nOOؿOOn vH _ _/_A_S_e_w___ \Y_u vd2d"W#ao no=o /SeωYn!}GE OFFSET
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
s?12:0] UF U #$%U&(+-U.01235 Ul4,< @%@ _MD ;C-_ 7 AU2@$ D7 JR H<(
|
VhdlType std_logic
|
U2El D7
R UlL (
|
VerilogType wire
|
4( U1( UO"D&aU=QJf )h" Ty+Uv' _ Ʌ &aQ-
|
SystemCType sc_logic
|
- H* 9( TYg EQ /, Guide TheDoc Page-1 Gesture Format Block Normal Visio 10 Block Shadow Visio 12 Block Highlt Visio 11 Connector Visio 90 Dot Connector Connector Arrow Visio 00 Visio 01 Visio 02 Visio 03 Visio 13 Visio 20 Visio 21 Visio 22 Visio 23 Visio 50 Visio 51 Visio 52 Visio 53 Visio 70 Visio 80 Box Dynamic connector.8 Box.3 Box.4 Box.5 Dynamic conn?ector Dynamic connector.10 Box.2 Box.24 Box.33 Dynamic connector.39 Dynamic connector.50 Dynamic connector.52 Dynamic connector.9 Dynamic connector.45 Box.13 _ 63 .F
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
E$ 8 4 C-
|
StateEquation Hex(Inc(0,2,5))
|
D NT G\ f U t w
U c
|
HighVoltageThreshold 5
|
u
|
LowVoltageThreshold 0
|
U Q
|
LSB 0
|
u
|
MSB 3
|
W u
|
SignalActionType 0
|
UU4 UL Gv d | , 9 F S ` m z$<TlJc U H A[* J[* { [ { U*,{ $[ { ?[ Ul{ ^[*t{ b*{ l[*{ p[*{ tT[ 0{ [*{ U!:{ *{ խ[*{ *W *$0[ Z:'D0 I)d0)+0^'l0/00*(! 0 xRf
|
isFallingEdgeSensitive False
|
I! :! T!!"#%%&'(*)*+!U-./0U1245 UjU
|
isRisingEdgeSensitive False
|
U
UUU Ul4,< @%@ T _K UC-UD3 7 A Ul4, =L
|
DrawAnalog 0
|
AJ- 3 G7 A _ *<N@ K IRVg IL 6uH<(
|
BooleanEquation
|
H<(
|
NegTolerance 0
|
_ *<NE L
RVg q k{ z
|
PosTolerance 0
|
* g"4pFX (4
@( q b@2y
|
UserSpecifiedSizeRatio 1
|
JlO :]R
|
VerilogCode
|
TQ U#u &T !B }U ?Q
>XC O :B m `O ĭ Gfi$̧ f'ơ#E^N,ç t)\*}1Ս=|` 2D :I UV
|
VHDLCode
|
O? L G}D 5 C=d #MJ!_ 5,Y @ Oh +'0 @ H h t Valued Sony Customer G (E x w
|
PROPS!
|
w
|
E0 X 3123 3123 1 0 DR 0
|
EMF E X V I S I O D r a w i n g M D ? ? l ( @ ( ʦ Pages Masters Page-1 Box Dynamic connector 8 _VPID_PREVIEWS _VPID_ALTERNATENAMES _PID_LINKBASE A
|
E1 V 13125 13125 Valid 1 0 DR 0
|
F Microsoft Visio Drawing VISIO 6.0 Shapes Visio.Drawing.6 9q P&l P
& " WMFC X x x j P &l EMF x l X V I S I O D r a w i n g
|
E2 X 13625 13625 1 0 DR 0
|
% R L A r i a l % T l ! y
|
E3 V 23125 23125 Valid 1 0 DR 0
|
@
|
E4 X 23625 23625 1 0 DR 0
|
@! y L X S E T 0 - - ) % T l !
|
E5 V 33125 33125 Valid 1 0 DR 0
|
@
|
E6 X 33625 33625 1 0 DR 0
|
@! L X S E T 1 - - ) % R L A r i a l JSTFm*i Wp LTSH& X OS/2 3 VPC AG ? 6VDMXVp ] cmapܣ 1 cvt ؔ 8 8fpgm Ggasp P glyf~( ިhdmx yhead fY | 6hhea $hmtxR p :kernAON *P Zloca % T ` b 6
|
E7 V 43125 43125 Valid 1 0 DR 0
|
|
E8 X 43750 43750 1 0 DR 0
|
@
|
E9 V 53124 53124 Valid 1 0 DR 0
|
@b L T . . . R L A r i a l F d $ X * n 2 $ f 0 F P B r , > P r R ª % T ` =
S
|
E10 X 53750 53750 1 0 DR 0
|
@
|
!
|
@=
L T S E T - - ) R L A r i a l Ѱ & b Ҟ 4 d ӊ Ӱ P Ԑ " Z Մ ծ 4 Z ք ֮ B r ע 0 ` ؐ $ ل ٸ P ڰ H ި All Rights ReservedArialBoldMonotype t)% T J
x
|
|
@
|
SIGNAL dwb_STB_O
|
@ J
L d D T L B _ S E T S - 1 TM & % % V 0 9
:
::
% ( R L A r i a l of the last decades of the twentieth century. Th erall treatment of curves is softer and fuller than in most industrial style sans serif faces. Terminal strokes are cut on th diagonal which helps to give the face a less mechanical appear ti% ( R L A r i a l in reports, presentations, magazines etc, and for play use in newspapers, advertising and promotions.http://www.monotype.com/html/mtname/ms_arial.htmlhttp://www.monotype.com/ht /mtname/ms_welcome.htmlNOTIFICATION OF LICENSE AGREEMENT
|
DIRECTION output
|
|
RADIX hex
|
Th ot% ( R L A r i a l reement. You have obtained this typeface software er directly from Monotype or together with software distributed by one of Monotypes licensees.
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
This software is a valuable sset of Monotype. Unless you have entered into a specific lice na% ( R L A r i a l own publishing use. You may not copy or distribute s software.
|
Clock Unclocked
|
|
EdgeLevel neg
|
If you have any question concerning your rights you should review the license agreement you received with the s tware or contact Monotype for a copy of the license agreement.
|
Set Not Used
|
% ( R L A r i a l //www.monotype.com/html/type/license.html N e g r a A r i a l N e g r e t a t u
n A r i a l t u
n f e d A r i a l f e d F e t t A r i a l F e t t A i a l T y p e f a c e T h e M o n o t y c % ( R L A r i a l T y p e S o l u t i o n s I n c . 1 9 9 0 - 9 2 . A l l R i g h t s R e s e r v e d A r i a l B o l d M o n o t y p e : A r i a l B o l d : V e r s i o n 2 . 7 ( M i c r o s o f t ) A r i a l B o l d V e r s i o n 2 i % ( R L A r i a l i o n p l c r e g i s t e r e d i n t h e S P a t & T M O f f . a n d e l s e w h e r e . M o n o t y p e T y p o g r a p h y M o n o t y p e T y p e r a w i n g O f f i c e - R o b i n N i c h o l a s , s % ( % R L A r i a l R | Ҧ P \ ך & l 8 > 0 Z , V ( R | & P V
|
Clear Not Used
|
@ B z ( R % T l [ {
|
ClockEnable Not Used
|
@
|
ActiveLowSetClear True
|
@ [ L X V P N 0 - - 0 % T l {
|
AsyncSetClear True
|
@
|
ActiveLowClockEnable True
|
@ L X V P N 1 - - 0 % R L A r i a l 4J 5 5 7 7 8` 8p 8 8 : : :( :8 < = > @
|
VhdlType std_logic
|
A B C D D E F HX Hh I J L L L L M N N N O O P P R R R R S U> Vj Wd Wt W W Y2 Z [ [ ^0 `z c eh % T ` 7
|
VerilogType wire
|
|
SystemCType sc_logic
|
@
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
@ L T . . . R L A r i a l t t t u u2 u\ u u u v v. vX v v w w* wT w~ w w w x& xP xz x x x y" yL yv z zZ z z {$ {N {x { { { | |J |t | | } }F }p } } } ~ ~B ~l ~ ~ ~ ( \ % ( % T ` ,
M d
|
StateEquation Hex(Inc(0,2,5))
|
@
|
HighVoltageThreshold 5
|
@ ,
L T V P N ! ! $ T v h
|
LowVoltageThreshold 0
|
@
|
SignalActionType 0
|
@v h
L d D T L B _ S E T S - 1 $ ! ! ! ! & % % V 0 j M k L L k k L% ( % R L A r i a l 8 p 2 b P p j 8 X s c o v e r e d u n d e r t h e t e r m s o f a l i c e n s e a g r e e m e n t Y o u h a v e o b t a i n e d t h i s t y p e f a c % T ~ b
|
MSB 0
|
@
|
LSB 0
|
@ L p E F F E C T I V E A D D R E S S b - ) ) - 0 ( - - - 0 0 0 - - - & % % V 0 F 6
G
5
5 GG
% ( R L A r i a l r a n t i n g y o u a d d i t i o n a l r i t s , y o u r u s e o f t h i s s o f t w a r e i s l i m i t e d t o y o u r w o r k s t a t i o n f o y o u r o w n p u b l i s h i n g u s e . Y o u m s % ( R L A r i a l a n y q u e s t i o n c o n c e r n i n g y r r i g h t s y o u s h o u l d r e v i e w t h e l i c e n s e a g r e e m e n t y o u r e c e i v e d w t h t h e s o f t w a r e o r c o n t a c t M o n o
|
isFallingEdgeSensitive False
|
! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j l m n o p q r s t u v w x y z { | } ~ f % ( R L & " WMFC 8 x A r i a l n b e c o n t a c t e d a t :
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
U S A ( 8 4 7 ) 7 1 8 - 0 4 0 0 U K - 0 1 1 4 4 0 1 7 3 7 7 6 5 9 5 9
|
BooleanEquation
|
h t t p : / / w w w . m o n o t y p e . c m h t t p : / / w w w . m o n o t y p e . c o m / h t m l / t o % ( R L A r i a l r d N o r m a l N o r m a l n y N o r m a l 1K K9 N o r m l n e N o r m a l N o r m a l N a v a d n o t h n g A r r u n t a N o r m a l N o r m a l N o r m a l N o m a l . 1 9 9 0 - 1 9 9 2 . A l l R i g h t s R e s e o % ( R L A r i a l r o s o f t ) A r i a l V e r s i o n 2 . 7 6 A a l M T A r i a l T r a d e m GSUB ' JSTFm*i *\ LTSH! Ud OS/2 2k VPCLT{>C 6VDMXPj Zx cmapܣ .@ cvt pv | 0fpgmw' w gasp P y% ( R L A r i a l Dmaxp name6 ` +postƬ%E 0 epq l
|
NegTolerance 0
|
y" yL yv z zZ z z {$ {N {x { { { | |J |t | | | } }F }p } } ~ ~B ~l ~ ~ ~ ( \ x z J . t ( % ( R L A r i a l * < ( L ^ p 0 6 ` . x H R d r , ` B
|
PosTolerance 0
|
P % ( R L A r i a l @ n ( ^ 0 ` > j 8 p 2 b P < p j 8 X rif desi , Arial contains more humanist characteristics than many of it i% ( %
( % R L A r i a l n in most industrial style sans serif faces. Term strokes are cut on the diagonal which helps to give the face a less mechanical appearance. Arial is an extremely versatile f ily of typefaces which can be used with equal success for text , % T l ] o
|
UserSpecifiedSizeRatio 1
|
@
|
VerilogCode
|
@] o L X P P N 0 om- - 0 % T l ]
|
VHDLCode
|
@
|
PROPS!
|
@] L X P P N 1 t- - 0 % % T ` ,
|
E0 0 3750 3750 1 0 DR 0
|
|
E1 1 13125 13125 1 0 DR 0
|
@
|
E2 0 13625 13625 1 0 DR 0
|
@ L T . . . of R L A r i a l types licensees.
|
E3 1 23125 23125 1 0 DR 0
|
|
E4 0 23625 23625 1 0 DR 0
|
This software is a valuable a of Monotype. Unless you have entered into a specific license agreement granting you additional rights, your use of this softw e is limited to your workstation for your own publishing use. s % T I
|
E5 1 33125 33125 1 0 DR 0
|
@
|
E6 0 33625 33625 1 0 DR 0
|
@ L l P P N D T L B _ S E T S - 2 t- - 0 0 ) % - % - - ) - % T O
|
E7 1 43124 43124 1 0 DR 0
|
@
|
E8 0 44466 44466 1 0 DR 0
|
@ O
L l P P N D T L B _ S E T S - 1 ty- - 0 0 ) % - % - - ) - % %
( & % % V 0 M L L L% ( %
( %
( & % % V 0 M LL L% ( & % % W , C $ L--% ( & % % W , Z
Y
Y
% ( & % % W , C K
|
E9 1 53124 53124 1 0 DR 0
|
B LB
|
E10 X 53750 53750 1 0 DR 0
|
% ( % % V 0 % %% % R L A r i a l o n t a i n s m o r e h u m a n i s t c h a c t e r i s t i c s t h a n m a n y o f i t s p r e d e c e s s o r s a n d a s s u c h i s m o r e i n t u n e w i t h t h e m o o d o f t h e l a s t e % T x k
|
!
|
@
|
|
@ k L \ T L B S E T ) % - - - ) T l
|
SIGNAL dwb_ACK_I
|
@
|
DIRECTION input
|
@ L X I N D E X 0 0 - + & % W $
|
RADIX hex
|
a
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
X
|
Clock Unclocked
|
% ( % % V , N =
|
EdgeLevel neg
|
N
|
Set Not Used
|
N=
|
Clear Not Used
|
N & % % V 0
% ( % % T d X
|
ClockEnable Not Used
|
@
|
ActiveLowSetClear True
|
@ X L T C O M P 0 4 7 - & % W $ q h% ( % % V , } ^ ^}^^ & % % W $
$ q
h% ( % % V , ^ B B^^B^ & % % V 0 % ( %
( % % T ` ' q
|
AsyncSetClear True
|
@
|
ActiveLowClockEnable True
|
@ ' L T I N V 0 - & % W $ W i @ ``7% ( % % V , 9 . .`9..%
( R L
|
VhdlType std_logic
|
|
VerilogType wire
|
A r i a l % ( %
( % % T l 8 #
|
SystemCType sc_logic
|
@
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
@ L X H I T 0 0 ) % %
( R L A r i a l % T X
|
StateEquation Hex(Inc(0,2,5))
|
@
|
HighVoltageThreshold 5
|
@ L P 3 1 % % R L A r i a l % T `
|
LowVoltageThreshold 0
|
@
|
SignalActionType 0
|
@ L T l o g R L A r i a l & " WMFC x g u s e . Y o u m y n o t c o p y o r d i s t r i b u t e t h i s s u% T T
|
MSB 0
|
@
|
LSB 0
|
@ L P 2 R L A r i a l t y o u r e c e i v e d w i t h t h e s t w a r e o r c o n t a c t M o n o t y p e f o r a c o p y o f t h e l i c e n s e a g r e e m e n t .
|
isFallingEdgeSensitive False
|
M o n o t y p e c a n b e c o n t a c t e d a t : 1% ( % T
|
isRisingEdgeSensitive False
|
@
|
DrawAnalog 0
|
@ L h ( D T L B _ S E T S ) + 1 3 $ ! ! ! ! %
( R L A r i a l 92. All Rights ReservedArialRegularMonotype:Arial lar:Version 2.76 (Microsoft)ArialVersion 2.76ArialMTArial Trademark of The Monotype Corporation plc registered in the US Pat TM Off. and elsewhere.Monotype TypographyMonotype Type Drawing S% T X I
|
BooleanEquation
|
@
|
NegTolerance 0
|
@I L P 1 3 % % % T T
|
PosTolerance 0
|
@
|
UserSpecifiedSizeRatio 1
|
@ L P 0 er% R L A r i a l serif faces. Terminal strokes are cut on the diag which helps to give the face a less mechanical appearance. Arial is an extremely versatile family of typefaces which can be ed with equal success for text setting in reports, presentatio u% T l
|
VerilogCode
|
@
|
VHDLCode
|
@ L X W A Y 0 :/O 9 8 . & % W $ { % ( % % V , % R L
|
PROPS!
|
|
E0 0 11250 11250 1 0 DR 0
|
A r i a l e distributed by one of Monotypes licensees.
|
E1 1 13125 13125 1 0 DR 0
|
|
E2 0 21250 21250 1 0 DR 0
|
T software is a valuable asset of Monotype. Unless you have entered into a specific license agreement granting you additional ri ts, your use of this software is limited to your workstation f y % T m
|
E3 1 23125 23125 1 0 DR 0
|
@
|
E4 0 31250 31250 1 0 DR 0
|
@ L ` D T L B M I S S t0 ) % - 7 - - T l
|
E5 1 33125 33125 1 0 DR 0
|
@
|
E6 0 41250 41250 1 0 DR 0
|
@l L ` E X C E P T I O N 7)- + 0 - - ) 4 0 %
( %
( R L A r i a l dL L L L M N N N O P P R R R R R S U> Vj Wd Wt W W Y2 Z [ [ ^0 `z c eh g jb l2 m n n@ nP n` n n n n o( oR ob or o o o p p p p0 p@ % T X
|
E7 1 43124 43124 1 0 DR 0
|
@
|
E8 0 51875 51875 1 0 DR 0
|
@ L P 1 2 % % & % W $ % ( % % V , & % % W $ % ( & % % W $
% ( & % % W $ % ( % % V 9
|
E9 1 53124 53124 1 0 DR 0
|
|
E10 X 53750 53750 1 0 DR 0
|
& % % W $ { % ( % % V , %
( %
( % R L
|
!
|
|
|
A r i a l r e d i s t r i b u t e d b y o n e o f n o t y p e s l i c e n s e e s .
|
SIGNAL dwb_CYC_O
|
|
DIRECTION output
|
T h i s s o f t w a r e i s a v a l u a b l e a s s e t o f M o n t y p e . U n l e s s y o u h a v e e n t e r e d i c % T j
|
RADIX hex
|
@
|
GRID 0 1 0 1 0 16711680 0 0
|
@ j L d P A D D R [ 3 1 : 1 3 ] - - 0 0 0 % % % % & % W ( C G L>% ( & % % W $ 5 3 >*% ( % % V , ! !! !R L A r i a l e n t y o u r e c e i v e d w i t h t h e o f t w a r e o r c o n t a c t M o n o t y p e f o r a c o p y o f t h e l i c e n s e a g r e e m e n t
|
ENDGRID -1
|
|
Clock Unclocked
|
M o n o t y p e c a n b e c o n t a c t e d a % ( % % T ~ T
|
EdgeLevel neg
|
@
|
Set Not Used
|
@~ L d P A G E O F F S E T o - - 4 - 4 ) ) - - ) T F 1
|
Clear Not Used
|
@
|
ClockEnable Not Used
|
@ F L d P A D D R [ 1 2 : 0 ] m - - 0 0 0 % % % %
( R L A r i a l a l N o r m a l e r t y o f M o n o t y p e p o g r a p h y a n d i t s u s e b y y o u i s c o v e r e d u n d e r t h e t e r m s o f a l i c n s e a g r e e m e n t . Y o u h a v e o b t a i n e o % ( R L A r i a l r t o g e t h e r w i t h s o f t w a r e s t r i b u t e d b y o n e o f M o n o t y p e s l i c e n s e e s .
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
T h i s s o f t w a r e i s a v a l u a b l e a s s e t o f M o n o t y p e . U n l r % ( %
( R L A r i a l o n a l r i g h t s , y o u r u s e o f i s s o f t w a r e i s l i m i t e d t o y o u r w o r k s t a t i o n f o r y o u r o w n p u b l i s h n g u s e . Y o u m a y n o t c o p y o r d i s % T `
|
ActiveLowClockEnable True
|
E
|
VhdlType std_logic
|
|
VerilogType wire
|
@
|
SystemCType sc_logic
|
@
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
L T l o g R L A r i a l racteristics than many of its predecessors and as is more in tune with the mood of the last decades of the twentieth century. The overall treatment of curves is softer and fu er than in most industrial style sans serif faces. Terminal s ch% T T F
|
StateEquation Hex(Inc(0,2,5))
|
W
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
@
|
SignalActionType 0
|
@F
|
MSB 0
|
L P 2 il R L A r i a l presentations, magazines etc, and for display use newspapers, advertising and promotions.http://www.monotype.com/html/mtname/ms_arial.htmlhttp://www.monotype.com/html/mtname/ms elcome.htmlNOTIFICATION OF LICENSE AGREEMENT
|
LSB 0
|
|
isFallingEdgeSensitive False
|
This typeface ap% T X
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
@
|
BooleanEquation
|
@X
|
NegTolerance 0
|
L h ( D T L B _ S E T S ) + 1 2 $ ! ! ! ! & % W $ % ( % & "WMFC x % V 0 z b
z b
b
z z % R L A r i a l or distribute this software.
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
If you have any q ion concerning your rights you should review the license agreement you received with the software or contact Monotype for a co of the license agreement.
|
VerilogCode
|
|
VHDLCode
|
Monotype can be contacted at:
|
PROPS!
|
01% T Y
.
|
E0 0 3125 3125 1 0 DR 0
|
@
|
E1 1 43125 43125 1 0 DR 0
|
@ L l D & A a t t r i b u t e s 0 - - % % % % " & % % V 0 `
|
E2 0 44375 44375 1 0 DR 0
|
f a
|
E3 1 53125 53125 1 0 DR 0
|
e e a
|
E4 0 53750 53750 1 0 DR 0
|
a
|
!
|
e% ( %
( % R L A r i a l p e : A r i a l R e g u l a r : V e r s i o n 7 6 ( M i c r o s o f t ) A r i a l V e r s i o n 2 . 7 6 A r i a l M T A r i a l T r a d e m a r k o f T h e M n o t y p e C o r p o r a t i o n p l c r e g i s t e r & % T
|
|
]
|
SIGNAL dwb_ERR_I
|
@
|
DIRECTION input
|
@
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
L ` P A G E F A U L T - - 4 - ) - 0 % ) & % W $ 0 B 9 9% ( % % V , a
|
ENDGRID -1
|
` a
|
Clock Unclocked
|
9 ` & % % W $ 0 9 % ( %
( % % V 0 m M mMMmmM % R L A r i a l f c u r v e s i s s o f t e r a n d f u e r t h a n i n m o s t i n d u s t r i a l s t y l e s a n s s e r i f f a c e s . T e r m i n a l s t o k e s a r e c u t o n t h e d i a g o n a l w h % T x v .
|
EdgeLevel neg
|
@
|
Set Not Used
|
@v L \ S R [ S U P V - 0 - 0 - - T T 4 ~
|
Clear Not Used
|
@
|
ClockEnable Not Used
|
@ 4 L P ] u & % W $ % ( % % V , a
|
ActiveLowSetClear True
|
a
|
AsyncSetClear True
|
& % % W $ % ( %
( %
( %
( % % V 0 } } }}R L A r i a l R R R R R S U> Vj Wd Wt W W Y2 [ [ ^0 `z c eh g jb l2 m n n@ nP n` n n n n n o( oR ob or o o o p p p p0 p@ pz p p p p q qB ql q q q r r> rh r % ( % R L A r i a l xP xz x x x y" yL yv z zZ z z {$ {x { { { | |J |t | | | } }F }p } } } ~ ~B ~l ~ ~ ~ ( \ x z J . t ( F n ( ^ ` % T p B
|
ActiveLowClockEnable True
|
@
|
VhdlType std_logic
|
@ B L X A C C E S S - 0 0 - - - T d g
|
VerilogType wire
|
@
|
SystemCType sc_logic
|
@ L T T Y P E ) - - - & % W $
{ %
% ( % % V , ] .
.
.
].
%
( %
( % % T z
H 0
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
@
|
StateEquation Hex(Inc(0,2,5))
|
@z
H
|
HighVoltageThreshold 5
|
L ` P R O T E C T I O N - 0 4 ) - 0 ) 4 0 T
& 2
|
LowVoltageThreshold 0
|
@
|
SignalActionType 0
|
@
|
MSB 0
|
L ` A T T R I B U T E S - ) ) 0 - 0 ) - - & % W $ \ e % ( % % V , f f R L
|
LSB 0
|
|
isFallingEdgeSensitive False
|
A r i a l e c i f i c l i c e n s e a g r e e m e n t a n t i n g y o u a d d i t i o n a l r i g h t s , y o u r u s e o f t h i s s o f t w a r e i s l i m i e d t o y o u r w o r k s t a t i o n f o r y o u r s % ( % R L
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
A r i a l
|
BooleanEquation
|
I f y o u h a v e a n y q u e s t i o c o n c e r n i n g y o u r r i g h t s y o u s h o u l d r e v i e w t h e l i c e n s e a g r e e m e n t o u r e c e i v e d w i t h t h e s o f t w a r e o e % T
2
|
NegTolerance 0
|
@
|
PosTolerance 0
|
@ L ` D M M U P A G E 0 7 7 0 - - 4 - T l Q L $
|
UserSpecifiedSizeRatio 1
|
@
|
VerilogCode
|
@Q L L X F A U L T / ) - 0 % ) T ?
|
VHDLCode
|
@
|
PROPS!
|
@ L ` E X C E P T I O N o - + 0 - - ) 4 0 & % W ( % ( % % V 9
|
E0 0 53125 53125 1 0 DR 0
|
|
E1 X 53750 53750 1 0 DR 0
|
. - C Arial ? ? ?? ? ? ? - 2
|
!
|
y! SET 0 - - ) % 2
|
|
! SET 1 - - ) % C Arial ?????? ????? ? ????? ? ?? - 2
|
SIGNAL dwb_RTY_I
|
b ... C Arial ????????????????????????? - 2
|
DIRECTION input
|
= SET - - ) * Arial ????????????????????????? - 2
|
RADIX hex
|
J
DTLB_SETS-1 - - $ :
::
- C Arial ???????????????????????? - C Arial ????????????????????????? - C Arial ????????????????????????? - C Arial ???????????5???4????????? - 2 Arial ????????????????????lNegr - 2 Arial Type Solutions Inc. 1990- - 2 Arial ion plc registered in the - - C Arial ?A?A?A?A?A?A?A?A?A?A?A?A? - 2
|
GRID 0 1 0 1 0 16711680 0 0
|
[ VPN 0 - - 0 % 2
|
ENDGRID -1
|
VPN 1 - - 0 % C Arial ????????????????????????? - 2
|
Clock Unclocked
|
... C Arial ????????????????????????? - - 2
|
EdgeLevel neg
|
,
VPN ! ! $ 2
|
Set Not Used
|
h
v DTLB_SETS-1 $ ! ! ! ! - - $ k L L k k L - - C Arial ????????????????????????? - ! 2
|
Clear Not Used
|
EFFECTIVE ADDRESS(- ) ) - 0 ( - - - 0 0 0 - - - -
|
ClockEnable Not Used
|
- $ G
5
5 GG
-
|
ActiveLowSetClear True
|
C Arial ranting you additional ri -
|
AsyncSetClear True
|
C Arial any question concerning y - C Arial n be contacted at:
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
USA - C Arial rdNormalNormalnyNorma???? - C Arial rosoft)ArialVersion 2.76A - C Arial ????? ? ???? ? ?????`? - C Arial ????????????????????????? -
|
VerilogType wire
|
C Arial ????????????????????????? -
|
SystemCType sc_logic
|
"System c pXρ / - - C Arial ????4??????????????????? - 2
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
o] PPN 0 - - 0 % 2
|
StateEquation Hex(Inc(0,2,5))
|
] PPN 1 - - 0 % - 2
|
HighVoltageThreshold 5
|
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DrawWndFont DEFAULT
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LabelWndFont USER {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
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LabelWndColor DEFAULT
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DefaultClockToOutLH 0
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SignalColor 2
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DefaultClockToOutHL 0
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LabelOffset 2
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DefaultSetup 0
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BusDisplay 0
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DefaultHold 0
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WaveFormWidth 0.500000
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DefaultRegStartupState unknown
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WaveFormColor 0
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DefaultPodSize 8
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InputWaveFormColor 16711680
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DefaultActiveLowSetClear True
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SlantedEdges 1
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DefaultAsyncSetClear True
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SlantAngle 75
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DefaultActiveLowClockEnable True
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RightJustifySigNames 1
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AutosplitEnabled 1
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AbortHdlCodeEnabled 1
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SampleHdlCodeEnabled 1
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LabelWndColor DEFAULT
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VerboseSequenceVerification 0
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MarkerDispPref 4
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ExecuteFromTopLevel 1
|
MarkerCustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
|
TimeOutInDiagramLengths 0
|
SignalColor 2
|
DefaultCycleClock Unclocked
|
LabelOffset 4
|
DefaultCycleEdge neg
|
BusDisplay 0
|
!
|
WaveFormWidth 0.500000
|
|
WaveFormColor 0
|
MACROS
|
InputWaveFormColor 16711680
|
!
|
SlantedEdges 1
|
|
SlantAngle 75
|
CORGROUP $$CLK_I_BufferRising
|
RightJustifySigNames 1
|
Percent 100
|
AutosplitEnabled 1
|
!
|
AutosplitChar _
|
|
DynamSizedSignals 1
|
CORGROUP $$CLK_I_BufferFalling
|
!
|
Percent 100
|
|
!
|
DIAGRAMTESTBENCHSETTINGS
|
|
FilesBeforeDiagramModel
|
CORGROUP $$CLK_I_BufferRisingFalling
|
FilesInsideDiagramModelDeclarationSection
|
Percent 100
|
AbortHdlCodeEnabled 1
|
!
|
DelayHdlCodeEnabled 1
|
|
SampleHdlCodeEnabled 1
|
CORGROUP $$CLK_I_BufferRising
|
MarkerHdlCodeEnabled 1
|
Percent 100
|
VerboseSamples 0
|
!
|
VerboseDelays 0
|
|
VerboseFileInput 0
|
CORGROUP $$CLK_I_BufferFalling
|
VerboseSequenceVerification 0
|
Percent 100
|
IncludeDelayTime 1
|
!
|
ExecuteFromTopLevel 1
|
|
TimeOutInDiagramLengths 0
|
CORGROUP $$CLK_I_BufferRisingFalling
|
DefaultCycleClock Unclocked
|
Percent 100
|
DefaultCycleEdge neg
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRising
|
MACROS
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRising
|
CORGROUP $$CLK_I_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
CORGROUP $$CLK_I_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRising
|
CORGROUP $$CLK_I_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
CORGROUP $$CLK_I_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRising
|
CORGROUP $$CLK_I_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
CORGROUP $$CLK_I_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRising
|
CORGROUP $$CLK_I_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
CORGROUP $$CLK_RISC_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRising
|
CORGROUP $$CLK_RISC_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
CORGROUP $$CLK_RISC_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRising
|
CORGROUP $$CLK_RISC_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
CORGROUP $$CLK_I_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
CORGROUP $$CLK_I_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CORGROUP $$CLK_RISC_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
CORGROUP $$CLK_RISC_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CORGROUP $$CLK_I_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRising
|
CORGROUP $$CLK_I_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
CORGROUP $$CLK_RISC_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
CORGROUP $$CLK_RISC_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CORGROUP $$CLK_I_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRising
|
CORGROUP $$CLK_I_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
CORGROUP $$CLK_RISC_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
CORGROUP $$CLK_RISC_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CORGROUP $$CLK_I_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRising
|
CORGROUP $$CLK_I_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
CORGROUP $$CLK_RISC_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
CORGROUP $$CLK_RISC_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CORGROUP $$CLK_I_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
CORGROUP $$CLK_I_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CORGROUP $$CLK_RISC_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
CORGROUP $$CLK_RISC_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CORGROUP $$CLK_I_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
CORGROUP $$CLK_I_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CORGROUP $$CLK_RISC_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
CORGROUP $$CLK_RISC_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CORGROUP $$CLK_I_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
CORGROUP $$CLK_I_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CORGROUP $$CLK_RISC_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
CORGROUP $$CLK_RISC_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CORGROUP $$CLK_I_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
CORGROUP $$CLK_I_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CORGROUP $$CLK_RISC_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
CORGROUP $$CLK_RISC_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CORGROUP $$CLK_I_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
CORGROUP $$CLK_I_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CORGROUP $$CLK_RISC_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
CORGROUP $$CLK_RISC_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CORGROUP $$CLK_I_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$clk_risc_BufferRising
|
CORGROUP $$CLK_I_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$clk_risc_BufferFalling
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$clk_risc_BufferRisingFalling
|
CORGROUP $$CLK_RISC_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$clk_risc_BufferRising
|
CORGROUP $$CLK_RISC_BufferFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$clk_risc_BufferFalling
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CORGROUP $$clk_risc_BufferRisingFalling
|
CORGROUP $$CLK_I_BufferRising
|
Percent 100
|
Percent 100
|
!
|
!
|
|
|
CLOCK clk_risc
|
CORGROUP $$CLK_I_BufferFalling
|
PERIODE 1
|
Percent 100
|
DUTY 50
|
!
|
OFFSETE 0
|
|
INITIAL LOW
|
CORGROUP $$CLK_I_BufferRisingFalling
|
MAXUNCERTRISE 0
|
Percent 100
|
MAXUNCERTFALL 0
|
!
|
MINUNCERTRISE 0
|
|
MINUNCERTFALL 0
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
JRISEE 0
|
Percent 100
|
JFALLE 0
|
!
|
GRID 1 1 1 2 2 16711680 0 0
|
|
ENDGRID -1
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
DIRECTION input
|
Percent 100
|
MASTERCLOCK None
|
!
|
Clock Unclocked
|
|
EdgeLevel neg
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
Set Not Used
|
Percent 100
|
Clear Not Used
|
!
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
CORGROUP $$dwb_CLK_I_BufferRising
|
AsyncSetClear True
|
Percent 100
|
ActiveLowClockEnable True
|
!
|
VhdlType std_logic
|
|
VerilogType wire
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
SystemCType sc_logic
|
Percent 100
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
!
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
LowVoltageThreshold 0
|
Percent 100
|
MSB 0
|
!
|
LSB 0
|
|
isFallingEdgeSensitive False
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
isRisingEdgeSensitive True
|
Percent 100
|
DrawAnalog 0
|
!
|
BooleanEquation
|
|
NegTolerance 0
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
PosTolerance 0
|
Percent 100
|
UserSpecifiedSizeRatio 1
|
!
|
VerilogCode
|
|
VHDLCode
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
PROPS!
|
Percent 100
|
E5 1 2500 2500 1 0 DR 0
|
!
|
E6 0 3000 3000 1 0 DR 0
|
|
!
|
CORGROUP $$dwb_CLK_I_BufferRising
|
|
Percent 100
|
SIGNAL dbg_adr_i
|
!
|
DIRECTION input
|
|
RADIX hex
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
GRID 0 1 0 1 0 16711680 0 0
|
Percent 100
|
ENDGRID -1
|
!
|
Clock Unclocked
|
|
EdgeLevel neg
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
Set Not Used
|
Percent 100
|
Clear Not Used
|
!
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
AsyncSetClear True
|
Percent 100
|
ActiveLowClockEnable True
|
!
|
VhdlType std_logic
|
|
VerilogType wire
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
SystemCType sc_logic
|
Percent 100
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
!
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
LowVoltageThreshold 0
|
Percent 100
|
LSB 0
|
!
|
MSB 31
|
|
SignalActionType 0
|
CORGROUP $$dwb_CLK_I_BufferRising
|
isFallingEdgeSensitive False
|
Percent 100
|
isRisingEdgeSensitive False
|
!
|
DrawAnalog 0
|
|
BooleanEquation
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
NegTolerance 0
|
Percent 100
|
PosTolerance 0
|
!
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
VHDLCode
|
Percent 100
|
PROPS!
|
!
|
E0 X 750 750 1 0 DR 0
|
|
E1 V 1750 1750 A20 1 0 DR 0
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
E2 V 3750 3750 A100 1 0 DR 0
|
Percent 100
|
E3 X 5750 5750 1 0 DR 0
|
!
|
!
|
|
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
SIGNAL dbg_dat_i
|
Percent 100
|
DIRECTION input
|
!
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
ENDGRID -1
|
Percent 100
|
Clock
|
!
|
EdgeLevel neg
|
|
Set Not Used
|
CORGROUP $$dwb_CLK_I_BufferRising
|
Clear Not Used
|
Percent 100
|
ClockEnable Not Used
|
!
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
ActiveLowClockEnable True
|
Percent 100
|
VhdlType std_logic
|
!
|
VerilogType wire
|
|
SystemCType sc_logic
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
Percent 100
|
StateEquation Hex(Inc(0,2,5))
|
!
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
CORGROUP $$dwb_CLK_RISC_BufferRising
|
LSB 0
|
Percent 100
|
MSB 31
|
!
|
SignalActionType 0
|
|
isFallingEdgeSensitive False
|
CORGROUP $$dwb_CLK_RISC_BufferFalling
|
isRisingEdgeSensitive False
|
Percent 100
|
DrawAnalog 0
|
!
|
BooleanEquation
|
|
NegTolerance 0
|
CORGROUP $$dwb_CLK_RISC_BufferRisingFalling
|
PosTolerance 0
|
Percent 100
|
UserSpecifiedSizeRatio 1
|
!
|
VerilogCode
|
|
VHDLCode
|
CORGROUP $$dwb_CLK_I_BufferRising
|
VhdlMapping DefaultVhdlMapping
|
Percent 100
|
PROPS!
|
!
|
E0 X 750 750 1 0 DR 0
|
|
E1 V 1750 1750 D20 1 0 DR 0
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
E2 X 5750 5750 1 0 DR 0
|
Percent 100
|
!
|
!
|
|
|
SIGNAL dbg_dat_o
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
DIRECTION output
|
Percent 100
|
RADIX hex
|
!
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
CORGROUP $$CLK_RISC_BufferRising
|
Clock
|
Percent 100
|
EdgeLevel neg
|
!
|
Set Not Used
|
|
Clear Not Used
|
CORGROUP $$CLK_RISC_BufferFalling
|
ClockEnable Not Used
|
Percent 100
|
ActiveLowSetClear True
|
!
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
VhdlType std_logic
|
Percent 100
|
VerilogType wire
|
!
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
CORGROUP $$iwb_CLK_I_BufferRising
|
StateEquation Hex(Inc(0,2,5))
|
Percent 100
|
HighVoltageThreshold 5
|
!
|
LowVoltageThreshold 0
|
|
LSB 0
|
CORGROUP $$iwb_CLK_I_BufferFalling
|
MSB 31
|
Percent 100
|
SignalActionType 0
|
!
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive True
|
CORGROUP $$iwb_CLK_I_BufferRisingFalling
|
DrawAnalog 0
|
Percent 100
|
BooleanEquation
|
!
|
NegTolerance 0
|
|
PosTolerance 0
|
CLOCK CLK_RISC
|
UserSpecifiedSizeRatio 1
|
PERIODE 2.5
|
VerilogCode
|
DUTY 50
|
VHDLCode
|
OFFSETE 0
|
VhdlMapping DefaultVhdlMapping
|
INITIAL HIGH
|
PROPS!
|
MAXUNCERTRISE 0
|
E0 V -1 -1 1 0 DR 0
|
MAXUNCERTFALL 0
|
E1 V 750 750 PC 1 0 DR 0
|
MINUNCERTRISE 0
|
E2 X 2750 2750 1 0 DR 0
|
MINUNCERTFALL 0
|
E3 V 3750 3750 D100 1 0 DR 0
|
JRISEE 0
|
E4 V 4750 4750 L/S EA 1 0 DR 0
|
JFALLE 0
|
E5 V 5750 5750 LOAD DATA 1 0 DR 0
|
GRID 0 1 0 2 0 16711680 0 0
|
!
|
ENDGRID -1
|
|
DIRECTION internal
|
SIGNAL dbg_op_i
|
MASTERCLOCK None
|
DIRECTION input
|
Clock Unclocked
|
RADIX hex
|
EdgeLevel neg
|
GRID 0 1 0 1 0 16711680 0 0
|
Set Not Used
|
ENDGRID -1
|
Clear Not Used
|
Clock Unclocked
|
ClockEnable Not Used
|
EdgeLevel neg
|
ActiveLowSetClear True
|
Set Not Used
|
AsyncSetClear True
|
Clear Not Used
|
ActiveLowClockEnable True
|
ClockEnable Not Used
|
VhdlType std_logic
|
ActiveLowSetClear True
|
VerilogType wire
|
AsyncSetClear True
|
SystemCType sc_logic
|
ActiveLowClockEnable True
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
VhdlType std_logic
|
StateEquation Hex(Inc(0,2,5))
|
VerilogType wire
|
HighVoltageThreshold 5
|
SystemCType sc_logic
|
LowVoltageThreshold 0
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
MSB 0
|
StateEquation Hex(Inc(0,2,5))
|
LSB 0
|
HighVoltageThreshold 5
|
isFallingEdgeSensitive False
|
LowVoltageThreshold 0
|
isRisingEdgeSensitive False
|
SignalActionType 0
|
DrawAnalog 0
|
MSB 3
|
BooleanEquation
|
LSB 0
|
NegTolerance 0
|
isFallingEdgeSensitive False
|
PosTolerance 0
|
isRisingEdgeSensitive False
|
UserSpecifiedSizeRatio 1
|
DrawAnalog 0
|
VerilogCode
|
BooleanEquation
|
VHDLCode
|
NegTolerance 0
|
PROPS!
|
PosTolerance 0
|
!
|
UserSpecifiedSizeRatio 1
|
|
VerilogCode
|
CLOCK iwb_CLK_I
|
VHDLCode
|
PERIODE 5
|
PROPS!
|
DUTY 50
|
E0 V 750 750 READ PC 0x0 1 0 DR 0
|
OFFSETE 0
|
E1 V 1750 1750 WRITE SPR 0x5 1 0 DR 0
|
INITIAL LOW
|
E2 V 3750 3750 READ SPR == 0x4 1 0 DR 0
|
MAXUNCERTRISE 0
|
E3 V 4750 4750 READ LSEA 0x1 1 0 DR 0
|
MAXUNCERTFALL 0
|
E4 V 5750 5750 READ LDAT 0x2 1 0 DR 0
|
MINUNCERTRISE 0
|
!
|
MINUNCERTFALL 0
|
|
JRISEE 0
|
SIGNAL dbg_stall_i
|
JFALLE 0
|
DIRECTION input
|
GRID 1 1 1 2 2 16711680 0 0
|
RADIX hex
|
ENDGRID -1
|
GRID 0 1 0 1 0 16711680 0 0
|
DIRECTION input
|
ENDGRID -1
|
MASTERCLOCK None
|
Clock Unclocked
|
Clock Unclocked
|
EdgeLevel neg
|
EdgeLevel neg
|
Set Not Used
|
Set Not Used
|
Clear Not Used
|
Clear Not Used
|
ClockEnable Not Used
|
ClockEnable Not Used
|
ActiveLowSetClear True
|
ActiveLowSetClear True
|
AsyncSetClear True
|
AsyncSetClear True
|
ActiveLowClockEnable True
|
ActiveLowClockEnable True
|
VhdlType std_logic
|
VhdlType std_logic
|
VerilogType wire
|
VerilogType wire
|
SystemCType sc_logic
|
SystemCType sc_logic
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
StateEquation Hex(Inc(0,2,5))
|
StateEquation Hex(Inc(0,2,5))
|
HighVoltageThreshold 5
|
HighVoltageThreshold 5
|
LowVoltageThreshold 0
|
LowVoltageThreshold 0
|
SignalActionType 0
|
MSB 0
|
MSB 0
|
LSB 0
|
LSB 0
|
isFallingEdgeSensitive False
|
isFallingEdgeSensitive False
|
isRisingEdgeSensitive True
|
isRisingEdgeSensitive False
|
DrawAnalog 0
|
DrawAnalog 0
|
BooleanEquation
|
BooleanEquation
|
NegTolerance 0
|
NegTolerance 0
|
PosTolerance 0
|
PosTolerance 0
|
UserSpecifiedSizeRatio 1
|
UserSpecifiedSizeRatio 1
|
VerilogCode
|
VerilogCode
|
VHDLCode
|
VHDLCode
|
PROPS!
|
PROPS!
|
!
|
E0 0 5750 5750 1 0 DR 0
|
|
!
|
SIGNAL iwb_ADR_O
|
|
DIRECTION output
|
cument.1 9q Timing Diagram
|
RADIX hex
|
F Microsoft Visio Drawing VISIO 6.0 Shapes Visio.Drawing.6 9q ՜. +,D ՜. +,Timing Diagram Editor v7.1g - Output File
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
PROJECT
|
Clock
|
BaseTimeUnit 1
|
EdgeLevel neg
|
DisplayTimeUnit 2
|
Set Not Used
|
TextGridX 625.000000
|
Clear Not Used
|
TextGridY 6
|
ClockEnable Not Used
|
EdgeGridX 625.000000
|
ActiveLowSetClear True
|
ImportStartTime 0.000000
|
AsyncSetClear True
|
ImportEndTime 281474976710656.000000
|
ActiveLowClockEnable True
|
TimePerPixel 17.543860
|
VhdlType std_logic
|
Visible DELAYS SETUPS HOLDS SAMPLES TEXT HIDDENATTACHMENTS CRITICALPATHS GRIDLINES UNCERTAINTY
|
VerilogType wire
|
ColWidths 144,216,288,423,488
|
SystemCType sc_logic
|
ScrollPos 0.000000,0.000000,0.000000
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
DefDelayRule 1
|
StateEquation Hex(Inc(0,2,5))
|
NoEventOverlap NO
|
HighVoltageThreshold 5
|
SigLabelFontHeight 8
|
LowVoltageThreshold 0
|
LabelHeight 10
|
LSB 0
|
LoadLibsToMem 1
|
MSB 31
|
UseFullPathNames 1
|
SignalActionType 0
|
LibPath
|
isFallingEdgeSensitive False
|
EntireTime YES
|
isRisingEdgeSensitive True
|
PrintTimeSpecified NO
|
DrawAnalog 0
|
FromTime 0
|
BooleanEquation
|
ToTime 15.625
|
NegTolerance 0
|
AllSignals YES
|
PosTolerance 0
|
CurrSelSigs NO
|
UserSpecifiedSizeRatio 1
|
PrintTo 2
|
VerilogCode
|
PrintFileName C:\DOCS\wb_writesingle.wmf
|
VHDLCode
|
PreviewInterchange YES
|
VhdlMapping DefaultVhdlMapping
|
PreviewTIFF5 NO
|
PROPS!
|
UseMargins NO
|
E0 V -1 -1 1 0 DR 0
|
PrintTimeLine NO
|
E1 X 3125 3125 1 0 DR 0
|
PrintBorderBox YES
|
E2 V 3126 3126 A0 1 0 DR 0
|
PrintSigNames YES
|
E3 X 3750 3750 1 0 DR 0
|
PrintSigNamesOnEachPage YES
|
E4 V 13125 13125 A0 1 0 DR 0
|
AddPreviewToEPS NO
|
E5 X 13625 13625 1 0 DR 0
|
PreviewRes 150
|
E6 V 23125 23125 A4 1 0 DR 0
|
MarginLR 1
|
E7 X 23625 23625 1 0 DR 0
|
MifImageWidth 6.00
|
E8 V 33125 33125 A8 1 0 DR 0
|
MarginTB Auto
|
E9 X 33625 33625 1 0 DR 0
|
Header %d %t;%f;%p
|
E10 V 43125 43125 A12 1 0 DR 0
|
Footer
|
E11 X 43750 43750 1 0 DR 0
|
ScaleHorz 100
|
!
|
ScaleVert 100
|
|
ScaleHPage 1
|
SIGNAL iwb_DAT_I
|
PrintImage DIAGRAM
|
DIRECTION input
|
DefaultTimingModel minmax
|
RADIX hex
|
DefaultClock Unclocked
|
GRID 0 1 0 1 0 16711680 0 0
|
DefaultEdgeLevel neg
|
ENDGRID -1
|
DefaultSet Not Used
|
Clock
|
DefaultClear Not Used
|
EdgeLevel neg
|
DefaultClockEnable Not Used
|
Set Not Used
|
DefaultClockToOutLH 0
|
Clear Not Used
|
DefaultClockToOutHL 0
|
ClockEnable Not Used
|
DefaultSetup 0
|
ActiveLowSetClear True
|
DefaultHold 0
|
AsyncSetClear True
|
DefaultRegStartupState unknown
|
ActiveLowClockEnable True
|
DefaultPodSize 8
|
VhdlType std_logic
|
DefaultActiveLowSetClear True
|
VerilogType wire
|
DefaultAsyncSetClear True
|
SystemCType sc_logic
|
DefaultActiveLowClockEnable True
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
SigLabelFontHeight 10
|
StateEquation Hex(Inc(0,2,5))
|
PROPS!
|
HighVoltageThreshold 5
|
!
|
LowVoltageThreshold 0
|
|
LSB 0
|
STYLE
|
MSB 31
|
DefaultFont USER {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
|
SignalActionType 0
|
DrawWndFont DEFAULT
|
isFallingEdgeSensitive False
|
DrawWndColor DEFAULT
|
isRisingEdgeSensitive False
|
GridWndFont DEFAULT
|
DrawAnalog 0
|
GridWndColor DEFAULT
|
BooleanEquation
|
LabelWndFont USER {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
|
NegTolerance 0
|
LabelWndColor DEFAULT
|
PosTolerance 0
|
ParamDispPref 0
|
UserSpecifiedSizeRatio 1
|
ParamWndCellDisplay 0
|
VerilogCode
|
CustDispString %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
|
VHDLCode
|
CustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
|
VhdlMapping DefaultVhdlMapping
|
MarkerDispPref 4
|
PROPS!
|
MarkerCustDispString %n v=%mv,%Mv d=%md %t
|
E0 X 11250 11250 1 0 DR 0
|
MarkerCustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
|
E1 V 13125 13125 D0 1 0 DR 0
|
SignalColor 2
|
E2 X 21250 21250 1 0 DR 0
|
LabelOffset 2
|
E3 V 23125 23125 D4 1 0 DR 0
|
BusDisplay 0
|
E4 X 31250 31250 1 0 DR 0
|
WaveFormWidth 0.500000
|
E5 V 33125 33125 D8 1 0 DR 0
|
WaveFormColor 0
|
E6 X 41250 41250 1 0 DR 0
|
InputWaveFormColor 16711680
|
E7 V 43125 43125 D12 1 0 DR 0
|
SlantedEdges 1
|
E8 X 43750 43750 1 0 DR 0
|
SlantAngle 75
|
!
|
RightJustifySigNames 1
|
|
AutosplitEnabled 1
|
SIGNAL iwb_DAT_O
|
AutosplitChar _
|
DIRECTION output
|
DynamSizedSignals 1
|
RADIX hex
|
!
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
DIAGRAMTESTBENCHSETTINGS
|
Clock Unclocked
|
FilesBeforeDiagramModel
|
EdgeLevel neg
|
FilesInsideDiagramModelDeclarationSection
|
Set Not Used
|
AbortHdlCodeEnabled 1
|
Clear Not Used
|
DelayHdlCodeEnabled 1
|
ClockEnable Not Used
|
SampleHdlCodeEnabled 1
|
ActiveLowSetClear True
|
MarkerHdlCodeEnabled 1
|
AsyncSetClear True
|
VerboseSamples 0
|
ActiveLowClockEnable True
|
VerboseDelays 0
|
VhdlType std_logic
|
VerboseFileInput 0
|
VerilogType wire
|
VerboseSequenceVerification 0
|
SystemCType sc_logic
|
IncludeDelayTime 1
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
ExecuteFromTopLevel 1
|
StateEquation Hex(Inc(0,2,5))
|
TimeOutInDiagramLengths 0
|
HighVoltageThreshold 5
|
DefaultCycleClock Unclocked
|
LowVoltageThreshold 0
|
DefaultCycleEdge neg
|
LSB 0
|
!
|
MSB 31
|
|
SignalActionType 0
|
MACROS
|
isFallingEdgeSensitive False
|
!
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
CORGROUP $$CLK_I_BufferRising
|
BooleanEquation
|
Percent 100
|
NegTolerance 0
|
!
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
CORGROUP $$CLK_I_BufferFalling
|
VerilogCode
|
Percent 100
|
VHDLCode
|
!
|
PROPS!
|
|
E0 X 43750 43750 1 0 DR 0
|
CORGROUP $$CLK_I_BufferRisingFalling
|
!
|
Percent 100
|
|
!
|
SIGNAL iwb_WE_O
|
|
DIRECTION output
|
CORGROUP $$CLK_I_BufferRising
|
RADIX hex
|
Percent 100
|
GRID 0 1 0 1 0 16711680 0 0
|
!
|
ENDGRID -1
|
|
Clock Unclocked
|
CORGROUP $$CLK_I_BufferFalling
|
EdgeLevel neg
|
Percent 100
|
Set Not Used
|
!
|
Clear Not Used
|
|
ClockEnable Not Used
|
CORGROUP $$CLK_I_BufferRisingFalling
|
ActiveLowSetClear True
|
Percent 100
|
AsyncSetClear True
|
!
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
CORGROUP $$CLK_I_BufferRising
|
VerilogType wire
|
Percent 100
|
SystemCType sc_logic
|
!
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
CORGROUP $$CLK_I_BufferFalling
|
HighVoltageThreshold 5
|
Percent 100
|
LowVoltageThreshold 0
|
!
|
SignalActionType 0
|
|
MSB 0
|
CORGROUP $$CLK_I_BufferRisingFalling
|
LSB 0
|
Percent 100
|
isFallingEdgeSensitive False
|
!
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
CORGROUP $$CLK_I_BufferRising
|
BooleanEquation
|
Percent 100
|
NegTolerance 0
|
!
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
CORGROUP $$CLK_I_BufferFalling
|
VerilogCode
|
Percent 100
|
VHDLCode
|
!
|
PROPS!
|
|
E0 X 3125 3125 1 0 DR 0
|
CORGROUP $$CLK_I_BufferRisingFalling
|
E1 1 3126 3126 1 0 DR 0
|
Percent 100
|
E2 0 13125 13125 1 0 DR 0
|
!
|
E3 X 13625 13625 1 0 DR 0
|
|
E4 0 23125 23125 1 0 DR 0
|
CORGROUP $$CLK_I_BufferRising
|
E5 X 23625 23625 1 0 DR 0
|
Percent 100
|
E6 0 33125 33125 1 0 DR 0
|
!
|
E7 X 33625 33625 1 0 DR 0
|
|
E8 0 43125 43125 1 0 DR 0
|
CORGROUP $$CLK_I_BufferFalling
|
E9 X 43625 43625 1 0 DR 0
|
Percent 100
|
!
|
!
|
|
|
SIGNAL iwb_SEL_O
|
CORGROUP $$CLK_I_BufferRisingFalling
|
DIRECTION output
|
Percent 100
|
RADIX hex
|
!
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
CORGROUP $$CLK_I_BufferRising
|
Clock Unclocked
|
Percent 100
|
EdgeLevel neg
|
!
|
Set Not Used
|
|
Clear Not Used
|
CORGROUP $$CLK_I_BufferFalling
|
ClockEnable Not Used
|
Percent 100
|
ActiveLowSetClear True
|
!
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
CORGROUP $$CLK_I_BufferRisingFalling
|
VhdlType std_logic
|
Percent 100
|
VerilogType wire
|
!
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
CORGROUP $$CLK_RISC_BufferRising
|
StateEquation Hex(Inc(0,2,5))
|
Percent 100
|
HighVoltageThreshold 5
|
!
|
LowVoltageThreshold 0
|
|
LSB 0
|
CORGROUP $$CLK_RISC_BufferFalling
|
MSB 3
|
Percent 100
|
SignalActionType 0
|
!
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
DrawAnalog 0
|
Percent 100
|
BooleanEquation
|
!
|
NegTolerance 0
|
|
PosTolerance 0
|
CORGROUP $$CLK_RISC_BufferRising
|
UserSpecifiedSizeRatio 1
|
Percent 100
|
VerilogCode
|
!
|
VHDLCode
|
|
PROPS!
|
CORGROUP $$CLK_RISC_BufferFalling
|
E0 V 0 0 Valid 1 0 DR 0
|
Percent 100
|
E1 X 3750 3750 1 0 DR 0
|
!
|
E2 V 13125 13125 Valid 1 0 DR 0
|
|
E3 X 13625 13625 1 0 DR 0
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
E4 V 23125 23125 Valid 1 0 DR 0
|
Percent 100
|
E5 X 23625 23625 1 0 DR 0
|
!
|
E6 V 33125 33125 Valid 1 0 DR 0
|
|
E7 X 33625 33625 1 0 DR 0
|
CORGROUP $$CLK_I_BufferRising
|
E8 V 43125 43125 Valid 1 0 DR 0
|
Percent 100
|
E9 X 43750 43750 1 0 DR 0
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
SIGNAL iwb_STB_O
|
Percent 100
|
DIRECTION output
|
!
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
CORGROUP $$CLK_I_BufferRisingFalling
|
ENDGRID -1
|
Percent 100
|
Clock Unclocked
|
!
|
EdgeLevel neg
|
|
Set Not Used
|
CORGROUP $$CLK_RISC_BufferRising
|
Clear Not Used
|
Percent 100
|
ClockEnable Not Used
|
!
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
CORGROUP $$CLK_RISC_BufferFalling
|
ActiveLowClockEnable True
|
Percent 100
|
VhdlType std_logic
|
!
|
VerilogType wire
|
|
SystemCType sc_logic
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
Percent 100
|
StateEquation Hex(Inc(0,2,5))
|
!
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
CORGROUP $$CLK_I_BufferRising
|
SignalActionType 0
|
Percent 100
|
MSB 0
|
!
|
LSB 0
|
|
isFallingEdgeSensitive False
|
CORGROUP $$CLK_I_BufferFalling
|
isRisingEdgeSensitive False
|
Percent 100
|
DrawAnalog 0
|
!
|
BooleanEquation
|
|
NegTolerance 0
|
CORGROUP $$CLK_I_BufferRisingFalling
|
PosTolerance 0
|
Percent 100
|
UserSpecifiedSizeRatio 1
|
!
|
VerilogCode
|
|
VHDLCode
|
CORGROUP $$CLK_RISC_BufferRising
|
PROPS!
|
Percent 100
|
E0 0 3750 3750 1 0 DR 0
|
!
|
E1 1 13125 13125 1 0 DR 0
|
|
E2 0 13625 13625 1 0 DR 0
|
CORGROUP $$CLK_RISC_BufferFalling
|
E3 1 23125 23125 1 0 DR 0
|
Percent 100
|
E4 0 23625 23625 1 0 DR 0
|
!
|
E5 1 33125 33125 1 0 DR 0
|
|
E6 0 33625 33625 1 0 DR 0
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
E7 1 43125 43125 1 0 DR 0
|
Percent 100
|
E8 X 43750 43750 1 0 DR 0
|
!
|
!
|
|
|
CORGROUP $$CLK_I_BufferRising
|
SIGNAL iwb_ACK_I
|
Percent 100
|
DIRECTION input
|
!
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
CORGROUP $$CLK_I_BufferFalling
|
ENDGRID -1
|
Percent 100
|
Clock Unclocked
|
!
|
EdgeLevel neg
|
|
Set Not Used
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Clear Not Used
|
Percent 100
|
ClockEnable Not Used
|
!
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
CORGROUP $$CLK_RISC_BufferRising
|
ActiveLowClockEnable True
|
Percent 100
|
VhdlType std_logic
|
!
|
VerilogType wire
|
|
SystemCType sc_logic
|
CORGROUP $$CLK_RISC_BufferFalling
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
Percent 100
|
StateEquation Hex(Inc(0,2,5))
|
!
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
SignalActionType 0
|
Percent 100
|
MSB 0
|
!
|
LSB 0
|
|
isFallingEdgeSensitive False
|
CORGROUP $$CLK_I_BufferRising
|
isRisingEdgeSensitive False
|
Percent 100
|
DrawAnalog 0
|
!
|
BooleanEquation
|
|
NegTolerance 0
|
CORGROUP $$CLK_I_BufferFalling
|
PosTolerance 0
|
Percent 100
|
UserSpecifiedSizeRatio 1
|
!
|
VerilogCode
|
|
VHDLCode
|
CORGROUP $$CLK_I_BufferRisingFalling
|
PROPS!
|
Percent 100
|
E0 0 11250 11250 1 0 DR 0
|
!
|
E1 1 13125 13125 1 0 DR 0
|
|
E2 0 21250 21250 1 0 DR 0
|
CORGROUP $$CLK_RISC_BufferRising
|
E3 1 23125 23125 1 0 DR 0
|
Percent 100
|
E4 0 31250 31250 1 0 DR 0
|
!
|
E5 1 33125 33125 1 0 DR 0
|
|
E6 0 41250 41250 1 0 DR 0
|
CORGROUP $$CLK_RISC_BufferFalling
|
E7 1 43125 43125 1 0 DR 0
|
Percent 100
|
E8 X 43750 43750 1 0 DR 0
|
!
|
!
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
SIGNAL iwb_CYC_O
|
Percent 100
|
DIRECTION output
|
!
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
CORGROUP $$CLK_I_BufferRising
|
ENDGRID -1
|
Percent 100
|
Clock Unclocked
|
!
|
EdgeLevel neg
|
|
Set Not Used
|
CORGROUP $$CLK_I_BufferFalling
|
Clear Not Used
|
Percent 100
|
ClockEnable Not Used
|
!
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
CORGROUP $$CLK_I_BufferRisingFalling
|
ActiveLowClockEnable True
|
Percent 100
|
VhdlType std_logic
|
!
|
VerilogType wire
|
|
SystemCType sc_logic
|
CORGROUP $$CLK_RISC_BufferRising
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
Percent 100
|
StateEquation Hex(Inc(0,2,5))
|
!
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
CORGROUP $$CLK_RISC_BufferFalling
|
SignalActionType 0
|
Percent 100
|
MSB 0
|
!
|
LSB 0
|
|
isFallingEdgeSensitive False
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
isRisingEdgeSensitive False
|
Percent 100
|
DrawAnalog 0
|
!
|
BooleanEquation
|
|
NegTolerance 0
|
CORGROUP $$dwb_CLK_I_BufferRising
|
PosTolerance 0
|
Percent 100
|
UserSpecifiedSizeRatio 1
|
!
|
VerilogCode
|
|
VHDLCode
|
CORGROUP $$dwb_CLK_I_BufferFalling
|
PROPS!
|
Percent 100
|
E0 0 3125 3125 1 0 DR 0
|
!
|
E1 1 43125 43125 1 0 DR 0
|
|
E2 0 43750 43750 1 0 DR 0
|
CORGROUP $$dwb_CLK_I_BufferRisingFalling
|
!
|
Percent 100
|
|
!
|
SIGNAL iwb_ERR_I
|
|
DIRECTION input
|
CLOCK CLK_RISC
|
RADIX hex
|
PERIODE 2.5
|
GRID 0 1 0 1 0 16711680 0 0
|
DUTY 50
|
ENDGRID -1
|
OFFSETE 0
|
Clock Unclocked
|
INITIAL HIGH
|
EdgeLevel neg
|
MAXUNCERTRISE 0
|
Set Not Used
|
MAXUNCERTFALL 0
|
Clear Not Used
|
MINUNCERTRISE 0
|
ClockEnable Not Used
|
MINUNCERTFALL 0
|
ActiveLowSetClear True
|
JRISEE 0
|
AsyncSetClear True
|
JFALLE 0
|
ActiveLowClockEnable True
|
GRID 0 1 0 2 0 16711680 0 0
|
VhdlType std_logic
|
ENDGRID -1
|
VerilogType wire
|
DIRECTION internal
|
SystemCType sc_logic
|
MASTERCLOCK None
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
Clock Unclocked
|
StateEquation Hex(Inc(0,2,5))
|
EdgeLevel neg
|
HighVoltageThreshold 5
|
Set Not Used
|
LowVoltageThreshold 0
|
Clear Not Used
|
SignalActionType 0
|
ClockEnable Not Used
|
MSB 0
|
ActiveLowSetClear True
|
LSB 0
|
AsyncSetClear True
|
isFallingEdgeSensitive False
|
ActiveLowClockEnable True
|
isRisingEdgeSensitive False
|
VhdlType std_logic
|
DrawAnalog 0
|
VerilogType wire
|
BooleanEquation
|
SystemCType sc_logic
|
NegTolerance 0
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
PosTolerance 0
|
StateEquation Hex(Inc(0,2,5))
|
UserSpecifiedSizeRatio 1
|
HighVoltageThreshold 5
|
VerilogCode
|
LowVoltageThreshold 0
|
VHDLCode
|
MSB 0
|
PROPS!
|
LSB 0
|
E0 0 43125 43125 1 0 DR 0
|
isFallingEdgeSensitive False
|
E1 X 43750 43750 1 0 DR 0
|
isRisingEdgeSensitive False
|
!
|
DrawAnalog 0
|
|
BooleanEquation
|
SIGNAL iwb_RTY_I
|
NegTolerance 0
|
DIRECTION input
|
PosTolerance 0
|
RADIX hex
|
UserSpecifiedSizeRatio 1
|
GRID 0 1 0 1 0 16711680 0 0
|
VerilogCode
|
ENDGRID -1
|
VHDLCode
|
Clock Unclocked
|
PROPS!
|
EdgeLevel neg
|
!
|
Set Not Used
|
|
Clear Not Used
|
CLOCK dwb_CLK_I
|
ClockEnable Not Used
|
PERIODE 5
|
ActiveLowSetClear True
|
DUTY 50
|
AsyncSetClear True
|
OFFSETE 0
|
ActiveLowClockEnable True
|
INITIAL LOW
|
VhdlType std_logic
|
MAXUNCERTRISE 0
|
VerilogType wire
|
MAXUNCERTFALL 0
|
SystemCType sc_logic
|
MINUNCERTRISE 0
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
MINUNCERTFALL 0
|
StateEquation Hex(Inc(0,2,5))
|
JRISEE 0
|
HighVoltageThreshold 5
|
JFALLE 0
|
LowVoltageThreshold 0
|
GRID 1 1 1 2 2 16711680 0 0
|
SignalActionType 0
|
ENDGRID -1
|
MSB 0
|
DIRECTION input
|
LSB 0
|
MASTERCLOCK None
|
isFallingEdgeSensitive False
|
Clock Unclocked
|
isRisingEdgeSensitive False
|
EdgeLevel neg
|
DrawAnalog 0
|
Set Not Used
|
BooleanEquation
|
Clear Not Used
|
NegTolerance 0
|
ClockEnable Not Used
|
PosTolerance 0
|
ActiveLowSetClear True
|
UserSpecifiedSizeRatio 1
|
AsyncSetClear True
|
VerilogCode
|
ActiveLowClockEnable True
|
VHDLCode
|
VhdlType std_logic
|
PROPS!
|
VerilogType wire
|
E0 0 43125 43125 1 0 DR 0
|
SystemCType sc_logic
|
E1 X 43750 43750 1 0 DR 0
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
!
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
MARKER MARK1
|
LowVoltageThreshold 0
|
ATTACH iwb_SEL_O NULL S6
|
MSB 0
|
TIME 17500.000000
|
LSB 0
|
RELATIVETIME 0.000000
|
isFallingEdgeSensitive False
|
DISPLAYAS 5
|
isRisingEdgeSensitive True
|
MARKERTYPE Timebreak(Curved)
|
DrawAnalog 0
|
WHILERETURN
|
BooleanEquation
|
REPEATNUMBER
|
NegTolerance 0
|
SNAPTO 0
|
PosTolerance 0
|
COMPRESSTIME 0.000000
|
UserSpecifiedSizeRatio 1
|
COMMENT
|
VerilogCode
|
!
|
VHDLCode
|
|
PROPS!
|
MARKER MARK2
|
!
|
ATTACH iwb_STB_O NULL S7
|
|
TIME 27500.000000
|
SIGNAL dwb_ADR_O
|
RELATIVETIME 0.000000
|
DIRECTION output
|
DISPLAYAS 5
|
RADIX hex
|
MARKERTYPE Timebreak(Curved)
|
GRID 0 1 0 1 0 16711680 0 0
|
WHILERETURN
|
ENDGRID -1
|
REPEATNUMBER
|
Clock
|
SNAPTO 0
|
EdgeLevel neg
|
COMPRESSTIME 0.000000
|
Set Not Used
|
COMMENT
|
Clear Not Used
|
!
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
MARKER MARK3
|
AsyncSetClear True
|
ATTACH iwb_STB_O NULL S7
|
ActiveLowClockEnable True
|
TIME 37500.000000
|
VhdlType std_logic
|
RELATIVETIME 0.000000
|
VerilogType wire
|
DISPLAYAS 5
|
SystemCType sc_logic
|
MARKERTYPE Timebreak(Curved)
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
WHILERETURN
|
StateEquation Hex(Inc(0,2,5))
|
REPEATNUMBER
|
HighVoltageThreshold 5
|
SNAPTO 0
|
LowVoltageThreshold 0
|
COMPRESSTIME 0.000000
|
LSB 0
|
COMMENT
|
MSB 31
|
!
|
SignalActionType 0
|
|
isFallingEdgeSensitive False
|
MARKER MARK0
|
isRisingEdgeSensitive True
|
ATTACH iwb_CLK_I NULL S1
|
DrawAnalog 0
|
TIME 7494.285714
|
BooleanEquation
|
RELATIVETIME 0.000000
|
NegTolerance 0
|
DISPLAYAS 5
|
PosTolerance 0
|
MARKERTYPE Timebreak(Curved)
|
UserSpecifiedSizeRatio 1
|
WHILERETURN
|
VerilogCode
|
REPEATNUMBER
|
VHDLCode
|
SNAPTO 0
|
VhdlMapping DefaultVhdlMapping
|
COMPRESSTIME 0.000000
|
PROPS!
|
COMMENT
|
E0 V -1 -1 1 0 DR 0
|
!
|
E1 X 3125 3125 1 0 DR 0
|
|
E2 V 13125 13125 Valid 1 0 DR 0
|
FQ/ %8 & " WMFC cR P3 PS x U > F Q/ EMF PS X V I S I O D r a w i n g
|
E3 X 15625 15625 1 0 DR 0
|
Y = & % % V 0 J J J J % ( % R L A r i a l d x _VarMemberFlags VB_Var@ ? > = < ; : 9 8 % T + . g = *A*A+ .
|
!
|
L ` C o n t e x t I D T | 5 > \ M *A*A5 > L \ ( 4 b i t s ) & % % V 0 } J J }J } J % ( % R L A r i a l % T . < = *A*A . L p P a g e I n d e x L e v e l 1 T | > M *A*A > L \ ( 8 b i t s ) & % % V 0 } i J }J iJ i } }J % ( % R L A r i a l % T . ( = *A*A . L p P a g e I n d e x L e v e l 2 T > M *A*A > L ` ( 1 1 b i t s ) & % % V 0 i U J iJ UJ U i iJ % ( % R L A r i a l % T . = *A*A . L d P a g e O f f s e t
|
|
T > M *A*A > L ` ( 1 3 b i t s ) R L A r i a l % T X " *A*A L P 3 5 R L A r i a l % ( % T X " *A*A L P 3 1 %
( R L A r i a l % T X b o " *A*Ab L P 2 4 %
( R L A r i a l ' x x
' #
|
SIGNAL dwb_DAT_I
|
P # Arial Arial % T X " *A*A L P 2 3 R L A r i a l P # Ari rial c,,y MMHM,,, % T X Q ^ " *A*AQ L P 1 3 %
( R L A r i a l r,HM(%MMM@MMm,BBBc
|
DIRECTION input
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock
|
H
|
EdgeLevel neg
|
c,,,,,,y,,,,,,,,,,,%c,,,,, 8 8 2 8 8 7 8 2 T 8 8 8 7 ! 2 % T X u " *A*Au L P 1 2 %
( R L A r i a l )@ ) GF )FF^F _F % T T F L " *A*AF L P 0 & % % V 0 i : :i:i :% ( %
( %
( % R L A r i a l GH@ GH FH) Arial % T w - *A*A L t P h y s i c a l P a g e N u m b e r T . L = *A*A . L ` ( 2 2 b i t s ) x & % % V 0 i U : i:U:U i i:% ( R L A r i a l ' x x
' #
|
Set Not Used
|
P # Arial Arial & " WMFC P PS % ( % % T . *A*A L d P a g e O f f s e t
|
Clear Not Used
|
T / > *A*A / L ` ( 1 3 b i t s ) %
( R L A r i a l rial Arial G@ G % T X *A*A L P 3 4 R L A r i a l % ( % T X O \ *A*AO L P 1 3 %
( R L A r i a l % T X u *A*Au L P 1 2 %
( R L A r i a l % T T F L *A*AF L P 0 & % W $ J J % ( % % V , & % % V & M & ( - 5 @ L Z h v ! . : Cv Jh MZ ML J@ C5 :- .( !& % ( R L A r i a l % ( % R L A r i a l % T A *A*AA
|
ClockEnable Not Used
|
L ` P a g e T a b l e T 8 *A*A8 L d B a s e A d d r e s s T ; . *A*A; L d d e p e n d i n g o n T A / > *A*AA / L d c u r r e n t C I D & % % V X
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
% ( %
( % R L A r i a l % T T *A*A L P + & % W ( a a a % ( % % V , & % % V 0 M M M M % ( & % % V 0 M M M M% ( %
( % R L A r i a l & ByVal Kt ( Call Gu * Case tL , CBool ~ Dir ge ? Dir$ \ @ Do 4 A DoEvents Do
B Double u Each V; D Else % T T *A*A L P + f & % W , % ( % % V , & % % W $ J J % ( % % V , & % % W $ J J % ( % % V , & % % V 0 : : : : % ( & rWMFC P PS & % % V 0 : 6 :66 : :6% ( R L A r i a l ! " # $ % & ' ( ) * + , . / 0 1 2 3 4 % ( % R L A r i a l F G H I J K L M N O P Q R S T U V W X ial ,% T d Y . x = *A*AY . L T P T E 2 & % % V 0 : 6 :6:6:% ( %
( % R L A r i a l ,,,,,,,,%c,,,,,
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
% T @ *A*A@
L h L 2 P a g e T a b l e & % W , - * *-*% ( % % V , , & : / ,&:*,/,& & % % W 0 6 * **66% ( % % V , 1 : :6 1: % R L A r i a l K K ! ! # 8 d d 2 ! ^ K K B 8 8 8 8 8 ! J % 8 : ! J 7 ( 7 ! ! ! : 6 C % T + q *A*A+ q L V i r t u a l P a g e N u m b e r ( V P N ) &
|
VerilogType wire
|
%
|
SystemCType sc_logic
|
W , I J I I J I [ I [ I % (
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
% % V , E N N I E N &
|
StateEquation Hex(Inc(0,2,5))
|
%
|
HighVoltageThreshold 5
|
% W , a i y a y iy ia % (
|
LowVoltageThreshold 0
|
%
( R L A r i a l % ( %
( % % T ` *A*A L T 2 5 5 R L A r i a l % T T *A*A L P 0 %
( R L A r i a l % T T *A*A L P 0 %
( %
( R L A r i a l @ ? > = < : 9 8 7 5 4 3 2 1 0 / . - , + ri% T d *A*A L T 2 0 4 7 <Y - - $ J J J - . -
Arial - 2
|
LSB 0
|
. +
|
MSB 31
|
Context ID 2
|
SignalActionType 0
|
> 5 (4 bits) - - $ J }J } J - -
Arial ????????????????????????? - " 2
|
isFallingEdgeSensitive False
|
. Page Index Level 1 2
|
isRisingEdgeSensitive False
|
> (8 bits) - - $ }J iJ i } }J - -
Arial ????????????????????????? - " 2
|
DrawAnalog 0
|
. Page Index Level 2 2
|
BooleanEquation
|
> (11 bits) - - $ iJ UJ U i iJ - -
Arial ????????????????????????? - 2
|
NegTolerance 0
|
. Page Offset
|
PosTolerance 0
|
2
|
UserSpecifiedSizeRatio 1
|
> (13 bits)
Arial ?????? ???????????????? -
|
VerilogCode
|
2
|
VHDLCode
|
35
Arial ????????????????????????? - -
|
VhdlMapping DefaultVhdlMapping
|
2
|
PROPS!
|
31 "System c p#ρP -
Arial ????????????????????????? -
|
E0 X 13125 13125 1 0 DR 0
|
2
|
E1 V 13126 13126 Valid 1 0 DR 0
|
b 24 -
Arial -
|
E2 X 15625 15625 1 0 DR 0
|
2
|
!
|
23
Arial A?? ??? ?? -
|
|
2
|
SIGNAL dwb_DAT_O
|
Q 13 -
Arial ?U??o????ooo??Eoou??????? -
|
DIRECTION output
|
2
|
RADIX hex
|
u 12 -
Arial - 2
|
GRID 0 1 0 1 0 16711680 0 0
|
F 0 -
|
ENDGRID -1
|
- $ :i:i : -
|
Clock Unclocked
|
- - -
Arial ?@? - % 2
|
EdgeLevel neg
|
Physical Page Number 2
|
Set Not Used
|
. (22 bits) - - $ i:U:U i i: -
Arial 'xx
? - - - 2
|
Clear Not Used
|
Page Offset
|
ClockEnable Not Used
|
2
|
ActiveLowSetClear True
|
/ (13 bits) -
Arial ????? -
|
AsyncSetClear True
|
2
|
ActiveLowClockEnable True
|
34
Arial ????????????????????????? - -
|
VhdlType std_logic
|
2
|
VerilogType wire
|
O 13 -
Arial ???????????? ???????????? -
|
SystemCType sc_logic
|
2
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
u 12 -
Arial ????????????????????????? - 2
|
StateEquation Hex(Inc(0,2,5))
|
F 0 - % J - - - $ -
|
HighVoltageThreshold 5
|
- : $ & ( - 5 @ L Z h v ! . : Cv Jh MZ ML J@ C5 :- .( !& -
|
LowVoltageThreshold 0
|
Arial ????????????????????????? -
|
LSB 0
|
-
Arial ????????????????????????? - 2
|
MSB 31
|
A
|
SignalActionType 0
|
Page Table 2
|
isFallingEdgeSensitive False
|
8 Base Address 2
|
isRisingEdgeSensitive False
|
; depending on 2
|
DrawAnalog 0
|
/A current CID - - " $
|
BooleanEquation
|
|
NegTolerance 0
|
- - - Arial ?? ???????? ????? - 2
|
PosTolerance 0
|
+ -
|
UserSpecifiedSizeRatio 1
|
% a a - - - $ - - $ M M M - - - $ M M M - - -
Arial &???l ?? ? -
2
|
VerilogCode
|
l PTE1 - - $ MMM -
Arial ?t ?? ?#H??? ?? - - - ! 2
|
VHDLCode
|
I L1 Page Directory - % < < A - - - $ @ M @ @ - - " $ - - Arial ?>~??r ?? ?????? - 2
|
PROPS!
|
+ - % - - - $ - - % J - - - $ - - % J - - - $ - - $ : : : - - - $ :66 : :6 -
Arial - -
Arial F G H I J K L -
2
|
E0 X 3125 3125 1 0 DR 0
|
.Y PTE2 -
- $ :6:6: -
-
|
E1 V 13125 13125 Valid 1 0 DR 0
|
-
Arial ?EEEE???????????????? -
|
E2 X 15625 15625 1 0 DR 0
|
2
|
!
|
@
L2 Page TableQ -
% *-* -
- - $ ,&:*,/,& -
- % **66 -
- - $ :6 1: -
Arial -
. 2
|
|
q + Virtual Page Number (VPN) - % I J I [ I [ I - - - $ N I E N - - % a y iy ia - -
Arial ????????????????????????? - - - - 2
|
SIGNAL dwb_WE_O
|
255
Arial ????????????????????????? - 2
|
DIRECTION output
|
0 -
Arial ????????????????????????? - 2
|
RADIX hex
|
0 - -
Arial ????????????????????????? -
2
|
GRID 0 1 0 1 0 16711680 0 0
|
2047 C o m p O b j q O b j I n f o s w V i s i o D o c u m e n t g V i s i o I n f o r m a t i o n " v x
|
ENDGRID -1
|
F Microsoft Visio Drawing VISIO 6.0 Shapes Visio.Drawing.6 9q ՜. +,D ՜. +,N
|
Clock Unclocked
|
@ H P \ h t
Pages Masters PageVisio (TM) Drawing
|
EdgeLevel neg
|
g TH jf | R d ! fff MMM 333 $
|
Set Not Used
|
$
|
Clear Not Used
|
US8@ Td Arial@$N@ Monotype Sorts@>NuWOingd R
N tSymbol 5T?? Y@ - 1 U
|
ClockEnable Not Used
|
J:D T1EW-hP T8 *
.U_ b a 酸0zGz?@3C fRbU|||%U
|
ActiveLowSetClear True
|
P } |KG/Y&4?\.? AfY&,,' /Dq&z&} |
|
AsyncSetClear True
|
|y }{})} ?2 | |
||||*|||E-?k4' -'CECE,'*CECECE-?H>?:`}'CEUCECECECEUCECE- O4F 2AJY;; AnVnVAbGTfY R_R__ `# f:/l b6p`fW /l
|
ActiveLowClockEnable True
|
/l Y?5?(\ #!&4$
|
tFf-|-|-|-wGQUo DOM`EtoA _3=OOOaOsOO??O?7ܻ u@L&d2?r# sU/-O%7 I[mRf J+
|
VhdlType std_logic
|
K5 . ||i| d'
0/UKiR?d?v4Gzt2#&Us s
|
VerilogType wire
|
s s) -0jӯY/ƛ!3)1D/// Q+p)?HdYc4Akǿٿ YfU|%1I߀O]-( fp
ɻ % -= Y[:!# :4)A/ q//YkϹ/p?2 Sπ '9}Fɇ7%õ8@\n1$ u (:L^p) B H>Z ՔU \ n4!'4#U2 q ?/%&k/%&`,`, `',ѓ4? | QԞQy ٓA G
$ X&bp6 q
/ #3=/Uq@T0'vr @1N!T0;UOauADV= 2r|UHE#E6 $2@1@1Bqq T ,$1Ѧ,/"dA0m+=Oa
/Q?c?u4D 3O贁 Nk?f 5 /:0/WOT/f/x/ - _2_D_dJt rIw 0(7 N`Da, Da/"oT f /dovoood`oo@ޑ W 7= FHݙA 1,ћ(/ //pP?0ܟt?ycT2No qł5Q2F Vt2bH)@ү 0S3 ,S* /ASe w@Пÿ1 'LG]7n5 0Ϧϸ 5Acrobat PDFWriwter$ }d x ) 3EWi{< # winspool Acrobat PDFWriter LPT1: UFDf P
h- RTUU U UF~@x
|
SystemCType sc_logic
|
BP(? 3h
)
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
wb Yb bbb b R))eqYkZ UHu P (: { W_q QRectangle. with text and connion points. Can be stretched to y dimen s s. bL&d2鿸\.?P?hHKMD?l? ~4
5DHDB
$# ?h-$>T TE=cA UF~?M&d2?F\_.?Q6 J u ` n?'u2
|
StateEquation Hex(Inc(0,2,5))
|
Ubaj jB> AV S> U5
gL @S{#I!N$5 A`7Copyright 1999 Visio Corporation. All s"s reserved. `~ _Sba.chm!#2243O0 l>#0>Udd#3 $ ] a %2+5U+0(T#FBS6.jRDRr6
|
HighVoltageThreshold 5
|
27(4M4]?
|
LowVoltageThreshold 0
|
o1t?1E> ?w9119T6 OHo?/G2M?;rA
|
SignalActionType 0
|
BCq,B^5/V: @%^ V"A(aCI |8Q
|
MSB 0
|
%[?-_?YM (|33Q:%^_ ?_Q_nKQEUIL_ _`I_U9E\_bo to o:nHl' - C{ ! Oya YEqF #T JB
|
LSB 0
|
\ ] [ak Jf @ +k Kf Ma$ f 8
Ul4,(9
D,m @r@ 2
A-d3 7 "A Ul4,(9
D,m @r@ $3 < *A-43 B7
Ul4,(9
D,m @r@ 3 *A-3 7 "A Ul4,(9
D,m @r@ 4
|
isFallingEdgeSensitive False
|
A-3 7 ;U~@1
FR0B
|2 H CD3 U_ Gcm _ MH<(
|
isRisingEdgeSensitive False
|
H<(
|
DrawAnalog 0
|
H<(
|
BooleanEquation
|
H<(
|
NegTolerance 0
|
U~E2
R0B
3 _
|
PosTolerance 0
|
<4 UFDf
h - TUU U@~@?x
|
UserSpecifiedSizeRatio 1
|
BP(?d
b:oqYTkQ4u23u` Connector
|
VerilogCode
|
`
|
VHDLCode
|
|
PROPS!
|
e1 C w
|
E0 X 3125 3125 1 0 DR 0
|
UH ^ -}|5 p`I` V ?}`xa 833 ސ ] 3σ3 u 33?, ? Gxpx ^ &
CThis connector automatically routes between the shap i
ts.HD
@# =hZ#8T H#3 BUF U@bX?\.nP6
|
E1 0 3467 3467 1 0 DR 0
|
u
|
E2 1 13125 13125 1 0 DR 0
|
`u b A @u *
E.# DB u `h?\hr|u a U
@-?bl;'b E-$ho' y(@r q ?@I ?$%?N
|
E3 0 13126 13126 1 0 DR 0
|
@ " *5Lz -b r_ ^vv"(2uM ."q28v"uh 9Bd &< /M z
|
E4 X 15625 15625 1 0 DR 0
|
#145 | `Vis_SE.chm!#20)@ `7Copyright 1999 @io Corporation. All ;Bs reserved. 4 U#1 ?# M7 A,@ +4j'v*Q8l>$UdvE \ 4
|
!
|
$dU' 1$b 24R(]Uv[D ZQi a59 93O ' 0"q? .g;2GHlu w- * O ` EW
|
|
)Fd # 7 B
|
SIGNAL dwb_SEL_O
|
GdIMo @k UFDf P
h- RTUU U UF~@x
|
DIRECTION output
|
BP(? 3h
)
|
RADIX hex
|
wb Yb bbb b R))eqYkZ UHC 5V o ? )> pp /q u u p wj lp ys opi` ;Generic circle with text and connection points. bL&d2P?hHKMl? j~45DHDD
# =hZ,>THYY9 A UF~?M&d2JQ6 u ` ?/u :m
|
GRID 0 1 0 1 0 16711680 0 0
|
biUr r~YA|XA@
|
ENDGRID -1
|
B > !"!"!"+&
|
Clock Unclocked
|
"
"
"S> U5
L @"'%9 ~lb 7 #FR&`0 ?F\.:55?P6 0)6#CL#EC 6 BLP{70 N #F;P 46B{#
|
EdgeLevel neg
|
AD5 A`7Copyright 1999 Visio Corporation. All 4Bs reservedo. `?@_Sba.chm!#22426 +l>(>UdPE
$w a BUE@(Z$6r;<
|
Set Not Used
|
5&
|
Clear Not Used
|
"($ 37; \-_?H4R ^3@R$iF76RRfQ%! _Z_k r#hb
nc_^,Q_kqYkOVsZX@8v BAo9R 3Rq%\ 8J6 _zs% u
^y _ zs% ~e 9qE {Xy"_ {Hl - _{ ! Oya YEqF$ # { B
|
ClockEnable Not Used
|
| Z D o5 o )PUFDf P
h- RTUU+U UF~@x
|
ActiveLowSetClear True
|
BP(? 3h
)
|
AsyncSetClear True
|
wb Yb bbb b ))eqYkZ UH. \? o _# ?. . : ? ? j n ` U ye k_k |f`cConnect two objs together. or can be ei
|
ActiveLowClockEnable True
|
a curve a straight line. shap. f). b]^ٿP&d2?LtQ"~i?
H D
# =hT#8>T #3 AA UF߅ < @F~?F} ?FP!3|@ A u
|
VhdlType std_logic
|
`u b vu`u
-
: @։u `h?mVu `b "@0S # eA ]&A dA W+ "W "4,4'> Dib@F\.@FĠ+?FM&d2?M " q&Vz&bV&V%. 'S""//87 ?5#'B?T:_UUb$@[
|
VerilogType wire
|
; tNzsS2 <b , 3a&G@140QD6 !468"8"dB#"R F 8!LS-!]{eE%?@r q ?@Ij@EE?j?rB=S*+@s`A*@bS_ SZg Ru bBTORrguh q4 `u# `@ 00u `dBsH4&L '8"{3AQ115 `Vis_Sba.chm!#2?2447 `7Copyright 1999 `io Corporation. All =bs reserv?ed. uG32Bq?oڗf2?|"?Jh 1al>
|
SystemCType sc_logic
|
(>U W(DE 30?P a%ra -s4p_(R @9$^$^8Mt<%??"1 Um-C U4u2F
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
1HBMt9B mxw}nha3 w9 qXh
|
StateEquation Hex(Inc(0,2,5))
|
A s`Change Arrowhead..o`1fthe a siz
ntyle for
|
HighVoltageThreshold 5
|
is con?nectoro`B?b)S"b%MGUύ[Jvc gU y
AR` PP `_Set As Stra>bLine
B`"1 l~А to be!ȓo`s
|
LowVoltageThreshold 0
|
(RiG82f86 iPPb3MO.`' 0crb".,jH a-!kX#gqP-@ ˁ?#|xy%qa
A# ^?=D TБg)ES5ArWb"_(9oh?ˁcB tL@ tR #SHl' ? { ! Oya YE_qF̭ w #D g B
|
LSB 0
|
| [ ca_ o W@ +k o :aL o t: ( < 7
S } Ϻ+ B ?,~( JR{ DG O >S" & /"\ w m$ )/ UP ?RT*@p@FDN Te@y
ahm $ TB qUF(9
D,m @Fr@?x
|
MSB 3
|
B P(?. K X] o `] q|J| 2 ? u ` h "&"u 0)@L&d2?~-ɏ(\.gҡ(.sU!&t /: e( '
|
SignalActionType 0
|
4 1!!R" U&)4
0 TR&! ^#%
|
isFallingEdgeSensitive False
|
\1H14`1 7f%4l174p1 74X17X181 7\18t17`18 7l187p18 7t181741 7|181718 718&!781 787181 718171881781G6&!8 1!718@178 D17181/g18 ,1718
1718):18*:18+:81871%4 7@187D54a718,:8-:18.:d18@|17,1813c(Al1\1\1`1D`1l1l1a1D1|1111D1|1|1 81Uďo@1 EQ/ / 1 ` Connector 1_` P
|
isRisingEdgeSensitive False
|
V 1[EiaiC X1|iEE M 7?@XV@@"?@Z"5?GO?(5o%K2c(1;1
1<M"?Il\10Rse V
둗!1 c( HϾQiEqQ8qpU2&fHn dк` 1 G!Ȧ f%)`WCU) %@ߕ߰l2Xtext ID
|
DrawAnalog 0
|
(4 bits)2hD f%͟ߟ'h+ g@>~?@ER!@'i0q@1|¯ԯf% ;M_q CϹ2& &z
|
BooleanEquation
|
|
NegTolerance 0
|
/c/2/ 5Page Index Level 1
|
PosTolerance 0
|
(8QT5d,hOB!3EWia RF9 E1 -?Q c Cl_ Q_) ; M _ q vX /ROՓo _//1.LQ/o u//,/
ot%q?72
|
UserSpecifiedSizeRatio 1
|
(11 Q藕:?xW?i?{?????$ds??O!O3O oa)eOwOO իOO"QOO_ _'_9__]___C ____(_o#o GoYoko}os) jou{ =Oaυ=O) Offs etp3Q2 ٣K@hdwΜq}s
@@|>?@'?@řĠչ?uPuu `Dn?up2 L0Пï ٌ> 2 k=!ߵ;w25'5 im uzcc#$ ' 2 q n %7I[mW G?@$>k@@܂oO?@@ŗ@n);M_ q) +/}/N 8 ?0?/i?/?@/ ??< 3dv 2 D V h |ZQJ .?@# ֩ AV &/8/J/\/n/// /OO&O/Q??u? oF?~%?? mo?oAOSK1bOtOOOOO CJQOOO_ _2_D_V_h_"0 @W߫ G ɖ / 1oCoUogoyooo
8oů ?h g ӯӿ;PM24_q˃ ҏ,>Pbz/V
|
VerilogCode
|
@И ___Y o 2DVhz 毢ֺ uF? ڿ ?g῝;M3\nπϒϤ˃
|
VHDLCode
|
);M_tgWO Gҕ؋§ Y /ASew ,/r /C( ? d?/?/??8P1Xj| ʄN ) ; M _ w̎#!S @'yӕ؈Sä NV// ,/>/P/b/t///? OO/lVoo?o @?h????a o?o5OGK2VOhOzOOOOC *aOOO__&_8_J_\_tՆC@%_@@"U0 U___ *aYoo)o;o Mo_oqooo olկ= /Wï { ÿ+L0Sew˃
w͌ޅz`,$r$@1'N`_El2=l@@fОP xكyЅQLُR+)s[7٪/(<1NM?\.?3,;ML,q @:q,1w䵡 zy :dBZ X?Q0 6'FKPhysical Page Number
|
PROPS!
|
(22 bits) ̂66 *
|
E0 X 3125 3125 1 0 DR 0
|
p,OB-_-O_@)_ p._P i Offset
|
E1 V 13125 13125 Valid 1 0 DR 0
|
(13ɏۏ폀#5GYk'?@ a?K@fRu*s1u 퓷ߖ[r ͟ɑ/'M?_?q? ?UOۯ? *vViz:3u ÏAph Kh(ϣ @34Oasυϗϩpcko}oooooooo
xzf_@@"ur?@P7' p0 K]rgfx}_ :!3 Ώ&S wߏ0(> Ѱe ߅Hϭe<͟ߟ 13 +=Omhz ¯ԯ
x̎#!S @ @"uP+u0$Bp@BWri~q~vdcsɿۿ #5ϓߥ߷ }9 $P tϘ Lߵp/Aiw@3 LW i 2@(:Lje w
xC@%" 0.1!3=O as_pa!6
1 y5L!6MO qO HI Om , > OfOt 0_IOT_f_
|
E2 X 15625 15625 1 0 DR 0
|
Bk0 //%/7/I/g# Di,#]aA! A/c;%!%!4'Q9,AEa1A/U@$ds@@N #@@L1z^
0t90{;rdJD20vA1]!u
nPu`rs3]a1 v8}&.{@ wiMP)"p%`w @z31r 2p A-A@RwbX(qCv|Mt@rHb?@IVۀ?фمI@D_e6kT3{1H1&0oNt (/d2N贁NkvS" V
"8g "`0 a@aS!@ .vc햡Xbrb(8<#]a*\.k?
|
!
|
E$719&C?OU@0O_ \O:uޯrWi! cqAi,Scoo G UA%A$dliI yEޱNP?@/]2@@~?*,!=Q b95П2pxqdc! >Źx< ?@|W>BA`Hxqmƣ3bI!Tcq
|
|
Base Address
|
SIGNAL dwb_STB_O
|
depending on
|
DIRECTION output
|
current CIDcEγ2ٿ뿀
|
RADIX hex
|
Eo]cX= (8=:CV@%N/zﷂE,'(A\UO 8dOn_@a5bh 5 1/M % %^ % \BWi!S11i, 3S15A¿Կ
|
GRID 0 1 0 1 0 16711680 0 0
|
h+ g@@lS
|
ENDGRID -1
|
@@4OFn ~NϢ6Sjϣ2Bf f!œ&v?@ڿNt*%3%#"S1 >P-S1Qz_oPo*o
|
Clock Unclocked
|
DaU32Oc1QE\+c, # 5 ]@！w x?K ?:
HV |_NXHO+@O [_W T_3S
_ _TO:o^ z{okj#kx70Ezu04'!IǑq9ЛǑD Ƭ?@ x@@)?@`Vj?@)uu{`uP0`A _ru
qu{br8
|
EdgeLevel neg
|
-g @@ 5 oL c c p:rA:@Rrp3p!w"r舆"r)wA 4܈xr q ǿ?@IMBtM}3uQ]FX-H& t 842N贁Nk:2 Wf
h p> `0 3q8L1:1 .Ϗ_/T_\.?
o_Kqi?{?L1Kq?U9WaGvFBgw;sp\tPT3l 0E;^ÿa! oy%ooo}N $
x7yAG}W}+Y-oR/p=B4 @@L"ɿ@4hhÑ 㿤|r~!yh ~+ M 7p%.{@@E&p0(JP@ :5r֨͏s U@c3u | P_CUgyˎNG*ZxFߟDß^!5 A.Kpz$
|
Set Not Used
|
L16 tNpvzsGۑE /+WwCs "!֥G袎OOE'߷S_?︿K~}jbql =
(տ ~=澀50 T 4b44"L1Q K5yKq!A$7y5E[y+#?@N$@G"hpl%}#q #?QIbt}! ѱ"t"6Uq% '0C*"'"@1 5kߤ+ k#g? ֥cAQccO }CWm '? 5}&KU N%C >VKE?.9 '995QEAU& o ao0c5[&_%n G%^&^_'l]tL[_ ____3uaA zoK-y$qIcOW/U@Hl% _x?@>~%@ eH sq s/+/$"// !
|
Clear Not Used
|
xQcQ.@R!RUovT?8?Ե= Onٷq ˏy(zE ZPr̟ ޟ|t p_9džXί_s@UTG` !!ôea!o
o(:L MQ`ڪF @@N #@dă şbX?d?PLQL!M:@@GbDTDh u!06B@"Th5h|uq qeo,o
|
ClockEnable Not Used
|
S [#i$!t'Ui$t#v ѣM
|
ActiveLowSetClear True
|
JaM 9 MȯLΑTL
|
AsyncSetClear True
|
@@?~ u3ߣ5 *@1!:| 26 !!3#0@%0 w 2A E7O pOE
|
ActiveLowClockEnable True
|
_t#_5_ WZOo_O__ __@^yåL1 Page Directory iڤMK4^j9mA#'O ' 2qlq$ <y<ܿ{1l7R14H7O
|
VhdlType std_logic
|
f6rH
|
VerilogType wire
|
2`0 BnqmAa .-~s<;M5TLݹ餿հ\BE ѕOUOoo+oOQ4}ƫUU]nX](C! OD,uCu wKuE;5¡Wt-wxwi ET+hO@@-g p4FZQI IS}rB2G1" ~s
|
SystemCType sc_logic
|
Yl2v?@NWtBK 2 *r(¯T4MR?waooo(om5aUKcAJai!Zh+D) \B4F߅EX!n(\Z Kh8Tߘ V `00c8 M2((:Id
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
%%Re ߾
rVA o NeXs 1 KUUY /5 -/
|
StateEquation Hex(Inc(0,2,5))
|
3/!G1o Md 1CUgyz3<@@"Hcwh uW?@0u¡ Q&6;P(9
D,m i@`5z@sVa]BXO@jOȃc4GOO 6#LC WYU@n@5ѱp` h.ZrݲPڟ "4FXj| kޯ h #G@k}5ϡz{U? pÈD\h_@gHX !!/ '/͏ ?.?@?R?d? vXth+ g@@QLC0L?@jZn0yֿ<2n?>IӖJV&.{z]㦣;m OG:UA-O,>CZk~Oޖ YЧ6_U xֿ[_m__u|~Q__o__oo&o8oJo}nf·ߢ+ƞo Too͛eq$ g y5Gp WuJ2 } .ߍ99T9 ҏ,>~P+hOE@?73@o.b099I\p,d
|
HighVoltageThreshold 5
|
*d58F OGuA32D GZqC9 Y~ 2s߅hz ¿Կ
|
LowVoltageThreshold 0
|
Ca1R T j|ϒ Ѣϴ OJ\D .~h"/4/wG ! $!q- q aq+:U!us9 &D)fkT/@@19~?@H?@ Xa5Zj5;"}/ d
LΒ S%663626666666Z+be"x( a
|
SignalActionType 0
|
x
|
MSB 0
|
Xs COuD1G:UDC+
qGGF0=Q1F0JQѴS%#s@
|
LSB 0
|
? ?.? vXtMv5N?@Gd5hv5c{0$c?]QItyqʹ S Mbt5Xb6qde PSgs!Mbmgxb Ou F0Y qTxU y c?F_G0 AI0U qnS bt/ P) uf{u~$es~{Qzms,
1IQ)[ ,4qw{09xxC 3ᓁe!fuˌ $fˌx N%z1 Qc_BT|_y)OOx_6u6 x?@>Bd5@v媣{0=oROk^oVdxb~o4imya l c%aCn,7YAeJcxHoTo1(: L^p0xɪ ϰ); M_qΟԋd,F0Mah سQar(Fi
@PTE2R__qT _____x3⨨̯ޯYaRUr
nfTr oSoBrۿ OA!3EWi ϱϯ ϓ "4FXj|ߎ 3/ߔ/ // ,$ /lc'/H?) {?֝'Vs |
Ip|дd(fkT/@@~@@~tRCߧE?PF݀y}uTaBunaz1|BV b\L"|* 0< r/` r 1//yB IPCIQUG_F E_oD'o9og _so_o (o ooDn1 "sCL2 Page Table i| S'tڅIXR~.\ ' 2<
|
isFallingEdgeSensitive False
|
@4] zAvAVA4S'q`SL~nyQʶh9@@[@@`?@`0 ?@xƂֿErDu\`;u
|
isRisingEdgeSensitive False
|
O AJQ;u=`u C\ S"
|
DrawAnalog 0
|
| q9Ui @@-g @@3 𰀌N #@ p n{ N@z3JQu{HpΖ!͟ߞ RB'mRBC\8F#U@ cX,ۿ@rr?@IV?~цFrD"yozӛԏl::Ar~* t2NoNkr 6<6vXxBB`0 pnQq .:
|
BooleanEquation
|
T±
i 鴿± "N'`R]/o/U!_U_ /ǀ o~goi"Ymn@ m(C] 4
1CUgy.@@YJ,P?@|>@~^@ޏ&; Ui@2=lh i`uXVQcȓ[#CYNϐ@e+pǡ2P^Cگ-V!K '9K]o sp⼿δ ٿ V_h_= VTfx0ߜɾ#m+"S R'U/C]ǥ/a.L?%?o(^?/?*
|
NegTolerance 0
|
BM{_rE 3(l鑵d8v>@@ x@@@dDCw 1SǢu) ,FǢ 19ANU+/OV2/ D/lEm/km\/ __LoXF_oo@A?:h_Wo_1+ <
|
PosTolerance 0
|
O7cu,OaE FIA61ZDH>EBEOU@`ڪF HNb?@ `EsuGqF aOMv_BF@ S @ L%U /Q_!*l_U __Jo on͒v o(ou+ +kݖVdЏ?П ;HZ@Virtual Page Number (VPN) iROdO ' 2Vqq11Q ooo 0BTfEBEm
@@Fh@@K;ֶ@E ~!QF1QsC "4FX j|" ;vGذ .@ߐϞ0yϝ߀-5M0uϯ- 0BTfx qsp(
|
UserSpecifiedSizeRatio 1
|
B ɿۿ $6HZl~ϐ ϴ$6a Vh5 ߰ } ߳ C Rdv .,>PbtZVQ*J_R?@P٪ 3! F 2DVhz / /2/L6 O OX X 0_ x_O _O__<
M2047m////// U.U
|
VerilogCode
|
U Ul4, (9
D,m @r@ <7 wV 'Cl0
|
VHDLCode
|
7 AU2@1 V7 KR H<(
|
PROPS!
|
U2EL1 W7
R UlL % 0 fV @ U?4% ) gR D3 W< U$
|
E0 0 3125 3125 1 0 DR 0
|
4( U1( UO"D&aU=QJf )h" Ty+U,
_ Ʌ >-
|
E1 1 13125 13125 1 0 DR 0
|
H*9( TYg
|
E2 0 15625 15625 1 0 DR 0
|
E / + Guide TheDoc Page-1 Gesture Format Basic Visio 00 Rectangle Rectangle.3 Rectangle.4 Rectangle.14 Connector Dynamic conn?ector Circle Visio 90 Line-curve connector ScaleFactor Circle.31 Rectangle.26 Rectangle.27 Rectangle.13 _ 3 BX
|
!
|
E L W-
|
|
b G Uz
|
SIGNAL dwb_ACK_I
|
_
U,_ D_ U \_
|
DIRECTION input
|
Ut_ AU_ _ Uԇ
|
RADIX hex
|
_ Ue_ ? _ Yv _ U$%4<%DT%Rl%c_ tX_ [ 0 xQm U Ul4,(9
D,m @r@ d5 Z C-T3
|
GRID 0 1 0 1 0 16711680 0 0
|
7 A Ul4, T0 [
|
ENDGRID -1
|
AJ-L3 7 A _ *<N@4 Z MRVgL+
[ 6uH<(
|
Clock Unclocked
|
H<(
|
EdgeLevel neg
|
_ *<NE5 [
RVg+ q > 7 DVh z
|
Set Not Used
|
. @ R d v 7 J3
|
Clear Not Used
|
3 3!/3/ E/W/i/{///// /// ? ?/?A?S? e?w??????;R o0tE n0r yO 5 IO 㰋[AV B ALOOO 5.O\@c_ jBbAT h i s D0c u m e2 __ @fA1 _S_fA_qD_ P R/ O J0C@__.TA
|
ClockEnable Not Used
|
__+ 3`
|
ActiveLowSetClear True
|
!.fA !!
kA3/B /R U!"#$U%&'(U)*+,3U./01236567
|
AsyncSetClear True
|
89/oo ,>Pbt~ . . q. kT ڥإT@zaA " U_N`WfA!
|
ActiveLowClockEnable True
|
!v!qx $F8ME;7/߿ A 2DV7 a SL? St?<\?- N`{`2`A-0RCڙ4`}=[ac뀂l8baaZH G]ZR]d=߮ί t Attribut e VB_NaP = "Th@Document"
|
VhdlType std_logic
|
|
VerilogType wire
|
Bas0{00021PA21- 0C $0046}
|GlobalSpacFalse dCreatabl Predecla Id Tru
BExpo~ Templ ateDerivBustomizDa$Ϳ߿*A PG ?* \ GꑇE Fɟ۟#.`#`#P:t|SG}PA M_F I L0SCPMOMC}RSPF@ *Hu@R0DrC6E`.@L#q@Au a UlBs@cUo@ u@pl a0i0n@`˰9`.@Rdǡ8y`nvψVSOLB 3H`* #¨ @UyeL@b@]aB [e@)v RPlP.1 ]?3_dv^nוWN@OS YT0Mt dP.TbRy`Ou0oPt&- . _ .
|
SystemCType sc_logic
|
ʋS <@L_|M`TOS`1c`ad4;U -R.%f@ (: L^p\ # 5 G Y k } $FcnB1v F"x`[A-R
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
d`Visio VBA0 Win16~C$32:!Mac =!6#
Figure2Damjan`stdole` 26t< ! _Evalu %jw '<&Q@:3P( b5b?=R 0* pH od!` p%@x" @@
|
StateEquation Hex(Inc(0,2,5))
|
=
|
HighVoltageThreshold 5
|
+x S̠8 J<
|
LowVoltageThreshold 0
|
r"e>s@0.rf %\ *\G{020430-; C!06}#2.0#C:\WI~OWS\SYEM\StdOi ? OOC_EOJ$[-k`A>|[wPOO(W3OO\3 dnOO_k/a(OO_$4k`N||___E__Fle2.TlbLE Automation`"t _F# #G QmSnY2 `H1`
|
SignalActionType 0
|
,QCإ"+ K0soooE)oFID="{C81BE968-281E-11D5-80A9-E8D506C1M0}@%=)/&Hqq
|
MSB 0
|
)e="p*@HelpContexta0@Ver5 nComp`ble32="393222M@CMG="1614A5C3ADC3B5C7y qPBpA18A9CFACD0sv@GCpE1Cp}BpBB8CCq4q
|
LSB 0
|
[Host Extender Info]
|
isFallingEdgeSensitive False
|
5v1={3832D640-CF90pCF-8E43-00A0C91p5A};VBE;5yoQc uϏ );M_q ˟ݟ %7I[m ǯٯ!3 EWi{ÿ տ /AS ewωϛϭϿ +=Oas ߗߩ '9K]o # 5GYk} E: XC [ M
|
isRisingEdgeSensitive False
|
B A{
|
DrawAnalog 0
|
* g"4pFX (M1@(ς@2Yy
|
BooleanEquation
|
K_LQ :TWR
|
NegTolerance 0
|
R v &O !B oX 71>} :B h U>O k 5O }
|
PosTolerance 0
|
% $Ft'C>:W QNl )TU11 =vy` 2y Y nV =Z?y C[ + GD5 C
_4f +< o _Y O.y S u m m a r y I n f o r m a t i o n ( y N D o c u m e n t S u m m a r y I n f o r m a t i o n 8
|
UserSpecifiedSizeRatio 1
|
_ 1 0 5 0 0 7 3 3 8 1 | Q<= Kuy @ @ O l e
|
VerilogCode
|
|
VHDLCode
|
! $ ; x & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : O = > ? @ A B C D E F G H I J K L M N w Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v { | } ~ Oh +'0 @ H h t Valued Sony Customer G M x U = F Q/ EMF M X V I S I O D r a w i n g
|
PROPS!
|
Y = & % % V 0 J J J J % ( % R L A r i a l % T + . g = A A+ .
|
E0 0 11250 11250 1 0 DR 0
|
L ` C o n t e x t I D T | 5 > \ M A A5 > L \ ( 4 b i t s ) & % % V 0 } J J }J } J % ( % R L A r i a l % % T . < = A A . L p P a g e I n d e x L e v e l 1 T > X M A A > L | ( V A D D R _ W I D T H - P 1 S - 1 b i t s )
& % % V 0 } i J }J iJ i } }J % ( % R L A r i a l % T . ( = A A . L p P a g e I n d e x L e v e l 2 T > M A A > L h ( P 1 S - P 2 S b i t s ) & % % V 0 i U J iJ UJ U i iJ % ( % R L A r i a l % T . = A A . L d P a g e O f f s e t
|
E1 1 13125 13125 1 0 DR 0
|
T > M A A >
|
E2 0 15625 15625 1 0 DR 0
|
L ` ( P 2 S b i t s ) R L A r i a l % T v " A A
L h V A D D R _ W I D T H - 1
R L A r i a l % T " A A
L h V A D D R _ W I D T H - 1
%
( % T ` \ t " A A\ L T P 1 S R L A r i a l B % T l " A A L X P 1 S - 1 %
( %
( R L A r i a l % T ` H ` " A AH L T P 2 S %
( R L A r i a l % T l t " A At L X P 2 S - 1 R L A r i a l % T T F L " A AF L P 0 & % % V 0 i : :i:i :% ( %
( %
( % R L A r i a l % T w - A A L t P h y s i c a l P a g e N u m b e r T . = A A . L | ( P A D D R _ W I D T H - P 2 S - 1 b i t s )
& % % V 0 i U 9 i9U9U i i9% ( %
( % R L A r i a l % T - A A L d P a g e O f f s e t
|
!
|
T . = A A .
|
|
L ` ( P 2 S b i t s ) %
( R L A r i a l % T l A A L d P A D D R _ W I D T H
R L A r i a l iT"Y Y Arial Arial c,,y MMHM,,,,,,,,,,HHH,c % T ` F ^ A AF L T P 2 S M %
( R L A r i a l
|
SIGNAL dwb_CYC_O
|
|
DIRECTION output
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
H
|
Clock Unclocked
|
c,,,,,,y,,,,,,,,,,,%c,,,,,
|
EdgeLevel neg
|
% T l t A At L X P 2 S - 1 %
( R L A r i a l
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
% T T F L A AF L P 0 & % W $ J J % ( % % V , & % % V & M & ( - 5 @ L Z h v ! . : Cv Jh MZ ML J@ C5 :- .( !& % ( %
( R L A r i a l % ( % R L A r i a l % T A A AA
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
L ` P a g e T a b l e T 8 A A8 L d B a s e A d d r e s s T ; . A A; L d d e p e n d i n g o n T A / > A AA / L d c u r r e n t C I D & % % V X
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
% ( %
( % R L A r i a l % T T A A L P + & % W ( a a a % ( % % V , & % % V 0 M M M M % ( & % % V 0 M M M M% ( %
( % R L A r i a l
|
LowVoltageThreshold 0
|
|
SignalActionType 0
|
|
MSB 0
|
% T d l A Al L T P T E 1 & % % V 0 M MMM% ( R L A r i a l
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
% ( % R L A r i a l % T S A AS
L h L 1 P a g e T a b l e & % W , A < < A % ( % % V , @ M @ M @ @ & % % V X % ( % R L A r i a l , - . / 0 1 2 3 4 5 6 7 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h q % T T A A L P + & % W , % ( % % V , & % % W $ J J % ( % % V , & % % W $ J J % ( % % V , & % % V 0 : : : : % ( & % % V 0 : 6 :66 : :6% ( %
( % R L A r i a l U V W X Y Z \ ] ^ _ ` a b c d e f g h i j l m n o p q r % T d Y . x = A AY . L T P T E 2 & % % V 0 : 6 :6:6:% ( R L A r i a l % % ( % R L A r i a l U V V U - n 0 0 0 A B % T @ A A@
L h L 2 P a g e T a b l e * &
|
PosTolerance 0
|
%
|
UserSpecifiedSizeRatio 1
|
W , - * *-*% (
|
VerilogCode
|
% % V , , & : / ,&:*,/,& &
|
VHDLCode
|
%
|
PROPS!
|
% W 0 6 * **66% (
|
E0 0 3125 3125 1 0 DR 0
|
% % V , 1 : :6 1: % R L
|
E1 1 13125 13125 1 0 DR 0
|
A r i a l P P W W W W P P Q : : - } { . | %
|
E2 0 15625 15625 1 0 DR 0
|
T - q A A- q L V i r t u a l P a g e N u m b e r ( V P N ) & % W , I J I I J I [ I [ I % ( % % V , E N N I E N & % % W , a i y a y iy ia % ( -1
|
!
|
Rectangle Dynamic connector Circle Line-curve connector 8 _VPID_PREVIEWS ` _VPID_ALTERNATENAMES _PID_LINKBASE ? A
|
|
Q<= Kuy Timing Diagram Timing.Document.1 9q Timing Diagram C o m p O b j { } i O b j I n f o ~ C O N T E N T S % \+ _ 1 0 5 0 1 9 5 4 1 8 Q<= Kuy @ @
|
SIGNAL dwb_ERR_I
|
Q<= Kuy Timing Diagram Timing.Document.1 9q TimingDiagram
|
DIRECTION input
|
F Microsoft Visio Drawing VISIO 6.0 Shapes Visio.Drawing.6 9q Timing Diagram Editor v7.1g - Output File
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
PROJECT
|
ENDGRID -1
|
BaseTimeUnit 1
|
Clock Unclocked
|
DisplayTimeUnit 2
|
EdgeLevel neg
|
TextGridX 250.000000
|
Set Not Used
|
TextGridY 6
|
Clear Not Used
|
EdgeGridX 250.000000
|
ClockEnable Not Used
|
ImportStartTime 0.000000
|
ActiveLowSetClear True
|
ImportEndTime 281474976710656.000000
|
AsyncSetClear True
|
TimePerPixel 6.571429
|
ActiveLowClockEnable True
|
Visible DELAYS SETUPS HOLDS SAMPLES TEXT HIDDENATTACHMENTS CRITICALPATHS GRIDLINES UNCERTAINTY
|
VhdlType std_logic
|
ColWidths 144,216,288,423,488
|
VerilogType wire
|
ScrollPos 0.000000,0.000000,0.000000
|
SystemCType sc_logic
|
DefDelayRule 1
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
NoEventOverlap NO
|
StateEquation Hex(Inc(0,2,5))
|
SigLabelFontHeight 10
|
HighVoltageThreshold 5
|
LabelHeight 12
|
LowVoltageThreshold 0
|
LoadLibsToMem 1
|
SignalActionType 0
|
UseFullPathNames 1
|
MSB 0
|
LibPath
|
LSB 0
|
EntireTime YES
|
isFallingEdgeSensitive False
|
PrintTimeSpecified NO
|
isRisingEdgeSensitive False
|
FromTime 0
|
DrawAnalog 0
|
ToTime 5.75
|
BooleanEquation
|
AllSignals YES
|
NegTolerance 0
|
CurrSelSigs NO
|
PosTolerance 0
|
PrintTo 2
|
UserSpecifiedSizeRatio 1
|
PrintFileName C:\DOCS\dbg_readwritespr.wmf
|
VerilogCode
|
PreviewInterchange YES
|
VHDLCode
|
PreviewTIFF5 NO
|
PROPS!
|
UseMargins NO
|
E0 0 15625 15625 1 0 DR 0
|
PrintTimeLine NO
|
!
|
PrintBorderBox YES
|
|
PrintSigNames YES
|
SIGNAL dwb_RTY_I
|
PrintSigNamesOnEachPage YES
|
DIRECTION input
|
AddPreviewToEPS NO
|
RADIX hex
|
PreviewRes 150
|
GRID 0 1 0 1 0 16711680 0 0
|
MarginLR 1.25
|
ENDGRID -1
|
MifImageWidth 6.00
|
Clock Unclocked
|
MarginTB Auto
|
EdgeLevel neg
|
Header %d %t;%f;%p
|
Set Not Used
|
Footer
|
Clear Not Used
|
ScaleHorz 100
|
ClockEnable Not Used
|
ScaleVert 100
|
ActiveLowSetClear True
|
ScaleHPage 1
|
AsyncSetClear True
|
PrintImage DIAGRAM
|
ActiveLowClockEnable True
|
DefaultTimingModel minmax
|
VhdlType std_logic
|
DefaultClock Unclocked
|
VerilogType wire
|
DefaultEdgeLevel neg
|
SystemCType sc_logic
|
DefaultSet Not Used
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
DefaultClear Not Used
|
StateEquation Hex(Inc(0,2,5))
|
DefaultClockEnable Not Used
|
HighVoltageThreshold 5
|
DefaultClockToOutLH 0
|
LowVoltageThreshold 0
|
DefaultClockToOutHL 0
|
SignalActionType 0
|
DefaultSetup 0
|
MSB 0
|
DefaultHold 0
|
LSB 0
|
DefaultRegStartupState unknown
|
isFallingEdgeSensitive False
|
DefaultPodSize 8
|
isRisingEdgeSensitive False
|
DefaultActiveLowSetClear True
|
DrawAnalog 0
|
DefaultAsyncSetClear True
|
BooleanEquation
|
DefaultActiveLowClockEnable True
|
NegTolerance 0
|
SigLabelFontHeight 10
|
PosTolerance 0
|
PROPS!
|
UserSpecifiedSizeRatio 1
|
!
|
VerilogCode
|
|
VHDLCode
|
STYLE
|
PROPS!
|
DefaultFont USER {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
|
E0 0 15625 15625 1 0 DR 0
|
DrawWndFont DEFAULT
|
!
|
DrawWndColor DEFAULT
|
|
GridWndFont DEFAULT
|
MARKER MARK0
|
GridWndColor DEFAULT
|
ATTACH dwb_DAT_O NULL S4
|
LabelWndFont USER {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
|
TIME 7500.000000
|
LabelWndColor DEFAULT
|
RELATIVETIME 0.000000
|
ParamDispPref 0
|
DISPLAYAS 5
|
ParamWndCellDisplay 0
|
MARKERTYPE Timebreak(Curved)
|
CustDispString %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
|
WHILERETURN
|
CustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
|
REPEATNUMBER
|
MarkerDispPref 4
|
SNAPTO 0
|
MarkerCustDispString %n v=%mv,%Mv d=%md %t
|
COMPRESSTIME 0.000000
|
MarkerCustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
|
COMMENT
|
SignalColor 2
|
!
|
LabelOffset 4
|
|
BusDisplay 0
|
Q&l ^ & " WMFC e x Q &l EMF S X V I S I O D r a w i n g
|
WaveFormWidth 0.500000
|
Q % R L A r i a l % T l W Q
|
WaveFormColor 0
|
@
|
InputWaveFormColor 16711680
|
@W Q L X S E T 0 - - ) % T l W
|
SlantedEdges 1
|
@
|
SlantAngle 75
|
@W L X S E T 1 - - ) % R L A r i a l B B d d
|
RightJustifySigNames 1
|
u J JS % T `
|
AutosplitEnabled 1
|
|
AutosplitChar _
|
@
|
DynamSizedSignals 1
|
@ L T . . . R L A r i a l PCM K % T ` s 1
{
|
!
|
@
|
|
@s 1
L T S E T - - ) R L A r i a l % T 6 r
2
|
DIAGRAMTESTBENCHSETTINGS
|
@
|
FilesBeforeDiagramModel
|
@6 r
L ` I C _ S E T S - 1 $ ! ! ! & % % V 0 o 3
p
2
2pp
% ( R L A r i a l F n % ( R L A r i a l ( : L ^ p 0 ` . x H R d r f , ` B
|
FilesInsideDiagramModelDeclarationSection
|
P Z & L % ( R L A r i a l 0 ` > j 8 p 2 b P < p j 8 X rif design, Arial contains more humanist haracteristics than many of its predecessors and as such is mo st% ( R L A r i a l r and fuller than in most industrial style sans se faces. Terminal strokes are cut on the diagonal which helps to give the face a less mechanical appearance. Arial is an extre ly versatile family of typefaces which can be used with equal s,% ( % R L A r i a l www.monotype.com/html/mtname/ms_arial.htmlhttp://w onotype.com/html/mtname/ms_welcome.htmlNOTIFICATION OF LICENSE AGREEMENT
|
AbortHdlCodeEnabled 1
|
|
DelayHdlCodeEnabled 1
|
This typeface is the property of Monotype Typograp and its use by you is covered under the terms of a license ag pe% T l o
|
SampleHdlCodeEnabled 1
|
@
|
MarkerHdlCodeEnabled 1
|
@ o L X T A G 0 pe) - 4 % T l
|
VerboseSamples 0
|
@
|
VerboseDelays 0
|
@ L X T A G 1 y) - 4 % R L A r i a l ishing use. You may not copy or distribute this so re.
|
VerboseFileInput 0
|
|
VerboseSequenceVerification 0
|
If you have any question concerning your rights you should review the license agreement you received with the software contact Monotype for a copy of the license agreement.
|
IncludeDelayTime 1
|
|
ExecuteFromTopLevel 1
|
Mono (% T ` 5 m ,
|
TimeOutInDiagramLengths 0
|
|
DefaultCycleClock Unclocked
|
@
|
DefaultCycleEdge neg
|
@5 L T . . . pe R L A r i a l y p e f a c e T h e M o n o t y p e C o o r a t i o n p l c . D a t a T h e M o n o t y p e C o r p o r a t i o n p l c / T y p e S o l u t i o n s I n c . 1 9 9 0 - 1 9 9 2 . A l l R i g h t s R e s e o % T ` I
|
!
|
@
|
|
@ L T T A G i ) - 4 T O
|
MACROS
|
@
|
!
|
@ O
L ` I C _ S E T S - 1 0 % - - ) - % & % % V 0
|
|
M L
|
CORGROUP $$CLK_I_BufferRising
|
L
|
Percent 100
|
L% ( %
( %
( R L A r i a l o r a r y s a n s s e r i f d e s i g n , i a l c o n t a i n s m o r e h u m a n i s t c h a r a c t e r i s t i c s t h a n m a n y o f i t s p r e e c e s s o r s a n d a s s u c h i s m o r e i n o % ( %
( % % T b
|
!
|
@
|
|
@ L p E F F E C T I V E A D D R E S S l - ) ) - 0 ( - - - 0 0 0 - - - & % % V 0 | l
}
k
k }}
% ( R L A r i a l a p p e a r a n c e . A r i a l i s a n x t r e m e l y v e r s a t i l e f a m i l y o f t y p e f a c e s w h i c h c a n b e u s e d w i t h e u a l s u c c e s s f o r t e x t s e B b % ( R L A r i a l b H d B ( ( h p v x p 4 > . ^ " R B r % ( R L A r i a l B ^ , \ & V 4 d 4 d * ! #0 %` ' )< ) ** * ,r -P .. . / 1 3 3 3 4 4 5 5 5& % ( % R L A r i a l E F G H I K KF K~ K K L
|
CORGROUP $$CLK_I_BufferFalling
|
L0 M Np N N N N O P Q Q R* R R S S T T T W Xl X Y" Z@ Z Z Z [ [ [ [ [ \ ] ^B ^ _ `V a a b b c c d e& fR f % T p o `
|
Percent 100
|
@
|
!
|
@ o L X W o r d 0 B % % % T p `
|
|
@
|
CORGROUP $$CLK_I_BufferRisingFalling
|
@ L X W o r d 1 B % % % % T ` ,
|
Percent 100
|
|
!
|
@ & " WMFC E
|
|
@ L T . . . R L A r i a l < H * h z $ b z B j t <
|
CORGROUP $$CLK_I_BufferRising
|
H æ ( Ɔ ư ǒ B l ˖ @ j ͔ ; < % T I
|
Percent 100
|
@
|
!
|
@ L h W o r d I C _ S E T S - 2 B % % 0 % - - ) - % T O
|
|
@
|
CORGROUP $$CLK_I_BufferFalling
|
@ O
L h W o r d I C _ S E T S - 1 B % % 0 % - - ) - % %
( & % % V 0
|
Percent 100
|
I M
|
!
|
LHLH
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
L% ( %
( %
( & % % V 0 ( M )L
|
Percent 100
|
L
|
!
|
) )L% ( & % % W , . C Z
|
|
QLQ-7-7
|
CORGROUP $$CLK_I_BufferRising
|
% ( & % % W ,
% ( & % % W $ .
|
Percent 100
|
@ d 7
|
!
|
7[% ( % % V , Q ^ ^Q7Q^Q% % V 0 c c c & % % 6 6 6 # 6 ' + 6 / 3 6 7 ; 6 ? C 6 G K 6 O S 6 W [ 6 _ c 6 g k 6 o s 6 w { 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 # 6 ' + 6 / 3 6 7 ; 6 ? C 6 G K 6 O S 6 W [ 6 _ c 6 g k 6 o s 6 w { 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 # 6 ' + 6 / 3 6 7 ; 6 ? C 6 G K 6 O S 6 W [ 6 _ c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c { c w 6 c s c o 6 c k c g 6 c c c _ 6 c [ c W 6 c S c O 6 c K c G 6 c C c ? 6 c ; c 7 6 c 3 c / 6 c + c ' 6 c # c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c { c w 6 c s c o 6 c k c g 6 c c c _ 6 c [ c W 6 c S c O 6 c K c G 6 c C c ? 6 c ; c 7 6 c 3 c / 6 c + c ' 6 c # c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c 6 ` \ 6 X T 6 P L 6 H D 6 @ < 6 8 4 6 0 , 6 ( $ 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 | 6 x t 6 p l 6 h d 6 ` \ 6 X T 6 P L 6 H D 6 @ < 6 8 4 6 0 , 6 ( $ 6 6 6 6 6 6 6 6 6 6 6 & " WMFC % 6 6 6 6 6 6 6 6 6 6 | 6 x t 6 p l 6 h d 6 ` \ 6 X T 6 P L 6 H D 6 @ < 6 8 4 6 0 , 6 ( $ 6 6 6 6 6 6 6 6 6 6 6 6 6
6 6 6 ! % 6 ) - 6 1 5 6 9 = 6 A E 6 I M 6 Q U 6 Y ] 6 a e 6 i m 6 q u 6 y } 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6
6 6 6 ! % 6 ) - 6 1 5 6 9 = 6 A E 6 I M 6 Q U 6 Y ] 6 a e 6 i m 6 q u 6 y } 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6
6 6 6 % ( % R L A r i a l % T d
|
|
@
|
CORGROUP $$CLK_I_BufferFalling
|
@ L T D M M U H S S H & % W , C
|
Percent 100
|
L
|
!
|
% ( & % % W $
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
|
!
|
% ( % % V , =
|
|
|
CORGROUP $$CLK_I_BufferRising
|
=
|
Percent 100
|
& % % V 0 C DDD% ( % R L A r i a l Arial Arial C C MSTT315b3b3a84t Arial `c
|
!
|
:y MS % T d 1 X
|
|
@
|
CORGROUP $$CLK_I_BufferFalling
|
@1 X L T C O M P 0 4 7 - & % W $ q h% ( % % V , o ^ ^o^^ & % % W $ H
Z q Q
Qh% ( % % V , * ^ x x^Q*^x^ & % % W , Z %%c% ( & % % W $ % ( % % V , o o % R L
|
Percent 100
|
|
!
|
A r i a l ?CO MSTT315b3b3a84t # XX> C ' ,f (Q Arial % T l n L
|
|
@
|
CORGROUP $$CLK_I_BufferRisingFalling
|
@ L X H I T 0 0 ) % %
( %
( R L A r i a l Arial Arial C C MSTT316eafa793t Arial IO ?CO % T X
|
Percent 100
|
@
|
!
|
@ L P 3 1 % % %
( R L A r i a l # XX< K C + C (Q % ( R L A r i a l d 4 d * #0 %` ' )< ) ** *: * ,r -P .. . / 1 3 3 3 4 4 5 5 5& 56 5F 6 6( 68 6 6 70 7@ 8: 8J 8Z 9f : : ;
|
|
;@ ;p ; ; < =R >( ? % ( R L A r i a l Q R* R R S S T T T W Xl X Y" Z Z Z [ [ [ [ [ \ ] ] ^B ^ _ `V a a b b c c d e& fR f gX gh iz j k k m o o o pR pb pr p p rr r s s tp u^ % T ` : }
|
CORGROUP $$CLK_I_BufferRising
|
@
|
Percent 100
|
@: L T l o g R L A r i a l < ` p B p 2 ~ H L 4 d ( . f ( 2 < H * h % T T ~
|
!
|
@
|
|
@~ L P 2 R L A r i a l B м ( R | Ҧ P \ ך & l 8 > ^ 0 Z , V & " WMFC ( R | & P P V
|
CORGROUP $$CLK_I_BufferFalling
|
@ % T
|
Percent 100
|
@
|
!
|
@ L d ( I C _ S E T S ) + 4 $ ! ! ! %
( % T T A
|
|
@
|
CORGROUP $$CLK_I_BufferRisingFalling
|
@ L P 4 % R L A r i a l 7 8` 8p 8 8 : : :( :8 ; < = > A B C D D E F HX Hh I J L L L L M N N N O O P P R R R R R S U> Vj Wt W W Y2 Z [ [ ^0 `z c eh g jb l2 m % T T h
|
Percent 100
|
@
|
!
|
@h L P 3 % R L A r i a l u2 u\ u u u v v. vX v v v w w* w~ w w w x& xP xz x x x y" yL yv z zZ z z {$ {N {x { { { | |J |t | | | } }F } } } ~ ~B ~l ~ ~ ~ ( \ x z J . % T T
|
|
@
|
CORGROUP $$CLK_I_BufferRising
|
@ L P 0 % R L A r i a l 6 ` . x H R d r f , ` B
|
Percent 100
|
P Z & L ~ f " v & N % T l
|
!
|
@
|
|
@ L X W A Y 0 O 9 8 . &
|
CORGROUP $$CLK_I_BufferFalling
|
%
|
Percent 100
|
% V 0 G * M HL)L) H HL% (
|
!
|
%
( %
( %
( % R L A r i a l serif faces. Terminal strokes are cut on the diag which helps to give the face a less mechanical appearance. Arial is an extremely versatile family of typefaces which can be ed with equal success for text setting in reports, presentatio u% T T "
|
|
@
|
CORGROUP $$CLK_I_BufferRisingFalling
|
@ L P 2 ht% %
( %
( R L A r i a l ype Z & L ~ " v & N 4 f @ n ( ^ 0 ` > j 8 p 2 b % T T I m
|
Percent 100
|
@
|
!
|
@I L P 1 ec% & % W ,
|
|
C L::% ( %
( % % V 0
g g
g
g % R L A r i a l versatile family of typefaces which can be used w equal success for text setting in reports, presentations, magazines etc, and for display use in newspapers, advertising and pr otions.http://www.monotype.com/html/mtname/ms_arial.htmlhttp:/ el% T N
|
CORGROUP $$CLK_RISC_BufferRising
|
@
|
Percent 100
|
@ N L d W O R D S E L E C T bB 4 0 0 - - % - 0 ) & % W $
|
!
|
% ( % % V , : :: &
|
|
% % V 0 z% ( &
|
CORGROUP $$CLK_RISC_BufferFalling
|
% % V 0 zz% ( & % % W $ 2 @ ))7% ( % % V , . P P.).P. & % % W $
% ( % % V ,
& % % W $ 2 )% ( % % V A 9 #&)+.1368:<>?@AAAAA@?><:8631.+)&# & % % W $ 2 ))% ( % % V , P )P% % V , P P)P%
( R L
|
Percent 100
|
|
!
|
A r i a l e s i g n , A r i a l c o n t a i n s m o r h u m a n i s t c h a r a c t e r i s t i c s t h a n m a n y o f i t s p r e d e c e s s o r s a n d a s s c h i s m o r e i n t u n e w i t h t h e m o o a % ( %
( % R L
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
A r i a l i s s o f t e r a n d f u l l e r t h a i n m o s t i n d u s t r i a l s t y l e s a n s s e
|
Percent 100
|
! " # % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o r s t u v w x y z { | } ~ r i f f a c e s . T e r m i n a l s t r o k e s a r c u t o n t h e d i a g o n a l w h i c h h e l p e % T e \ 8
|
!
|
@
|
|
@e \ L d T O / F R O M C P U e ) 4 ) 0 4 7 0 - 0 T K L
|
CORGROUP $$CLK_RISC_BufferRising
|
@
|
Percent 100
|
@ L p T O / F R O M E X T E N I / F r ) 4 ) 0 4 7 - + ) - 0 ) & % W ( C ^ LU% ( & % % W $ L i U`% ( % % V , W WW W % R L A r i a l # XX< K ' C + C (Q Arial Arial C C % T d g
|
!
|
@
|
|
@ L T B Y T E - - ) - T x w F
|
CORGROUP $$CLK_RISC_BufferFalling
|
@
|
Percent 100
|
@w F L \ S E L E C T S - - % - 0 ) - %
( %
( R L A r i a l # XX< K ' C + C (Q Arial % ( R L A r i a l al IO ?CO MSTT315b3b3a84t # XX> C ' ,f % ( R L & WMFC A r i a l ,, u Q 4 2r d 2 2 d r-% T ` G
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
@
|
Percent 100
|
@G
|
!
|
L T l o g X R L A r i a l XXXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX % T T
|
|
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
@
|
!
|
@
|
|
L P 2 R L A r i a l % ( % T
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
@
|
!
|
@
|
|
L d ( I C _ S E T S ) + 3 $ ! ! ! F . - C Arial ? ? ?? ? ? ? - 2
|
CORGROUP $$CLK_I_BufferRisingFalling
|
QW SET 0 - - ) % 2
|
Percent 100
|
W SET 1 - - ) % C Arial ? ? - 2
|
!
|
... C Arial ?? ? - 2
|
|
1
s SET - - ) 2 Arial - 2
|
CORGROUP $$CLK_RISC_BufferRising
|
r
6 IC_SETS-1 $ ! ! ! - - $ p
2
2pp
- C Arial - C Arial ????????????????????????? - C Arial ????????????????????????? - C Arial ????????????4???????????? - - C Arial ????????????????????????? - 2
|
Percent 100
|
o TAG 0 ) - 4 % 2
|
!
|
TAG 1 ) - 4 % C Arial ???????5???4????????????? - 2
|
|
5 ... C Arial ypeface The Monotype Co - 2
|
CORGROUP $$CLK_RISC_BufferFalling
|
TAG ) - 4 2
|
Percent 100
|
O
IC_SETS-1 0 % - - ) - % -
|
!
|
- $ L
|
|
L
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
L -
|
Percent 100
|
"System c č ρ -
|
!
|
-
|
|
C Arial orary sans serif design, - -
|
CORGROUP $$CLK_I_BufferRising
|
- - ! 2
|
Percent 100
|
EFFECTIVE ADDRESS- ) ) - 0 ( - - - 0 0 0 - - - - - $ }
k
k }}
- C Arial appearance. Arial is an - C Arial ? ? ? ? ? ? ? ? ? ? ? ? ? - C Arial ?A?A?A?A?A?A?A?A?A?A?A?A? - - C Arial ?A?A?A?A?A?A?A?A?A?A?A?A? - 2
|
!
|
o Word 0B % % % 2
|
|
Word 1B % % % - 2
|
CORGROUP $$CLK_I_BufferFalling
|
... C Arial ?A?A?A?A?A?A?A?A?A?A?A?A? - 2
|
Percent 100
|
Word IC_SETS-2B % % 0 % - - ) - % 2
|
!
|
O
Word IC_SETS-1B % % 0 % - - ) - % -
|
|
- - $
|
CORGROUP $$CLK_I_BufferRisingFalling
|
LHLH
|
Percent 100
|
|
!
|
L - -
|
|
-
|
CORGROUP $$CLK_RISC_BufferRising
|
- - $ )L
|
Percent 100
|
L
|
!
|
) )L - - - % QLQ-7-7
|
|
- - - %
- - - % 7
|
CORGROUP $$CLK_RISC_BufferFalling
|
7[ - - - $ ^Q7Q^Q - - $ c c - - # ' + / 3 7 ; ? C G K O S W [ _ c g k o s w { # ' + / 3 7 ; ? C G K O S W [ _ c g k o s w { # ' + / 3 7 ; ? C G K O S W [ _ c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c {c wc sc oc kc gc cc _c [c Wc Sc Oc Kc Gc Cc ?c ;c 7c 3c /c +c 'c #c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c {c wc sc oc kc gc cc _c [c Wc Sc Oc Kc Gc Cc ?c ;c 7c 3c /c +c 'c #c c c c c c c c c c c c c c c c c c c c c c c c c ` \ X T P L H D @ < 8 4 0 , ( $ | x t p l h d ` \ X T P L H D @ < 8 4 0 , ( $ | x t p l h d ` \ X T P L H D @ < 8 4 0 , ( $
! % ) - 1 5 9 = A E I M Q U Y ] a e i m q u y }
! % ) - 1 5 9 = A E I M Q U Y ] a e i m q u y }
- - d Arial ? ? ? ? ? ? -
2
|
Percent 100
|
DMMUH S S H - % L
|
!
|
- - - %
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
- - - $
|
Percent 100
|
=
|
!
|
- - $ DDD - - C Arial ??? ?????? -
2
|
|
X1 COMP0 4 7 - - % h - - - $ ^o^^ - - % Q
Qh - - - $ x^Q*^x^ - - % %%c - - - % - - - $ o - C
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
Arial ???? ? u ???????t - 2
|
!
|
HIT 0 0 ) % -
|
|
-
|
CORGROUP $$CLK_I_BufferFalling
|
C Arial ? ? ?????? -
|
Percent 100
|
2
|
!
|
31% % -
|
|
! Arial - 2 Arial ?A?A?A?A?A?A?A?A?A?A?A?A? - 2 Arial ?A?A?A?A?A?A?A?A?A?A?A?A? - 2
|
CORGROUP $$CLK_I_BufferRisingFalling
|
: log ! Arial ?A?A?A?A?A?A?A?A?A?A?A?A? - 2
|
Percent 100
|
~ 2 2 Arial ?A?A?A?A?A?A?A?A?A?A?A?A? - 2
|
!
|
(IC_SETS)+4 $ ! ! ! -
|
|
- 2
|
CORGROUP $$CLK_RISC_BufferRising
|
4% C Arial ????????????????????????? - 2
|
Percent 100
|
h 3% C Arial ??????????????????????w?? - 2
|
!
|
0% S Arial ????????????????????????? -
2
|
|
WAY 0 O 9 8 . - - $ HL)L) H HL - -
|
CORGROUP $$CLK_RISC_BufferFalling
|
-
|
Percent 100
|
-
|
!
|
- C Arial ???????????????????????? - 2
|
|
2% -
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
-
|
Percent 100
|
C Arial ??????????????????????? - 2
|
!
|
I 1% - % L:: - -
|
|
- - $ g
g
g - C Arial ????????????????????????? - 2
|
CORGROUP $$CLK_RISC_BufferRising
|
N WORD SELECT B 4 0 0 - - % - 0 ) - % - - - $ ::
|
Percent 100
|
- - $ z -
|
!
|
- - $ zz - - - % ))7 - - - $ P.).P. - - % - - - $
- - % ) - - - v $9 #&)+.1368:<>?@AAAAA@?><:8631.+)&# - - % )) - - - $ )P - - $ P)P -
|
|
C
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
Arial esign, Arial contains mor - -
|
!
|
- C
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
Arial is softer and fuller tha - 2
|
Percent 100
|
\e TO/FROM CPU ) 4 ) 0 4 7 0 - 0 ! 2
|
!
|
TO/FROM EXTEN I/F) 4 ) 0 4 7 - + ) - 0 ) -
|
|
% LU - - - % U` - - - $ WW W - C Arial ???< ? K??? -
2
|
CORGROUP $$CLK_RISC_BufferRising
|
BYTE- - ) - 2
|
Percent 100
|
Fw SELECTS - - % - 0 ) - -
|
!
|
-
|
|
! Arial - 2 Arial ? ? - 2 Arial - 2
|
CORGROUP $$CLK_RISC_BufferFalling
|
G
|
Percent 100
|
log ! Arial ????????????????????????? - 2
|
!
|
|
|
2 2 Arial - - 2
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
(IC_SETS)+3 $ ! ! ! Visio (TM) Drawing
|
!
|
:N TH L R l ! fff MMM 333 $
|
|
$
|
CORGROUP $$CLK_RISC_BufferRising
|
U38@ Td Arial@N Wingdz s@N@tMonotype Sort+
N tSymbol 5T?? Y@ - 1 U J:D T1EW-hT T< *
|
Percent 100
|
/U b
bO 0zGz?@8@H2!kWb*U
|
!
|
+$ PL/^&9^$? { Ak^&,,'%/v&& *
|
|
1y
) P? 2
U
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AsVsVA!gLTkY W_W__ !`# k4l b6u`kW *4l
|
CORGROUP $$CLK_RISC_BufferFalling
|
4l %Y?P:?-\
#!+|QtKf2|2|2|I2wGQ A UoTMeE$ttA%_ 8BOTOfOxOO??HO?7ܻ XuW?YsU42
|
Percent 100
|
T*
|
!
|
x x x
|
|
0jPvȲl^/!3jBj6D///$Q 0p?Mdj^cj4Ak[~ϐ$YkU1% 1F-(kp
ٻ A. $5-B i`# 9)F/Pv// ߾/u?2trߜKS52 7xߢ#6@h$MuLh Ճ %ԊՑ ) <OU # 5 G ::U2 q ?/&w&
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
<<7H 1O QjP SH QywH At///Y OG$_ p4b%F! 8q/#P?C/N^qhE! @d)n{r1P1 @ /Oqt}Q!n =k@Ʊ셩{B'ɂXVP_0TNJg21 1R5P"QQ[O" P!q[rr qqӂqq¢ӁӁP¡¡Waa7$VW7P$q"$qP1q1qP>q">qPKqKqPXq Xq2eqeqZ2Sob ZZdSTQcd PQQ P1H[<k?ta}Y M/OO*Dd3qO/NkS\O 9E/ / _ ? ?-??=___ѷ'sϖdI,O 0R 7nO&ګa ̗ѫaW?O // ?*
|
Percent 100
|
K ϥϷϾCNa \ "4FXj ߲K߳ BTf_/q/ //, ڭaRdv *<+/`bbiA nFUj?|?~/ "C??Va]? Ia(G
|
!
|
rpl/YDE@a1LO pO #Q/I SGQۍBQfQaIq_Uyj ( ȄBb_(_:_/^_ //Q__a1 _ OO-OF ZO Qo~MA %o C AOOMgy N_r_O7 Zg @ :o,Ko -XyCŮbddpddp A͟ߟ'@9K]vAB(Onl=# ??6HZl Ǝ' ;M_q 2DV hzόϞϰ
|
|
.@Rdv ߚ߬߾#} (:L^p Uɑۏ"4FXj@|X *<N`r & 8 J \ n Y / ///A/S/e/w///F/L// ? ?$?6?H?Z?l?~?? ?????? O"O4OFOXOjO|O OOOOO _ _ 0_B_T_f___ _____oo'o 9oKo]oFxoOoo oooo,>PPfx ,> nBsgcEf Ώ (ٴJ\n ȟڟ" OeOj|@į֯ ( :L^pʿܿ B#vXT+Sb b z @v 6M_Toρ6 ϱi -?Qcu ߙ߽߫ ϭ, /-?eY[Ưy +=Oas 1ńR Z sc<Ɠ`Zl~ sb6-1R# # 5 G Y k } x;6/ F%/jI/[/m////) ////
|
CORGROUP $$CLK_RISC_BufferRising
|
? ?.?@?R?d?v??? YTV
|?bO 2ODOVOzOaq OOOOOO_ !_3_E_W_i_{___ _____ o o/o Ao}x^oK Acrobat Distiller o d 7X X6 $)/@o .0 ²r
|
Percent 100
|
dt ' 9 K ] o Custom ?page 0 ,/FBN#/#1>//?/Q/
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h> / T6DUmA@
?ۿI? Y{O1@3 EE b O e Z
|
!
|
Hu P (: { W_q QGeneric box with text and connection points. Can be stretched to y dimwens s. mb?贁No ? k? 4
HDD
$# =h-(>TTE=UA??Q6 u ` 6u mB> 00 0 (2s@sJs&T> 5
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|
|
<h b
261
|
CORGROUP $$CLK_RISC_BufferFalling
|
g,s724?`b?M1^%Y? r? 91M1E; 6==5(2?;zrA
|
Percent 100
|
IB=OCq ,^35/rV:?@F AC MAOMOO@ _2A#[ 6OMZM"3A^%\ $___Z__B#[@ o_9Bo[(
^text Hl& ' ! Oya GEF # o JB
|
!
|
j] \a\k _ @ +dk 3ak I k % Ul4,_j @%@ ] A-3 c7 "A % Ul4,_j @%@ | A-3 7U~}@L eFR0BTf*
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|
|
H<(
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
U~E ,
R0BTf
, 9 UFDf
h - TUU [U@@??I?`d
buoqYkQhu23u` Connector
|
Percent 100
|
`
|
!
|
e1 C rw
|
|
UH ^ -}|5 p`I` V ?}`xa 833 ސ ] 3σ3 u 33?, ? Gxpx ^ &
CThis connector automatically routes between the shap i
ts.b?贁N ? HD
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|
CORGROUP $$CLK_RISC_BufferRising
|
u
|
Percent 100
|
`u# `b A @u
J .Q# DB # ։u `h?U\hr|Su Za { @-?bHl;'b E-ho' y(
|
!
|
2r q ?@I k?$%?
|
|
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|
CORGROUP $$CLK_RISC_BufferFalling
|
#145 `Vis_SBl.chm!#22474 `7Copyright 1999 @io Corporation. All $AUd3 CE \^ 4
|
Percent 100
|
*L 1$b 24R(^[w[D ZQi a59 93O ' 2"q?/g;2GHls ' $ ! Oya GEӧF y # G 7 B
|
!
|
L ~$ dro @ +Ik "sk 5o ( S J + B ?9 = 3R D FPi{" / | UPx P4FD Tey
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|
|
` *"
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
*e3a$$$ !aU !
*U6$ U!"#'U()*+,-2!+1H<47 47 "7 !7 4a71817 18171817 47 18 17 !8!7'18'17 +18/17/18317318:718?17 ;18G17?189!78 :G18W17 K18_17O18c17@9!87W18%:4&:_18k17 c18o17g18s17k18/Go180:s181:w18 17{18!7184:185:18U 68P31qq11W1W1 !g1g1a!!19a9a1!! 1VaVa![q[q/1w1w1?1119a.Eo1aa1qq[q1iEiaZC< 1|ZE !!E !5)E:m@@|_=$@2п2?p! {1H-J21a2P?1v<Do1<<< [?l 1a UU1=E/
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Percent 100
|
2ضVhz0 !4Q\a q'?k? A|0ΟT /ASew% ȯ 0BTfx ƿ 꿵 \ &/@& yD/ c/χ//%8TAG 0
|
!
|
v"11
|
|
-6...-7"0
|
CORGROUP $$CLK_RISC_BufferRising
|
IC_SETS-1e5qU3
|
Percent 100
|
# 2|U?: Y}8 38 `7״߆J!߃qqE?qq`kq;OMO55BUQZ1@Rua s`?r?% +=(qVfpoT}9 eQ+=Oas ! | f 0 B T f x /h / j Vo(
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!
|
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|
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|
CORGROUP $$CLK_RISC_BufferFalling
|
B (s sH1L%OO¯ ԯ92I7[ /: L~ވߖ! q,>Pbt[& ,gHwɮ1u)Q!2 EygP-DT![->}b x@"1xyv rr
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Percent 100
|
srrhߠ(: qLٸ x=
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0Œ!e qRRbA]4q9CT*r$U, / Ǥa13;o g;5nDE28Q""\U3,\R.H/Z$qQ#lF U0O3kR(}p0q3&\SNS Z,T;OZ?g?aaUpiDMMUh٥2yߋߝQdFo rQ-Q-Qak F(_T%k,'o Bo'%onooR[ OoXlOU _#G5 arԚ"پ 1%fQ`oђ{ s'%TzU/itϡϗy{' 2U
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|
͂ůM " ߄@]?755a4~}a9^"=:mӆ@@|= ħC
|
|
V<x!2 6i$ pxCv' u@˨+E秜(OS
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
2r q ?@I0?&. g`|L'%&;H )2A' *â "ux1 B P`0 #!X+/=-xBBOTlbъQji_y|@՜//o)m 9'[
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Percent 100
|
,z9{g ߊy
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!
|
:bc]STf g
|
|
Ϳ/ , +a/s/// ////o ':O 8?yTq <%L%@,Q 43
|
CORGROUP $$CLK_RISC_BufferRising
|
53Iρ 76(e2T ! OLG 2(q??6T+? 8Ugd | ߝ $8 ~K& O0M,OO ߣ;_ONw_O_^9~ESET 0
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Percent 100
|
,a1
|
!
|
7f...7g1bIC _,`S-1pPA v/*TAUɁ3ԃ bU<aon cƄPoiɇgju(}d74 !3r Av vu?`Րkr]$ZWB /x$% >Ke= LA6l-E*?@E_$ %3غ33?QO)pvE1? .'ICƗaPVTٟ?{O+O=O OOaL rI_ I{AE@{۪eq^h obILJ< <ªyvE ֳ9y[' ysSϞsA%ܵ!hCOMPYeZ累~I/m/ro/%P-DT!FXj| ?$?$
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|
29/
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|
CORGROUP $$CLK_RISC_BufferFalling
|
_ ]pQ0[; ?zԀ 0]Yk) }`Vƙ
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Percent 100
|
C|`u S
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!
|
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|
|
v@Yd!Y0:R%;\O %U2 ߧȹE*%$U^Q|+|"(9 &)|A2Q !|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
ꌠ
|
Percent 100
|
S
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!
|
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1 (Ģs]٪_X3 EoI {ƨ`+o ";1
|
|
*2߿U[tcw1 qgy膟~WbvH/Omi%2Mr>17lr b.oooooo -?xPp|(Tfxu(2 1@{N,AS ewя 2+6$K ]ɟz #5Gk}Gৡ_a!$@ͭ>1 m9ODž9D6i@@I?@SC]SBzw8B,(@b_Sƍ_S(A,)3e Xp:_eŃ!@ F1!?pMX !vÔܯC?U?g?y?;&G
|
CORGROUP $$CLK_RISC_BufferRising
|
@@S 95@G???? O O0O0BOTOvxOv,(&O#` L@%E_ F(&'''T/.(&'-7'/l_~_Ua______ o oKoVo4G ?g1 " @:m @@" /{RNuhh` &1v /
|
Percent 100
|
8A,VA*OAe L@)3RpA :g kP@z3[Q4b:oLn{#@VgW$onV gmWo??U><+N?¬SAczre?w?????? ??wX.GC>O >iEWOGE<4yl`
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!
|
zr?yAM lh ]hMZ R7Yf@DzVtC᪡q-B)F o̕ ?qzI2r q fEI7,X7S@CVQrE5&YxyBqE"4zvP;3M4) kPp` A1I?ǣAu<CY4ԿCjq,w|;@KE}|tS>u7ϐ6͕$ ]f?m۶m|; ݩϻϼVeX`` MO_OqOOOOOOٓ/?@^X_r =_O_a_s__0____?,)A/I?_eO?y%@$ASTԯ,8
8?(\? ٿ<P
|
|
yC'TO/FROM CPU
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
EXTEN I/F FȁCȁ~d @Ə؏C @@|W=i$E J Tf@l艙l&C ( )o$@ 4b phe&Po/.f'(<{"77
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|
!
|
|
|
SELECTS U> U#$%&U*-.0U1234 Ul4,_j @K%@ DC- T7 AU2@$ ZD7 JR H<(
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
U2El D7
R UlL O( D @ ?,% ) R- ) < ;U$
|
Percent 100
|
4( U1( UO"D&aU=QJf )h" Ty+Uv' _ Ʌ &aQ-
|
!
|
- H* 9( TYg EQ /, Guide TheDoc Page-1 Gesture Format Block Normal Visio 10 Block Shadow Visio 12 Block Highlt Visio 11 Connector Visio 90 Dot Connector Connector Arrow Visio 00 Visio 01 Visio 02 Visio 03 Visio 13 Visio 20 Visio 21 Visio 22 Visio 23 Visio 50 Visio 51 Visio 52 Visio 53 Visio 70 Visio 80 Box Box.3 Box.4 Box.5 Dynamic conn?ector Dynamic connector.10 Dynamic connector.23 Box.37 Dynamic connector.40 Dynamic connector.50 Dynamic connector.52 Box.2 Box.9 Box.13 _ 53 E
|
|
E F
-
|
CORGROUP $$CLK_RISC_BufferRising
|
R - G U0- A- }
Nc
|
Percent 100
|
U, _u
|
!
|
D lQ
|
|
U\ u
|
CORGROUP $$CLK_RISC_BufferFalling
|
t - U u
|
Percent 100
|
U- U - UUԃ u
|
!
|
}u
|
|
u
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
7Gv 47ML7 Md7*M|77M7DM7QM7^M7kM7xM M$M<MdcM ATM d7*l7*t7*|I**I*MM UH8)** 'W :* 0>*$ 0B 04 0M:T 0l*\ 0p:| 0: 0 0: 0TE63*(! 0 xfR! T! !"# !%&'()*+T-./U0124 UjU
|
Percent 100
|
U
UUU Ul4,_j @K%@ L K UUC-<3 q7 A Ul4, K
|
!
|
AJ- 3 7 A _ *<N@ wK LRVg q 6uH<(
|
|
H<(
|
CORGROUP $$CLK_RISC_BufferRising
|
_ *<NE KL
RVg Xq >={ z
|
Percent 100
|
* g"4pFX (r@(ja@2y
|
!
|
JlO :]R
|
|
TQ U#u &T !B }U ?Q
>4YC O 9B m `O y Nfi$S f'D ON4_ >E)UdG1UW=` 2L H EV
|
CORGROUP $$CLK_RISC_BufferFalling
|
O?
L F e5 C=| 5 J!_k 5 @ Oh +'0 @ H h t Valued Sony Customer G (E x w
|
Percent 100
|
w
|
!
|
EMF E X V I S I O D r a w i n g M D ? ? l ( @ ( ʦ " @ H P \ h t
Pages Masters Page-1 Box Dynamic connector 8 _VPID_PREVIEWS _VPID_ALTERNATENAMES @ _PID_LINKBASE ÿ A 8h
& >WMFC x - 8 h EMF u X V I S I O D r a w i n g
|
|
o
& % % V 0 -
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
0
|
Percent 100
|
|
!
|
0
0
|
|
% ( % R L A r i a l Custom page 0 B B % T ` h
|
CORGROUP $$clk_risc_BufferRising
|
@
|
Percent 100
|
@ L T C P U 0 - 0 & % W $ # % ( % R L T i m e s N e w R o m a n % T T 2
|
!
|
, P
|
|
|
CORGROUP $$clk_risc_BufferFalling
|
@
|
Percent 100
|
@2
|
!
|
, L P / %
( & % W $
|
|
E s K
|
CORGROUP $$clk_risc_BufferRisingFalling
|
Hp H% ( % R L A r i a l % T
|
Percent 100
|
2 ]
|
!
|
@
|
|
@
|
CORGROUP $$clk_risc_BufferRising
|
L d B r e a k p o i n t s - % % " % % % " % % V , e ' o e o He 'e o & % % V 0 ! $ $ $ % ( % R L A r i a l % T ` v i
|
Percent 100
|
|
!
|
@
|
|
@ v L T D M R 0 7 0 & % W $
|
CORGROUP $$clk_risc_BufferFalling
|
|
Percent 100
|
S
|
!
|
|
|
P% ( & % % V 0 % ( %
( % R L A r i a l % T ` k !
|
CORGROUP $$clk_risc_BufferRisingFalling
|
@
|
Percent 100
|
@ k L T D S R 0 - 0 & % % V 0 ! $ $ $ % ( %
( % R L A r i a l * < ( L ^ p 0 6 ` . x H R d r , ` B
|
!
|
P % T ` k e
|
|
|
CLOCK clk_risc
|
@
|
PERIODE 1
|
@ k L T D R R 0 0 0 %
( & % % V 0 6
|
DUTY 50
|
|
OFFSETE 0
|
|
INITIAL LOW
|
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|
MAXUNCERTRISE 0
|
@
|
MAXUNCERTFALL 0
|
@ L d B r e a k p o i n t s , - % % " % % % " & % W $ & ##% ( g
. - - $ 0
|
MINUNCERTRISE 0
|
|
MINUNCERTFALL 0
|
0
0
|
JRISEE 0
|
- - C Arial - 2
|
JFALLE 0
|
CPU 0 - 0 - % # - - n Times New Roman - 2
|
GRID 1 1 1 2 2 16711680 0 0
|
,2
|
ENDGRID -1
|
/1 "System ! x x - - %
|
DIRECTION input
|
Hp H - - C Arial - 2
|
MASTERCLOCK None
|
|
Clock Unclocked
|
Breakpoints - % % " % % % " - - $ e o He 'e o - - $ $ $ $ - - C Arial - 2
|
EdgeLevel neg
|
v DMR 0 7 0 - %
|
Set Not Used
|
|
Clear Not Used
|
P - - - $ - - - C Arial - 2
|
ClockEnable Not Used
|
k DSR 0 - 0 - - $ $ $ $ - - - C Arial ????????????????????????? - 2
|
ActiveLowSetClear True
|
k DRR 0 0 0 - - - $
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
9 9 - - C Arial ????????????????????????? - 2
|
VhdlType std_logic
|
Breakpoints - % % " % % % " - % ## -
|
VerilogType wire
|
F Microsoft Visio Drawing VISIO 6.0 Shapes Visio.Drawing.6 9q ՜. +,D ՜. +, @ H P \ h t
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|
SystemCType sc_logic
|
0 TH g/ R t ! fff MMM 3?33 V$
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
$
|
StateEquation Hex(Inc(0,2,5))
|
U38@ Td Arial@N Wingdz s@N1 Courier WNew@N Times _Roman@Q @tMonotype SorUt+
N tSymbol 5T?? Y@ - 1 TJD T1EWP-hT T< U*U
|
HighVoltageThreshold 5
|
U
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LowVoltageThreshold 0
|
+ PL/^&9^$? { Ak^&,",'%/v&Q&
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MSB 0
|
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LSB 0
|
4l %Y ?:?-\
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|
isFallingEdgeSensitive False
|
T *
|
isRisingEdgeSensitive True
|
x x x
|
DrawAnalog 0
|
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BooleanEquation
|
.@ Rdvk }*
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NegTolerance 0
|
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PosTolerance 0
|
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UserSpecifiedSizeRatio 1
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VerilogCode
|
6/H/ Z/l/~////// //? ?2?D?V?h? z????= /8
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VHDLCode
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PROPS!
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E5 1 2500 2500 1 0 DR 0
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E6 0 3000 3000 1 0 DR 0
|
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|
d(y #e>
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SIGNAL dbg_adr_i
|
˞$6H~`i~m Ac虯 Է++A3ӱ=c֜OO@OO R R_P0_-_?_Q_UO`0W%PP$
ad_ k1 'oܲ{oPaPm kPe !3gTadl Ta:Q`۱-5G
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DIRECTION input
|
}ş4U@g Yk} :{?O@ $ \KzFLI կ/ /ASew .M_qad/aܨZmi01?35) ; M _ NN, - m^>? l&Y !!sF O#/5/G/Y'/d/v//////+1//?"?4?F?X?j?|?ad;AՋ,ڣ ????r #O5O =߳Сj' ; Q!vOOFOO OY/
|
RADIX hex
|
_ _._@_R_d_v_ 4_______ ooњ>@@?I%qDoVohozoooooo yX`^o nd@ܳ )+=as tC H
ɷ5VۼA@SeY.Y( ]LYYNџm]$CK@@t?@hmLH ㈐,> b OR/$Gnz뎟 x#dmZȡg\ |ߎߠ߮߄ %
1ˑ|ה2 qUЬ?Tf֯?\.>H$U m{{U*c ՠ%2BreakpointsAJ\n!#sۚfԼ>С6Ь@׀ זf;kI@@}{x?@!)Q`nĿֿ迍8η})< DC1t w9 SRuχ@ØϪ @'EX,vo݈ U 2TY ) 0Q d);; -| L/ /`- /.С7
|
GRID 0 1 0 1 0 16711680 0 0
|
.@y]o&:`@@xY?@8O 8ߺkuy JEq! ?B$=!J GDV z
|
ENDGRID -1
|
3 JF CUgy
^F 2 D V h z X) /mܫF!IiF O/+/=/O/a/s////// N c/
?18ȯWVI
|
Clock Unclocked
|
@@Jc ?@be6tdKe¿????E1W%e ,O e,MVFO җ;QHv (f_L8rssnπϕϧϹ@0 UqqHaQ 9q #^r"vb |iA AbbVcJ`sTۓ 45MeΏXU b=b
|
EdgeLevel neg
|
]pd_8Q__ =O____o>&9o Ko]o#oooh@1 }n/G);M q %7I ˟ݟ, Eiq RS+as9nJo˯ݯﯨߺ7I[p&4$OmI &˿ ?%π7I[mϑϣ VP b t P //$/6/H/Z/l/~//h>u~/1y vV/?_&?8?J?\?n??????? W?OO%O7OIO[OmOO;@@R֓HRrG~qOOO__&Y Wmg9_ SlV]@uj!a_ _I____
o o1oCoB_apo Ul4,j @FuK@ < t) UA-3 z7 ;U2@d )7 IR H<(
|
Set Not Used
|
U2E )7
R UlL 4 c) @ ?% ) R+ D$ ;U$
|
Clear Not Used
|
4( U1( UO"D&aU=QJf )h" Ty+Uv' _ Ʌ &aQ-
|
ClockEnable Not Used
|
- H* 9( TYg EQ /, Guide TheDoc Page-1 Gesture Format Visio 90 Connector Visio 00 Visio 01 Visio 02 Visio 03 Visio 10 Visio 11 Visio 12 Visio 13 Visio 20 Visio 21 Visio 22 Visio 23 Visio 50 Visio 51 Visio 52 Visio 53 Visio 70 Visio 80 Basic Basic Shadow _ h 3 %+
|
ActiveLowSetClear True
|
UE, / _ :-
|
AsyncSetClear True
|
; E G ]
_ j 4_ xc
|
ActiveLowClockEnable True
|
L_ c
|
VhdlType std_logic
|
d_ c
|
VerilogType wire
|
|_ c
|
SystemCType sc_logic
|
_ c
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
_ c
|
StateEquation Hex(Inc(0,2,5))
|
_ c
|
HighVoltageThreshold 5
|
ܪ_ c
|
LowVoltageThreshold 0
|
_ c
|
LSB 0
|
c
|
MSB 31
|
$%Zc
|
SignalActionType 0
|
<%,d T%UMl%!M%U.M%;M%UHM%UM%bM %lM^ }MAL [U D 0 fx)U^U
|
isFallingEdgeSensitive False
|
U
UU Ul4,j @FuK@ - KC-3 . A Ul4, T h.
|
isRisingEdgeSensitive False
|
A>- r7 A _ *<N@$ . MRVgP tq 7uH<(
|
DrawAnalog 0
|
H<(
|
BooleanEquation
|
_ *<NEl .
RVgP q Pt{
|
NegTolerance 0
|
* g"4pFX (F<@(Xϊqc 2y
|
PosTolerance 0
|
K R :WR }O
|
UserSpecifiedSizeRatio 1
|
P 4# &S J!B oT k >C 1w F } k `s} L n% $Uy' * ON kT)<tU1|=_` 2, k EV ? .tD / C= NG
|
VerilogCode
|
OJ!jg aG @ Oh +'0 @ H h t Valued Sony Customer G > x a 8 h EMF > X V I S I O D r a w i n g
|
VHDLCode
|
d & % % V 0 7 7 7 7 % ( % R L T i m e s N e w R o m a n % T ` Q ~ 7 A AQ L T C P U & % % V 0 / / / /% ( % R L T i m e s N e w R o m a n % T / A A L p I n s t r u c t i o n C a c h e
|
PROPS!
|
|
E0 X 750 750 1 0 DR 0
|
|
E1 V 1750 1750 A20 1 0 DR 0
|
& % % V 0 G . a G aa.G .G a% ( % R L T i m e s N e w R o m a n '
x x 9 # (R om% T s I a A As I
|
E2 V 3750 3750 A100 1 0 DR 0
|
L ` D a t a C a c h e
|
E3 X 5750 5750 1 0 DR 0
|
|
!
|
& % W $ % 6 % % 6 % % ( % % V , , % , & % % W $ g 6 g " g 6 g "% ( % % V , ` o / ` g /o ` & % % W $ B " B "% ( % % V , 6 E E 6 E E % % V , / / % R L T i m e s N e w R o m a n ' x x 6 dP Courier N % T l A A L X I F E A
R L T i m e s N e w R o m a n ?[@ ?[ [ >[2[6[ 7[ '
x x 9 % T d A A L T L S E
R L T i m e s N e w R o m a n c,,y MMH ,,,,,,,,,,HHH,c
|
|
,A
|
SIGNAL dbg_dat_i
|
|
DIRECTION input
|
cc,M,,,,,, ,,,,M,NNH, ,M,,MM % T T A A L P A %
( R L T i m e s N e w R o m a n 8 8 2 8 8 7 8 2 8 8 8 7 ! 2 8 1 G 1 1 1 ' x x 1 " Q ew% T x A A L \ L S d a t a
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
& % W $ % % % ( & % % W $ g g % ( & % % W $ % ( & % % V 0 a 7 7 a7 a 7 % ( %
( % R L T i m e s N e w R o m a n (R 9 Times New Roman Times New Roman % T ) X A A A ) L ` D V R 0 / D C R 0 & % % V 0 6 X X X 6 6 X % ( %
( % R L T i m e s N e w R o m a n % T J y b A A J L ` D V R 7 / D C R 7 & % W $ . p p . % ( & % % W $ > > % ( & % % W $ W W % ( & % % W $ > W > > >W % ( & % % V 0 . . . % ( & % % V 0 . O . OO . . % ( & % % V 0 ( ( ( % ( % R L T i m e s N e w R o m a n ,UE ^? T? > % T X A A L P W P %
( R L T i m e s N e w R o m a n V I S I O D r a n g
|
ENDGRID -1
|
d & % % V 0 7 7 7 7 % % T T
|
Clock
|
A A
|
EdgeLevel neg
|
L P / %
( %
( R L T i m e s N e w R o m a n % T ` Q ~ 7 A AQ L T C P U % T X A A L P B P %
( & % W $ % ( %
( %
( % R L T i m e s N e w R o m a n % T / A A L I n s t r u c t i o n C a c h e % T 6 A A6 L d B r e a k p o i n t s
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
& % W $ & } & } % ( % % V , { { { { & % % V 0 6 9 X X 9X 96 6 X % ( %
( % R L T i m e s N e w R o m a n % T ` J b A A J L T D M R & % W $ W W % ( %
( % R L T i m e s N e w R o m a n D % T 6 A A6 L d W a t c h p o i n t s
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
%
( & % W $ & } & } % ( % % V , { { { { & % % W $ x x x x % ( & % % W $ x x % ( & % % W $ > > % ( & % % W $ % ( % R L T i m e s N e w R o m a n % T x A A L \ M a t c h 0 %
( R L T i m e s N e w R o m a n h
% T x A A L \ M a t c h 7 & % % V 0 q q q q % ( % R L T i m e s N e w R o m a n % T T { A A{ L P ? %
( & % % V 0 % ( % R L T i m e s N e w R o m a n % T T A A L P ? %
( & % W $ % ( & % % V 0 ` 4 V `VV4`4`V% ( % R L T i m e s N e w R o m a n '
x x 9 # (R 9 Times New Roman Times New Roman % T ` | I a A A| I L T D S R x %
( & % % V 0 4 9 V V9V944V% ( %
( % R L T i m e s N e w R o m a n # (R 9 Times New Roman Times New Roman x % T ` I a A A I L T D R R & % % V 0 H 4 V HVV4H4HV% ( %
( % R L T i m e s N e w R o m a n 9 Times N oman Times New Roman '
x x 9 % T ` f I a A Af I L T D I R %
( _VPID_ALTERNATENAMES _VPID_PREVIEWS _PID_LINKBASE A
|
VerilogType wire
|
F Microsoft Visio Drawing VISIO 6.0 Shapes Visio.Drawing.6 9q Visio (TM) Drawing
|
SystemCType sc_logic
|
2 TH 0 ~ R l ! fff MMM 333 $
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
$
|
StateEquation Hex(Inc(0,2,5))
|
U,8@ Td Arial@N Wingdz s@N@tMonotype Sort+
N tSymbol 5T?? Y@ - 1 U J:D T1EW-hT T< *
|
HighVoltageThreshold 5
|
/U b
bO 0zGz?@8@H2!kWb*U
|
LowVoltageThreshold 0
|
+$ PL/^&9^$? { Ak^&,,'%/v&& *
|
LSB 0
|
1y
) P? 2
U
U12?k9 a BBHEHEHEHEHEHEH@?>?:`T2BBHEHEHEUHEHEHEHE%H@%O9 F 7AOY@;P
AsVsVA!gLTkY W_W__ !`# k4l b6u`kW *4l
|
MSB 31
|
4l %Y?P:?-\
#!+|QtKf2|2|2|I2wGQ A UoTMeE$ttA%_ 8BOTOfOxOO??HO?7ܻ XuW?YsU42
|
SignalActionType 0
|
T*
|
isFallingEdgeSensitive False
|
x x x
|
isRisingEdgeSensitive False
|
0jPvȲl^/!3jBj6D///$Q 0p?Mdj^cj4Ak[~ϐ$YkU1% 1F-(kp
ٻ A. $5-B i`# 9)F/Pv// ߾/u?2trߜKS52 7xߢ#6@h$MuLh Ճ %ԊՑ ) <OU # 5 G ::U2 q ?/&w&
|
DrawAnalog 0
|
<<7H 1O QjP SH QywH At///Y OG$_ p4b%F! 8q/#P?C/N^qhE! @d)n{r1P1 @ /Oqt}Q!n =k@Ʊ셩{B'ɂXVP_0TNJg21 1R5P"QQ[O" P!q[rr qqӂqq¢ӁӁP¡¡Waa7$VW7P$q"$qP1q1qP>q">qPKqKqPXq Xq2eqeqZ2Sob ZZdSTQcd PQQ P1H[<k?ta}Y M/OO*Dd3qO/NkS\O 9E/ / _ ? ?-??=___ѷ'sϖdI,O 0R 7nO&ګa ̗ѫaW?O // ?*
|
BooleanEquation
|
K ϥϷϾCNa \ "4FXj ߲K߳ BTf_/q/ //, ڭaRdv *<+/`bbiA nFUj?|?~/ "C??Va]? Ia(G
|
NegTolerance 0
|
rpl/YDE@a1LO pO #Q/I SGQۍBQfQaIq_Uyj ( ȄBb_(_:_/^_ //Q__a1 _ OO-OF ZO Qo~MA %o C AOOMgy N_r_O7 Zg @ :o,Ko -XyCŮbddpddp A͟ߟ'@9K]vAB(Onl=# ??6HZl Ǝ' ;M_q 2DV hzόϞϰ
|
PosTolerance 0
|
.@Rdv ߚ߬߾#} (:L^p Uɑۏ"4FXj@|X *<N`r & 8 J \ n Y / ///A/S/e/w///F/L// ? ?$?6?H?Z?l?~?? ?????? O"O4OFOXOjO|O OOOOO _ _ 0_B_T_f___ _____oo'o 9oKo]oFxoOoo oooo,>PPfx ,> nBsgcEf Ώ (ٴJ\n ȟڟ" OeOj|@į֯ ( :L^pʿܿ B#vXT+Sb b z @v 6M_Toρ6 ϱi -?Qcu ߙ߽߫ ϭ, /-?eY[Ưy +=Oas 1ńR Z sc<Ɠ`Zl~ sb6-1R# # 5 G Y k } x;6/ F%/jI/[/m////) ////
|
UserSpecifiedSizeRatio 1
|
? ?.?@?R?d?v??? YTV
|?bO 2ODOVOzOaq OOOOOO_ !_3_E_W_i_{___ _____ o o/o Ao}x^oK Acrobat PDFWriwter $
|
VerilogCode
|
wod x ) 3EWi{< # winspool Acrobat PDFWriter LPT1: 4( UPx 7@?TFD Te]y P
ahZ ^T UIQ/ @It@
|
VHDLCode
|
@2?I
|
VhdlMapping DefaultVhdlMapping
|
?*N ` d * ? q ^ua `h<u<e p5!5! a< U U
|
PROPS!
|
%J*!H$a '$<'<$p! 'p!(t!'t!(x! 'x!(|!'|!( '$!'!(!'!(!G!( ! G!(!'!( !'!(!'!( !'('!( '!(!'!( '!(!'( !'(!'!(5!'( *!( *!( *!( #!:5ip!<|x!-m H5 1%H5 N @@:m@*y? ?/ qe# v lx!0^ RU8x!Aid/ <^ ` $b b -t!
|
E0 X 750 750 1 0 DR 0
|
"v*wf- #<d3E H5me5q2! r .4 !LTICMR ii$goyo#t' 25Uɒ2$a oo(o:oLo^o~o`looo o
|
E1 V 1750 1750 D20 1 0 DR 0
|
a$y9K ]o*N tayҶ
r Uy(ϯ^ -?^Mask Fu?nctionlN `Ɵ#< 5ꘀ
9<$@0Eg t `6i @@-DT!"-^u `u `b u `u @"^耨 @P!̯ޯ{W,(ui{cd{?/Vhhi x0O贁Nk
|
E2 X 5750 5750 1 0 DR 0
|
l+ R:LOcUw*|; v!@hdv]M/W.С:Lxm u&);M_q &s%uI6 ?%?3i?Ӊ?u 5?U??4r?3 Q!Y k } @ @ b/)/;/ M/_/e!mV// ///// ??0? t&ayfb?Qo?uo ?o?3OEOO(O 7LO^OToONaO OOOOVT\ⱷebU@N ءY $6_am 6@ o ާK,>Pbt h^._ew\LmpLDeXPj a}
|
!
|
&a,W\ ee"aʡqDe o^oonooS @a
|
|
@߷j ]lZߎT±P btο..`]֏ 0BT@R i)y)LY&'f
gyz
v Я1#e < n@! X\͏Wi{ PYe6'VXNXU@e67d7 ?>e6 G=t7O $ 6 H Z ~ O< p!b / )"a(0'Y"a'%^/+ F//////` ??-???Q?QPi9f~?^Wf wg /~ fdw0}gnE@tTϨ`pHG2 qpa??=
HPA5HOZO lO~OOOOOO(XBq0#UINT [31:/2] j 0'Y(%!QXIx !390U HP 1` Q,`7_I_[_ /1CU] s?@S$$0s'(-DT! q=ϣoebtܑ
ڥt&I ӬB Ñi3Õ
|
SIGNAL dbg_dat_o
|
JYTPÑ]wEK rYcu7W_[v ZaEr 5>a"tլ̓EG`IfH mƞϬȀ. Pb qa hΨ _Nǟٟ!3EWqf-P`?@?@Lh#!`,ߡůׯ,!}$ -( L Ni3"g
|
DIRECTION output
|
Nw :%
ɿۿ#@ >@FH3 BC?@ZD(@W.[űQ@klP>KK- >R NϿ ? ? @0ۍ 3XQ.Ft( B9vC?@W]//[ " (tJ L!vCϬo.R? @ ۼ//r% 'U@u$kpD qQ*Q'TU@7VD]M@ @qk skvmjTfF8 OEsKMsBFrsK:Fe4?̆僾XaPÑo NS\TNgSq? ?????OO'K6E:m @FOXOjO|OOH$
ffvEsfDfff f2_!_3_E_tYa g_yTvfsoak:p ___oo ^pJooܩ 쯘! EfbY bw =fb);V {/A S/wω߭Ͽ / $7uQ cu߇ߙn?u/j )j|_@
1C{ f1
|
RADIX hex
|
b q4fI bݓɟ ۟ # 5 G Y k } /ůUg # //-/?/Q/ c/////j| ?2?D?V?h? ϋPP9P`@rvϞϰ }6AW@@>bM6 bQAho!3W#YFy&J0X'qfI ` Iq7I)5Y!
|
GRID 0 1 0 1 0 16711680 0 0
|
aM6 ,?%1?g1 .??#g1v;@?+?K!uQ2OEusryPrC UuQSTTUPICPR iP rTPx#$e' 2U"R?Gr^2Dr P |$G cК[#0XqZ u X@@9P_v6S6P$G;Hq- P`uxp`b u
:f]Y@"8qCh:3h7P@9a*3b>a{cHbCbdG/Y/k+7Q})f坥 !@@ M] 0I @Q6Rfg/rg>Puf|wH}gPp T0O贁Nk)R FusKW@]_[)*mOT4O5V^o'8_J_\_n__Q[DcQU_U@&M ^jJ@@ O ZӶ6h >9/r)Q*o
|
ENDGRID -1
|
%,vi hRt¯Ԯi խxPp+ =Oasƿ'ɏۏ__l_\?X<; ?@.O<h?=9p&oş ן
1CU })ւ,P]xl$@ӯ
|
Clock
|
@@LǘF%xpf .
|
EdgeLevel neg
|
F 2߀DVhzߌߞ߰})YCi?Wz? $u H@@f?YXRt Y h/b08G)2
q ?/&3$k?2A %7I [m11xF?ZCOFINT 0 jOOO+I
|
Set Not Used
|
W$O !3&B0 T5.F@Y&'' 2D~]t*kl b7?@U;~ S /@;v> " 4 F 2iVr ~@i6PbեF?A59V TgWRtUognVg hm go9/K/]/o// -//////? #?5??Y?t^?? 1???;S O$O6ICIP `@@'QWOiO {OOOOOOOVު@@ asDK_ ]_o_______I٩oף 婦rdI Soo ~&ܿ J\nΘ8KLOWPRIO 1EXCEPT ^p?ʏ9O KE,,>Pbt2Gr) W Ο( :L^pV, ]Y¯cܡo oYXrdYh ѿ+ =Oasυϩϻ@ V KHIG H ION*<@N`r߄ߖKE /AS@b ;'?@.gx+4ԑ !3Ed! i
Fr2!8 W B`#5Me
FeG GrdfOxN
FGyM GO9 K o>_ # 5 Y T,>_ 0TICK
ѷ߉//߿) (9(TdE5E5E5Ŗ60v?O:??wavUa?! TaYaiUQa_"[n_b9oaeryavbq-
|
Clear Not Used
|
"kiF1 "9v5GeOeU rtEgaeV G q a28ebra0ƫ ʛPI CSR i oo(D[' 25U@ R|d j/oooV-bpq\bbe?0v(~VE8-?DT!X?j? |??????r]&O 9v*]FNOabǠ@_ ______To PFfa[mǯٯyTw?@rV+ l.@Rdv`пIM|26* 6]FMLDM \ 0߀Bߑfߒl e/߭/////G t(x" E?W?'9I&fx*"=Ϭ&7'D?> &L7='V?OO_ #_5_?Y_k_}_?Q cuD $OIo \k~b ( : L ^ p @,fBv /"/4/F/X/j/|//@yQyf/V,FƷfwg"~fWw#}ga? ?????
|
ClockEnable Not Used
|
O O .O@OROdOvOOOO OOOU !_ 3_E_+=OUUU o%o7oIo[omoo oooğ@ƝFƺ%Z& ɧd-9K]o ⏷ߘ _/ASZ_l_~__h_)@ r8ӄ_!3E Wi{DQ ӯأ - qr ( J'п U*8 Ul4,Q/ @t@
|
ActiveLowSetClear True
|
@ | 9* *A-3 ?7U2@$ E*7 CR H<(
|
AsyncSetClear True
|
U2ET *7
R UlL\ s(* @ ?% ) R }D ; U$
|
ActiveLowClockEnable True
|
4( U1( UO"D&aU=QJf )h" Ty+Uv' _ Ʌ &aQ-
|
VhdlType std_logic
|
- H* 9( TYg EQ /, Guide TheDoc Page-1 Gesture Format Block Normal Visio 10 Block Shadow Visio 12 Block Highlt Visio 11 Connector Visio 90 Dot Connector Connector Arrow Visio 00 Visio 01 Visio 02 Visio 03 Visio 13 Visio 20 Visio 21 Visio 22 Visio 23 Visio 50 Visio 51 Visio 52 Visio 53 Visio 70 Visio 80 _ 35 +
|
VerilogType wire
|
E -
|
SystemCType sc_logic
|
G 6 _, $_ U'c
<_ 4c
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
UT_ Eu
|
StateEquation Hex(Inc(0,2,5))
|
l_ Rc T_ ju
|
HighVoltageThreshold 5
|
_ wc _ u
|
LowVoltageThreshold 0
|
̪_ c U_ c U_ u
|
LSB 0
|
7 u
|
MSB 31
|
,%ܪu
|
SignalActionType 0
|
D%u
|
isFallingEdgeSensitive False
|
\%Zu
|
isRisingEdgeSensitive True
|
t%-v %Uq% q%U*q%7q%}Dq8 QqU ^q4kqULxqdq%A%& 0 xRf!
|
DrawAnalog 0
|
E UjU
|
BooleanEquation
|
U
UUU Ul4,Q/ @t@
|
NegTolerance 0
|
@ . UC- H/ A Ul4, /
|
PosTolerance 0
|
AJ- 3 7 A _ *<N@ N/ PRVg" q 6uH<(
|
UserSpecifiedSizeRatio 1
|
H<(
|
VerilogCode
|
_ *<NE &0
RVg\" 3 q t> {
|
VHDLCode
|
* g"4pFX (_,9@(m@2Yy
|
VhdlMapping DefaultVhdlMapping
|
K_DO :]WR
|
PROPS!
|
LQ |#u{ &U ]!B G?Q
> :B >O ko5O ĭ _ $O '4*^N_/ $+)0 -1T==w=` 22 - fV ?t8 / FD$; @0P=
|
E0 V -1 -1 1 0 DR 0
|
OC !_k G @ Oh +'0 @ H h t Valued Sony Customer G < x /K EMF 4 X V I S I O D r a w i n g
|
E1 V 750 750 PC 1 0 DR 0
|
& % % V 0 V > > V> V > % ( % R L A r i a l % T d & < A A & L T I C M R & % % V 0 V VV % ( % R L A r i a l % T : A A
L h M a s k F u n c t i o n
|
E2 X 2750 2750 1 0 DR 0
|
|
E3 V 3750 3750 D100 1 0 DR 0
|
|
E4 V 4750 4750 L/S EA 1 0 DR 0
|
|
E5 V 5750 5750 LOAD DATA 1 0 DR 0
|
|
!
|
|
|
& % W $ > > % ( % % V , & % % V 0 z G z G G z % ( & % % V 0 ) e j ) )jeBe) % ( & % % W $ V V % ( & % % W , ) . .).% ( & % % W $ G G % ( & % % W $ e . . e..% ( & % % W $ % ( % % V , % R L A r i a l % T J A A
|
SIGNAL dbg_op_i
|
L ` I N T [ 3 1 : 2 ] & % W X {rfYL?2' % ( & % % W X {rfYL?2' % ( & % % W X \ ~ s i b ] \ % ( & % % W X \ ~ s i b ^ \ % ( & % % V 0 > > > > % ( % R L A r i a l % T d & ? < A A & L T I C P R
& % W $ ) > ) )> ) % ( % % V , % . . ) % . & % % W $ ) \ G \ )\ G\ % ( & % % W $ G \ G G\ G % ( % % V , B K K GB K & % % W $ y z z y % ( % % V , u ~ u y ~ u % R L A r i a l % T l 0 A A L X I N T 0 & % W $ j j jj% ( % % V , f o fjof % R L A r i a l % T l } 0 A A } L X I N T 1 & % W $ L z L LzL% ( % % V , y G Q yGLyQyG % R L A r i a l % T _ F n A A _ L d L O W P R I O I N T
|
DIRECTION input
|
|
RADIX hex
|
T p o $ ~ A A o L X E X C E P T & % W $ z z % ( % % V , y y y y %
( % % T G A A L d H I G H P R I O I N T
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
T : A A L ` E X C E P T I O N
|
Clock Unclocked
|
՜. +,D ՜. +, @ H P \ h t
Pages Page-1 8 _VPID_ALTERNATENAMES ^ _VPID_PREVIEWS _PID_LINKBASE ? A Q&l ^ & " WMFC Z e x Q &l EMF S X V I S I O D r a w i n g
|
EdgeLevel neg
|
Q % R L A r i a l % T l W Q
|
Set Not Used
|
@
|
Clear Not Used
|
@W Q L X S E T 0 - - ) % T l W
|
ClockEnable Not Used
|
@
|
ActiveLowSetClear True
|
@W L X S E T 1 - - ) % R L A r i a l m^ n n oL o ph q q r s t u v x< xj y y y y y z { | }
|
AsyncSetClear True
|
}: } ~8 ~ ~ b x x \ * n ( r 2 n N d ^ V % T `
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
@
|
VerilogType wire
|
@ L T . . . R L A r i a l 2 f B R H b Z b Ì b Ǽ ʬ ˘ ` > π Ѭ : t Ԓ բ J t \ ؆ ذ . X ق ٬
|
SystemCType sc_logic
|
4 % T ` s 1
{
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
@
|
StateEquation Hex(Inc(0,2,5))
|
@s 1
L T S E T - - ) R L A r i a l R f H H D n
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
@
|
SignalActionType 0
|
j
|
MSB 3
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
< f 8 b
$
P Z > 8 H ! #8 $ $ %l & 'T 'd (0 % T + r
=
|
isRisingEdgeSensitive False
|
@
|
DrawAnalog 0
|
@+ r
L ` D C _ S E T S - 1 $ $ ! ! ! & % % V 0 o 3
p
2
2pp
% ( R L A r i a l |l ~ @ B Z " L \ l
|
BooleanEquation
|
4 ^ n ~ 2 \ . X * T ~ & P z " L v % ( R L A r i a l F p B l h : d 6 j F d $ X * n 2 $ f 0 F P B % ( R L A r i a l N Ø . Ć N Ť & x 4 Ǡ L Ȍ 6 Ɋ ɰ 0 ` ʐ : x n ̲ N ͎ ʹ 6 \ ΰ $ π Ϻ R Ц . p Ѱ & b Ҟ % ( R L A r i a l 0 ` ؐ $ ل ٸ P ڰ H ި % ( % R L A r i a l % T l o
|
NegTolerance 0
|
@
|
PosTolerance 0
|
@ o L X T A G 0 ) - 4 % T l
|
UserSpecifiedSizeRatio 1
|
@
|
VerilogCode
|
@ L X T A G 1 ) - 4 % R L A r i a l % T ` 5 m ,
|
VHDLCode
|
|
PROPS!
|
@
|
E0 V 750 750 READ PC 0x0 1 0 DR 0
|
@5 L T . . . R L A r i a l ܣ .@ cvt pv | 0fpgmw' w gasp P glyfq hdmxB: ( yheadGN | 6hheam $hmtxWnd :kern7a96 D `loca A Dmaxp name6 ` +postƬ%E 0 1prepq l
|
E1 V 1750 1750 WRITE SPR 0x5 1 0 DR 0
|
% T ` I
|
E2 V 3750 3750 READ SPR == 0x4 1 0 DR 0
|
@
|
E3 V 4750 4750 READ LSEA 0x1 1 0 DR 0
|
@ L T T A G ) - 4 T O
|
E4 V 5750 5750 READ LDAT 0x2 1 0 DR 0
|
@
|
!
|
@ O
L ` D C _ S E T S - 1 0 0 % - - ) - % & % % V 0
|
|
M L
|
SIGNAL dbg_stall_i
|
L
|
DIRECTION input
|
L% ( %
( %
( R L A r i a l f " v & N 4 f @ n ( ^ 0 ` > j 8 p 2 b P < p j 8 X e % ( %
( % % T b
|
RADIX hex
|
@
|
GRID 0 1 0 1 0 16711680 0 0
|
@ L p E F F E C T I V E A D D R E S S er- ) ) - 0 ( - - - 0 0 0 - - - & % % V 0 | l
}
k
k }}
% ( R L A r i a l ns, magazines etc, and for display use in newspape advertising and promotions.http://www.monotype.com/html/mtname/ms_arial.htmlhttp://www.monotype.com/html/mtname/ms_welcome.htm OTIFICATION OF LICENSE AGREEMENT
|
ENDGRID -1
|
|
Clock Unclocked
|
This typeface is the prope u% ( R L A r i a l ed this typeface software either directly from Mon e or together with software distributed by one of Monotypes licensees.
|
EdgeLevel neg
|
|
Set Not Used
|
This software is a valuable asset of Monotype. Unle you have entered into a specific license agreement granting y th% ( R L A r i a l may not copy or distribute this software.
|
Clear Not Used
|
|
ClockEnable Not Used
|
If yo ve any question concerning your rights you should review the license agreement you received with the software or contact Monot e for a copy of the license agreement.
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
Monotype can be cont U% ( % R L A r i a l m a l o b y
e j n n o r m a l S t a n d a r d T y p e f a c e T h e M o n o t y p e C o r p o r a t i o n p l c . D a t a T h e M o n o t p e C o r p o r a t i o n p l c / T y p e S o l u t i o . % T p o `
|
ActiveLowClockEnable True
|
@
|
VhdlType std_logic
|
@ o L X W o r d 0 B % % % T p `
|
VerilogType wire
|
@
|
SystemCType sc_logic
|
@ L X W o r d 1 B % % % % T ` ,
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
@ & " WMFC E
|
HighVoltageThreshold 5
|
@ L T . . . d R L A r i a l D r a w i n g O f f i c e - R o b i n N i o l a s , P a t r i c i a S a u n d e r s 1 9 8 2 C o n t e m p o r a r y s a n s s e r i f d e s i g n , A r i l c o n t a i n s m o r e h u m a n i s t c h a r a c n % T I
|
LowVoltageThreshold 0
|
@
|
SignalActionType 0
|
@ L h W o r d D C _ S E T S - 2 B % % 0 0 % - - ) - % T O
|
MSB 0
|
@
|
LSB 0
|
@ O
L h W o r d D C _ S E T S - 1 B % % 0 0 % - - ) - % %
( & % % V 0
|
isFallingEdgeSensitive False
|
I M
|
isRisingEdgeSensitive False
|
LHLH
|
DrawAnalog 0
|
|
BooleanEquation
|
L% ( %
( %
( & % % V 0 ( M )L
|
NegTolerance 0
|
L
|
PosTolerance 0
|
) )L% ( & % % W , . C Z
|
UserSpecifiedSizeRatio 1
|
QLQ-7-7
|
VerilogCode
|
% ( & % % W ,
% ( & % % W $ .
|
VHDLCode
|
@ d 7
|
PROPS!
|
7[% ( % % V , Q ^ ^Q7Q^Q% % V 0 c c c & % % 6 6 6 # 6 ' + 6 / 3 6 7 ; 6 ? C 6 G K 6 O S 6 W [ 6 _ c 6 g k 6 o s 6 w { 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 # 6 ' + 6 / 3 6 7 ; 6 ? C 6 G K 6 O S 6 W [ 6 _ c 6 g k 6 o s 6 w { 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 # 6 ' + 6 / 3 6 7 ; 6 ? C 6 G K 6 O S 6 W [ 6 _ c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c { c w 6 c s c o 6 c k c g 6 c c c _ 6 c [ c W 6 c S c O 6 c K
|
E0 0 5750 5750 1 0 DR 0
|
! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o q r s t u v w x y z { | } ~ c G 6 c C c ? 6 c ; c 7 6 c 3 c / 6 c + c ' 6 c # c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c { c w 6 c s c o 6 c k c g 6 c c c _ 6 c [ c W 6 c S c O 6 c K c G 6 c C c ? 6 c ; c 7 6 c 3 c / 6 c + c ' 6 c # c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c c 6 c 6 ` \ 6 X T 6 P L 6 H D 6 @ < 6 8 4 6 0 , 6 ( $ 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 | 6 x t 6 p l 6 h d 6 ` \ 6 X T 6 P L 6 H D 6 @ < 6 8 4 6 0 , 6 ( $ 6 6 6 6 6 6 6 6 6 6 6 & " WMFC % 6 6 6 6 6 6 6 6 6 6 | 6 x t 6 p l 6 h d 6 ` \ 6 X T 6 P L 6 H D 6 @ < 6 8 4 6 0 , 6 ( $ 6 6 6 6 6 6 6 6 6 6 6 6 6
6 6 6 ! % 6 ) - 6 1 5 6 9 = 6 A E 6 I M 6 Q U 6 Y ] 6 a e 6 i m 6 q u 6 y } 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6
6 6 6 ! % 6 ) - 6 1 5 6 9 = 6 A E 6 I M 6 Q U 6 Y ] 6 a e 6 i m 6 q u 6 y } 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6
6 6 6 % ( % R L A r i a l (Q al Arial # XX< % T d
|
!
|
@
|
|
@ L T D M M U H S S H & % W , C
|
O l e
|
L
|
C o m p O b j i O b j I n f o C O N T E N T S < % Timing Diagram Editor v7.1g - Output File
|
% ( & % % W $
|
|
|
PROJECT
|
|
BaseTimeUnit 1
|
|
DisplayTimeUnit 2
|
% ( % % V , =
|
TextGridX 250.000000
|
|
TextGridY 6
|
=
|
EdgeGridX 250.000000
|
& % % V 0 C DDD% ( % R L A r i a l # X 9 ' 3 ! 2 (Q Arial rial T3% T d 1 X
|
ImportStartTime 0.000000
|
@
|
ImportEndTime 281474976710656.000000
|
@1 X L T C O M P 0 4 7 - & % W $ q h% ( % % V , o ^ ^o^^ & % % W $ H
Z q Q
Qh% ( % % V , * ^ x x^Q*^x^ & % % W , Z ##c% ( & % % W $ % ( % % V , o o % R L
|
TimePerPixel 5.428571
|
|
Visible DELAYS SETUPS HOLDS SAMPLES TEXT HIDDENATTACHMENTS CRITICALPATHS GRIDLINES UNCERTAINTY
|
A r i a l * ! #0 %` ' )< ) ** * ,r -P .. . / 1 3 3 3 4 4 5 5 5& 56 5F 6 6( 68 6 6 70 7@ 8* 8: 8J 8Z 9f : : ;@ ;p ; ; < =R >( ? @ @ A@ BZ C2 CB CR % T l n L
|
ColWidths 144,216,288,423,488
|
@
|
ScrollPos 0.000000,0.000000,0.000000
|
@ L X H I T 0 0 ) % %
( %
( R L A r i a l m o o o pR pb pr p p rr r s s u^ v v w w y z zT { { | | | } } ~ ~ H : x 2
|
DefDelayRule 1
|
N v B v > ~ % T X
|
NoEventOverlap NO
|
@
|
SigLabelFontHeight 10
|
@ L P 3 1 % % %
( R L A r i a l < H * h z $ b z B j t <
|
LabelHeight 12
|
H æ ( Ɔ ư ǒ Ǽ B l ˖ @ j ͔ ; % ( R L A r i a l 0 Z , V ( R | & P P V
|
LoadLibsToMem 1
|
@ B z ( | $ N x J t % ( R L A r i a l > N d J Z n H ! "l " # $2 % &z & '" '2 ' ( ( ( ) * + + -< -L / / 1 1 3: 3J 4: 5 5 7 7 8` 8p 8 8 : : :( :8 ; < = % T ` / r
|
UseFullPathNames 1
|
@
|
LibPath
|
@/ L T l o g R L A r i a l n n n o( oR ob or o o o p p p p@ pP pz p p p p q qB ql q q q r r> rh r r r s s: sd s s s t t6 t` t t t u2 u\ u u u v v. vX v v v w w* wT w~ % T T s
|
EntireTime YES
|
@
|
PrintTimeSpecified NO
|
@s L P 2 R L A r i a l n ( ^ ` j b r * * < & " WMFC ( : L ^ p 0 6 ` . x H % T
|
FromTime 0
|
@
|
ToTime 4.75
|
@ L d ( D C _ S E T S ) + 4 $ $ ! ! ! %
( % T T A
|
AllSignals YES
|
@
|
CurrSelSigs NO
|
@ L P 4 % R L A r i a l ore humanist characteristics than many of its pred sors and as such is more in tune with the mood of the last decades of the twentieth century. The overall treatment of curves softer and fuller than in most industrial style sans serif fa th% T T h
|
PrintTo 2
|
@
|
PrintFileName C:\DOCS\untitled1.wmf
|
@h L P 3 % R L A r i a l humanist characteristics than many of its predeces and as such is more in tune with the mood of the last decades of the twentieth century. The overall treatment of curves is s ter and fuller than in most industrial style sans serif faces. di% T T
|
PreviewInterchange YES
|
@
|
PreviewTIFF5 NO
|
@ L P 0 er% R L A r i a l in reports, presentations, magazines etc, and for play use in newspapers, advertising and promotions.http://www.monotype.com/html/mtname/ms_arial.htmlhttp://www.monotype.com/ht /mtname/ms_welcome.htmlNOTIFICATION OF LICENSE AGREEMENT
|
UseMargins NO
|
|
PrintTimeLine NO
|
Th ot% T l
|
PrintBorderBox YES
|
@
|
PrintSigNames YES
|
@ L X W A Y 0 inO 9 8 . &
|
PrintSigNamesOnEachPage YES
|
%
|
AddPreviewToEPS NO
|
% V 0 G * M HL)L) H HL% (
|
PreviewRes 150
|
%
( %
( %
( % R L A r i a l our own publishing use. You may not copy or distri this software.
|
MarginLR 1.25
|
|
MifImageWidth 6.00
|
If you have any question concerning your rights you should review the license agreement you received with t software or contact Monotype for a copy of the license agreem at% T T "
|
MarginTB Auto
|
@
|
Header %d %t;%f;%p
|
@ L P 2 ty% %
( %
( R L A r i a l e M o n o t y p e C o r p o r a t i o n p l D a t a T h e M o n o t y p e C o r p o r a t i o n p l c / T y p e S o l u t i o n s I n c . 1 9 9 0 - 1 9 2 . A l l R i g h t s R e s e r v e d A r i a l R e g l % T T I m
|
Footer
|
@
|
ScaleHorz 100
|
@I L P 1 % & % W ,
|
ScaleVert 100
|
C L::% ( %
( % % V 0
g g
g
g % R L A r i a l o b i n N i c h o l a s , P a t r i c i a S n d e r s 1 9 8 2 C o n t e m p o r a r y s a n s s e r i f d e s i g n , A r i a l c o n t a i n s m o r e h m a n i s t c h a r a c t e r i s t i c s t h a n m a n s % T N
|
ScaleHPage 1
|
@
|
PrintImage DIAGRAM
|
@ N L d W O R D S E L E C T s B 4 0 0 - - % - 0 ) & % W $
|
DefaultTimingModel minmax
|
% ( % % V , : :: &
|
DefaultClock Unclocked
|
% % V 0 z% ( &
|
DefaultEdgeLevel neg
|
% % V 0 zz% ( & % % W $ 2 @ ))7% ( % % V , . P P.).P. & % % W $
% ( % % V ,
& % % W $ 2 )% ( % % V A 9 #&)+.1368:<>?@AAAAA@?><:8631.+)&# & % % W $ 2 ))% ( % % V , P )P% % V , P P)P%
( R L
|
DefaultSet Not Used
|
|
DefaultClear Not Used
|
A r i a l MSTT315b3b3a84t # XX> C ' ,f (Q Arial Arial % ( %
( % R L
|
DefaultClockEnable Not Used
|
|
DefaultClockToOutLH 0
|
A r i a l # XX> N ' - C hQ Arial Arial C C MSTT316eafa79 % T e \ 8
|
DefaultClockToOutHL 0
|
@
|
DefaultSetup 0
|
@e \ L d T O / F R O M C P U ) 4 ) 0 4 7 0 - 0 T K L
|
DefaultHold 0
|
@
|
DefaultRegStartupState unknown
|
@ L p T O / F R O M E X T E N I / F ri) 4 ) 0 4 7 - + ) - 0 ) & % W ( C ^ LU% ( & % % W $ L i U`% ( % % V , W WW W % R L A r i a l rial IO @CO MSTT315b3b3a84t # XX> C ' ,f (Q % T d g
|
DefaultPodSize 8
|
@
|
DefaultActiveLowSetClear True
|
@ L T B Y T E - - ) - T x w F
|
DefaultAsyncSetClear True
|
@
|
DefaultActiveLowClockEnable True
|
@w F L \ S E L E C T S - - % - 0 ) - %
( %
( R L A r i a l C C MSTT315b3b3a84t Arial IO mCO MSTT315b3b3a84t # XX> C f % ( R L A r i a l Arial # XX> N ' E - % ( R L & WMFC A r i a l C + C (Q Arial Arial C MSTT315b3b3a84t % T ` <
|
SigLabelFontHeight 10
|
|
PROPS!
|
|
!
|
@
|
|
@<
|
STYLE
|
L T l o g R L A r i a l (Q Arial Arial % T T
|
DefaultFont USER {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
|
|
DrawWndFont DEFAULT
|
|
DrawWndColor DEFAULT
|
@
|
GridWndFont DEFAULT
|
@
|
GridWndColor DEFAULT
|
L P 2 R L A r i a l ` p B p 2 ~ H L 4 d ( . f ( 2 \ < H * h % ( % T
|
LabelWndFont USER {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
|
|
LabelWndColor DEFAULT
|
@
|
ParamDispPref 0
|
@
|
ParamWndCellDisplay 0
|
L d ( D C _ S E T S ) + 3 $ $ ! ! ! F . - C Arial ? ? ?? ? ? ? - 2
|
CustDispString %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
|
QW SET 0 - - ) % 2
|
CustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
|
W SET 1 - - ) % C Arial ?A?A?A?A?A?A?A?A?A?A?A?A? - 2
|
MarkerDispPref 4
|
... C Arial ?A?A?A?A?A?A?A?A?AhA?A?A? - 2
|
MarkerCustDispString %n v=%mv,%Mv d=%md %t
|
1
s SET - - ) 2 Arial ?????? ?????????????????? - 2
|
MarkerCustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
|
r
+ DC_SETS-1$ $ ! ! ! - - $ p
2
2pp
- C Arial ???????????????????????? - C Arial ????????????????????????? - C Arial ????????????????????????? - C Arial ????????????????????????? - - C Arial ????????????????????????? - 2
|
SignalColor 2
|
o TAG 0 ) - 4 % 2
|
LabelOffset 2
|
TAG 1 ) - 4 % C Arial ????????????????????????? - 2
|
BusDisplay 0
|
5 ... C Arial ?? ? ??4?? ? ????? ? ???? - 2
|
WaveFormWidth 1.000000
|
TAG ) - 4 2
|
WaveFormColor 0
|
O
DC_SETS-10 0 % - - ) - % -
|
InputWaveFormColor 16711680
|
- $ L
|
SlantedEdges 1
|
L
|
SlantAngle 75
|
L -
|
RightJustifySigNames 1
|
"System c č ρ -
|
AutosplitEnabled 1
|
-
|
AutosplitChar _
|
C Arial ???????????????????????? - -
|
DynamSizedSignals 1
|
- - ! 2
|
!
|
EFFECTIVE ADDRESS(- ) ) - 0 ( - - - 0 0 0 - - - - - $ }
k
k }}
- C Arial ????????????????????????? - C Arial ????????????????????????? - C Arial ???4????????????????????? - - C Arial malobZ
ejnnormalStandar? - 2
|
|
o Word 0B % % % 2
|
DIAGRAMTESTBENCHSETTINGS
|
Word 1B % % % - 2
|
FilesBeforeDiagramModel
|
... C Arial Drawing Office - Robin Ni - 2
|
FilesInsideDiagramModelDeclarationSection
|
Word DC_SETS-2B % % 0 0 % - - ) - % 2
|
AbortHdlCodeEnabled 1
|
O
Word DC_SETS-1B % % 0 0 % - - ) - % -
|
DelayHdlCodeEnabled 1
|
- - $
|
SampleHdlCodeEnabled 1
|
LHLH
|
MarkerHdlCodeEnabled 1
|
|
VerboseSamples 0
|
L - -
|
VerboseDelays 0
|
-
|
VerboseFileInput 0
|
- - $ )L
|
VerboseSequenceVerification 0
|
L
|
IncludeDelayTime 1
|
) )L - - - % QLQ-7-7
|
ExecuteFromTopLevel 1
|
- - - %
- - - % 7
|
TimeOutInDiagramLengths 0
|
7[ - - - $ ^Q7Q^Q - - $ c c - - # ' + / 3 7 ; ? C G K O S W [ _ c g k o s w { # ' + / 3 7 ; ? C G K O S W [ _ c g k o s w { # ' + / 3 7 ; ? C G K O S W [ _ c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c {c wc sc oc kc gc cc _c [c Wc Sc Oc Kc Gc Cc ?c ;c 7c 3c /c +c 'c #c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c c {c wc sc oc kc gc cc _c [c Wc Sc Oc Kc Gc Cc ?c ;c 7c 3c /c +c 'c #c c c c c c c c c c c c c c c c c c c c c c c c c ` \ X T P L H D @ < 8 4 0 , ( $ | x t p l h d ` \ X T P L H D @ < 8 4 0 , ( $ | x t p l h d ` \ X T P L H D @ < 8 4 0 , ( $
! % ) - 1 5 9 = A E I M Q U Y ] a e i m q u y }
! % ) - 1 5 9 = A E I M Q U Y ] a e i m q u y }
- - d Arial ?A?? ??? -
2
|
DefaultCycleClock Unclocked
|
DMMUH S S H - % L
|
DefaultCycleEdge neg
|
- - - %
|
!
|
|
|
- - - $
|
MACROS
|
=
|
!
|
- - $ DDD - - C Arial ?? -
2
|
|
X1 COMP0 4 7 - - % h - - - $ ^o^^ - - % Q
Qh - - - $ x^Q*^x^ - - % ##c - - - % - - - $ o - C
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
Arial ?A?A?A?A?A?A?A?A?A?A?A?A? - 2
|
!
|
HIT 0 0 ) % -
|
|
-
|
CORGROUP $$CLK_I_BufferFalling
|
C Arial ?A?A?A?A?A?A?A?A?A?A?A?A? -
|
Percent 100
|
2
|
!
|
31% % -
|
|
! Arial ?A?A?A?A?A?A?A?A?A?A?A?A? - 2 Arial ?A?A?A?A?A?A?A?A?A?A?A?A? - 2 Arial ????????????????????????? - 2
|
CORGROUP $$CLK_I_BufferRisingFalling
|
/ log ! Arial ????????????????????p??? - 2
|
Percent 100
|
s 2, 2 Arial ????????????????????????? - 2
|
!
|
(DC_SETS)+4 $ $ ! ! ! -
|
|
- 2
|
CORGROUP $$CLK_I_BufferRising
|
4,% C Arial ????????????????????????? - 2
|
Percent 100
|
h 3,% C Arial ????????????????????????? - 2
|
!
|
0,% S Arial ????????????????????????? -
2
|
|
WAY 0 O 9 8 . - - $ HL)L) H HL - -
|
CORGROUP $$CLK_I_BufferFalling
|
-
|
Percent 100
|
-
|
!
|
- C Arial ?????????????5???4??????? - 2
|
|
2,% -
|
CORGROUP $$CLK_I_BufferRisingFalling
|
-
|
Percent 100
|
C Arial e Monotype Corporation pl - 2
|
!
|
I 1,% - % L:: - -
|
|
- - $ g
g
g - C Arial obin Nicholas, Patricia S - 2
|
CORGROUP $$CLK_I_BufferRising
|
N WORD SELECT B 4 0 0 - - % - 0 ) - % - - - $ ::
|
Percent 100
|
- - $ z -
|
!
|
- - $ zz - - - % ))7 - - - $ P.).P. - - % - - - $
- - % ) - - - v $9 #&)+.1368:<>?@AAAAA@?><:8631.+)&# - - % )) - - - $ )P - - $ P)P -
|
|
C
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
Arial ? ? u ???????t - -
|
!
|
- C
|
|
|
CORGROUP $$CLK_I_BufferRisingFalling
|
Arial ???> ? N??? ? ? - 2
|
Percent 100
|
\e TO/FROM CPU ) 4 ) 0 4 7 0 - 0 ! 2
|
!
|
TO/FROM EXTEN I/F() 4 ) 0 4 7 - + ) - 0 ) -
|
|
% LU - - - % U` - - - $ WW W - C Arial ?? ??O? ?????? ? -
2
|
CORGROUP $$CLK_I_BufferRising
|
BYTE- - ) - 2
|
Percent 100
|
Fw SELECTS - - % - 0 ) - -
|
!
|
-
|
|
! Arial ??? ????????? - 2 Arial ??? - 2 Arial ? ?C+?? ? AC ?A?? - 2
|
CORGROUP $$CLK_I_BufferFalling
|
<
|
Percent 100
|
log ! Arial A? ?A?? ??? - 2
|
!
|
|
|
2, 2 Arial ?A?A?A?A?A?A?A?A?A?A?A?A? - - 2
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
(DC_SETS)+3 $ $ ! ! !
|
!
|
F Microsoft Visio Drawing VISIO 6.0 Shapes Visio.Drawing.6 9q ՜. +,D ՜. +," @ H P \ h t
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|
|
MN TH L R l ! fff MMM 333 $
|
CORGROUP $$CLK_I_BufferRising
|
$
|
Percent 100
|
U38@ Td Arial@N Wingdz s@N@tMonotype Sort+
N tSymbol 5T?? Y@ - 1 U J:D T1EW-hT T< *
|
!
|
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|
|
+$ PL/^&9^$? { Ak^&,,'%/v&& *
|
CORGROUP $$CLK_I_BufferFalling
|
1y
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U
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|
Percent 100
|
4l %Y?P:?-\
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|
!
|
T*
|
|
x x x
|
CORGROUP $$CLK_I_BufferRisingFalling
|
0jPvȲl^/!3jBj6D///$Q 0p?Mdj^cj4Ak[~ϐ$YkU1% 1F-(kp
ٻ A. $5-B i`# 9)F/Pv// ߾/u?2trߜKS52 7xߢ#6@h$MuLh Ճ %ԊՑ ) <OU # 5 G ::U2 q ?/&w&
|
Percent 100
|
<<7H 1O QjP SH QywH At///Y OG$_ p4b%F! 8q/#P?C/N^qhE! @d)n{r1P1 @ /Oqt}Q!n =k@Ʊ셩{B'ɂXVP_0TNJg21 1R5P"QQ[O" P!q[rr qqӂqq¢ӁӁP¡¡Waa7$VW7P$q"$qP1q1qP>q">qPKqKqPXq Xq2eqeqZ2Sob ZZdSTQcd PQQ P1H[<k?ta}Y M/OO*Dd3qO/NkS\O 9E/ / _ ? ?-??=___ѷ'sϖdI,O 0R 7nO&ګa ̗ѫaW?O // ?*
|
!
|
K ϥϷϾCNa \ "4FXj ߲K߳ BTf_/q/ //, ڭaRdv *<+/`bbiA nFUj?|?~/ "C??Va]? Ia(G
|
|
rpl/YDE@a1LO pO #Q/I SGQۍBQfQaIq_Uyj ( ȄBb_(_:_/^_ //Q__a1 _ OO-OF ZO Qo~MA %o C AOOMgy N_r_O7 Zg @ :o,Ko -XyCŮbddpddp A͟ߟ'@9K]vAB(Onl=# ??6HZl Ǝ' ;M_q 2DV hzόϞϰ
|
CORGROUP $$CLK_I_BufferRising
|
.@Rdv ߚ߬߾#} (:L^p Uɑۏ"4FXj@|X *<N`r & 8 J \ n Y / ///A/S/e/w///F/L// ? ?$?6?H?Z?l?~?? ?????? O"O4OFOXOjO|O OOOOO _ _ 0_B_T_f___ _____oo'o 9oKo]oFxoOoo oooo,>PPfx ,> nBsgcEf Ώ (ٴJ\n ȟڟ" OeOj|@į֯ ( :L^pʿܿ B#vXT+Sb b z @v 6M_Toρ6 ϱi -?Qcu ߙ߽߫ ϭ, /-?eY[Ưy +=Oas 1ńR Z sc<Ɠ`Zl~ sb6-1R# # 5 G Y k } x;6/ F%/jI/[/m////) ////
|
Percent 100
|
? ?.?@?R?d?v??? YTV
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!
|
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|
|
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|
CORGROUP $$CLK_I_BufferFalling
|
<h b
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|
Percent 100
|
g,s724?`b?M1^%Y? r? 91M1E; 6==5(2?;zrA
|
!
|
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|
|
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CORGROUP $$CLK_I_BufferRisingFalling
|
H<(
|
Percent 100
|
U~EQ .
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|
!
|
`
|
|
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|
CORGROUP $$CLK_RISC_BufferRising
|
UH ^ -}|5 p`I` V ?}`xa 833 ސ ] 3σ3 u 33?, ? Gxpx ^ &
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|
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|
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|
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|
2r q ?@I k?$%?
|
CORGROUP $$CLK_RISC_BufferFalling
|
@ "V *5L -b r/ ^vԜv"(2u &."q28iv"uh 9Bd &< O/M {
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Percent 100
|
#145 `Vis_SBl.chm!#22474 `7Copyright 1999 @io Corporation. All $AUd3 CE \^ 4
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!
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|
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CORGROUP $$CLK_RISC_BufferRisingFalling
|
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|
Percent 100
|
*e3a$$$ !aU !
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|
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CORGROUP $$CLK_RISC_BufferRising
|
-6...-7"0
|
Percent 100
|
DC_SETS-1e5qU3
|
!
|
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|
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|
CORGROUP $$CLK_RISC_BufferFalling
|
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Percent 100
|
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|
|
͂ůM " ߄@]?755a4~}a9^"=:mӆ@@|= ħC
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CORGROUP $$CLK_RISC_BufferRisingFalling
|
V<x!2 6i$ pxCv' u@˨+E秜(OS
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Percent 100
|
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|
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|
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CORGROUP $$CLK_I_BufferRising
|
Ϳ/ , +a/s/// ////o ':O 8?yTq <%L%@,Q 43
|
Percent 100
|
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|
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CORGROUP $$CLK_I_BufferFalling
|
29/
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Percent 100
|
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|
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|
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|
CORGROUP $$CLK_I_BufferRisingFalling
|
v@Yd
|
Percent 100
|
!Y0:R%;\ O%U2 ߐ߹E*%U$U^QI|+|"m(9 &))|A2Q !|
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|
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|
CORGROUP $$CLK_RISC_BufferRising
|
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|
Percent 100
|
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|
!
|
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|
|
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|
CORGROUP $$CLK_RISC_BufferFalling
|
8A,VA*OAe L/@)3RpAw :g kP'@z3[Q4b:oLn{#VgW$on VgmWo??U><+N?¬SAczre?w????? ???wX.GC >O>iEWOGE<4yl`@
|
Percent 100
|
zr?yAM h ]aZ R7Yf@DzVtTCq-B)1F o̕ ?qzI2r q fI7,X7SCVQrE5& YxyBqE"4zvP;3M4S kPp` A1 I?ǣAu<ChYԿC(jq,w|;娉KE}|ߍtS>u7 6͕$ ]fm۶m| ;ݩϻϼVeX` `MO_OqOOOOOO_?@^X_r =_O_a_s_`_____?,)A/I?_ eO?y%@$AST ԯ,8
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|
!
|
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|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
EXTEN I/FFȁCȁ~d Ə؏C @@|=i$E J Tfl艙l&JC ( )$@ 4b phe&Po/.f'P<{"77
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|
Percent 100
|
|
!
|
SELECTS U> U#$%&U*-.0U1234 Ul4,_j @K%@ Q 1DC- 3 e7 A U2@TP kD7 IR H<(
|
|
U2EP D7
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CORGROUP $$CLK_I_BufferRising
|
4( U1( UO"D&aU=QJf )h" Ty+Uv' _ Ʌ &aQ-
|
Percent 100
|
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|
!
|
F
|
|
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|
CORGROUP $$CLK_I_BufferFalling
|
<; * G#; B l; S
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|
Percent 100
|
; qu
|
!
|
; ~Q
|
|
; u
|
CORGROUP $$CLK_I_BufferRisingFalling
|
; ; u
|
Percent 100
|
U, UD u
|
!
|
\ Zu
|
|
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CORGROUP $$CLK_RISC_BufferRising
|
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Percent 100
|
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|
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|
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CORGROUP $$CLK_RISC_BufferFalling
|
_ *<NES ]L
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Percent 100
|
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|
!
|
JO :]R P
|
|
4du &S !B T ?Q
>C F C m `s Ĭ Pfk$O f'D^N4_ PE)1Y1i=Ի` 2 H DV
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
O?~ Lt $ w5 C=% 5 J! 5 @ Oh +'0 @ H h t Valued Sony Customer G (E x w
|
Percent 100
|
w
|
!
|
EMF E X V I S I O D r a w i n g M D ? ? l ( @ ( ʦ 7 -1 Box Dynamic connector 8 _VPID_ALTERNATENAMES ` _VPID_PREVIEWS _PID_LINKBASE A
|
|
F Microsoft Visio Drawing VISIO 6.0 Shapes Visio.Drawing.6 9q 1 h& & " WMFC C 8 x Z j 1 EMF 8 ~ X V I S I O D r a w i n g
|
CORGROUP $$CLK_I_BufferRising
|
\ l & % '
|
Percent 100
|
% V 0 Z j jZjZ j% ( % ( % R L A r i a l d x % T 8 *A*A
L h O p e n R I S C 1 2 0 0
& % ' B
|
!
|
% V 0 r r T TrTrr r T% ( % ( % R L A r i a l X<( % T x ` *A*A L \ C P U / D S P & % ' B
|
|
% V 0 5 55 % ( % ( % R L A r i a l % T p *A*A L X D C a c h e
T ` *A*A L T 8 K B
& % ' B
|
CORGROUP $$CLK_I_BufferFalling
|
% V 0 5 T T5T5T% ( % ( % R L A r i a l CA CA ! CA CA 0 ! @CA CA% T d = W *A*A = L T D M M U & % ' B
|
Percent 100
|
% V 0 ' T ' T T ' ' T% ( % ( % R L A r i a l ?f b`CAfc`;@AA a`b`CAfc`<PA b`CAgc`=@AA a`b`CAgc`>@A a` b`CAec`RAA lCA2A % T ` e = W *A*Ae = L T P I C & % ' B
|
!
|
% V 0 ' ' ' ' % ( % ( % R L A r i a l b` CAfc`;@AA a`b` CAfc`<PA b` CAgc`=@AA a`b` CAgc`>@AA a` b` CAec`RAA P 2A2A ! CA CA CA 0 ! CA@CAdCA P ! CA CA % T 5 *A*A5
|
|
L ` T I C K T I M E R & % ' B
|
CORGROUP $$CLK_I_BufferRisingFalling
|
% V 0 ' r ' r ' r ' % ( % ( % R L A r i a l b`PCAec`RAA A pb`0b` A ! CA CACA CA ! @ 2A CATCA ! CA@CACA& CA ! CA CA ! @CA@CA % T l L *A*AL L X D E B U G & % ' B
|
Percent 100
|
% V 0 ' \ ' \ \ ' ' \ % ( % ( %
( % R L A r i a l ? ? b`CAfc`CAA CACA$pCACAdCA 1 CA2AdCA ! vCAvCAČCA @ ! vCA0CA CA% CA ` ! CA CA % T p A E _ *A*AA E L X P O W E R M & % ' B
|
!
|
% V 0 r 5 5 5r r % ( % ( R L A r i a l
|
|
|
CORGROUP $$CLK_RISC_BufferRising
|
b`CAec`RAA @ 2A2A ! CAvCACA @ ! vCA0CA CA$ CA ` ! @CA@CA ! `CA`CA ! CACA b`b` % ( % R L A r i a l f b`CAfc`;@AA a`b`CAfc`<PA b`CAgc`=@AA a`b`CAgc`>@A a` b`CAec`RAA ! CA CA CA% T p
|
Percent 100
|
*A*A L X I C a c h e
T ` *A*A L T 8 K B
& % '
|
!
|
B
|
|
%
|
CORGROUP $$CLK_RISC_BufferFalling
|
V 0 5 \ \ 5\ 5 \ % ( % (
|
Percent 100
|
R L
|
!
|
A r i a l v ' h x @ @ @ @ @ @ ( x @ @ ? x(L @ v % %
|
|
( % R L A r i a l PX 0 X @
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
" @ $ @ XX b b b @ ? @ ? @ ? @ ? a @ ? @ @ ? @ ? a a b b ?% T d E _ *A*A E L T I M M U & % W $ o r % ( & & &WMFC 8 % % W $ o r % ( & % % W $ o 3 9 6r6% ( & % % W $ Z ; A > ]> % ( & % % W $ Z ; ` u ]r ]> % ( & % % W $ 3 9 6 6% ( & % % W $ ; A > > % ( & % % W $ % ( & % % W $ % ( & % % W $ ; u r > % ( & % ' % V 0 5 Z 5 Z Z 5 5 % ( %
( %
( % R L A r i a l @ @
|
Percent 100
|
@ @
|
!
|
L @ T @
|
|
@ $ @
|
CORGROUP $$CLK_RISC_BufferRising
|
@ @
|
Percent 100
|
@ @
|
!
|
t @ | % T X < c Q r *A*A< c L P W B
T T F s I *A*AF s L P I & % % V 0 5 Z T 5TZTZ 5 5T% ( %
( R L A r i a l b b b @ ? @ ? @ ? @ ? a @ ? @ ? @ ? @ ? a a b b b b sUUUUU? sUUUUU? b % ( % % T X < Q *A*A< L P W B
T T C K ' *A*AC L P D & % % V 0 r ' ' ' r r % ( %
( R L A r i a l % ( R L A r i a l
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
% ( %
(
|
Percent 100
|
% % T X *A*A L P D B T `
*A*A
L T I / F &
|
!
|
%
|
|
% V 0 ' T T' T' T% (
|
CORGROUP $$CLK_RISC_BufferRising
|
%
( % R L A r i a l ` 8 @ @ @@ 8 @ @ @@ 8 @ @ ? ` b b b @ ? @ ? @ ? @ % T `
|
Percent 100
|
2 A *A*A
|
!
|
2 L T I N T UU T `
B Q *A*A
B L T I / F &
|
|
%
|
CORGROUP $$CLK_RISC_BufferFalling
|
% V 0 ' \ \ ' \ ' \ % (
|
Percent 100
|
%
( % R L A r i a l P @ @ @ @ @ @ @@ 8 ? @ @@ % T X : I *A*A : L P P M T `
J Y *A*A
J L T I / F &
|
!
|
%
|
|
W $ Y u r \ % (
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
&
|
Percent 100
|
%
|
!
|
% W $ % (
|
|
&
|
CORGROUP $$CLK_RISC_BufferRising
|
%
|
Percent 100
|
% V 0 & & & % (
|
!
|
%
( % R L A r i a l H < @ @ @@ h @ @ ? HC: % T *A*A
|
|
L ` S y s t e m I / F k\ -
|
CORGROUP $$CLK_RISC_BufferFalling
|
- $ jZjZ j - - . - Arial d? ?? ?? ? - 2
|
Percent 100
|
OpenRISC 1200
- B
|
!
|
- $ TrTrr r T - - - Arial - 2
|
|
CPU/DSP - B
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
- $ 55 - - - Arial - 2
|
Percent 100
|
DCache
2
|
!
|
8KB
- B
|
|
- $ T5T5T - - - Arial -
2
|
CORGROUP $$CLK_RISC_BufferRising
|
= DMMU - B
|
Percent 100
|
- $ ' T T ' ' T - - - Arial - 2
|
!
|
=e PIC - B
|
|
- $ ' ' ' - - - Arial ??????L?A ????????l? - 2
|
CORGROUP $$CLK_RISC_BufferFalling
|
5
|
Percent 100
|
TICK TIMER - B
|
!
|
- $ ' r ' r ' - - - Arial ??????? ? A ???? - 2
|
|
L DEBUG - B
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
-
|
Percent 100
|
$ ' \ \ ' ' \ - -
|
!
|
"System c č ρ - - Arial ? ? ? ? - 2
|
|
E A POWERM -
|
CORGROUP $$CLK_RISC_BufferRising
|
B
|
Percent 100
|
- $ 5 5r r -
|
!
|
- Arial
|
|
|
CORGROUP $$CLK_RISC_BufferFalling
|
??????? ? ? ????? -
|
Percent 100
|
- Arial - 2
|
!
|
ICache
2
|
|
8KB
- B
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
- $ \ 5\ 5 \ - - Arial ?? ?? - - Arial ?? 0? @
|
Percent 100
|
?c @ ?c -
2
|
!
|
E IMMU - % r - - - % r - - - % 6r6 - - - % > ]> - - - % ]r ]> - - - % 6 6 - - - % > > - - - % - - - % - - - % r > - - -
$ 5 Z Z 5 5 - - - -
Arial ?C @ ?C @
|
|
?C @ -
|
CORGROUP $$CLK_RISC_BufferRising
|
2
|
Percent 100
|
c < WB
2
|
!
|
s F I - -
$ 5TZTZ 5 5T - -
Arial a A ? b ? @ - - -
|
|
2
|
CORGROUP $$CLK_RISC_BufferFalling
|
< WB
2
|
Percent 100
|
C D - -
$ ' ' r r - -
Arial -
Arial
-
|
!
|
- - -
|
|
2
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
DB 2
|
Percent 100
|
I/F - -
$ T' T' T - - -
Arial - 2
|
!
|
2
|
|
INT 2
|
CORGROUP $$CLK_RISC_BufferRising
|
B
I/F - -
$ \ ' \ ' \ - - -
Arial P? ?? ?? -
|
Percent 100
|
2
|
!
|
: PM 2
|
|
J
I/F - % r \ - - - % - - -
$ & & - - -
Arial ? H ?C ? ? ? - 2
|
CORGROUP $$CLK_RISC_BufferFalling
|
|
Percent 100
|
System I/F Visio (TM) Drawing
|
!
|
B TH ?A t R x ! fff MMM 333 ? Ba$
|
|
$
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
U,8@ Td Arial@N Wingdz s@N@tMonotype Sort+
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Percent 100
|
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!
|
+ PL/^&9^$? { Ak^&,",'%/v&Q&
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|
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CORGROUP $$CLK_RISC_BufferRising
|
4l %Y ?:?-\
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Percent 100
|
T *
|
!
|
x x x
|
|
0jvȲ^/!M3jj6D///$Q0p?Mdj^cjnj4BAk[~ϐ $YkU1%1@F-( kp
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CORGROUP $$CLK_RISC_BufferFalling
|
.@Rdv k}*
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|
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|
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CORGROUP $$CLK_RISC_BufferRisingFalling
|
Hu P (: { W_q QRectangle. with text and connion points. Can be stretched to y dimen s s. mb?贁No ? k? 4
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Percent 100
|
<h b
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|
g,s724?`b?M1EY? r? 91M1|; 6==5P2?;zrA
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|
IB=OCq ,^35/V:N AC =AK?OI= "3AO<_ OOKAE[ 6:_ L_Ij_|U|\_o o_AnHl& ' n ! Oya GE-szF # % JB
|
CORGROUP $$clk_risc_BufferRising
|
o [atk @ +|k 3a 5 \ & Ul4,-@ p AJ-3
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Percent 100
|
7 "A & Ul4,-@
|
!
|
_J A-$3 P7UzZ@\q >R0B*
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|
H<(
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CORGROUP $$clk_risc_BufferFalling
|
UzZEq
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Percent 100
|
`
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|
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|
UH ^ -}|5 p`I` V ?}`xa 833 ސ ] 3σ3 u 33?, ? Gxpx ^ &
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CORGROUP $$clk_risc_BufferRisingFalling
|
u
|
Percent 100
|
`u b A @]u
.(# DB uu `h?\hr|u Va @ -?bl;'b E-ho'$ y(
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!
|
2r q ?@I ?$%?
|
|
@ " U*5L -b r ^vv"(2u I."q28v"uh 9Bd &< /MS z
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CORGROUP $$clk_risc_BufferRising
|
#145 | `Vis_SE.chm!#20)@ `7Copyright 1999 @io Corporation. All ;Bs reserved. 4 U#1 # 7) A,@A+4j'vQ8l>$UdvE \ b4
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Percent 100
|
* 1B$b 24R(@][v[D ZQi@ a59 93O ' 2"q?.g;2GHls w' * O ` EW
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|
|
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CORGROUP $$clk_risc_BufferFalling
|
@25?
|
Percent 100
|
?. K ] o %j
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!
|
)@-?--"(qu ` h`"j"p"u z)R?$5%&..(sU16t 1?e"ge?' PԖ4 " (&Tu `
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|
'1)E{&0 3Color Schemes... 1`'Set the cNBsTB fP@this documesnt\@`2`
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|
CORGROUP $$clk_risc_BufferRisingFalling
|
5P9QEAEAc 𩁸 Áa{!{!!݁c"#'=R( 1)+Q*8F+EMQE1oD??P@%I!5 Q0 ConnectorD Aʒ
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Percent 100
|
КpQU i %| -u@vI!E*@?$5%p (X3 (.;8 b b b zYP@G2 qq?p?\.5?{ A`!D %<
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|
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|
(#5G@]o<ʠ5%* 5%5%
|
CORGROUP $$clk_risc_BufferRising
|
'H 1&1Q0RRQ ]3E bB bVX1d #ӁT%+ JY5Q%`!CP U/DSP );M $HZ~ϐ φ/.a/& N6H /l:oXd/??9EAR
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|
*G#_;/UQ)8Oi5 x)hDb__ U)))DVhz F7 T 4 F W1`DCach e
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!
|
8KB //H?6/ Q/u/=/ b/y/??'?9?K?%Ǫ;O~?O 5Cm[=Ўߑ>w[OF (O
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|
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CORGROUP $$clk_risc_BufferFalling
|
8KBSe w Ǐ=as 1ߏ| 'yKo뉟 j{ &){Ci p3Z SWrԯ
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Percent 100
|
.Rdoд wo"4FXjρTC/b)r2y
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CORGROUP $$clk_risc_BufferRisingFalling
|
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|
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|
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OFFSETE 0
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INITIAL LOW
|
! s["4FXj|C:\Program Files\Visio\Solution Extras\Backgrounds.vss # s[ #5GYk}C:\Program Files\Visio\Solutions\Block Dia\Basic Shapes.vss ( s["4FXj|C:\Program Files\Visio\Solution Extras\Borders and Tit .vss v(B* 8 yC!܁ + ~/ ?9 / U1( UO"D&aU=QJf )h" Ty+U
|
MAXUNCERTRISE 0
|
"_ Ʌ &aQ-
|
MAXUNCERTFALL 0
|
- H*9( TYkPEQ /, Guide TheDoc Page-1 Gesture Format Visio 90 Connector Visio 00 Visio 01 Visio 02 Visio 03 Visio 10 Visio 11 Visio 12 Visio 13 Visio 20 Visio 21 Visio 22 Visio 23 Visio 50 Visio 51 Visio 52 Visio 53 Visio 70 Visio 80 Basic Basic Shadow Rectangle SchemeName Rectangle.28 Rectangle.4 Rectangle.5 Rectangle.6 Rectangle.7 Rectangle.8 Rectangle.9 Rectangle.10 Rectangle.11 Dynamic conn?ector Rectangle.16 Rectangle.17 Rectangle.18 Rectangle.24 Rectangle.25 _ %,3 :
|
MINUNCERTRISE 0
|
E -
|
MINUNCERTFALL 0
|
S G M U
4M U LM c
|
JRISEE 0
|
dM Uc
|
JFALLE 0
|
|M c
|
GRID 1 1 1 2 2 16711680 0 0
|
M c
|
ENDGRID -1
|
M ;d ĪM
|
DIRECTION input
|
M "
|
MASTERCLOCK None
|
M /
|
Clock Unclocked
|
<
|
EdgeLevel neg
|
$I
|
Set Not Used
|
<V
|
Clear Not Used
|
Tc
|
ClockEnable Not Used
|
lp
|
ActiveLowSetClear True
|
}
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
| I x< \< t%*'%*7%*G%*W%*g|% x*U % A % UD *\ *t ʪ* ۑ* &"U 0 fx!(!*! !"#!&'()*+U^U
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
U
UU Ul4,@ > KC-44/? A Ul4, u?
|
StateEquation Hex(Inc(0,2,5))
|
AJ-3 7 A _ *<N@:? GRVg
|
HighVoltageThreshold 5
|
H<(
|
LowVoltageThreshold 0
|
_ *<NE @
RVgPq & AM 3 ' AM 3 ( PPT ) PPT 1 _( *'9 K]o # 5 G Y k }
/ /1/C/U/g/y//// o@
A" |* * J"&') { z
|
MSB 0
|
* g"4pFX (S0@(9xqR 2^z J}$Q :R T
|
LSB 0
|
R u &O (!B U[ I >l8B >O 9B No5O g^$ f$
|
isFallingEdgeSensitive False
|
' 7 SN 8)49 J1 =` 2 < V ?W , FD_ # C}=\ f .U Oh +'0 @ ` l x Valued Sony Customer A C:\Program Files\Visio\Solutions\Block Diagram\Basic Diagram.vst ՜. +,D ՜. +,( @ L X d
Pages Masters Page-1
|
isRisingEdgeSensitive True
|
Rectangle Dynamic connector 0 l x _VPID_ALTERNATENAMES B` _PID_LINKBASE A
|
DrawAnalog 0
|
Q<= Kuy Timing Diagram Timing.Document.1 9q Timing Diagram
|
BooleanEquation
|
F Microsoft Visio Drawing VISIO 6.0 Shapes Visio.Drawing.6 9q Oh +'0 @ ` l x Valued STiming Diagram Editor v7.1g - Output File
|
NegTolerance 0
|
|
PosTolerance 0
|
PROJECT
|
UserSpecifiedSizeRatio 1
|
BaseTimeUnit 1
|
VerilogCode
|
DisplayTimeUnit 2
|
VHDLCode
|
TextGridX 250.000000
|
PROPS!
|
TextGridY 6
|
!
|
EdgeGridX 250.000000
|
|
ImportStartTime 0.000000
|
SIGNAL dbg_wp_o[11]
|
ImportEndTime 281474976710656.000000
|
DIRECTION output
|
TimePerPixel 6.497175
|
RADIX hex
|
Visible DELAYS SETUPS HOLDS SAMPLES TEXT HIDDENATTACHMENTS CRITICALPATHS GRIDLINES UNCERTAINTY
|
GRID 0 1 0 1 0 16711680 0 0
|
ColWidths 144,216,288,423,488
|
ENDGRID -1
|
ScrollPos 0.000000,0.000000,0.000000
|
Clock Unclocked
|
DefDelayRule 1
|
EdgeLevel neg
|
NoEventOverlap NO
|
Set Not Used
|
SigLabelFontHeight 10
|
Clear Not Used
|
LabelHeight 12
|
ClockEnable Not Used
|
LoadLibsToMem 1
|
ActiveLowSetClear True
|
UseFullPathNames 1
|
AsyncSetClear True
|
LibPath
|
ActiveLowClockEnable True
|
EntireTime YES
|
VhdlType std_logic
|
PrintTimeSpecified NO
|
VerilogType wire
|
FromTime 0
|
SystemCType sc_logic
|
ToTime 5.75
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
AllSignals YES
|
StateEquation Hex(Inc(0,2,5))
|
CurrSelSigs NO
|
HighVoltageThreshold 5
|
PrintTo 2
|
LowVoltageThreshold 0
|
PrintFileName C:\DOCS\reset_gated.wmf
|
SignalActionType 0
|
PreviewInterchange YES
|
MSB 0
|
PreviewTIFF5 NO
|
LSB 0
|
UseMargins NO
|
isFallingEdgeSensitive False
|
PrintTimeLine NO
|
isRisingEdgeSensitive False
|
PrintBorderBox YES
|
DrawAnalog 0
|
PrintSigNames YES
|
BooleanEquation
|
PrintSigNamesOnEachPage YES
|
NegTolerance 0
|
AddPreviewToEPS NO
|
PosTolerance 0
|
PreviewRes 150
|
UserSpecifiedSizeRatio 1
|
MarginLR 1.25
|
VerilogCode
|
MifImageWidth 6.00
|
VHDLCode
|
MarginTB Auto
|
PROPS!
|
Header %d %t;%f;%p
|
E0 0 1750 1750 1 0 DR 0
|
Footer
|
E1 1 3750 3750 1 0 DR 0
|
ScaleHorz 100
|
E2 0 4750 4750 1 0 DR 0
|
ScaleVert 100
|
!
|
ScaleHPage 1
|
|
PrintImage DIAGRAM
|
SIGNAL dbg_bp_o
|
DefaultTimingModel minmax
|
DIRECTION output
|
DefaultClock Unclocked
|
RADIX hex
|
DefaultEdgeLevel neg
|
GRID 0 1 0 1 0 16711680 0 0
|
DefaultSet Not Used
|
ENDGRID -1
|
DefaultClear Not Used
|
Clock Unclocked
|
DefaultClockEnable Not Used
|
EdgeLevel neg
|
DefaultClockToOutLH 0
|
Set Not Used
|
DefaultClockToOutHL 0
|
Clear Not Used
|
DefaultSetup 0
|
ClockEnable Not Used
|
DefaultHold 0
|
ActiveLowSetClear True
|
DefaultRegStartupState unknown
|
AsyncSetClear True
|
DefaultPodSize 8
|
ActiveLowClockEnable True
|
DefaultActiveLowSetClear True
|
VhdlType std_logic
|
DefaultAsyncSetClear True
|
VerilogType wire
|
DefaultActiveLowClockEnable True
|
SystemCType sc_logic
|
SigLabelFontHeight 10
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
PROPS!
|
StateEquation Hex(Inc(0,2,5))
|
!
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
STYLE
|
SignalActionType 0
|
DefaultFont USER {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
|
MSB 0
|
DrawWndFont DEFAULT
|
LSB 0
|
DrawWndColor DEFAULT
|
isFallingEdgeSensitive False
|
GridWndFont DEFAULT
|
isRisingEdgeSensitive False
|
GridWndColor DEFAULT
|
DrawAnalog 0
|
LabelWndFont USER {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
|
BooleanEquation
|
LabelWndColor DEFAULT
|
NegTolerance 0
|
ParamDispPref 0
|
PosTolerance 0
|
ParamWndCellDisplay 0
|
UserSpecifiedSizeRatio 1
|
CustDispString %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
|
VerilogCode
|
CustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
|
VHDLCode
|
MarkerDispPref 4
|
PROPS!
|
MarkerCustDispString %n v=%mv,%Mv d=%md %t
|
E0 0 2750 2750 1 0 DR 0
|
MarkerCustomDisplayStringRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
|
E1 1 4750 4750 If Enabled 1 0 DR 0
|
SignalColor 2
|
!
|
LabelOffset 4
|
|
BusDisplay 0
|
SIGNAL dbg_ewt_i
|
WaveFormWidth 0.500000
|
DIRECTION input
|
WaveFormColor 0
|
RADIX hex
|
InputWaveFormColor 16711680
|
GRID 0 1 0 1 0 16711680 0 0
|
SlantedEdges 1
|
ENDGRID -1
|
SlantAngle 75
|
Clock Unclocked
|
RightJustifySigNames 1
|
EdgeLevel neg
|
AutosplitEnabled 1
|
Set Not Used
|
AutosplitChar _
|
Clear Not Used
|
DynamSizedSignals 1
|
ClockEnable Not Used
|
!
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
DIAGRAMTESTBENCHSETTINGS
|
ActiveLowClockEnable True
|
FilesBeforeDiagramModel
|
VhdlType std_logic
|
FilesInsideDiagramModelDeclarationSection
|
VerilogType wire
|
AbortHdlCodeEnabled 1
|
SystemCType sc_logic
|
DelayHdlCodeEnabled 1
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
SampleHdlCodeEnabled 1
|
StateEquation Hex(Inc(0,2,5))
|
MarkerHdlCodeEnabled 1
|
HighVoltageThreshold 5
|
VerboseSamples 0
|
LowVoltageThreshold 0
|
VerboseDelays 0
|
SignalActionType 0
|
VerboseFileInput 0
|
MSB 0
|
VerboseSequenceVerification 0
|
LSB 0
|
IncludeDelayTime 1
|
isFallingEdgeSensitive False
|
ExecuteFromTopLevel 1
|
isRisingEdgeSensitive False
|
TimeOutInDiagramLengths 0
|
DrawAnalog 0
|
DefaultCycleClock Unclocked
|
BooleanEquation
|
DefaultCycleEdge neg
|
NegTolerance 0
|
!
|
PosTolerance 0
|
|
UserSpecifiedSizeRatio 1
|
MACROS
|
VerilogCode
|
!
|
VHDLCode
|
|
PROPS!
|
CORGROUP $$CLK_I_BufferRising
|
E0 0 1250 1250 1 0 DR 0
|
Percent 100
|
E1 1 3750 3750 1 0 DR 0
|
!
|
E2 0 4750 4750 1 0 DR 0
|
|
!
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
MARKER MARK10
|
!
|
ATTACH dbg_wp_o[11] NULL S1
|
|
TIME 1610.903040
|
CORGROUP $$CLK_I_BufferRisingFalling
|
RELATIVETIME 0.000000
|
Percent 100
|
DISPLAYAS 5
|
!
|
MARKERTYPE Timebreak(Curved)
|
|
WHILERETURN
|
CORGROUP $$CLK_I_BufferRising
|
REPEATNUMBER
|
Percent 100
|
SNAPTO 0
|
!
|
COMPRESSTIME 0.000000
|
|
COMMENT aaa
|
CORGROUP $$CLK_I_BufferFalling
|
!
|
Percent 100
|
|
!
|
MARKER MARK20
|
|
ATTACH dbg_bp_o NULL S2
|
CORGROUP $$CLK_I_BufferRisingFalling
|
TIME 2644.928640
|
Percent 100
|
RELATIVETIME 0.000000
|
!
|
DISPLAYAS 5
|
|
MARKERTYPE Timebreak(Curved)
|
CORGROUP $$CLK_I_BufferRising
|
WHILERETURN
|
Percent 100
|
REPEATNUMBER
|
!
|
SNAPTO 0
|
|
COMPRESSTIME 0.000000
|
CORGROUP $$CLK_I_BufferFalling
|
COMMENT
|
Percent 100
|
!
|
!
|
|
|
_ 1 0 4 7 9 8 3 6 8 0 F @ N O l e
|
CORGROUP $$CLK_I_BufferRisingFalling
|
P R I N T P L C o m p O b j q 1 h& & " WMFC C 8 x Z j 1 EMF 8 ~ X V I S I O D r a w i n g
|
Percent 100
|
\ l & % '
|
!
|
% V 0 Z j jZjZ j% ( % ( % R L A r i a l d x % T 8 *A*A
L h O p e n R I S C 1 2 0 0
& % ' B
|
|
% V 0 r r T TrTrr r T% ( % ( % R L A r i a l X<( % T x ` *A*A L \ C P U / D S P & % ' B
|
CORGROUP $$CLK_I_BufferRising
|
% V 0 5 55 % ( % ( % R L A r i a l % T p *A*A L X D C a c h e
T ` *A*A L T 8 K B
& % ' B
|
Percent 100
|
% V 0 5 T T5T5T% ( % ( % R L A r i a l CA CA ! CA CA 0 ! @CA CA% T d = W *A*A = L T D M M U & % ' B
|
!
|
% V 0 ' T ' T T ' ' T% ( % ( % R L A r i a l ?f b`CAfc`;@AA a`b`CAfc`<PA b`CAgc`=@AA a`b`CAgc`>@A a` b`CAec`RAA lCA2A % T ` e = W *A*Ae = L T P I C & % ' B
|
|
% V 0 ' ' ' ' % ( % ( % R L A r i a l b` CAfc`;@AA a`b` CAfc`<PA b` CAgc`=@AA a`b` CAgc`>@AA a` b` CAec`RAA P 2A2A ! CA CA CA 0 ! CA@CAdCA P ! CA CA % T 5 *A*A5
|
CORGROUP $$CLK_I_BufferFalling
|
L ` T I C K T I M E R & % ' B
|
Percent 100
|
% V 0 ' r ' r ' r ' % ( % ( % R L A r i a l b`PCAec`RAA A pb`0b` A ! CA CACA CA ! @ 2A CATCA ! CA@CACA& CA ! CA CA ! @CA@CA % T l L *A*AL L X D E B U G & % ' B
|
!
|
% V 0 ' \ ' \ \ ' ' \ % ( % ( %
( % R L A r i a l ? ? b`CAfc`CAA CACA$pCACAdCA 1 CA2AdCA ! vCAvCAČCA @ ! vCA0CA CA% CA ` ! CA CA % T p A E _ *A*AA E L X P O W E R M & % ' B
|
|
% V 0 r 5 5 5r r % ( % ( R L A r i a l
|
CORGROUP $$CLK_I_BufferRisingFalling
|
|
Percent 100
|
b`CAec`RAA @ 2A2A ! CAvCACA @ ! vCA0CA CA$ CA ` ! @CA@CA ! `CA`CA ! CACA b`b` % ( % R L A r i a l f b`CAfc`;@AA a`b`CAfc`<PA b`CAgc`=@AA a`b`CAgc`>@A a` b`CAec`RAA ! CA CA CA% T p
|
!
|
*A*A L X I C a c h e
T ` *A*A L T 8 K B
& % '
|
|
B
|
CORGROUP $$CLK_I_BufferRising
|
%
|
Percent 100
|
V 0 5 \ \ 5\ 5 \ % ( % (
|
!
|
R L
|
|
A r i a l v ' h x @ @ @ @ @ @ ( x @ @ ? x(L @ v % %
|
CORGROUP $$CLK_I_BufferFalling
|
( % R L A r i a l PX 0 X @
|
Percent 100
|
" @ $ @ XX b b b @ ? @ ? @ ? @ ? a @ ? @ @ ? @ ? a a b b ?% T d E _ *A*A E L T I M M U & % W $ o r % ( & & &WMFC 8 % % W $ o r % ( & % % W $ o 3 9 6r6% ( & % % W $ Z ; A > ]> % ( & % % W $ Z ; ` u ]r ]> % ( & % % W $ 3 9 6 6% ( & % % W $ ; A > > % ( & % % W $ % ( & % % W $ % ( & % % W $ ; u r > % ( & % ' % V 0 5 Z 5 Z Z 5 5 % ( %
( %
( % R L A r i a l @ @
|
!
|
@ @
|
|
L @ T @
|
CORGROUP $$CLK_I_BufferRisingFalling
|
@ $ @
|
Percent 100
|
@ @
|
!
|
@ @
|
|
t @ | % T X < c Q r *A*A< c L P W B
T T F s I *A*AF s L P I & % % V 0 5 Z T 5TZTZ 5 5T% ( %
( R L A r i a l b b b @ ? @ ? @ ? @ ? a @ ? @ ? @ ? @ ? a a b b b b sUUUUU? sUUUUU? b % ( % % T X < Q *A*A< L P W B
T T C K ' *A*AC L P D & % % V 0 r ' ' ' r r % ( %
( R L A r i a l % ( R L A r i a l
|
CORGROUP $$CLK_I_BufferRising
|
|
Percent 100
|
|
!
|
|
|
|
CORGROUP $$CLK_I_BufferFalling
|
|
Percent 100
|
% ( %
(
|
!
|
% % T X *A*A L P D B T `
*A*A
L T I / F &
|
|
%
|
CORGROUP $$CLK_I_BufferRisingFalling
|
% V 0 ' T T' T' T% (
|
Percent 100
|
%
( % R L A r i a l ` 8 @ @ @@ 8 @ @ @@ 8 @ @ ? ` b b b @ ? @ ? @ ? @ % T `
|
!
|
2 A *A*A
|
|
2 L T I N T UU T `
B Q *A*A
B L T I / F &
|
CORGROUP $$CLK_RISC_BufferRising
|
%
|
Percent 100
|
% V 0 ' \ \ ' \ ' \ % (
|
!
|
%
( % R L A r i a l P @ @ @ @ @ @ @@ 8 ? @ @@ % T X : I *A*A : L P P M T `
J Y *A*A
J L T I / F &
|
|
%
|
CORGROUP $$CLK_RISC_BufferFalling
|
W $ Y u r \ % (
|
Percent 100
|
&
|
!
|
%
|
|
% W $ % (
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
&
|
Percent 100
|
%
|
!
|
% V 0 & & & % (
|
|
%
( % R L A r i a l H < @ @ @@ h @ @ ? HC: % T *A*A
|
CORGROUP $$CLK_RISC_BufferRising
|
L ` S y s t e m I / F k\ -
|
Percent 100
|
- $ jZjZ j - - . - Arial d? ?? ?? ? - 2
|
!
|
OpenRISC 1200
- B
|
|
- $ TrTrr r T - - - Arial - 2
|
CORGROUP $$CLK_RISC_BufferFalling
|
CPU/DSP - B
|
Percent 100
|
- $ 55 - - - Arial - 2
|
!
|
DCache
2
|
|
8KB
- B
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
- $ T5T5T - - - Arial -
2
|
Percent 100
|
= DMMU - B
|
!
|
- $ ' T T ' ' T - - - Arial - 2
|
|
=e PIC - B
|
CORGROUP $$CLK_I_BufferRising
|
- $ ' ' ' - - - Arial ??????L?A ????????l? - 2
|
Percent 100
|
5
|
!
|
TICK TIMER - B
|
|
- $ ' r ' r ' - - - Arial ??????? ? A ???? - 2
|
CORGROUP $$CLK_I_BufferFalling
|
L DEBUG - B
|
Percent 100
|
-
|
!
|
$ ' \ \ ' ' \ - -
|
|
"System c č ρ - - Arial ? ? ? ? - 2
|
CORGROUP $$CLK_I_BufferRisingFalling
|
E A POWERM -
|
Percent 100
|
B
|
!
|
- $ 5 5r r -
|
|
- Arial
|
CORGROUP $$CLK_RISC_BufferRising
|
|
Percent 100
|
??????? ? ? ????? -
|
!
|
- Arial - 2
|
|
ICache
2
|
CORGROUP $$CLK_RISC_BufferFalling
|
8KB
- B
|
Percent 100
|
- $ \ 5\ 5 \ - - Arial ?? ?? - - Arial ?? 0? @
|
!
|
?c @ ?c -
2
|
|
E IMMU - % r - - - % r - - - % 6r6 - - - % > ]> - - - % ]r ]> - - - % 6 6 - - - % > > - - - % - - - % - - - % r > - - -
$ 5 Z Z 5 5 - - - -
Arial ?C @ ?C @
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
?C @ -
|
Percent 100
|
2
|
!
|
c < WB
2
|
|
s F I - -
$ 5TZTZ 5 5T - -
Arial a A ? b ? @ - - -
|
CORGROUP $$CLK_I_BufferRising
|
2
|
Percent 100
|
< WB
2
|
!
|
C D - -
$ ' ' r r - -
Arial -
Arial
-
|
|
- - -
|
CORGROUP $$CLK_I_BufferFalling
|
2
|
Percent 100
|
DB 2
|
!
|
I/F - -
$ T' T' T - - -
Arial - 2
|
|
2
|
CORGROUP $$CLK_I_BufferRisingFalling
|
INT 2
|
Percent 100
|
B
I/F - -
$ \ ' \ ' \ - - -
Arial P? ?? ?? -
|
!
|
2
|
|
: PM 2
|
CORGROUP $$CLK_RISC_BufferRising
|
J
I/F - % r \ - - - % - - -
$ & & - - -
Arial ? H ?C ? ? ? - 2
|
Percent 100
|
|
!
|
System I/F O b j I n f o V i s i o D o c u m e n t z B V i s i o I n f o r m a t i o n " S u m m a r y I n f o r m a t i o n ( Oh +'0 @ ` l x Valued Sony Customer A C:\Program Files\Visio\Solutions\Block Diagram\Basic Diagram.vst ՜. +,D ՜. +, d [
|
|
Visio (TM) Drawing
|
CORGROUP $$CLK_RISC_BufferFalling
|
B TH ?A t R x ! fff MMM 333 ? Ba$
|
Percent 100
|
$
|
!
|
U,8@ Td Arial@N Wingdz s@N@tMonotype Sort+
N tSymbol 5T?? Y@ - 1 TJD T1EWP-hT T< U*U
|
|
U
=/U b
b 酸 0zGz?@8H2!kWbU%U
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
+ PL/^&9^$? { Ak^&,",'%/v&Q&
|
Percent 100
|
1y
) ? 2
J12?k9 a UBBHEHEHEUHEHEHEH@?>?:`2BBHEHEHEHEHEHEHEH@$%O9F 7AOY@;
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CORGROUP $$CLK_I_BufferFalling
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CORGROUP $$CLK_I_BufferRisingFalling
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CORGROUP $$CLK_RISC_BufferRising
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CORGROUP $$CLK_RISC_BufferRising
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CORGROUP $$CLK_RISC_BufferFalling
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- H*9( TYkPEQ /, Guide TheDoc Page-1 Gesture Format Visio 90 Connector Visio 00 Visio 01 Visio 02 Visio 03 Visio 10 Visio 11 Visio 12 Visio 13 Visio 20 Visio 21 Visio 22 Visio 23 Visio 50 Visio 51 Visio 52 Visio 53 Visio 70 Visio 80 Basic Basic Shadow Rectangle SchemeName Rectangle.28 Rectangle.4 Rectangle.5 Rectangle.6 Rectangle.7 Rectangle.8 Rectangle.9 Rectangle.10 Rectangle.11 Dynamic conn?ector Rectangle.16 Rectangle.17 Rectangle.18 Rectangle.24 Rectangle.25 _ %,3 :
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Percent 100
|
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|
M c
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CORGROUP $$CLK_RISC_BufferRising
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M /
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Percent 100
|
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$I
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CORGROUP $$CLK_RISC_BufferFalling
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|
lp
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CORGROUP $$CLK_RISC_BufferRisingFalling
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Percent 100
|
|
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CORGROUP $$CLK_RISC_BufferRising
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|
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CORGROUP $$CLK_RISC_BufferRisingFalling
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CORGROUP $$CLK_RISC_BufferRisingFalling
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CORGROUP $$CLK_RISC_BufferRising
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*r$ҷ}<]`7 O{ʡ^.?.'ĞrWSWE]9kHc> Hx J π.7Fx jꪨ"Grm },}< /aF
Jx3zHkhP
*r$ҷ}) }P ߣ)dx3}b 8Të ɵ}$m <1T+cpF v|(8Ojꪨ"Grm },}D TUz\P gO}ɍ'V*iM#w*5j8_EU9kHc>f̦S=h C%= @/ lA x|ɵ}$g3'O{{ޕ~Y/,GO'Ğ,>N] @]?udK>c 4 爽g89; fbrR#PO]?9gAo8ce< ᐁg89; fbrR#PO]?9gAo8S <!pKsKӗw32ˑF0 ~r%V K O0
|
|
|A,,&/,geQ#7K` >@]?udK>c*g9=s gOӜ`p`PˑF0 g''[,hm 3Pf 4!gO,Pp`0zЀ8{: f:?[,hg|@wGP
j]o
|
CORGROUP $$CLK_RISC_BufferFalling
|
zW .7[o"DRꖒA
|
Percent 100
|
fr$ςVgk"p5%6ϡ D`ˍgm:C{KlC
|
!
|
fr$ҷ}܂6<2b+ Mz, ]n k mh2b+ Ru5#>c% V5xXZ:4uvJV5h-Z Ru5#>c mxvrh7
|
|
Hk[6wĺ Ru5#><xSM`=~vHvh?$C
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
fr$ҷ}! M =\n ! Ru5#> 0^#C)=^\ncekpHS5SL>Xx8> M{98r#}OX>;:&8{{0Od TK[Jj)8L]39kHc>fC=h C= @/ lA Rpt<u>X7?Yo>{^5!vC;\>bwrúoeɧIln;P#wRA]9xs:[ήtP9`.yv&z]n=k2uhsswRA]9kHc>nBp R`vo =.7ҿ5LNeV8t;렮 ɵ}$m +zBա `ˍW&'XC':ȑ\Gr K [6< ;u9ۙhlq&d$ :ȑ\Gr K vxxc 4 爽o 8r#}gɤ>#C':yWGr Kqx{á /c.7?|h 冷r$ҷ}) }oޣ)dM>K π} 冷r$ҷ}|sS<<_o~G9Ě|̧h<_ 冷r$ҷ}LAw 9SmPKn?5<
|
Percent 100
|
;u}A'] ɵ}$m 3Pf 4 ΞJYΗHk2Ѯ
/p脳a%Coλ`
>ʂO9"O9
|
!
|
@
|
|
C A ? " 2 M9h ]ʣi `! M9h ]ʣiFk Z = Pc B X xkXA誱 fF Y7$AW\77J[Aݸ 5U(Zl+PBZrN{Ր(s,/dCyw1\ş8{1Qg5,_ߟQ?t]/Aewv]6ɨՏ{_mupނf &r{onnj5jTSSyRԌ3ƌǨ0
|
CORGROUP $$CLK_RISC_BufferRising
|
˫_ܿ
|
Percent 100
|
S?qNCZR7: p aX
V%I[xվ? 1dK ڧӪK5Ъ Cl oƎvK)HnD !r
|
!
|
Jf+e&9 R ;!/^@x9J>!NjeزɖSBBByBR9H/sEQ:mwrE(?-b.h m)bUC=c/'t%osR:Is?XGF.cC]z(:<'wv9J>U`.Tow[ }w:X
q
|
|
|G4v#u'q|U(9NL -
pop^\P %;
GvȎ7,ѼMf5Tr1
|
CORGROUP $$CLK_RISC_BufferFalling
|
XBՒ: j\jΗ. Rz8Sxq(Lͯg\l\4_0,\/B?k:K
|
Percent 100
|
_.{#VzZcC!<,P{Fq0tOGVOtlMǪt[Դ'yjΆIפʠFh5Ӣ
|
!
|
kŸtQN8=;?#;f"b_S0 0;?=¼F IY|:z &Z}?wǦtNWEHFb meiUF\x6㳆mHQY /Cۋ4gL٧BuzQLGEǖ:j= d3@?!\kASEPg
Yu貲}4h:11x!w+;&"}K^ "+\ɽInϰDjZEӷQ+ EõN1}ul^}>],"#:M賈6/2am"h}Jwl\cݒpXGU>sYE8 ߂lƔ!7` Iac[-Cza,ܴ1a'p'ޠPN+h#((ϦeJ!#eȡCDrYhD4"X mWYµFZ-XX^5Nj8K1U#Y%xY\}
|
|
PA
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
|
Percent 100
|
%0!l+(-X
`]$._ ɦWȔ>d:zP-$;3pt,~i{Bs^~|
s|18O<QR Kחa$%3[so2hu(Nԫ^їuU' }=k
4N }Ʀo5hu DSE{Hz
45M_-o(o7 &gh_Xp7pɶh{ _`S JCy 1jNF&vcÖٵM C.v;»AG$6~䷳5&(Z^
|
!
|
q iwG4|NÞ$ !~kdwO2lpӶ#'XJ Ko("k:a
ȳlC.w/ru{zsՋOPMᠢzㅲӢ| k
4 \'K ގ5>X,Vm^>xRr Qm])DYmiQmEo[ЯH
|
|
礧fIT[wݛ cZm E NES{9 ×zmOv\ /F%ggiv= O
|
CORGROUP $$CLK_RISC_BufferRising
|
/Ck2S/^^!\kyZM<%K0Ü&+1ܜT
|
Percent 100
|
ֿTCS0c@@3G%f` fc`Ƙ 3F3hJ,R1fKaX3"(ʟ̱ 3ヴA3fn/}pēQΖ$D7 KP7~XGeB Q m=|s]<# JM F1 |N" X7W'/m;m?nqڝ/$/ ,%I&sQk0@i=I&7G*:-!\o`+ t|YI^D D^N $q#6ϙt6g4`1l@0o}ޚ,>#|?Ɏ}b?| Bo2_!} d9SЦ<g\R?Ws7 }
|
!
|
y9l,dfĵje
4N[Fj>~ż3'-iѶ"e+ƕ5'F!k %]"6{T;mɿd~x"}PL}{C!~T_NP_D;}9_H_>r_$G}e:
|
|
L!O\h#~E^ٽw$Mķ16ɹ9/$t9I
y@$hߞ/aoļӸfQL9E3p%h?
:KymCAT_-\9_ψ۪g\ O' ᝄ "~w~ -݄ '' {OO1L(/q3!6iɭN/!*f b[KznwC%kvwu~6zt@OiWU?!|@
|
CORGROUP $$CLK_RISC_BufferFalling
|
uV p9u@Ǯ|\^ !E2Nd&+e__i:4(!? 1&iNMߞ1e*\.S(7L}!n:v'WɏG̯x7S~> w=?&%0
?I&OXX.O`NCN J +?Q= Nʯ q`(Ƀ]AߧnyaKh >+q>S9?ڍie6*J%
z>kd O"ޝd[Z] wU bRKe#<.YS F
|
Percent 100
|
*;rhFsGbK^RӘvodb sŭ!`M262wrppM:͍Է\hCXLGc|̫DZћYX\;d/b3TI)Y
|
!
|
*
|
|
}BΜأS*dŘ
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
CcWJJ{khЋhQrS _#uhU pQ ~ 9::SqonUǜ2ƪVqoruԡ i+b۷ ݒ_86&=ŝ :UvI6snVV{
|
Percent 100
|
KPj6 5TC}q:pp/(o ٠_xJ>!ʲvאOӳEuC=,g{ )]ܖs)p546& X{jx={ [KIּ~
|
!
|
|
|
N[b]!C] F.7q>8~e BV}W[ͥl
nnj-0JY<
|
CORGROUP $$CLK_RISC_BufferRising
|
|Z=
-;mɷG8
m ˊNH4E5,ILphkA.puʍ5PgZZU( ȱ-cCT nku/bPm ̊Λgl\EW QX絟i \k˛Ep
a_hԋ.Gϣ?g} D y K _ R e f 5 1 3 3 4 3 2 2 7 } D y K _ R e f 5 1 3 3 4 6 0 9 4 T D d &(I J
|
Percent 100
|
A
|
!
|
C A ? " 2 M9h ]ʣi M `! M9h ]ʣiFk Z = Pc B X xkXA誱 fF Y7$AW\77J[Aݸ 5U(Zl+PBZrN{Ր(s,/dCyw1\ş8{1Qg5,_ߟQ?t]/Aewv]6ɨՏ{_mupނf &r{onnj5jTSSyRԌ3ƌǨ0
|
|
˫_ܿ
|
CORGROUP $$CLK_RISC_BufferFalling
|
S?qNCZR7: p aX
V%I[xվ? 1dK ڧӪK5Ъ Cl oƎvK)HnD !r
|
Percent 100
|
Jf+e&9 R ;!/^@x9J>!NjeزɖSBBByBR9H/sEQ:mwrE(?-b.h m)bUC=c/'t%osR:Is?XGF.cC]z(:<'wv9J>U`.Tow[ }w:X
q
|
!
|
|G4v#u'q|U(9NL -
pop^\P %;
GvȎ7,ѼMf5Tr1
|
|
XBՒ: j\jΗ. Rz8Sxq(Lͯg\l\4_0,\/B?k:K
|
CORGROUP $$CLK_RISC_BufferRisingFalling
|
_.{#VzZcC!<,P{Fq0tOGVOtlMǪt[Դ'yjΆIפʠFh5Ӣ
|
Percent 100
|
kŸtQN8=;?#;f"b_S0 0;?=¼F IY|:z &Z}?wǦtNWEHFb meiUF\x6㳆mHQY /Cۋ4gL٧BuzQLGEǖ:j= d3@?!\kASEPg
Yu貲}4h:11x!w+;&"}K^ "+\ɽInϰDjZEӷQ+ EõN1}ul^}>],"#:M賈6/2am"h}Jwl\cݒpXGU>sYE8 ߂lƔ!7` Iac[-Cza,ܴ1a'p'ޠPN+h#((ϦeJ!#eȡCDrYhD4"X mWYµFZ-XX^5Nj8K1U#Y%xY\}
|
!
|
PA
|
|
|
CORGROUP $$clk_risc_BufferRising
|
%0!l+(-X
`]$._ ɦWȔ>d:zP-$;3pt,~i{Bs^~|
s|18O<QR Kחa$%3[so2hu(Nԫ^їuU' }=k
4N }Ʀo5hu DSE{Hz
45M_-o(o7 &gh_Xp7pɶh{ _`S JCy 1jNF&vcÖٵM C.v;»AG$6~䷳5&(Z^
|
Percent 100
|
q iwG4|NÞ$ !~kdwO2lpӶ#'XJ Ko("k:a
ȳlC.w/ru{zsՋOPMᠢzㅲӢ| k
4 \'K ގ5>X,Vm^>xRr Qm])DYmiQmEo[ЯH
|
!
|
礧fIT[wݛ cZm E NES{9 ×zmOv\ /F%ggiv= O
|
|
/Ck2S/^^!\kyZM<%K0Ü&+1ܜT
|
CORGROUP $$clk_risc_BufferFalling
|
ֿTCS0c@@3G%f` fc`Ƙ 3F3hJ,R1fKaX3"(ʟ̱ 3ヴA3fn/}pēQΖ$D7 KP7~XGeB Q m=|s]<# JM F1 |N" X7W'/m;m?nqڝ/$/ ,%I&sQk0@i=I&7G*:-!\o`+ t|YI^D D^N $q#6ϙt6g4`1l@0o}ޚ,>#|?Ɏ}b?| Bo2_!} d9SЦ<g\R?Ws7 }
|
Percent 100
|
y9l,dfĵje
4N[Fj>~ż3'-iѶ"e+ƕ5'F!k %]"6{T;mɿd~x"}PL}{C!~T_NP_D;}9_H_>r_$G}e:
|
!
|
L!O\h#~E^ٽw$Mķ16ɹ9/$t9I
y@$hߞ/aoļӸfQL9E3p%h?
:KymCAT_-\9_ψ۪g\ O' ᝄ "~w~ -݄ '' {OO1L(/q3!6iɭN/!*f b[KznwC%kvwu~6zt@OiWU?!|@
|
|
uV p9u@Ǯ|\^ !E2Nd&+e__i:4(!? 1&iNMߞ1e*\.S(7L}!n:v'WɏG̯x7S~> w=?&%0
?I&OXX.O`NCN J +?Q= Nʯ q`(Ƀ]AߧnyaKh >+q>S9?ڍie6*J%
z>kd O"ޝd[Z] wU bRKe#<.YS F
|
CORGROUP $$clk_risc_BufferRisingFalling
|
*;rhFsGbK^RӘvodb sŭ!`M262wrppM:͍Է\hCXLGc|̫DZћYX\;d/b3TI)Y
|
Percent 100
|
*
|
!
|
}BΜأS*dŘ
|
|
CcWJJ{khЋhQrS _#uhU pQ ~ 9::SqonUǜ2ƪVqoruԡ i+b۷ ݒ_86&=ŝ :UvI6snVV{
|
CORGROUP $$clk_risc_BufferRising
|
KPj6 5TC}q:pp/(o ٠_xJ>!ʲvאOӳEuC=,g{ )]ܖs)p546& X{jx={ [KIּ~
|
Percent 100
|
|
!
|
N[b]!C] F.7q>8~e BV}W[ͥl
nnj-0JY<
|
|
|Z=
-;mɷG8
m ˊNH4E5,ILphkA.puʍ5PgZZU( ȱ-cCT nku/bPm ̊Λgl\EW QX絟i \k˛Ep
a_hԋ.Gϣ?g} D y K _ R e f 5 1 3 3 4 3 2 2 7 } D y K _ R e f 5 1 3 3 4 6 0 9 4 } D y K _ R e f 5 1 3 3 2 9 3 0 6 D d t% 0
|
CORGROUP $$clk_risc_BufferFalling
|
B
|
Percent 100
|
# A 2 At+9e ;yf=c 0 `! At+9e ;yf=c: \ xYkSW>V[vk R3L4fɈFiT}S,d}"*āl`C?
|
!
|
) loA<$'XyURAP[
"RW:JDb.8|%3~Bv랦tv?
K Z!@ t/iU=oŐsxݡ+V%-]m5]{fO1o6WĹŹ9/KX%ړTj EngN n4LoQxڄr>¼\Kry/7W{B^eJ{t/ˋprNmɷd jk'ܶ|}5_X;t!QnUxYyQ#Be=
|
|
S;XH CN 8"1w
1tX" -# ]IOD@1 S@O= ͘i:@ߓӠl4 :YifK 4"njU uDmhXEMmSoae<]{FU;Eu(z$N*4\NA$ati:hȣCAܕn+}_J&g x}ڼZ
1kիX">>d]`O ף>BI(0l E͗ẁ%i!VGӨXX9λ?wKĻ45m(:<X @mBW&ϯ(]ߌڨ?44^krP"Gp_/ f/A[BIU|p77{I#_PTru\ mA
|
CORGROUP $$clk_risc_BufferRisingFalling
|
3=h X5($-jh q^y 1GYl5+5rA7f e 1{b~ty=+zW q3+:*ж<>5JSUإBZDs^<=yB4h6C=⬘#W1ٚK4&ۏW:CI>=c!?&M)mcR|A11 ?z q q^yq 1'i1s&t/zĝJ^k-Y+JTn5
|
Percent 100
|
1MD㦿jiBÏ DmBW@^BQh7\;wɩqc/µz~̵ ot՞= 1 'ͧODɰ{yhCk k7h\LZd.i!vGӨXX9mw>u& I&o;-Z*WX~㽋]i8z&?%"`7| ڒ8~%p{{eq8C+eT;M4 DmBW@^BQx~+/mrwV
7} ٍ =#6q~Fa6z,^7~MYM~G1F c-Q̼]1؊8ߡv moEuhjT ?&!,!]AC} D y K _ R e f 5 1 3 3 2 9 8 5 2 } D y K _ R e f 5 1 3 3 2 6 4 8 4 } D y K _ R e f 5 1 3 3 2 6 2 1 9 } D y K _ R e f 5 1 3 3 2 4 6 7 0 D d t% J
|
!
|
C
|
|
C A ? " 2 AI@ z#y>- 9 `! AI@ z#y>-8 h \ ( xڽXO[U~)k)tnK2UҘI E/f!2d/4$t@Q& ~9¿l ~\;I}i{{t$j'={ι\Aa@O CH!(R ~Ŀx}DPȈrjw6suwvauyh/ PS4٥=`ERK50}=j$ ם Tk5>RZ]ά6 !dZ径בz_NS|L91\:hڵ"eWO.ek^d/L5 )㳟/|@Mok bC-N'4F%ľNG sot\b v|@1 Eְx
ǵ$4m.i
e:
|
CORGROUP $$clk_risc_BufferRising
|
f ]ZJ$TW+XT gk}ڭY8ɱ*Ďmn N 蕀h5@̦8۶-g__2 _|zl3*T%uzMvMk{2},ZZ 68]J}=g4SY#+k QWX vYJ)k{Hm;-}
֧ma3I.Wb>gU[aaieQ,g(七gMf3Us14lb*nO:O/3k neQ,*GcnFka Z7~o(OP
V;s7;v53sKu6tZ{uZY,*gc ݳ3OL+S5]N,?;Y~vtZglikN>ԩHÜɵ* οNZLzGS켆Qf?Ԩg۶ݖwcWg"ѣw
|
Percent 100
|
ǰ>ƛS>(l4J%[=>=/VB 1
|
!
|
|
|
ʈ+G6v(ߓȭb@ ~4J%: @Lz16Q 2|[ W}ahH 06Q/E $Wc `ǀq&5*ĕWu1
I
i [N^9$WcI i [N^A\qe(_
|
CORGROUP $$clk_risc_BufferFalling
|
)
|
Percent 100
|
+Guqw0
|
!
|
c8ly c,0ۤF
|
|
Qn y\:! !
d`ib9 I՟XHv(W@\>?ߤ/eߗof{foMX_Tk } D y K _ R e f 5 1 3 3 0 9 4 1 0 } D y K _ R e f 5 0 7 2 5 7 6 9 4 i D d M
\ J
|
CORGROUP $$clk_risc_BufferRisingFalling
|
D
|
Percent 100
|
C A ? " 2 &]_)%ݢ4 AA `! &]_)%ݢ4L \ k x2F J* m x\]h\>sv]E' iR*nH+)l܍7F6:Y'yi!
`ȃ5% y*i
|
!
|
?\\0$Vϙ?i̝;93> >x` AFR}0@gT 2 cy09% *9KX6tHnX` g GGp^}-lH_FV<)*MC1+:hg: L 7h|y]ig.ϟb-" ) ~5jyt?0q8x*SÓv FWznp'kXHK{h[kH_9Nꃈ@: g`{c &9;e'A0&5HdN:s[}>mp~ I$oaɈn|)ma\C~w7ؽm? ςm[b#Xvl| ЀE>z S:vU~t@u"ph]
|
|
-
|
CORGROUP $$clk_risc_BufferRising
|
^C].TeN>g? \FsFҟ+N`ũ&8eh.Fsqvnodjdnl|
|
Percent 100
|
UeI>qu?*?(|#7ْ|2&Q -ς|
|
!
|
|3C|3/q e ;茑U #YG:⛠U+kZ = "p\0pܔ8
|
|
Ǘ1OtฐDž,~+lG Ы $x}COiU_#o̪Mg1V]gP{ E`3ZX]y
|
CORGROUP $$clk_risc_BufferFalling
|
+<v}Ę\)Ywg`X%5 ,q\$iX ψc/Ǟccf5<2扚n| .0F[@ =}ۚOX>7OPeI>=]sAk9t1\zsAi} |U/Z|2*|_ku7¤E?5 ~t^D{XmPC_ m#&bOTY|[Mη)LGңH?d4筲D8 += AEmmFWmKLS`MA;tS"OCF5in@1^1
|
Percent 100
|
_z^0=X|P_d,bnsA@ xu@XKݏ *K[/
bla\#,LMpjba6Pl~?~29_ V||<}|ak#|K5C+cLTeV?' jOx 0'ai| _DqBۃbajSYc? }Tm>db/1d >gC/:9/c2_cVSܰ{
8U}R~P3*K
sSYgST7D>An&R4w!~$Wf7#}Kvks%V7y* /ē\!d'M>Thz ]vYQm}o_ @!-ά|6_ܹmEyF`s?J;eh+v؆>tz8סCp+-Zm,oBn:f
]jǐ#vELF65S=zJ;K;pظg?4j&i{vfr}˭a]g1JM\@ְe
|
!
|
J}QGuGT҂&ivIV$iLV? B>{PKNqn٤/Jiw[n`H | Ѥ.B3ӋH7/^&ovy=C^_w\1zd[οfܝ5+m- IoLzYG(jlxF+jޯse|Cs oe9[j-XK/nrᒦ=d..h{lqKj
;r/8FSJW6]ʄm;p5Q$ج/vt__z龾m}+jIծ] :oإa֏R`b:j>05QH승Z쵨x { }d;5ѹ )zA<՛8L MX&ʬ51945 Ini#doϱko:5lK
##B4,F 8ШY1B ܹg϶H&Qc\ M75x 7OBcQ!9fSƨz(tEazOϥ~mq Zz@TP-q-zEz' D d `
|
|
|
CORGROUP $$clk_risc_BufferRisingFalling
|
C < A $ o c _ l o g o _ s m a l l . w m f 2 c +q8BERwZt ? M `!7 +q8BERwZt& ~ x1nAq $4t=0 #
R9 -kGT~}(Dh=edg6fݯ1ϱb}; ^߷7_~zuzø?w or?zX<?qw;oZ$I$I$I< CH8)N
|
Percent 100
|
!@H8)N
|
!
|
!@H8)N
|
|
!N 'pRNH8AvDNQ!%
|
CORGROUP $$clk_risc_BufferRising
|
' pNI8$pI8 'EfrK8U
|
Percent 100
|
KNM8ՂԄK8H'WYb I,RiK8Ki H,RK8N,|,,KN8yké,4TSYg hOfJ@ϩuRrNcK 9I eT3299!˩
E jN-9Sh "vfJ'۱5 VnE?NN.*#dNN !pLYLYLYLYLY꘥OsDyH y R+AN3]ts ֛Ʉ4lPL՞e}Ur55n m~(:2 RyRm:UN'%Zrbb Op Ē[QR {wK 5R,TKw@RQN,'K $K 4e⬅,H8MxjgxUz['r*tY{ VNGRNNE=ea@vT
|
!
|
'tUN\d˶*r28< 5N )'ËHɐp2
|
|
d )AS'åNJ! B8 p2,
|
CORGROUP $$clk_risc_BufferFalling
|
d@PH$I$x/ͻc- D y K y K 4 h t t p : / / w w w . o p e n c o r e s . o r g / QJ ^J ( K (
|
Percent 100
|
S a l u t a t i o n ` . @ . S i g n a t u r e
|
!
|
a ^ L , L T a b l e o f A u t h o r i t i e s b ^ ` D . D T O A H e a d i n g c x 5OJ QJ \^J aJ r Br P r e f o r m a t t e d ; d
# ~= z9 !v% *$ 5$7$8$9D H$ OJ QJ h
|
|
)
|
CORGROUP $$clk_risc_BufferRisingFalling
|
|
Percent 100
|
|
!
|
|
|
) 0 ? ! z ! z ! z ! z ! z ! z ! z ! z ! z !
|
CORGROUP $$clk_risc_BufferRising
|
z ! z ! z !
z ! z ! z z ! z ! z ! z ! z ! z ! z ! z ! z ! z ! z ! z ! z ! z ! z ! z ! z ! z !! z !" z !# z !$ z !% z !& z !' z !( z !) z !* z !+ z !, z !- z !. z !/ z !0 z !1 z !2 z !3 z !4 z !5 z !6 z !7 z !8 z !9 z !: z !; z !< z != z !> z _ B k% X* v1 3 7 U= A H I N YP Q T T NX X \ Vc h %i l ms os ps rs ss us vs xs ys {s |s ~s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z - ͈ & Ւ d Ǡ 1 s ί P c 0 ! - F V W 6 < 7 e
|
Percent 100
|
i H @ H N o r m a l *$5$ 7$ 8$ 9D H$ CJ _HmH sH tH Z @ Z H e a d i n g 1 . $$
|
!
|
& F
f!&d @& P a$ 5CJ` D @ D H e a d i n g 2 $
|
|
& F
f!@& 5CJ( D @ D H e a d i n g 3 $
|
CORGROUP $$clk_risc_BufferFalling
|
& F
f!@& 5CJ J @ J H e a d i n g 4 $$
|
Percent 100
|
& F
f!@&a$ 6CJ$ R @ R H e a d i n g 5 $$
|
!
|
& F
f!@&a$ 6B*CJ ph L L H e a d i n g 6 < *$ 5$7$8$9D @&H$ 6CJ P P H e a d i n g 7 < *$ 5$7$8$9D @&H$ CJ OJ QJ T T H e a d i n g 8 < *$ 5$7$8$9D @&H$ 6CJ OJ QJ V V H e a d i n g 9 < *$ 5$7$8$9D @&H$ 56CJ OJ QJ < A@ < D e f a u l t P a r a g r a p h F o n t @ O @ H e a d e i n g 1 N a m e $a$ 5CJH B OB W W - D e f a u l t P a r a g r a p h F o n t ( U@( H y p e r l i n k >*B*& )@!& P a g e N u m b e r < O1< B u l l e t S y m b o l s CJ OJ QJ kH* : R: H e a d i n g
$ x CJ OJ QJ * B@ R* B o d y T e x t x , @ b, H e a d e r
! , @ r, F o o t e r
! @ >@ @ T i t l e $ < a$ 5CJ@ KH OJ QJ . J AR. S u b t i t l e $a$ 6 4 Q4 T a b l e C o n t e n t s $ : :
T a b l e H e a d i n g $a$ 560 P@ 0 B o d y T e x t 2 $a$ > V@ > F o l l o w e d H y p e r l i n k >*B* ph @
T O C 1 & @ &
T O C 2
|
|
^ & @ &
T O C 3
|
CORGROUP $$clk_risc_BufferRisingFalling
|
^ & @ &
T O C 4
|
Percent 100
|
! ^ & @ &
T O C 5
|
!
|
" ^ & @ &
T O C 6
|
|
# ^ & @ &
T O C 7
|
CLOCK clk_risc
|
$ ^ & @ &
T O C 8
|
PERIODE 1
|
% ^ & @ &
T O C 9
|
DUTY 50
|
& ^ 4 "@ 4 C a p t i o n
|
OFFSETE 4.5
|
' x x
|
INITIAL HIGH
|
5CJ \D #@ D T a b l e o f F i g u r e s ( ^` AR
|
MAXUNCERTRISE 0
|
H e a d i n g 1 0 i )
|
MAXUNCERTFALL 0
|
& F1$ >T . Tf 5CJ B @ B
F o o t n o t e T e x t * *$ 5$7$8$9D H$ < T <
|
MINUNCERTRISE 0
|
B l o c k T e x t + x ]^ 6 Q 6 B o d y T e x t 3 , x CJ aJ H M QH B o d y T e x t F i r s t I n d e n t
|
MINUNCERTFALL 0
|
- ` @ C @ B o d y T e x t I n d e n t . hx ^h L N L B o d y T e x t F i r s t I n d e n t 2
|
JRISEE 0
|
/ ` J R J B o d y T e x t I n d e n t 2 0 hd x ^h L S L B o d y T e x t I n d e n t 3 1 hx ^h CJ aJ * ? "* C l o s i n g
|
JFALLE 0
|
2 ^ 0 20 C o m m e n t T e x t 3 CJ L D a t e 4 J Y RJ D o c u m e n t M a p 5 -D M
|
GRID 1 1 0 2 2 16711680 0 0
|
OJ QJ ^J 4 [ b4 E - m a i l S i g n a t u r e 6 0 + r0 E n d n o t e T e x t 7 CJ d $ d E n v e l o p e A d d r e s s ! 8 @ &+D/ ^@ OJ QJ ^J aJ B % B E n v e l o p e R e t u r n 9 CJ OJ QJ ^J 2 ` 2 H T M L A d d r e s s : 6]F e F H T M L P r e f o r m a t t e d ; CJ OJ QJ ^J 2
|
ENDGRID -1
|
2
I n d e x 1 < ^ ` 2 2
I n d e x 2 = ^` 2 2
I n d e x 3 > ^` 2
2
I n d e x 4 ? ^` 2 2
I n d e x 5 @ ^` 2 2
I n d e x 6 A ^` 2 2
I n d e x 7 B ^` 2 2
I n d e x 8 C ^` 2 2
I n d e x 9 D p^p` @ ! @
I n d e x H e a d i n g E 5OJ QJ \^J , / b, L i s t F h^h` 0 2 r0 L i s t 2 G ^` 0 3 0 L i s t 3 H 8^8` 0 4 0 L i s t 4 I ^` 0 5 0 L i s t 5 J ^` 2 0 2
L i s t B u l l e t K
|
DIRECTION input
|
& Fg 6 6 6
L i s t B u l l e t 2 L
|
MASTERCLOCK None
|
& Fh 6 7 6
L i s t B u l l e t 3 M
|
Clock Unclocked
|
& Fi 6 8 6
L i s t B u l l e t 4 N
|
EdgeLevel neg
|
& Fj 6 9 6
L i s t B u l l e t 5 O
|
Set Not Used
|
& Fk : D :
L i s t C o n t i n u e P hx ^h > E > L i s t C o n t i n u e 2 Q x ^ > F "> L i s t C o n t i n u e 3 R 8x ^8 > G 2> L i s t C o n t i n u e 4 S x ^ > H B> L i s t C o n t i n u e 5 T x ^ 2 1 R2 L i s t N u m b e r U
|
Clear Not Used
|
& Fl 6 : b6
L i s t N u m b e r 2 V
|
ClockEnable Not Used
|
& Fm 6 ; r6
L i s t N u m b e r 3 W
|
ActiveLowSetClear True
|
& Fn 6 < 6
L i s t N u m b e r 4 X
|
AsyncSetClear True
|
& Fo 6 = 6
L i s t N u m b e r 5 Y
|
ActiveLowClockEnable True
|
& Fp x - x
|
VhdlType std_logic
|
M a c r o T e x t 5 Z
` @
*$5$ 7$ 8$ 9D H$ OJ QJ ^J _HmH sH tH I M e s s a g e H e a d e r g [ 8$d %d &d 'd -D M
|
VerilogType wire
|
N O P Q ^8` OJ QJ ^J aJ 0 ^ 0 N o r m a l ( W e b ) \ aJ 6 6
N o r m a l I n d e n t
|
SystemCType sc_logic
|
] ^ , O , N o t e H e a d i n g ^ 8 Z 8
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
P l a i n T e x t _ CJ OJ W X N t 8 $ !) ) i N
|
StateEquation Hex(Inc(0,2,5))
|
" i
|
HighVoltageThreshold 5
|
A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
|
LowVoltageThreshold 0
|
! W " # ` $ % & ' ( ) * + G , - . @ / 0 1 2 3 2
|
MSB 0
|
3 D 2 3 D 2 # 3 4 5 6 5 6 7 6 % 7 8 9 : ; < = >
|
LSB 0
|
! / 0 1 H ^ _ ` i u v w x y ! 0 * + / 7 F ] ^ _ q r
|
isFallingEdgeSensitive False
|
A R S j% m% z% {% 4' ( ( '( (( ;* X* + + + + L, , - :. 9/ :/ 0 G0 H0 Q0 R0 0 0 1 <1 t1 v1 x1 1 1 2 2 52 U2 w2 2 2 2 3 23 `3 a3 ~3 3 3 3 3 3 U4 5 5 05 i5 j5 {5 |5 6 7 7 [8 \8 v8 w8 |9 }9 : : : : : &; x; ; ; ; ; O< h< < < < < < == U= j= = = = = = > > > > > > ? ? ? ? @ 3@ S@ @ @ @ @ A A B
|
isRisingEdgeSensitive True
|
B B B B C C C C C $C (C )C 5C 9C :C FC TC UC C C C C KD D D E E |F F SH H H H H I I I I J J J J J J J J J J J J J J J J K K K K K "K &K 'K 3K 7K 8K DK HK IK UK cK dK K K K L hL L M M N N O XP YP vP wP Q Q $Q %Q R R R %R &R 9R IR JR ]R mR nR R R R R R R S S S CS US zS S T T JT T T T T T T T T U U U U U V V V (V 8V 9V LV fV gV {V V V V V V W (W MW W W W
|
DrawAnalog 0
|
X MX NX kX lX X X X X ZY [Y \Y yY Y Y Z [ [ [ [ [ [ !\ J\ \ \ \ \ 9] :] S] T] ] ] )^ b^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ _ _ _ _ "_ #_ V_ W_ ` ` ` a a a b b b Ic Jc Uc Vc `d ad ~d d d e e e e Xg Yg
|
BooleanEquation
|
h h h h !i #i $i %i 'i 1i 2i i i i i Wj Xj wj j j k k Cl Dl cl l l l l
|
NegTolerance 0
|
n n n n n $n -n 8n 9n :n =n @n Cn Fn In Ln On Rn Un Xn [n ^n an dn gn jn mn pn sn vn yn |n ~n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n o o o
|
PosTolerance 0
|
o
o o o o o o o o o "o $o &o (o *o +o 2o >o @o Bo Do Eo Fo Io Lo Oo Ro Uo Xo [o ^o ao do go jo mo po so vo yo |o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o p p p p p p p p p p p !p #p %p 'p )p +p -p /p 1p 3p 5p 6p =p Ip Kp Mp Op Pp Qp Tp Wp Zp ]p `p cp fp ip lp op rp up xp {p ~p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p p q q q q q
|
UserSpecifiedSizeRatio 1
|
q q q q q q q $q &q 'q (q +q .q 1q 4q 7q :q =q @q Cq Fq Iq Lq Oq Rq Uq Xq [q ^q aq dq gq jq lq nq pq rq tq vq xq zq |q ~q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q r r r r r r r r r r r r r #r &r )r ,r /r 2r 5r 8r ;r >r Ar Dr Fr Hr Jr Lr Nr Pr Rr Tr Vr Xr Yr _r jr lr mr nr qr tr wr zr }r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r s s s s s s s s s s s !s $s 's *s -s 0s 2s 4s 6s 8s :s s @s Bs Ds Es Js Vs _s as js ks ls os rs us xs {s ~s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s t t t
|
VerilogCode
|
t
t t t t t t t !t #t %t 't )t +t -t /t 1t 3t 4t :t Ft Ht Jt Lt Mt Nt Qt Tt Wt Zt ]t `t ct ft it lt ot rt ut xt {t ~t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t u u u u u u
u u u u u u u (u *u ,u .u /u 0u 3u 6u 9u
|
VHDLCode
|
v v v v v v v v v v !v $v 'v *v -v 0v 3v 6v 9v
|
PROPS!
|
x x x x x x x x x #x &x )x ,x /x 2x 5x 8x ;x >x Ax Dx Gx Jx Mx Ox Qx Sx Ux Wx Yx [x ]x _x ax bx ix ux wx yx {x |x }x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x y
|
E5 1 7000 7000 1 0 DR 0
|
y y y y y y y #y &y )y ,y /y 2y 5y 8y ;y >y Ay Dy Gy Jy My Py Sy Vy Yy [y ]y _y ay cy ey gy iy ky my ny ty y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y z
z z !z "z #z &z )z ,z /z 2z 5z 8z ;z >z Az Dz Gz Jz Mz Pz Sz Vz Yz \z _z bz ez gz iz kz mz oz qz sz uz wz yz zz z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z z { { {
|
E6 0 7500 7500 1 0 DR 0
|
{
{ { { { { { { "{ %{ ({ +{ .{ 1{ 4{ 7{ :{ ={ @{ C{ F{ I{ K{ M{ O{ Q{ S{ U{ W{ Y{ [{ ]{ ^{ e{ q{ s{ u{ ~{ { { { { { { { { { { { { { { { { { { { { { { { { { { { { { { { { { { { { { { { { { { { { { | | | | | | | | | | | #| &| )| ,| /| 2| 5| 8| ;| >| A| C| E| G| I| K| M| O| Q| S| U| V| ]| j| l| n| w| x| y| || | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | } } } } } } } } } } } !} $} '} *} -} 0} 3} 6} 8} :} <} >} @} B} D} F} H} J} K} S} `} b} d} m} n} o} r} u} x}
|
E7 1 8000 8000 1 0 DR 0
|
|
E9 1 9000 9000 1 0 DR 0
|
|
!
|
|
|
|
SIGNAL rst
|
|
DIRECTION input
|
|
RADIX hex
|
|
GRID 0 1 0 1 0 16711680 0 0
|
|
ENDGRID -1
|
|
Clock Unclocked
|
|
EdgeLevel neg
|
|
Set Not Used
|
|
Clear Not Used
|
|
ClockEnable Not Used
|
|
ActiveLowSetClear True
|
|
AsyncSetClear True
|
|
ActiveLowClockEnable True
|
|
VhdlType std_logic
|
|
VerilogType wire
|
|
SystemCType sc_logic
|
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
|
StateEquation Hex(Inc(0,2,5))
|
|
HighVoltageThreshold 5
|
|
LowVoltageThreshold 0
|
|
SignalActionType 0
|
|
MSB 0
|
|
LSB 0
|
|
isFallingEdgeSensitive False
|
|
isRisingEdgeSensitive False
|
|
DrawAnalog 0
|
|
BooleanEquation
|
|
NegTolerance 0
|
|
PosTolerance 0
|
!
|
UserSpecifiedSizeRatio 1
|
"
|
VerilogCode
|
#
|
VHDLCode
|
$
|
PROPS!
|
%
|
E0 0 1750 1750 1 0 DR 0
|
&
|
E1 1 3750 3750 1 0 DR 0
|
'
|
E2 0 5750 5750 1 0 DR 0
|
(
|
!
|
)
|
|
*
|
SIGNAL dbg_dat_o
|
+
|
DIRECTION output
|
,
|
RADIX hex
|
-
|
GRID 0 1 0 1 0 16711680 0 0
|
.
|
ENDGRID -1
|
/
|
Clock
|
0
|
EdgeLevel neg
|
1
|
Set Not Used
|
2
|
Clear Not Used
|
3
|
ClockEnable Not Used
|
4
|
ActiveLowSetClear True
|
5
|
AsyncSetClear True
|
6
|
ActiveLowClockEnable True
|
7
|
VhdlType std_logic
|
8
|
VerilogType wire
|
9
|
SystemCType sc_logic
|
:
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
;
|
StateEquation Hex(Inc(0,2,5))
|
<
|
HighVoltageThreshold 5
|
=
|
LowVoltageThreshold 0
|
>
|
LSB 0
|
?
|
MSB 31
|
@
|
SignalActionType 0
|
A
|
isFallingEdgeSensitive False
|
B
|
isRisingEdgeSensitive True
|
C
|
DrawAnalog 0
|
D
|
BooleanEquation
|
E
|
NegTolerance 0
|
F
|
PosTolerance 0
|
G
|
UserSpecifiedSizeRatio 1
|
H
|
VerilogCode
|
I
|
VHDLCode
|
J
|
VhdlMapping DefaultVhdlMapping
|
K
|
PROPS!
|
L
|
E0 X 1750 1750 1 0 DR 0
|
M
|
E1 V 4750 4750 0x0 1 0 DR 0
|
N
|
E2 V 5750 5750 0x4 1 0 DR 0
|
O
|
!
|
P
|
|
Q
|
SIGNAL dbg_op_i
|
R
|
DIRECTION input
|
S
|
RADIX hex
|
T
|
GRID 0 1 0 1 0 16711680 0 0
|
U
|
ENDGRID -1
|
V
|
Clock Unclocked
|
W
|
EdgeLevel neg
|
X
|
Set Not Used
|
Y
|
Clear Not Used
|
Z
|
ClockEnable Not Used
|
[
|
ActiveLowSetClear True
|
\
|
AsyncSetClear True
|
]
|
ActiveLowClockEnable True
|
^
|
VhdlType std_logic
|
_
|
VerilogType wire
|
`
|
SystemCType sc_logic
|
a
|
TemporalEquation 8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
|
b
|
StateEquation Hex(Inc(0,2,5))
|
c
|
HighVoltageThreshold 5
|
d
|
LowVoltageThreshold 0
|
e
|
SignalActionType 0
|
f
|
MSB 3
|
g
|
LSB 0
|
h
|
isFallingEdgeSensitive False
|
i
|
isRisingEdgeSensitive False
|
j
|
DrawAnalog 0
|
k
|
BooleanEquation
|
l
|
NegTolerance 0
|
m
|
PosTolerance 0
|
n
|
UserSpecifiedSizeRatio 1
|
o
|
VerilogCode
|
p
|
VHDLCode
|
q
|
PROPS!
|
r
|
E0 V 5750 5750 READ PC 0x0 1 0 DR 0
|
s
|
!
|
t
|
|
u
|
MARKER MARK0
|
v
|
ATTACH rst NULL S1
|
w
|
TIME 2750.000000
|
x
|
RELATIVETIME 0.000000
|
y
|
DISPLAYAS 5
|
z
|
MARKERTYPE Timebreak(Curved)
|
{
|
WHILERETURN
|
|
|
REPEATNUMBER
|
}
|
SNAPTO 0
|
~
|
COMPRESSTIME 0.000000
|
|
COMMENT
|
|
!
|
{} ~} } } } } } } } } } } } } } } } } } } } } } } } } } } } } } } } } } } } } } } } } } } ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ #~ &~ )~ ,~ .~ 0~ 2~ 4~ 6~ 8~ :~ <~ >~ @~ A~ I~ V~ X~ Z~ c~ d~ e~ h~ k~ n~ q~ t~ w~ z~ }~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
|
|
" $ & ( * , . 0 2 4 6 7 ? L N P Y Z [ ^ a d g j m p s v y | " $ & ( * , - 5 B D F O P Q T W Z ] ` c f i l o r u x { ~ ɀ ʀ ˀ р Ԁ ׀ ڀ ݀
|
1 & " WMFC S `
|
! " ' 3 5 7 9 ; < = @ C F I L O R U X [ ^ a d g j m p s v y | Ɂ ԁ Ձ ց ف ܁ ߁ " $ & ( * , - 4 @ B D M X Z [ \ _ b e h k n q t w z } ł ǂ ɂ ˂ Ԃ ߂
|
`* x K t 1 EMF `* D X V I S I O D r a w i n g
|
" % ( + . 1 4 7 9 ; = ? A C E G I K L S _ a c l w y z { ~ Ã Ń ǃ Ƀ ˃ ̓ σ у ҃ # & ) , / 2 5 8 ; > A D G J M P S V X Z \ ^ ` b d f h j k r ~ Ą DŽ ʄ ̈́ Є ӄ ք ل ܄ ބ & 1 2 3 6 9 < ? B E H K N Q T W Z ] ` c f i l o r u w y { } Å ƅ Ʌ ̅ υ ҅ Յ ۅ ޅ # & ) , / 2 5 8 ; > A D G J M P S V X Z \ ^ ` b d f h j k q } ņ Ȇ ˆ Ά ц Ԇ ׆ چ ݆ g h · χ ̈ ͈ d e o p ԋ 4 5 G _ ` Ќ Ҍ ӌ ڌ ܌ % & ڍ ۍ ! , - ǐ ؐ ِ " # 3 9 ё ґ Ԓ Ւ ߒ / 5 d e Ó ɓ ) * 6 < _ ` k q Д є # $ 9 : W X % & ޗ 5 6 ? | } c d ۜ 5 6 П џ Ơ Ǡ K L e f ϡ С
|
\ l & % ' B 0 % V 0 > K = > =K=K > > =% ( % ( % R L A r i a l d x ` E x c e p t i o n s
& % T x / w I *A*A / L \ C P U / D S P ] & % ' % V 0 k o k o o k k o % ( % R L A r i a l % % W $ 9 - < <0 % ( & ccc,Mc,
|
% & Σ ϣ A B W X 0 1 { | ا ٧ ] ר ب n o s t ! " B C ֬ q r ۭ ܭ ͯ ί O P ڱ ۱ д Ѵ 5 6 E } ~ ε Q R ݷ ; < Z [ ' ( ½ ý H I [ b c { Ŀ ſ ݿ & ' * + 5 $ % I J Z [ P Q ) 1 2 A { | @ A c d y z F G b c h i < = e f | } Z [ K L V W ` a l m C D f g M N Y Z H I ^ _ ? @ V W F G \ ] k s t x ? @ D M N f g O P 5 6 : T U Y s t x & ' + 4 5 9 D E I R S W f g k t u y * + / H I M j k o / 2 < = ( ) + - 0 2 4 E F H J N P R h i k m u w y
1 2 4 6 = ? A j k m o u w y 0 1 3 6 ; = A W X Z d o q u
|
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l * 0 k k 0 0 0 * 0 k k 0 0 0 0 0 * 0 k k 0 t 0 t 0 t 0 t 0 t 0 t 0 t * 0 k k 0 = 0 = ( 0 = ( 0 = ( 0 = ( 0 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = 0 = '0 = 0 = 0 = 0 = * 0 k k 0 0 0 * 0 k k 0 f 0 f 0 f * 0 k k 0 0 & 0 & 0 & 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 '0 0 0 0 0 g g * 0 * 0 * 0 0 # 0 # 0 # 0 # 0 # 0 # 0 # '0 # 0 # 0 # 0 # 0 # * 0 0 0 0 0 '0 0 0 0 0 0 0 0 '0 0 0 0 0 * 0 0 ˜ 0 ˜ 0 ˜ * 0 0 0 0 * 0 0 0 0 * 0 0 0 0 * 0 0 0 * 0 * 0
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0 Z 0 0 Z 0 Z 0 Z 0 Z 0 Z 0 Z 0 Z 0 Z 0 Z 0 Z 0 Z 0 Z 0 Z 0 Z 0 Z 0 Z '0 Z 0 Z 0 Z 0 Z * 0 0 0 0 0 g g 0 * 0 0 0 0 * 0 0 0 0 0 '0 0 0 0 * 0 0 0 0 * 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 '0 0 0 0 0 * 0 0 m 0 m 0 m 0 m 0 m 0 m 0 m * 0 0 0 0 * 0 0 0 0 0 0 0 * 0 0 0 0 * 0 0 0 0 * 0 0 0 0 * 0 0 0 0 * 0
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0 0 0 @ 0 @ 0 @ 0 @ 0 @ 0 @ 0 @ 0 @ 0 @ 0 @ 0 @ 0 @ 0 @ 0 @ 0 @ 0 '0 0 * 0 Q Q 0 0 0 0 i i 0 0 0 0 0 0 i i 0 0 0 0 0 0 i i 0 * 0 0 0 0 * 0 0 0 0 0 0 0 0 * 0 0 0 0 0 0 * 0 0 0 0 0 0 0 0 * 0 0 + 0 0 + * 0 0 ~ 0 ~ 0 ~ 0 i i 0 0 0 * 0 0 ( 0 0 ( * 0 0 \ 0 0 \ 0 \ 0 \ 0
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i i 0 C 0 C 0 C * 0 C C 0 0 0 0 0 0 * 0 * 0 C C 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' '0 ' 0 ' 0 ' 0 ' * 0 C * 0 C C 0 ~ 0 ~ 0 ~ '0 ~ 0 ~ 0 ~ 0 ~ 0 ~ 0 ~ * 0 C C 0 j 0 j 0 j 0 j 0 j 0 j
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0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j 0 j '0 j 0 j 0 j 0 j * 0 C C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 '0 0 0 0 * 0 C C 0 0 0 0 '0
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OpenRISC 1200 IP Core Title 8 @ _PID_HLINKS A 4 7 $ _ T o c 5 1 1 1 6 1 5 6 4 7 _ T o c 5 1 1 1 6 1 5 6 3 7 _ T o c 5 1 1 1 6 1 5 6 2 7 _ T o c 5 1 1 1 6 1 5 6 1 7 _ T o c 5 1 1 1 6 1 5 6 0 7 _ T o c 5 1 1 1 6 1 5 5 9 7 _ T o c 5 1 1 1 6 1 5 5 8 7 _ T o c 5 1 1 1 6 1 5 5 7 7 _ T o c 5 1 1 1 6 1 5 5 6 7 _ T o c 5 1 1 1 6 1 5 5 5 7 _ T o c 5 1 1 1 6 1 5 5 4 7 _ T o c 5 1 1 1 6 1 5 5 3 7 _ T o c 5 1 1 1 6 1 5 5 2 7 _ T o c 5 1 1 1 6 1 5 5 1 7 _ T o c 5 1 1 1 6 1 5 5 0 7 _ T o c 5 1 1 1 6 1 5 4 9 7 _ T o c 5 1 1 1 6 1 5 4 8 7 _ T o c 5 1 1 1 6 1 5 4 7 7 _ T o c 5 1 1 1 6 1 5 4 6 7 _ T o c 5 1 1 1 6 1 5 4 5 7 _ T o c 5 1 1 1 6 1 5 4 4 7 _ T o c 5 1 1 1 6 1 5 4 3 7 _ T o c 5 1 1 1 6 1 5 4 2 7 _ T o c 5 1 1 1 6 1 5 4 1 7 _ T o c 5 1 1 1 6 1 5 4 0 7 _ T o c 5 1 1 1 6 1 5 3 9 7 _ T o c 5 1 1 1 6 1 5 3 8 7 _ T o c 5 1 1 1 6 1 5 3 7 7 | _ T o c 5 1 1 1 6 1 5 3 6 7 v _ T o c 5 1 1 1 6 1 5 3 5 7 p _ T o c 5 1 1 1 6 1 5 3 4 7 g _ T o c 5 1 1 1 6 1 5 3 3 7 a _ T o c 5 1 1 1 6 1 5 3 2 7 [ _ T o c 5 1 1 1 6 1 5 3 1 7 U _ T o c 5 1 1 1 6 1 5 3 0 7 O _ T o c 5 1 1 1 6 1 5 2 9 7 I _ T o c 5 1 1 1 6 1 5 2 8 7 C _ T o c 5 1 1 1 6 1 5 2 7 7 = _ T o c 5 1 1 1 6 1 5 2 6 7 7 _ T o c 5 1 1 1 6 1 5 2 5 7 1 _ T o c 5 1 1 1 6 1 5 2 4 7 + _ T o c 5 1 1 1 6 1 5 2 3 7 % _ T o c 5 1 1 1 6 1 5 2 2 7 _ T o c 5 1 1 1 6 1 5 2 1 7 _ T o c 5 1 1 1 6 1 5 2 0 7 _ T o c 5 1 1 1 6 1 5 1 9 7
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