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[/] [openrisc/] [trunk/] [or1200/] [doc/] [openrisc1200_spec.doc] - Diff between revs 401 and 481

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Rev 401 Rev 481
аЯрЁБс;ўџ  ƒ      ўџџџ€€‚ƒ„€€€€€     €     џџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџ§џџџџџџџ4
аЯрЁБс;ўџ  ‡      ўџџџ€€‚ƒ„€€€€€     €     џџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџ§џџџџџџџ4

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џџџџ РFMicrosoft Word-Dokument
џџџџ РFMicrosoft Word-Dokument
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щ§OpenRISC 1200 IP Core%OpenRISC 1200 IP Core SpecificationsDamjan LampretJulius Baxter43@~Њіg@NžeчР@’4sвР
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щ§OpenRISC 1200 IP Core%OpenRISC 1200 IP Core SpecificationsDamjan LampretJulius Baxter45@€ч>'i@NžeчР@’4sвР
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OpenRISC 1200
IP Core
Specification


Author: Damjan Lampret
lampret@opencores.org


Rev. 0.11
January, 2011




Preliminary Draft
Revision History

Rev.DateAuthorDescription0.128/3/01Damjan LampretFirst Draft0.216/4/01Damjan LampretFirst time published0.329/4/01Damjan LampretAll chapters almost finished. Some bugs hidden waiting for an update. Awaiting feedback.0.416/5/01Damjan LampretSynchronization with OR1K Arch Manual0.524/5/01Damjan LampretFixed bugs0.628/5/01Damjan LampretChanged some SPR addresses.0.706/9/01Damjan LampretSimplified debug unit.0.830/08/10Julius BaxterAdding information about FPU implementation, data cache write-back capability.
PIC behavior update.
Instruction list update.
Update of bits in config registers, bringing into line with latest OR1200   not entirely complete.0.912/9/10Julius BaxterClarified supported parts of OR1K instruction set
Updated core clock input information
Fixed up reference to instruction execute stage cycle table
Added divide cycles to execute stage cycle table
0.101/11/10Julius BaxterAdded FF1/FL1 instructions to supported instructions table.0.1119/1/11Julius BaxterCache information update
Wishbone behavior clarification
Serial integer multiply/divide update
Reset address clarificationTable Of Contents

 TOC \o "1-2" \t "Headeing 1 Name;1" \h HYPERLINK  \l "_toc272"Table Of Contents        3
 HYPERLINK  \l "_toc332"Table Of Figures   5
 HYPERLINK  \l "_toc351"Table Of Tables     6
 HYPERLINK  \l "_toc389"1 7
Introduction 7
 HYPERLINK  \l "_toc395"OpenRISC Family       7
 HYPERLINK  \l "_toc403"OpenRISC 1200 8
 HYPERLINK  \l "_toc414"Features   8
 HYPERLINK  \l "_toc422"2 9
Architecture 9
 HYPERLINK  \l "_toc441"CPU/FPU/DSP       10
 HYPERLINK  \l "_toc511"Data Cache     13
 HYPERLINK  \l "_toc566"Instruction Cache       16
 HYPERLINK  \l "_toc624"Data MMU 18
 HYPERLINK  \l "_toc676"Instruction MMU   20
 HYPERLINK  \l "_toc728"Programmable Interrupt Controller       22
 HYPERLINK  \l "_toc739"Tick Timer     22
 HYPERLINK  \l "_toc751"Power Management Support 23
 HYPERLINK  \l "_toc804"Debug unit     23
 HYPERLINK  \l "_toc813"Clocks & Reset	24
 HYPERLINK  \l "_toc819"WISHBONE Interfaces	24
 HYPERLINK  \l "_toc825"3	26
Operation	26
 HYPERLINK  \l "_toc830"Reset	26
 HYPERLINK  \l "_toc846"CPU/FPU/DSP	27
 HYPERLINK  \l "_toc1733"Data Cache Operation	33
 HYPERLINK  \l "_toc1816"Instruction Cache Operation	36
 HYPERLINK  \l "_toc1864"Data MMU	38
 HYPERLINK  \l "_toc2001"Instruction MMU	42
 HYPERLINK  \l "_toc2125"Programmable Interrupt Controller	45
 HYPERLINK  \l "_toc2143"Tick Timer	45
 HYPERLINK  \l "_toc2149"Power Management	45
 HYPERLINK  \l "_toc2185"Debug Unit	47
 HYPERLINK  \l "_toc2199"Development Interface	47
 HYPERLINK  \l "_toc2446"4	51
Registers	51
 HYPERLINK  \l "_toc2451"Registers list	51
 HYPERLINK  \l "_toc3163"Register VR description	52
 HYPERLINK  \l "_toc3234"Register UPR description	53
 HYPERLINK  \l "_toc3436"Register CPUCFGR description	53
 HYPERLINK  \l "_toc3549"Register DMMUCFGR description	54
 HYPERLINK  \l "_toc3660"Register IMMUCFGR description	54
 HYPERLINK  \l "_toc3771"Register DCCFGR description	55
 HYPERLINK  \l "_toc3924"Register ICCFGR description	56
 HYPERLINK  \l "_toc4074"Register DCFGR description	56
 HYPERLINK  \l "_toc4123"5	58
IO ports	58
 HYPERLINK  \l "_toc4136"Instruction WISHBONE Master Interface	58
 HYPERLINK  \l "_toc4300"Data WISHBONE Master Interface	59
 HYPERLINK  \l "_toc4464"System Interface	59
 HYPERLINK  \l "_toc2199"Development Interface	60
 HYPERLINK  \l "_toc4708"Power Management Interface	60
 HYPERLINK  \l "_toc4881"Interrupt Interface	61
 HYPERLINK  \l "_toc4912"A	62
Core HW Configuration	62
Table Of Figures

 TOC \c "FIGURE" Figure 1. Core's Architecture	9
Figure 2. CPU/FPU/DSP Block Diagram	10
Figure 3. Block Diagram of Debug Unit	24
Figure 4. Power-Up and Reset Sequence	26
Figure 5. Power-Up and Reset Sequence w/ Gated Clock	26
Figure 6. WISHBONE Write Cycle	33
Figure 7. WISHBONE Block Read Cycle	34
Figure 8. WISHBONE Block Read/Write Cycle	34
Figure 9. WISHBONE Block Read Cycle	37
Figure 10. 32-bit Address Translation Mechanism using Two-Level Page Table	39
Figure 11. 32-bit Address Translation Mechanism using Two-Level Page Table	42
Figure 12. Development Interface Cycles	48
Figure 13. Assertion of External Watchpoint Trigger	50
Figure 14. Core s Interfaces	58 
Table Of Tables

 TOC \c "TABLE" Table 1. Possible Data Cache Configurations of OR1200	13
Table 2. Possible Instruction Cache Configurations of OR1200	16
Table 3. Possible Data TLB Configurations of OR1200	18
Table 4. Possible Instruction TLB Configurations of OR1200	20
Table 5. Block Diagram of the Interrupt Controller	22
Table 6. Power Consumption	23
Table 7: Instructions implemented in OR1200	28
Table 8. Execution Time of Integer Instructions	30
Table 9: Execution time of floating point instructions	31
Table 10. List of Implemented Exceptions	32
Table 11. Protection Attributes for Load/Store Accesses	40
Table 12.  Cached and uncached regions	41
Table 13. Protection Attributes for Instruction Fetch Accesses	43
Table 14.  Cached and uncached regions	44
Table 15. Development Interface Operation Commands	48
Table 16. Status of the Load/Store Unit	49
Table 17. Status of the Instruction Unit	49
Table 18. List of All Registers	52
Table 19. VR Register	53
Table 20. UPR Register	53
Table 21. CPUCFGR Register	54
Table 22. DMMUCFGR Register	54
Table 23. IMMUCFGR Register	55
Table 24. DCCFGR Register	56
Table 25. ICCFGR Register	56
Table 26. DCFGR Register	57
Table 27. Instruction WISHBONE Master Interface  Signals	59
Table 28. Data WISHBONE Master Interface  Signals	59
Table 29. System Interface Signals	60
Table 30. Development Interface	60
Table 31. Power Management Interface	61
Table 32. Interrupt Interface	61
Table 33: Core HW configuration table	62
1
Introduction

Purpose of this document is to define specifications of the OpenRISC 1200 implementation. This specification defines all implementation specific variables that are not part of the general architecture specification. This includes type and size of data and instruction caches, type and size of data and instruction MMUs, details of all execution pipelines, implementation of exception unit, interrupt controller and other supplemental units.
This document does not cover general architecture topics like instruction set, memory addressing modes and other architectural definitions. See OpenRISC 1000 System Architecture Manual for more information about architecture.

OpenRISC Family

OpenRISC 1000 is architecture for a family of free, open source RISC processor cores. As architecture, OpenRISC 1000 allows for a spectrum of chip and system implementations at a variety of price/performance points for a range of applications. It is a 32/64-bit load and store RISC architecture designed with emphasis on performance, simplicity, low power requirements, scalability and versatility. OpenRISC 1000 architecture targets medium and high performance networking, embedded, automotive and portable computer environments.
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All OpenRISC implementations, whose first digit in identification number is  1 , belong to OpenRISC 1000 family. Second digit defines which features of OpenRISC 1000 architecture are implemented and in which way they are implemented. Last two digits define how an implementation is configured before it is used in a real application.

However, at present the OR1200 is the only major RTL implementation of the OR1K architecture spec, and the OR1200 name has stuck, despite the high level of reconfigurability possible that would, strictly speaking, mean the core is either a OR1000, OR1300, etc. So, despite the various features that may or may not be implemented, the core is still only referred to as the OR1200.

OpenRISC 1200

The OR1200 is a 32-bit scalar RISC with Harvard microarchitecture, 5 stage integer pipeline, virtual memory support (MMU) and basic DSP capabilities.
Default caches are 1-way direct-mapped 8KB data cache and 1-way direct-mapped 8KB instruction cache, each with 16-byte line size. Both caches are physically tagged.
By default MMUs are implemented and they are constructed of 64-entry hash based 1-way direct-mpped data TLB and 64-entry hash based 1-way direct-mapped instruction TLB.
Supplemental facilities include debug unit for real-time debugging, high resolution tick timer, programmable interrupt controller and power management support.
When implemented in a typical 0.18u 6LM process it should provide over 300 dhrystone 2.1 MIPS at 300MHz and 300 DSP MAC 32x32 operations, at least 20% more than any other competitor in this class. OR1200 in default configuration has about 1M transistors.

OR1200 is intended for embedded, portable and networking applications. It can successfully compete with latest scalar 32-bit RISC processors in his class and can efficiently run any modern operating system.
Competitors include ARM10, ARC and Tensilica RISC processors.

Features

The following lists the main features of OR1200 IP core:
All major characteristics of the core can be set by the user
High performance of 300 Dhrystone 2.1 MIPS at 300 MHz using 0.18u process
High performance cache and MMU subsystems
WISHBONE SoC Interconnection Rev. B3 compliant interface
 
2
Architecture

 REF _Ref511206923 \h Figure 1 below shows general architecture of OR1200 IP core. It consists of several building blocks: 
CPU/FPU/DSP central block
Direct-mapped data cache
Direct-mapped instruction cache
Data MMU based on hash based DTLB
Instruction MMU based on hash based ITLB
Power management unit and power management interface
Tick timer
Debug unit and development interface
Interrupt controller and interrupt interface
Instruction and Data WISHBONE host interfaces

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Figure  SEQ "Figure" \*Arabic 1. Core's Architecture


CPU/FPU/DSP

CPU/FPU/DSP is a central part of the OR1200 RISC processor.  REF _Ref511208730 \h Figure 2 shows basic block diagram of the CPU/DSP. Not pictured are the FPU components.
OR1200 CPU/FPU/DSP ony implements sections of the ORBIS32 and ORFPX32 instruction set. No ORBIS64, ORFBX64 or ORVDX64 instructions are  implemented in OR1200.

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Figure  SEQ "Figure" \*Arabic 2. CPU/FPU/DSP Block Diagram

Instruction unit

The instruction unit implements the basic instruction pipeline, fetches instructions from the memory subsystem, dispatches them to available execution units, and maintains a state history to ensure a precise exception model and that operations finish in order. It also executes conditional branch and unconditional jump instructions.
The sequencer can dispatch a sequential instruction on each clock if the appropriate execution unit is available. The execution unit must discern whether source data is available and to ensure that no other instruction is targeting the same destination register.

Instruction unit handles only ORBIS32 and, optionally, a subset of the ORFPX32 instruction class. Some ORFPX32 and all ORFPX3264 and ORVDX64 instruction classes are not supported by the OR1200 at present.

General-Purpose Registers

OpenRISC 1200 implements 32 general-purpose 32-bit registers. OpenRISC 1000 architecture also support shadow copies of register file to implement fast switching between working contexts, however this feature is not implemented in current OR1200 implementation.

OR1200 implements general-purpose register file as two synchronous dual-port memories with capacity of 32 words by 32 bits per word.

Load/Store Unit

The load/store unit (LSU) transfers all data between the GPRs and the CPU's internal bus. It is implemented as an independent execution unit so that stalls in memory subsystem only affect master pipeline if there is a data dependency.
The following are LSU's main features:
all load/store instruction implemented in hardware (atomic instructions included)
address entry buffer
pipelined operation
aligned accesses for fast memory access

When load and store instructions are issued, the LSU determines if all operands are available. These operands include the following:
address register operand
source data register operand (for store instructions)
destination data register operand (for load instructions)

Integer Execution Pipeline

The core implements the following types of 32-bit integer instructions:
Arithmetic instructions
Compare instructions
Logical instructions
Rotate and shift instructions

Most integer instructions can execute in one cycle. For details about timing see Table 8. Execution Time of Integer Instructions .

MAC Unit

The MAC unit executes DSP MAC operations. MAC operations are 32x32 with 48-bit accumulator. MAC unit is fully pipelined and can accept new MAC operation in each new clock cycle.

Floating Point Unit

The FPU implementation is based on two other FPUs available from OpenCores.org For the comparison and conversion functions, parts were taken from the FPU project by Rudolf Usselmann, and for the arithmetic operations, the fpu100 project by Jidan Al-Eryani was converted to Verilog HDL.

All ORFPX32 instructions except for lf.madd.s and lf.rem.s are supported when the FPU is enabled in the OR1200 configuration.

System Unit

The system unit connects all other signals of the CPU/FPU/DSP that are not connected through instruction and data interfaces. It also implements all system special-purpose registers (e.g. supervisor register).

Exceptions

Core exceptions can be generated when an exception condition occurs. Exception sources in OR1200 include the following:
External interrupt request
Certain memory access condition
Internal errors, such as an attempt to execute unimplemented opcode
System call
Internal exception, such as breakpoint exceptions

Exception handling is transparent to user software and uses the same mechanism to handle all types of exceptions. When an exception is taken, control is transferred to an exception handler at an offset defined by for the type of exception encountered. Exceptions are handled in supervisor mode.

Data Cache

The default configuration of OR1200 data cache is 8-Kbyte, 1-way direct-mapped data cache, which allows rapid core access to data. However data cache can be configured according to the  REF _Ref512098491 \h Table 1.

Direct mapped16B/line, 256 lines, 1 way4KB16B/line, 512 lines, 1 way8KB (default)16B/line, 1024 lines, 1 way16KB32B/line, 1024 lines, 1 way32KBTable  SEQ "Table" \*Arabic 1. Possible Data Cache Configurations of OR1200

It is possible to operate the data cache with write-through or write-back strategies, however write-back is currently experimental.

Features:
data cache is separate from instruction cache (Harvard architecture)
data cache implements a least-recently used (LRU) replacement algorithm within each set
the cache directory is physically addressed. The physical address tag is stored in the cache directory
write-through or write-back operation
entire cache can be disabled, lines invalidated, flushed or forced to be written back, by writing to cache special purpose registers

On a miss, and appropriate conditions, the cache line is filled or emptied (written back) with 16-byte bursts. The burst fill is performed as a critical-word-first operation; the critical word is simultaneously written to the cache and forwarded to the requesting unit, thus minimizing stalls due to cache fill latency. Data cache provides storage for cache tags and performs cache line replacement function.
Data cache is tightly coupled to external interface to allow efficient access to the system memory controller.
The data cache supplies data to the GPRs by means of a 32-bit interface to the load/store unit. The LSU provides all logic required to calculate effective addresses, handles data alignment to and from the data cache, and provides sequencing for load and store operations. Write operations to the data cache can be performed on a byte, half-word or word basis.

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Each line contains four contiguous words from memory that are loaded from a cache line aligned boundary. As a result, cache lines are aligned with page boundaries.

Instruction Cache

The default configuration of OR1200 instruction cache is 8-Kbyte, 1-way direct mapped instruction cache, which allows rapid core access to instructions. However instruction cache can be configured according to the  REF _Ref512099081 \h .

Direct mapped16B/line, 32 lines, 1 way512B16B/line, 256 lines, 1 way4KB16B/line, 512 lines, 1 way8KB (Default)16B/line, 1024 lines, 1 way16KB32B/line, 1024 lines, 1 way32KBTable  SEQ "Table" \*Arabic 2. Possible Instruction Cache Configurations of OR1200

Features:
instruction cache is separate from data cache (Harvard architecture)
instruction cache implements a least-recently used (LRU) replacement algorithm within each set
the cache directory is physically addressed. The physical address tag is stored in the cache directory
it can be disabled or invalidated by writing to cache special purpose registers

On a miss, the cache is filled in with 16-byte bursts. The burst fill is performed as a critical-word-first operation; the critical word is simultaneously written to the cache and forwarded to the requesting unit, thus minimizing stalls due to cache fill latency. Instruction cache provides storage for cache tags and performs cache line replacement function.
Instruction cache is tightly coupled to external interface to allow efficient access to the system memory controller.
The instruction cache supplies instructions to the instruction sequencer by means of a 32-bit interface to the instruction fetch subunit. The instruction fetch subunit provides all logic required to calculate effective addresses.

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OpenRISC 1200
IP Core
Specification


Author: Damjan Lampret
lampret@opencores.org


Rev. 0.10
November, 2010




Preliminary Draft
Revision History

Rev.DateAuthorDescription0.128/3/01Damjan LampretFirst Draft0.216/4/01Damjan LampretFirst time published0.329/4/01Damjan LampretAll chapters almost finished. Some bugs hidden waiting for an update. Awaiting feedback.0.416/5/01Damjan LampretSynchronization with OR1K Arch Manual0.524/5/01Damjan LampretFixed bugs0.628/5/01Damjan LampretChanged some SPR addresses.0.706/9/01Damjan LampretSimplified debug unit.0.830/08/10Julius BaxterAdding information about FPU implementation, data cache write-back capability.
PIC behavior update.
Instruction list update.
Update of bits in config registers, bringing into line with latest OR1200   not entirely complete.0.912/9/10Julius BaxterClarified supported parts of OR1K instruction set
Updated core clock input information
Fixed up reference to instruction execute stage cycle table
Added divide cycles to execute stage cycle table
0.101/11/10Julius BaxterAdded FF1/FL1 instructions to supported instructions table.Table Of Contents

 TOC \o "1-2" \t "Headeing 1 Name;1" \h HYPERLINK  \l "_toc257"Table Of Contents    3
 HYPERLINK  \l "_toc317"Table Of Figures   5
 HYPERLINK  \l "_toc336"Table Of Tables     6
 HYPERLINK  \l "_toc373"1 7
Introduction 7
 HYPERLINK  \l "_toc379"OpenRISC Family       7
 HYPERLINK  \l "_toc387"OpenRISC 1200 8
 HYPERLINK  \l "_toc398"Features   8
 HYPERLINK  \l "_toc406"2 9
Architecture 9
 HYPERLINK  \l "_toc425"CPU/DSP       10
 HYPERLINK  \l "_toc495"Data Cache     13
 HYPERLINK  \l "_toc551"Instruction Cache       16
 HYPERLINK  \l "_toc604"Data MMU 18
 HYPERLINK  \l "_toc656"Instruction MMU   20
 HYPERLINK  \l "_toc708"Programmable Interrupt Controller       22
 HYPERLINK  \l "_toc719"Tick Timer     22
 HYPERLINK  \l "_toc731"Power Management Support 23
 HYPERLINK  \l "_toc784"Debug unit     23
 HYPERLINK  \l "_toc793"Clocks & Reset	24
 HYPERLINK  \l "_toc799"WISHBONE Interfaces	24
 HYPERLINK  \l "_toc804"3	26
Operation	26
 HYPERLINK  \l "_toc809"Reset	26
 HYPERLINK  \l "_toc825"CPU/DSP	26
 HYPERLINK  \l "_toc1667"Data Cache Operation	31
 HYPERLINK  \l "_toc1750"Instruction Cache Operation	34
 HYPERLINK  \l "_toc1798"Data MMU	36
 HYPERLINK  \l "_toc1935"Instruction MMU	40
 HYPERLINK  \l "_toc2059"Programmable Interrupt Controller	43
 HYPERLINK  \l "_toc2077"Tick Timer	43
 HYPERLINK  \l "_toc2083"Power Management	43
 HYPERLINK  \l "_toc2119"Debug Unit	45
 HYPERLINK  \l "_toc2133"Development Interface	45
 HYPERLINK  \l "_toc2380"4	49
Registers	49
 HYPERLINK  \l "_toc2385"Registers list	49
 HYPERLINK  \l "_toc3097"Register VR description	50
 HYPERLINK  \l "_toc3168"Register UPR description	51
 HYPERLINK  \l "_toc3370"Register CPUCFGR description	51
 HYPERLINK  \l "_toc3483"Register DMMUCFGR description	52
 HYPERLINK  \l "_toc3594"Register IMMUCFGR description	52
 HYPERLINK  \l "_toc3705"Register DCCFGR description	53
 HYPERLINK  \l "_toc3858"Register ICCFGR description	54
 HYPERLINK  \l "_toc4008"Register DCFGR description	54
 HYPERLINK  \l "_toc4057"5	56
IO ports	56
 HYPERLINK  \l "_toc4070"Instruction WISHBONE Master Interface	56
 HYPERLINK  \l "_toc4234"Data WISHBONE Master Interface	57
 HYPERLINK  \l "_toc4398"System Interface	57
 HYPERLINK  \l "_toc2133"Development Interface	58
 HYPERLINK  \l "_toc4642"Power Management Interface	58
 HYPERLINK  \l "_toc4815"Interrupt Interface	59
 HYPERLINK  \l "_toc4846"A	60
Core HW Configuration	60
Table Of Figures

 TOC \c "FIGURE" Figure 1. Core's Architecture	9
Figure 2. CPU/DSP Block Diagram	10
Figure 3. Block Diagram of Debug Unit	24
Figure 4. Power-Up and Reset Sequence	26
Figure 5. Power-Up and Reset Sequence w/ Gated Clock	26
Figure 6. WISHBONE Write Cycle	31
Figure 7. WISHBONE Block Read Cycle	32
Figure 8. WISHBONE Block Read/Write Cycle	32
Figure 9. WISHBONE Block Read Cycle	35
Figure 10. 32-bit Address Translation Mechanism using Two-Level Page Table	37
Figure 11. 32-bit Address Translation Mechanism using Two-Level Page Table	40
Figure 12. Development Interface Cycles	46
Figure 13. Assertion of External Watchpoint Trigger	48
Figure 14. Core s Interfaces	56 
Table Of Tables

 TOC \c "TABLE" Table 1. Possible Data Cache Configurations of OR1200	13
Table 2. Possible Instruction Cache Configurations of OR1200	16
Table 3. Possible Data TLB Configurations of OR1200	18
Table 4. Possible Instruction TLB Configurations of OR1200	20
Table 5. Block Diagram of the Interrupt Controller	22
Table 6. Power Consumption	23
Table 7: Instructions implemented in OR1200	27
Table 8. Execution Time of Integer Instructions	29
Table 9: Execution time of floating point instructions	29
Table 10. List of Implemented Exceptions	30
Table 11. Protection Attributes for Load/Store Accesses	38
Table 12.  Cached and uncached regions	39
Table 13. Protection Attributes for Instruction Fetch Accesses	41
Table 14.  Cached and uncached regions	42
Table 15. Development Interface Operation Commands	46
Table 16. Status of the Load/Store Unit	47
Table 17. Status of the Instruction Unit	47
Table 18. List of All Registers	50
Table 19. VR Register	51
Table 20. UPR Register	51
Table 21. CPUCFGR Register	52
Table 22. DMMUCFGR Register	52
Table 23. IMMUCFGR Register	53
Table 24. DCCFGR Register	54
Table 25. ICCFGR Register	54
Table 26. DCFGR Register	55
Table 27. Instruction WISHBONE Master Interface  Signals	57
Table 28. Data WISHBONE Master Interface  Signals	57
Table 29. System Interface Signals	58
Table 30. Development Interface	58
Table 31. Power Management Interface	59
Table 32. Interrupt Interface	59
1
Introduction

Purpose of this document is to define specifications of the OpenRISC 1200 implementation. This specification defines all implementation specific variables that are not part of the general architecture specification. This includes type and size of data and instruction caches, type and size of data and instruction MMUs, details of all execution pipelines, implementation of exception unit, interrupt controller and other supplemental units.
This document does not cover general architecture topics like instruction set, memory addressing modes and other architectural definitions. See OpenRISC 1000 System Architecture Manual for more information about architecture.

OpenRISC Family

OpenRISC 1000 is architecture for a family of free, open source RISC processor cores. As architecture, OpenRISC 1000 allows for a spectrum of chip and system implementations at a variety of price/performance points for a range of applications. It is a 32/64-bit load and store RISC architecture designed with emphasis on performance, simplicity, low power requirements, scalability and versatility. OpenRISC 1000 architecture targets medium and high performance networking, embedded, automotive and portable computer environments.
 EMBED Microsoft Visio Drawing 
All OpenRISC implementations, whose first digit in identification number is  1 , belong to OpenRISC 1000 family. Second digit defines which features of OpenRISC 1000 architecture are implemented and in which way they are implemented. Last two digits define how an implementation is configured before it is used in a real application.

However, at present the OR1200 is the only major RTL implementation of the OR1K architecture spec, and the OR1200 name has stuck, despite the high level of reconfigurability possible that would, strictly speaking, mean the core is either a OR1000, OR1300, etc. So, despite the various features that may or may not be implemented, the core is still only referred to as the OR1200.

OpenRISC 1200

The OR1200 is a 32-bit scalar RISC with Harvard microarchitecture, 5 stage integer pipeline, virtual memory support (MMU) and basic DSP capabilities.
Default caches are 1-way direct-mapped 8KB data cache and 1-way direct-mapped 8KB instruction cache, each with 16-byte line size. Both caches are physically tagged.
By default MMUs are implemented and they are constructed of 64-entry hash based 1-way direct-mpped data TLB and 64-entry hash based 1-way direct-mapped instruction TLB.
Supplemental facilities include debug unit for real-time debugging, high resolution tick timer, programmable interrupt controller and power management support.
When implemented in a typical 0.18u 6LM process it should provide over 300 dhrystone 2.1 MIPS at 300MHz and 300 DSP MAC 32x32 operations, at least 20% more than any other competitor in this class. OR1200 in default configuration has about 1M transistors.

OR1200 is intended for embedded, portable and networking applications. It can successfully compete with latest scalar 32-bit RISC processors in his class and can efficiently run any modern operating system.
Competitors include ARM10, ARC and Tensilica RISC processors.

Features

The following lists the main features of OR1200 IP core:
All major characteristics of the core can be set by the user
High performance of 300 Dhrystone 2.1 MIPS at 300 MHz using 0.18u process
High performance cache and MMU subsystems
WISHBONE SoC Interconnection Rev. B3 compliant interface
 
2
Architecture

 REF _Ref511206923 \h Figure 1 below shows general architecture of OR1200 IP core. It consists of several building blocks: 
CPU/FPU/DSP central block
Direct-mapped data cache
Direct-mapped instruction cache
Data MMU based on hash based DTLB
Instruction MMU based on hash based ITLB
Power management unit and power management interface
Tick timer
Debug unit and development interface
Interrupt controller and interrupt interface
Instruction and Data WISHBONE host interfaces

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Figure  SEQ "Figure" \*Arabic 1. Core's Architecture


CPU/FPU/DSP

CPU/FPU/DSP is a central part of the OR1200 RISC processor.  REF _Ref511208730 \h Figure 2 shows basic block diagram of the CPU/DSP. Not pictured are the FPU components.
OR1200 CPU/FPU/DSP ony implements sections of the ORBIS32 and ORFPX32 instruction set. No ORBIS64, ORFBX64 or ORVDX64 instructions are  implemented in OR1200.

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Figure  SEQ "Figure" \*Arabic 2. CPU/FPU/DSP Block Diagram

Instruction unit

The instruction unit implements the basic instruction pipeline, fetches instructions from the memory subsystem, dispatches them to available execution units, and maintains a state history to ensure a precise exception model and that operations finish in order. It also executes conditional branch and unconditional jump instructions.
The sequencer can dispatch a sequential instruction on each clock if the appropriate execution unit is available. The execution unit must discern whether source data is available and to ensure that no other instruction is targeting the same destination register.

Instruction unit handles only ORBIS32 and, optionally, a subset of the ORFPX32 instruction class. Some ORFPX32 and all ORFPX3264 and ORVDX64 instruction classes are not supported by the OR1200 at present.

General-Purpose Registers

OpenRISC 1200 implements 32 general-purpose 32-bit registers. OpenRISC 1000 architecture also support shadow copies of register file to implement fast switching between working contexts, however this feature is not implemented in current OR1200 implementation.

OR1200 implements general-purpose register file as two synchronous dual-port memories with capacity of 32 words by 32 bits per word.

Load/Store Unit

The load/store unit (LSU) transfers all data between the GPRs and the CPU's internal bus. It is implemented as an independent execution unit so that stalls in memory subsystem only affect master pipeline if there is a data dependency.
The following are LSU's main features:
all load/store instruction implemented in hardware (atomic instructions included)
address entry buffer
pipelined operation
aligned accesses for fast memory access

When load and store instructions are issued, the LSU determines if all operands are available. These operands include the following:
address register operand
source data register operand (for store instructions)
destination data register operand (for load instructions)

Integer Execution Pipeline

The core implements the following types of 32-bit integer instructions:
Arithmetic instructions
Compare instructions
Logical instructions
Rotate and shift instructions

Most integer instructions can execute in one cycle. For details about timing see Table 8. Execution Time of Integer Instructions .

MAC Unit

The MAC unit executes DSP MAC operations. MAC operations are 32x32 with 48-bit accumulator. MAC unit is fully pipelined and can accept new MAC operation in each new clock cycle.

Floating Point Unit

The FPU implementation is based on two other FPUs available from OpenCores.org For the comparison and conversion functions, parts were taken from the FPU project by Rudolf Usselmann, and for the arithmetic operations, the fpu100 project by Jidan Al-Eryani was converted to Verilog HDL.

All ORFPX32 instructions except for lf.madd.s and lf.rem.s are supported when the FPU is enabled in the OR1200 configuration.

System Unit

The system unit connects all other signals of the CPU/FPU/DSP that are not connected through instruction and data interfaces. It also implements all system special-purpose registers (e.g. supervisor register).

Exceptions

Core exceptions can be generated when an exception condition occurs. Exception sources in OR1200 include the following:
External interrupt request
Certain memory access condition
Internal errors, such as an attempt to execute unimplemented opcode
System call
Internal exception, such as breakpoint exceptions

Exception handling is transparent to user software and uses the same mechanism to handle all types of exceptions. When an exception is taken, control is transferred to an exception handler at an offset defined by for the type of exception encountered. Exceptions are handled in supervisor mode.

Data Cache

The default configuration of OR1200 data cache is 8-Kbyte, 1-way direct-mapped data cache, which allows rapid core access to data. However data cache can be configured according to the  REF _Ref512098491 \h Table 1.

Direct mapped1KB per set1KB2KB per set2KB4KB per set4KB8KB per set8KB (default)Table  SEQ "Table" \*Arabic 1. Possible Data Cache Configurations of OR1200

It is possible to operate the data cache with write-through or write-back stratergies.

Features:
data cache is separate from instruction cache (Harvard architecture)
data cache implements a least-recently used (LRU) replacement algorithm within each set
the cache directory is physically addressed. The physical address tag is stored in the cache directory
write-through or write-back operation
entire cache can be disabled, lines invalidated, flushed or forced to be written back, by writing to cache special purpose registers

On a miss, and appropriate conditions, the cache line is filled or emptied (written back) with 16-byte bursts. The burst fill is performed as a critical-word-first operation; the critical word is simultaneously written to the cache and forwarded to the requesting unit, thus minimizing stalls due to cache fill latency. Data cache provides storage for cache tags and performs cache line replacement function.
Data cache is tightly coupled to external interface to allow efficient access to the system memory controller.
The data cache supplies data to the GPRs by means of a 32-bit interface to the load/store unit. The LSU provides all logic required to calculate effective addresses, handles data alignment to and from the data cache, and provides sequencing for load and store operations. Write operations to the data cache can be performed on a byte, half-word or word basis.
The data cache is organized as 512 sets of one line. Each line consists of 16 bytes, state bits and an address tag. It can also be configured with 256 or 32 lines.

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Each line contains four contiguous words from memory that are loaded from a four-word aligned boundary. As a result, cache lines are aligned with page boundaries.

Instruction Cache

The default configuration of OR1200 instruction cache is 8-Kbyte, 1-way direct mapped instruction cache, which allows rapid core access to instructions. However instruction cache can be configured according to the  REF _Ref512099081 \h .

Direct mapped1KB per set1KB2KB per set2KB4KB per set4KB8KB per set8KB (default)Table  SEQ "Table" \*Arabic 2. Possible Instruction Cache Configurations of OR1200

Features:
instruction cache is separate from data cache (Harvard architecture)
instruction cache implements a least-recently used (LRU) replacement algorithm within each set
the cache directory is physically addressed. The physical address tag is stored in the cache directory
it can be disabled or invalidated by writing to cache special purpose registers

On a miss, the cache is filled in with 16-byte bursts. The burst fill is performed as a critical-word-first operation; the critical word is simultaneously written to the cache and forwarded to the requesting unit, thus minimizing stalls due to cache fill latency. Instruction cache provides storage for cache tags and performs cache line replacement function.
Instruction cache is tightly coupled to external interface to allow efficient access to the system memory controller.
The instruction cache supplies instructions to the instruction sequencer by means of a 32-bit interface to the instruction fetch subunit. The instruction fetch subunit provides all logic required to calculate effective addresses.
The data cache is organized as 512 sets of one line. Each line consists of 16 bytes, state bits and an address tag.

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Each line contains four contiguous words from memory that are loaded from a four-word aligned boundary. As a result, cache lines are aligned with page boundaries.

Data MMU

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 !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~€‚ƒ„…ўџџџ‡ˆ‰Š‹ŒŽ‘’“”•–—˜™š›œžŸ ЁЂЃЄЅІЇЈЉЊЋЌ­ЎЏАБВГДЕЖЗИЙКЛМНОПРСТУФХЦЧШЩЪЫЬЭЮЯабвгдежзўџџџйклмнопрстуфхцчшщъыьэюя№ёђѓєѕіїјљњћќ§ўџўџџџ  aligned boundary. As a result, cache lines are aligned with page boundaries.

Data MMU

The OR1200 implements a virtual memory management scheme that provides memory access protection and effective-to-physical address translation. Protection granularity is as defined by OpenRISC 1000 architecture - 8-Kbyte and 16-Mbyte pages.

Direct mapped16 entries per way16 DTLB entries32 entries per way32 DTLB entries64 entries per way64 DTLB entries (default)128 entries per way128 DTLB entriesTable  SEQ "Table" \*Arabic 3. Possible Data TLB Configurations of OR1200

Features:
data MMU is separate from instruction MMU
page size 8-Kbyte
comprehensive page protection scheme
direct mapped hash based translation lookaside buffer (DTLB) with the default of 1 way and the following features:
miss and fault exceptions
software tablewalk
high performance because of hashed based design
variable number DTLB entries with default of 64 per each way

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The MMU hardware supports two-level software tablewalk.

Instruction MMU

The OR1200 implements a virtual memory management scheme that provides memory access protection and effective-to-physical address translation. Protection granularity is as defined by OpenRISC 1000 architecture - 8-Kbyte and 16-Mbyte pages.

Direct mapped16 entries per way16 DTLB entries32 entries per way32 DTLB entries64 entries per way64 DTLB entries (default)128 entries per way128 DTLB entriesTable  SEQ "Table" \*Arabic 4. Possible Instruction TLB Configurations of OR1200

Features:
instruction MMU is separate from data MMU
pages size 8-Kbyte
comprehensive page protection scheme
1 way direct-mapped hash based translation lookaside buffer (ITLB) with the following features:
miss and fault exceptions
software tablewalk
high performance because of hashed based design
Variable number of ITLB entries with default of 64 entries per way

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The MMU hardware supports two-level software tablewalk.

Programmable Interrupt Controller

The interrupt controller receives interrupts from external sources and forwards them as low or high priority interrupt exception to the CPU core.


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Table  SEQ "Table" \*Arabic 5. Block Diagram of the Interrupt Controller

Programmable interrupt controller has three special-purpose registers and 32 interrupt inputs. Interrupt input 0 and 1 are always enabled and connected to high and low priority interrupt input, respectively.
30 other interrupt inputs can be masked and assigned low or high priority through programming special-purpose registers.

Tick Timer

OR1200 implements tick timer facility. Basically this is a timer that is clocked by RISC clock and is used by the operating system to precisely measure time and schedule system tasks.

OR1200 precisely follow architectural definition of the tick timer facility:
Maximum timer count of 2^32 clock cycles
Maximum time period of 2^28 clock cycles between interrupts
Maskable tick timer interrupt
Single run, restartable or continues timer

Tick timer operates from independent clock source so that doze power management mode can be implemented.

Power Management Support

To optimize power consumption, the OR1200 provides low-power modes that can be used to dynamically activate and deactivate certain internal modules.

OR1200 has three major features to minimize power consumption:
Slow and Idle Modes (SW controlled clock freq reduction)
Doze and Sleep Modes (interrupt wake-up)

Power Minimization FeatureApprox Power Consumption ReductionSlow and Idle mode2x   10xDoze mode100xSleep mode200xDynamic clock gatingN/ATable  SEQ "Table" \*Arabic 6. Power Consumption

Slow down mode takes advantage of the low-power dividers in external clock generation circuitry to enable full functionality, but at a lower frequency so that a power consumption is reduced.
PMR[SDF] 4 bits are broadcasted on pm_clksd and external clock generation for the RISC should adapt RISC clock frequency according to the value on pm_clksd.

When software initiates the doze mode, software processing on the core suspends. The clocks to the RISC internal modules are disabled except to the tick timer. However any other on-chip blocks can continue to function as normal.
The OR1200 will leave doze mode and enter normal mode when a pending interrupt occurs.

In sleep mode, all OR1200 internal units are disabled and clocks gated. Optionally implementation may choose to lower the operating voltage of the OR1200 core.
The OR1200 should leave sleep mode and enter normal mode when a pending interrupt occurs.

Dynamic Clock gating (unit clock gating on clock by clock basis) is not supported by OR1200.

Debug unit

Debug unit assists software developers to debug their systems. It provides support only for basic debugging and does not have support for more advanced debug features of OpenRISC 1000 architecture such as watchpoints, breakpoints and program-flow control registers.

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Figure  SEQ "Figure" \*Arabic 3. Block Diagram of Debug Unit

Watchpoints and breakpoints are events triggered by program- or data-flow matching the conditions programmed in the debug registers. Breakpoints unlike watchpoints also suspend execution of the current program-flow and start breakpoint exception.

Clocks & Reset

The OR1200 core has a clock input each for the instruction and data Wishbone interface logic, and for the CPU core. Clock input clk_cpu clocks everything inside the Wishbone interfaces. Data Wishbone interface is clocked by dwb_clk_i, instruction Wishbone interface is clocked by iwb_clk_i.

OR1200 has asynchronous reset signal. Reset signal rst, when asserted high, immediately resets all flip-flops inside OR1200. When deasserted, OR1200 will start reset exception.

WISHBONE Interfaces

Two WISHBONE interfaces connect OR1200 core to external peripherals and external memory subsystem. They are WISHBONE SoC Interconnection specification Rev. B3 compliant. The implementation implements a 32-bit bus width and does not support other bus widths.
Wishbone registered-feedback incrementing burst accesses occur when not disabled, and cache lines are filled. The burst size (beats) is determined by the cache line size.


3
Operation

This section describes the operation of the OR1200 core. For operations that pertain to the architectural definitions, see OpenRISC 1000 System Architecture Manual.

Reset

OR1200 has one asynchronous reset signal that can be used by a soft and hard reset on a higher system hierarchy levels.

 EMBED  
Figure  SEQ "Figure" \*Arabic 4. Power-Up and Reset Sequence

 REF _Ref513206810 \h Figure 4 shows how asynchronous reset is applied after powering up the OR1200 core. Reset is connected to asynchronous reset of almost all flip-flops inside RISC core. Special care must be taken to ensure hold and setup times of all flip-flops compared to main RISC clock.

If system implements gated clocks, then clock gating can be used to ensure proper reset timing.

 EMBED  
Figure  SEQ "Figure" \*Arabic 5. Power-Up and Reset Sequence w/ Gated Clock

The address the PC assumes at hard reset (assertion of external reset signal) is definable at synthesis time, via the OR1200_BOOT_ADR define. This is not to be confused with the ability to set the exception prefix address with the EPH bit.

CPU/FPU/DSP

CPU/FPU/DSP is implementation of the 32-bit part of the OpenRISC 1000 architecture and only a subset of all features is implemented.


Instructions

The following table lists the instructions implemented in the OR1200. Those optionally implemented are indicated as such.
Instruction 
mnemonicOpt.Instruction 
mnemonicOpt.Instruction 
mnemonicOpt.Instruction 
mnemonicOpt.l.addl.macrcYl.shlf.sflt.sYl.addcYl.msbYl.slllf.sfne.sYl.addil.mfsprl.sllilf.sub.sYl.andl.movhil.sral.andil.mtsprl.srail.bfl.mulYl.srll.bnfl.muliYl.srlil.divYl.nopl.subYl.ff1Yl.orl.swl.fl1Yl.oril.sysl.jl.rfel.trapl.jall.roril.xorl.jalrl.sbl.xoril.jrl.sfeqlf.add.sYl.lbsl.sfgeslf.div.sYl.lbzl.sfgeulf.ftoi.sYl.lhsl.sfgtslf.itof.sYl.lhzl.sfgtulf.mul.sYl.lwsl.sfleulf.sfeq.sYl.lwzl.sfltslf.sfge.sYl.macYl.sfltulf.sfgt.sYl.maciYl.sfnelf.sfle.sYTable  SEQ "Table" \*Arabic 7: Instructions implemented in OR1200
For a complete description of each instruction's format refer to the OpenRISC 1000 System Architecture Manual.

Instruction Unit

Instruction unit generates instruction fetch effective address and fetches instructions from instruction cache. Each clock cycle one instruction can be fetched. Instruction fetch EA is further translated into physical address by IMMU.

General-Purpose Registers

General-purpose register file can supply two read operands each clock cycle and store one result in a destination register.

GPRs can be also read and written through development interface.

Load/Store Unit

LSU can execute one load instruction every two clock cycles assuming load instruction have a hit in the data cache. Execution of store instructions takes one clock cycle assuming they have a hit in the data cache.

LSU performs calculation of the load/store effective address. EA is further translated into physical address by DMMU.

Load/store effective address and load and store data can be also accessed through development interface.





















Integer Execution Pipeline

The core implements the following types of 32-bit integer instructions:
Arithmetic instructions
Compare instructions
Logical instructions
Rotate and shift instructions

Instruction GroupClock Cycles to ExecuteArithmetic except Multiply/Divide1Multiply3Divide32Compare1Logical1Rotate and Shift1Others1Table  SEQ "Table" \*Arabic 8. Execution Time of Integer Instructions

 REF _Ref513308588 \h Table 8 lists execution times for instructions executed by integer execution pipeline. Most instructions are executed in one clock cycle.

Integer multiply can be either serial or parallel implementations. Serial operations require one clock cycle per bit of operand, which is 32-cycles on the OR1200. At present no synthesis tools support division operators, and so the serial option must be used.

MAC Unit

MAC unit executes l.mac instructions. MAC unit implements 32x32 fully pipelined multiplier and 48-bit accumulator. MAC unit can accept one new l.mac instruction each clock cycle.
Care should be taken when executing l.macrc (MAC read and clear) too soon after the final l.mac instruction as the operation may still be underway and the result will not be valid in time. It is recommended at least 3 other instructions (or just l.nops) are inserted between the final l.mac and l.macrc.

Floating Point Unit
The floating point unit has a mechanism to stall the processor pipeline until processing has completed.
The following table indicates the number of cycles per operation

OperationCyclesAdd/subtract10Multiply38Divide37Compare2Convert7Table  SEQ "Table" \*Arabic 9: Execution time of floating point instructions

System Unit

System unit implements system control and status special-purpose registers and executes all l.mtspr/l.mfspr instructions.


























Exceptions

The core implements a precise exception model. This means that when an exception is taken, the following conditions are met:
Subsequent instructions in program flow are discarded
Previous instructions finish and write back their results
The address of faulting instruction is saved in EPCR registers and the machine state is saved to ESR registers

Exception TypeVector Offsetcausing conditionsReset0x100Caused by reset.Bus Error0x200Caused by an attempt to access invalid physical address.Data Page Fault0x300Generated artificially by DTLB miss exception handler when no matching PTE found in page tables or page protection violation for load/store operations.Instruction Page Fault0x400Generated artificially by ITLB miss exception handler when no matching PTE found in page tables or page protection violation for instruction fetch.Low Priority External Interrupt0x500Low priority external interrupt asserted.Alignment0x600Load/store access to naturally not aligned location.Illegal Instruction0x700Illegal instruction in the instruction stream.High Priority External Interrupt0x800High priority external interrupt asserted.D-TLB Miss0x900No matching entry in DTLB (DTLB miss).I-TLB Miss0xA00No matching entry in ITLB (ITLB miss).System Call0xC00System call initiated by software.Floating point exception0xD00FP operation caused flags in FPCSR to become set.Trap0xE00Trap instruction was decodedTable  SEQ "Table" \*Arabic 10. List of Implemented Exceptions
The OR1200 exception support does not include support for range exceptions or fast context switching.

Data Cache Operation

Data Cache Load/Store Access

Load/store unit requests data from the data cache and stores them into the general-purpose register file and forwards them to integer execution units. Therefore LSU is tightly coupled with the data cache.

If there is no data cache line miss nor DTLB miss, load operations take two clock cycles to execute and store operations take one clock cycle to execute. LSU does all the data alignment work.

Data can be written to the data cache on a word, half-word or byte basis. Since data cache only operates in write-through mode, all writes are immediately written back to main memory or to the next level of caches.

 EMBED  
Figure  SEQ "Figure" \*Arabic 6. WISHBONE Write Cycle

 REF _Ref513193242 \h Figure 6 shows how a write-through cycle on data WISHBONE interface is performed when a store instruction hits in the data cache.
If dwb_ERR_I or dwb_RTY_I is asserted instead of usual dwb_ACK_I, bus error exception is invoked.

Data Cache Line Fill Operation

When executing load instruction and a cache miss occurs, depending on whether the cache uses write-through or write-back strategy and the line is clean or invalid, a 4 beat sequential read burst with critical word first is performed. If the strategy is write-back and the line is dirty, the line is first written back to memory. The critical word is forwarded to the load/store unit to minimize performance loss because of the cache miss.

 EMBED  
Figure  SEQ "Figure" \*Arabic 7. WISHBONE Block Read Cycle

 REF _Ref513194821 \h Figure 7 shows how a cache line is read in WISHBONE read block cycle composed out of four read transfers.
If dwb_ERR_I or dwb_RTY_I is asserted instead of usual dwb_ACK_I, bus error exception is invoked.

When executing a store instruction with the cache in write-through strategy, and a cache miss occurs, the write is simply put on the bus and no caching occurs. If it is a miss and the cache is in write back strategy and the line is valid and clean or invalid,  a 4 beat sequential read burst to fill the line is performed, and the the write to cache occurs. If storing and a cache miss occurs, and the desired line is valid and dirty, it is first written back to memory before the desired line is read.


 EMBED  
Figure  SEQ "Figure" \*Arabic 8. WISHBONE Block Read/Write Cycle

 REF _Ref513195072 \h Figure 8 shows how a cache line is read in WISHBONE read block cycle followed by a write transfer.
If dwb_ERR_I or dwb_RTY_I is asserted instead of usual dwb_ACK_I, bus error exception is invoked.

Cache/Memory Coherency

Data cache in OR1200 operates in either write-through or write-back mode, definable at synthesis time, for default use, and runtime when DMMU is used. There is currently no coherency support between local data cache and caches of other processors.

Data Cache Enabling/Disabling

Data cache is disabled at power up. Entire data cache can be enabled by setting bit SR[DCE] to one. Before data cache is enabled, it must be invalidated.

Data Cache Invalidation

Data cache in OR1200 does not support invalidation of entire data cache. Normal procedure to invalidate entire data cache is to cycle through all data cache lines and invalidate each line separately.

Data Cache Locking

Data cache implements way locking bits in data cache control register DCCR. Bits LWx lock individual ways when they are set to one.

Data Cache Line Prefetch

Data cache line prefetch is optional in the OpenRISC 1000 architecture and is not implemented in OR1200.

Data Cache Line Flush

Operation is performed by writing effective address to the DCBFR register.

When a cache line is valid and clean, or the cache is in write-through strategy, the line is invalidated and no write-back occurs.

Data Cache Line Invalidate

Data cache line invalidate invalidates a single data cache line. Operation is performed by writing effective address to the DCBIR register.
If cache is in write-back strategy, it is best to use the line flush function.

Data Cache Line Write-back

Operation is performed by writing effective address to the DCBWR register.

If cache is in write-through strategy, this operation is ignored as no lines will be cached and dirty, capable of being written back.

Data Cache Line Lock

Locking of individual data cache lines is not implemented in OR1200.

Data Cache inhibit with address bit 31 set

If DMMU is disabled, by default all addresses with bit 31 of the address asserted high will cause the data cache to be inhibited, meaning no reads or writes are cached.

If the DMMU is enabled, it is possible for any address to be inhibited or not, and in these modes the cache behaves accordingly.


Instruction Cache Operation

Instruction Cache Instruction Fetch Access

Instruction unit requests instruction from the instruction cache and forwards them to the instruction queue inside instruction unit. Therefore instruction unit is tightly coupled with the instruction cache.

If there is no instruction cache line miss nor ITLB miss, instruction fetch operation takes one clock cycle to execute.

Instruction cache cannot be explicitly modified like data cache can be with store instructions.

Instruction Cache Line Fill Operation

On a cache miss, a 4 beat sequential read burst with critical word first is performed. Critical word is forwarded to the instruction unit to minimize performance loss because of the cache miss.

 EMBED  
Figure  SEQ "Figure" \*Arabic 9. WISHBONE Block Read Cycle

 REF _Ref513197552 \h Figure 9 shows how a cache line is read in WISHBONE read block cycle composed out of four read transfers.
If iwb_ERR_I or iwb_RTY_I is asserted instead of usual dwb_ACK_I, bus error exception is invoked.

Cache/Memory Coherency

OR1200 is not intended for use in multiprocessor environments. Therefore no support for coherency between local instruction cache and caches of other processors or main memory is implemented.

Instruction Cache Enabling/Disabling

Instruction cache is disabled at power up. Entire instruction cache can be enabled by setting bit SR[ICE] to one. Before instruction cache is enabled, it must be invalidated.

Instruction Cache Invalidation

Instruction cache in OR1200 does not support invalidation of entire instruction cache. Normal procedure to invalidate entire instruction cache is to cycle through all instruction cache lines and invalidate each line separately.

Instruction Cache Locking

Instruction cache implements way locking bits in instruction cache control register ICCR. Bits LWx lock individual ways when they are set to one.

Instruction Cache Line Prefetch

Instruction cache line prefetch is optional in the OpenRISC 1000 architecture and is not implemented in OR1200.

Instruction Cache Line Invalidate

Instruction cache line invalidate invalidates a single instruction cache line. Operation is performed by writing effective address to the ICBIR register.

Instruction Cache Line Lock

Locking of individual instruction cache lines is not implemented in OR1200.

Data MMU

Translation Disabled

Load/store address translation can be disabled by clearing bit SR[DME]. If translation is disabled, then physical address used to access data cache and optionally provided on dwb_ADDR_O, is the same as load/store effective address.

Translation Enabled

Load/store address translation can be enabled by setting bit SR[DME]. If translation is enabled, it provides load/store effective address to physical address translation and page protection for memory accesses.

 EMBED Microsoft Visio Drawing 
Figure  SEQ "Figure" \*Arabic 10. 32-bit Address Translation Mechanism using Two-Level Page Table

In OR1200 case, page tables must be managed by operating system s virtual memory management subsystem.  REF _Ref513343227 \h Figure 10 shows address translation using two-level page table. Refer to OpenRISC 1000 System Architecture Manual for one-level page table address translation as well as for details about address translation and page table content.

DMMUCR and Flush of Entire DTLB

DMMUCR is not implemented in OR1200. Therefore page table base pointer (PTBP) must be stored in software variable. Flush of entire DTLB must be performed by software flush of every DTLB entry separately. Software flush is performed by manually writing  bits from the TLB entries back to PTEs.

Page Protection

After a virtual address is determined to be within a page covered by the valid PTE, the access is validated by the memory protection mechanism. If this protection mechanism prohibits the access, a data page fault exception is generated.

The memory protection mechanism allows selectively granting read access and write access for both supervisor and user modes. The page protection mechanism provides protection at all page level granularities.

Protection attributeMeaningDTLBWyTR[SREx]Enable load operations in supervisor mode to the page.DTLBWyTR[SWEx]Enable store operations in supervisor mode to the page.DTLBWyTR[UREx]Enable load operations in user mode to the page.DTLBWyTR[UWEx]Enable store operations in user mode to the page.Table  SEQ "Table" \*Arabic 11. Protection Attributes for Load/Store Accesses

 REF _Ref513346094 \h Table 11 lists page protection attributes defined in DTLBWyTR pregister. For the individual page appropriate strategy out of seven possible strategies programmed with the PPI field of the PTE. Because OR1200 does not implement DMMUPR, translation of PTE[PPI] into suitable set of protection bits must be performed by software and written into DTLBWyTR.

DTLB Entry Reload

OR1200 does not implement DTLB entry reloads in hardware. Instead software routine must be used to search page table for correct page table entry (PTE) and copy it into the DTLB. Software is responsible for maintaining accessed and dirty bits in the page tables.

When LSU computes load/store effective address whose physical address is not already cached by DTLB, a DTLB miss exception is invoked.

DTLB reload routine must load the correct PTE to correct DTLBWyMR and DTLBWyTR register from one of possible DTLB ways.

DTLB Entry Invalidation

Special-purpose register DTLBEIR must be written with the effective address and corresponding DTLB entry will be invalidated in the local DTLB.

Locking DTLB Entries

Since all DTLB entry reloads are performed in software, there is no hardware locking of DTLB entries. Instead it is up to the software reload routine to avoid replacing some of the entries if so desired.

Page Attribute   Dirty (D)

Dirty (D) attribute is not implemented in OR1200 DTLB. It is up to the operating system to generate dirty attribute bit with page protection mechanism.

Page Attribute   Accessed (A)

Accessed (A) attribute is not implemented in OR1200 DTLB. It is up to the operating system to generate accessed attribute bit with page protection mechanism.

Page Attribute   Weakly Ordered Memory (WOM)

Weakly ordered memory (WOM) attribute is not needed in OR1200 because all memory accesses are serialized and therefore this attribute is not implemented.

Page Attribute   Write-Back Cache (WBC)

Write-back cache (WBC) attribute is not implemented as the data cache cannot be configured at run time to be write-back enabled if write-through strategy was selected at synthesis-time.

Page Attribute   Caching-Inhibited (CI)

Caching-inhibited (CI) attribute is not implemented in OR1200 DTLB. Cached and uncached regions are divided by bit 30 of data effective address.

Effective AddressRegion0x00000000 - 0x3FFFFFFFCached0x40000000 - 0x7FFFFFFFUncached0x80000000 - 0xBFFFFFFFCached0xC0000000 - 0xFFFFFFFFUncachedTable  SEQ "Table" \*Arabic 12.  Cached and uncached regions

Uncached accesses must be performed when I/O registers are memory mapped and all reads and writes must be always performed directly to the external interface and not to the data cache.

Page Attribute   Cache Coherency (CC)

Cache coherency (CC) attribute is not needed in OR1200 because it doesn t implement support for multiprocessor environments and because data cache operates only in write-through mode and therefore this attribute is not implemented.

Instruction MMU

Translation Disabled

Instruction fetch address translation can be disabled by clearing bit SR[IME]. If translation is disabled, then physical address used to access instruction cache and optionally provided on iwb_ADDR_O, is the same as instruction fetch effective address.

Translation Enabled

Instruction fetch address translation can be enabled by setting bit SR[IME]. If translation is enabled, it provides instruction fetch effective address to physical address translation and page protection for instruction fetch accesses.

 EMBED Microsoft Visio Drawing 
Figure  SEQ "Figure" \*Arabic 11. 32-bit Address Translation Mechanism using Two-Level Page Table

In OR1200 case, page tables must be managed by operating system s virtual memory management subsystem.  REF _Ref513343227 \h Figure 10 shows address translation using two-level page table. Refer to OpenRISC 1000 System Architecture Manual for one-level page table address translation as well as for details about address translation and page table content.

IMMUCR and Flush of Entire ITLB

IMMUCR is not implemented in OR1200. Therefore page table base pointer (PTBP) must be stored in software variable. Flush of entire ITLB must be performed by software flush of every ITLB entry separately. Software flush is performed by manually writing bits from the TLB entries back to PTEs.

Page Protection

After a virtual address is determined to be within a page covered by the valid PTE, the access is validated by the memory protection mechanism. If this protection mechanism prohibits the access, an instruction page fault exception is generated.

The memory protection mechanism allows selectively granting execute access for both supervisor and user modes. The page protection mechanism provides protection at all page level granularities.

Protection attributeMeaningITLBWyTR[SXEx]Enable execute operations in supervisor mode of the page.ITLBWyTR[UXEx]Enable execute operations in user mode of the page.Table  SEQ "Table" \*Arabic 13. Protection Attributes for Instruction Fetch Accesses

 REF _Ref513346094 \h Table 11 lists page protection attributes defined in ITLBWyTR pregister. For the individual page appropriate strategy out of seven possible strategies programmed with PPI field of the PTE. Because OR1200 does not implement IMMUPR, translation of PTE[PPI] into suitable set of protection bits must be performed by software and written into ITLBWyTR.


ITLB Entry Reload

OR1200 does not implement ITLB entry reloads in hardware. Instead software routine must be used to search page table for correct page table entry (PTE) and copy it into the ITLB. Software is responsible for maintaining accessed bit in the page tables.

When LSU computes instruction fetch effective address whose physical address is not already cached by ITLB, an ITLB miss exception is invoked.

ITLB reload routine must load the correct PTE to correct ITLBWyMR and ITLBWyTR register from one of possible ITLB ways.

ITLB Entry Invalidation

Special-purpose register ITLBEIR must be written with the effective address and corresponding ITLB entry will be invalidated in the local ITLB.

Locking ITLB Entries

Since all ITLB entry reloads are performed in software, there is no hardware locking of ITLB entries. Instead it is up to the software reload routine to avoid replacing some of the entries if so desired.

Page Attribute   Dirty (D)

Dirty (D) attribute resides in the PTE but it is not used by the IMMU.

Page Attribute   Accessed (A)

Accessed (A) attribute is not implemented in OR1200 ITLB. It is up to the operating system to generate accessed attribute bit with page protection mechanism.

Page Attribute   Weakly Ordered Memory (WOM)

Weakly ordered memory (WOM) attribute is not needed in OR1200 because all instruction fetch accesses are serialized and therefore this attribute is not implemented.

Page Attribute   Write-Back Cache (WBC)

Write-back cache (WBC) attribute resides in the PTE but it is not used by the IMMU.

Page Attribute   Caching-Inhibited (CI)

Caching-inhibited (CI) attribute is not implemented in OR1200 ITLB. Cached and uncached regions are divided by bit 30 of instruction effective address.

Effective AddressRegion0x00000000 - 0x3FFFFFFFCached0x40000000 - 0x7FFFFFFFUncached0x80000000 - 0xBFFFFFFFCached0xC0000000 - 0xFFFFFFFFUncachedTable  SEQ "Table" \*Arabic 14.  Cached and uncached regions

Page Attribute   Cache Coherency (CC)

Cache coherency (CC) attribute resides in the PTE but it is not used by the IMMU.

Programmable Interrupt Controller

PICMR special-purpose register is used to mask or unmask up to 30 programmable interrupt sources. PICPR special-purpose register is used to assign low or high priority to maximum of 30 interrupt sources.

PICSR special-purpose register is used to determine status of each interrupt input. Bits in PICSR represent status of the interrupt inputs and the actual interrupt must be cleared in the device that is the source of a pending interrupt.

The PIC implementation in the OR1200  differs from the architecture specification. The PIC instead offers a latched level-sensitive interrupt.

Once an interrupt line is latched (i.e. its value appears in PICSR), no new interrupts can be triggered for that line until its bit in PICSR is cleared. The usual sequence for an interrupt handler is then as follows.

Peripheral asserts interrupt, which is latched and triggers handler. 
Handler processes interrupt.
Handler notifies peripheral that the interrupt has been processed (typically via a memory mapped register).
 Peripheral deasserts interrupt.
Handler clears corresponding bit in PICSR and returns.

It is assumed that the peripheral will de-assert its interrupt promptly (within 1-2 cycles). Otherwise on exiting the interrupt handler, having cleared PICSR, the level sensitive interrupt will immediately retrigger.

Tick Timer

Tick timer facility is enabled with TTMR[M]. TTCR is incremented with each clock cycle and a high priority interrupt can be asserted whenever lower 28 bits of TTCR match TTMR[TP] and TTMR[IE] is set.

TTCR restarts counting from zero when match event happens and TTMR[M] is 0x1. If TTMR[M] is 0x2, TTCR is stoped when match event happens and TTCR must be changed to start counting again. When TTMR[M] is 0x3, TTCR keeps counting even when match event happens.

Power Management

Clock Gating and Frequency Changing Versus CPU Stalling

If system doesn t support clock gating and if changing clock frequency in slow down mode is not possible, CPU can be stalled for certain number of clock cycles. This is much lower benefit on power consumption however it still reduces power consumption.

Slow Down Mode

Slow down mode is software controlled with the 4-bit value in PMR[SDF]. Lower value specifies higher expected performance from the processor core. Usually PMR[SDF] is dynamically set by the operating system s idle routine, that monitors the usage of the processor core.

PMR[SDF] is broadcasted on pm_clksd. External clock generator should adjust clock frequency according to the value of pm_clksd. Exact slow down factors are not defined but 0xF should go all the way down to 32.768 KHz.

With pm_clksd equal to 0xF, pm_lvolt is asserted. This is an indication for the external power supply to lower the voltage.

Doze Mode

To switch to doze mode, software should set the PMR[DME]. Once an interrupt is received by the programmable interrupt controller (PIC), pm_wakeup is asserted and external clock generation circuitry should enable all clocks. Once clocks are running RISC is switched back again to the normal mode and PMR[DME] is cleared.

When doze mode is enabled, pm_dc_gate, pm_ic_gate, pm_dmmu_gate, pm_immu_gate and pm_cpugate are asserted. As a result all clocks except clk_tt should be gated by external clock generation circuitry.

Sleep Mode

To switch to sleep mode, software should set the PMR[SME]. Once an interrupt is received by the programmable interrupt controller (PIC), pm_wakeup is asserted and external clock generation should enable all clocks. Once clocks are running, RISC is switched back again to the normal mode and PMR[SME] is cleared.

When sleep mode is enabled, pm_dc_gate, pm_ic_gate, pm_dmmu_gate, pm_immu_gate, pm_cpu_gate and pm_tt_gate are asserted. As a result all clocks including clk_tt should be gated by external clock generation circuitry.

In sleep mode, pm_lvolt is asserted. This is an indication for the external power supply to lower the voltage.

Clock Gating

Clock gating feature is not implemented in OR1200 power management. 

Disabled Units Force Clock Gating

Units that are disabled in special-purpose register SR, have their clock gate signals asserted. Cleared bits SR[DCE], SR[ICE], SR[DME] and SR[IME] directly force assertion of pm_dc_gate, pm_ic_gate, pm_dmmu_gate and pm_immu_gate.

Debug Unit

Debug unit can be controlled through development interface or it can operate independently programmed and handled by the RISC s resident debug software.

Watchpoints

OR1200 debug unit does not implement OR12000 architecture watchpoints.

Breakpoint Exception

Which breakpointDMR2[WGB] bits specify which watchpoints invoke breakpoint exception. By invoking breakpoint exception, target resident debugger can be built.

Breakpoint is broadcasted on development interface on dbg_bp_o.

Development Interface

NOTE: The information in this section is to be reviewed. It is the author's opinion that the debug interface is now largely provided by the SPR mappings, and no special sideband functions exist aside from stalling and resetting the core.

An additional development and debug interface IP core may be used to connect OpenRISC 1200 to standard debuggers using IEEE.1149.1 (JTAG) protocol.

Debugging Through Development Interface

The DSR special-purpose register specifies which exceptions cause the core to stop the execution of the exception handler and turn over control to development interface. It can be programmed by the resident debug software or by the development interface.

The DRR special-purpose register is specifies which event caused the core to stop the execution of program flow and turned over control to the development interface. It should be cleared by the resident debug software or by the development interface.

The DIR special-purpose register is not implemented.

Reading PC, Load/Store EA, Load Data, Store Data, Instruction

Crucial information like program counter (PC), load/store effective address (LSEA), load data, store data and current instruction in execution pipeline can be asynchronously read through the development interface.

dbg_op_i[2:0]Meaning0x0Reading Program Counter (PC)0x1Reading Load/Store Effective Address0x2Reading Load Data0x3Reading Store Data0x4Reading SPR0x5Writing SPR0x6Reading Instruction in Execution Pipeline0x7ReservedTable  SEQ "Table" \*Arabic 15. Development Interface Operation Commands

 REF _Ref513329306 \h Table 15 lists operation commands that control what is read or written through development interface. All reads except reads and writes of SPRs are asynchronous.

Reading and Writing SPRs Through Development Interface

For reads and write to SPRs dbg_op_i must be set to 0x4 and 0x5, respectively.

 EMBED  
Figure  SEQ "Figure" \*Arabic 12. Development Interface Cycles

 REF _Ref513329852 \h Figure 12 shows development interface cycles. Writes must be synchronous to the main RISC clock positive edge and should take one clock cycle. Reads must take two clock cycles because access to synchronous cache lines or to TLB entries introduces one clock cycle of delay.

If required, external debugger can stop the CPU core by asserting dbg_stall_i. This way it can have enough time to read all interesting registers from the RISC or guarantee that writes into SPRs are performed without RISC writing to the same registers.

Tracking Data Flow

An external debugger can monitor and record data flow inside the RISC for debugging purposes and profiling analysis. This is accomplished by monitoring status of the load/store unit, load/store effective address and load/store data, all available at the development interface.

dbg_lss_o[3:0]Load/Store Instruction in Execution0x0No load/store instruction in execution0x1Reserved for load doubleword0x2Load byte and zero extend0x3Load byte and sign extend0x4Load halfword and zero extend0x5Load halfword and sign extend0x6Load singleword and zero extend0x7Load singleword and sign extend0x8Reserved for store doubleword0x9Reserved0xAStore byte0xBReserved0xCStore halfword0xDReserved0xEStore singleword0xFReservedTable  SEQ "Table" \*Arabic 16. Status of the Load/Store Unit

External trace buffer can capture all interesting data flow events by analyzing status of the load/store unit available on dbg_lss_o.  REF _Ref513326484 \h Table 16 lists different status encoding for the load/store unit.

Tracking Program Flow

An external debugger can monitor and record program flow inside the RISC for debugging purposes and profiling analysis. This is accomplished by monitoring status of the instruction unit, PC and fetched instruction word, all available at the development interface.

dbg_is_o[1:0]Instruction Fetch Status0x0No instruction fetch in progress0x1Normal instruction fetch0x2Executing branch instruction0x3Fetching instruction in delay slotTable  SEQ "Table" \*Arabic 17. Status of the Instruction Unit

External trace buffer can capture all interesting program flow events by analyzing status of the instruction unit available on dbg_is_o.  REF _Ref513326219 \h Table 17 lists different status encoding for the instruction unit.

Triggering External Watcpoint Event

 REF _Ref513324670 \h Figure 13 shows how development interface can assert dbg_ewt_I and cause watchpoint event. If programmed, external watchpoint event will cause a breakpoint exception.

 EMBED  
Figure  SEQ "Figure" \*Arabic 13. Assertion of External Watchpoint Trigger
4
Registers

This section describes all registers inside the OR1200 core. Shifting GRP number 11 bits left and adding REG number computes the address of each special-purpose register. All registers are 32 bits wide from software perspective. USER MODE and SUPV MODE specify the valid access types for each register in user mode and supervisor mode of operation. R/W stands for read and write access and R stands for read only access.

Registers list

Grp
#Reg #Reg NameUSER MODESUPV
MODEDescription00VR RVersion Register01UPR RUnit Present Register02CPUCFGR RCPU Configuration Register03DMMUCFGR RData MMU Configuration Register04IMMUCFGR RInstruction MMU Configuration Register05DCCFGR RData Cache Configuration Register06ICCFGR RInstruction Cache Configuration Register07DCFGR RDebug Configuration Register016PC R/WPC mapped to SPR space017SR R/WSupervision Register020FPCSR-R/WFP Control Status Register032EPCR0 R/WException PC Register048EEAR0 R/WException EA Register064ESR0 R/WException SR Register01024-1055GPR0-GPR31 R/WGPRs mapped to SPR space12DTLBEIR WData TLB Entry Invalidate Register11024-1151DTLBW0MR0-DTLBW0MR127 R/WData TLB Match Registers Way 011536-1663DTLBW0TR0-DTLBW0TR127 R/WData TLB Translate Registers Way 022ITLBEIR WInstruction TLB Entry Invalidate Register21024-1151ITLBW0MR0-ITLBW0MR127 R/WInstruction TLB Match Registers Way 021536-1663ITLBW0TR0-ITLBW0TR127 R/WInstruction TLB Translate Registers Way 030DCCR R/WDC Control Register32DCBFRWWDC Block Flush Register33DCBIRWWDC Block Invalidate Register34DCBWRWWDC Block Write-back register40ICCR R/WIC Control Register4256ICBIRWWIC Block Invalidate Register5256MACLOR/WR/WMAC Low5257MACHIR/WR/WMAC High616DMR1 R/WDebug Mode Register 1617DMR2 R/WDebug Mode Register 2620DSR R/WDebug Stop Register621DRR R/WDebug Reason Register80PMR R/WPower Management Register90PICMR R/WPIC Mask Register92PICSR R/WPIC Status Register100TTMR R/WTick Timer Mode Register101TTCRR*R/WTick Timer Count RegisterTable  SEQ "Table" \*Arabic 18. List of All Registers

 REF _Ref513309410 \h Table 18 lists all OpenRISC 1000 special-purpose registers implemented in OR1200. Registers VR and UPR are described below. For description of other registers refer to OpenRISC 1000 System Architecture Manual document.

Register VR description

Special-purpose register VR identifies the version (model) and revision level of the OpenRISC 1000 processor. It also specifies possible standard template on which this implementation is based.

Bit #AccessResetDescription5:0RRevisionREV
Revision number of this document.15:6R0x0Reserved23:16R0x00CFG
Configuration should be read from UPR and configuration registers31:24R0x12VER
Version number for OR1200 is fixed at 0x1200.Table  SEQ "Table" \*Arabic 19. VR Register

Register UPR description

Special-purpose register UPR identifies the units present in the processor. It has a bit for each implemented unit or functionality. Lower sixteen bits identify present units defined in the OpenRISC 1000 architecture. Upper sixteen bits define present custom units.

Bit #AccessResetDescription0R1UP
UPR present1R1DCP
Data cache present*2R1ICP
Instruction cache present*3R1DMP
Data MMU present*4R1IMP
Instruction MMU present*5R1MP
MAC present*6R1DUP
Debug unit present*7R0PCUP
Performance counters unit not present*8R1PMP
Power Management Present*9R1PICP
Programmable interrupt controller present10R1TTP
Tick timer present11R1FPP
Floating point present*23:12RXReserved31:24R0xXXXXCUP
The user of the OR1200 core adds custom units.Table  SEQ "Table" \*Arabic 20. UPR Register
* if enabled at synthesis time

Register CPUCFGR description

Special-purpose register CPUCFGR identifies the capabilities and configuration of the CPU. 

Bit #AccessResetDescription3:0R0x0NSGF
Zero number of shadow GPR files4R0HGF
No half GPR files*5R1OB32S
ORBIS32 supported6R0OB64S
ORBIS64 not supported7R1OF32S
ORFPX32 supported**8R0OF64S
ORFPX64 not supported9R0OV64S
ORVDX64 not supportedTable  SEQ "Table" \*Arabic 21. CPUCFGR Register
* If disabled at synthesis time
** If FPU enabled at synthesis time

Register DMMUCFGR description

Special-purpose register DMMUCFGR identifies the capabilities and configuration of the DMMU. 

Bit #AccessResetDescription1:0R0x0NTW
One DTLB way4:2R0x4   0x7NTS
16, 32, 64 or 128 DTLB sets7:5R0x0NAE
No ATB Entries8R0CRI
No DMMU control register implemented9R0PRI
No protection register implemented10R1TEIRI
DTLB entry invalidate register implemented11R0HTR
No hardware DTLB reloadTable  SEQ "Table" \*Arabic 22. DMMUCFGR Register

Register IMMUCFGR description

Special-purpose register IMMUCFGR identifies the capabilities and configuration of the IMMU. 

Bit #AccessResetDescription1:0R0x0NTW
One ITLB way4:2R0x4   0x7NTS
16, 32, 64 or 128 ITLB sets7:5R0x0NAE
No ATB Entries8R0CRI
No IMMU control register implemented9R0PRI
No protection register implemented10R1TEIRI
ITLB entry invalidate register implemented11R0HTR
No hardware ITLB reloadTable  SEQ "Table" \*Arabic 23. IMMUCFGR Register

Register DCCFGR description

Special-purpose register DCCFGR identifies the capabilities and configuration of the data cache. 

Bit #AccessResetDescription2:0R0x0NCW
One DC way6:3R0x4   0x7NCS
16, 32, 64 or 128 DC sets7R0x0CBS
16-byte cache block size8R0CWS
Cache write-through strategy*9R1CCRI
DC control register implemented10R1CBIRI
DC block invalidate register implemented11R0CBPRI
DC block prefetch register not implemented12R0CBLRI
DC block lock register not implemented13R1CBFRI
DC block flush register implemented14R1CBWBRI
DC block write-back register  implemented**Table  SEQ "Table" \*Arabic 24. DCCFGR Register
*If Write-through enabled at synthesis time
**If Write-through disabled at synthesis time


Register ICCFGR description

Special-purpose register ICCFGR identifies the capabilities and configuration of the instruction cache. 

Bit #AccessResetDescription2:0R0x0NCW
One IC way6:3R0x4   0x7NCS
16, 32, 64 or 128 IC sets7R0x0CBS
16-byte cache block size8R0CWS
Cache write-through strategy9R1CCRI
IC control register implemented10R1CBIRI
IC block invalidate register implemented11R0CBPRI
IC block prefetch register not implemented12R0CBLRI
IC block lock register not implemented13R1CBFRI
IC block flush register implemented14R0CBWBRI
IC block write-back register not implementedTable  SEQ "Table" \*Arabic 25. ICCFGR Register

Register DCFGR description

Special-purpose register DCFGR identifies the capabilities and configuration of the debut unit. 

Bit #AccessResetDescription3:0R0x0NDP
Zero DVR/DCR pairs*4R0 WPCI
Watchpoint counters not implementedTable  SEQ "Table" \*Arabic 26. DCFGR Register
* If hardware breakpoints disabled at synthesis time
      


5
IO ports

OR1200 IP core has several interfaces.  REF _Ref507257694 \h Figure 14 below shows all interfaces:
Instruction and data WISHBONE host interfaces
Power management interface
Development interface
Interrupts interface

 EMBED Microsoft Visio Drawing 

Figure  SEQ "Figure" \*Arabic 14. Core s Interfaces

Instruction WISHBONE Master Interface

OR1200 has two master WISHBONE Rev B compliant interfaces. Instruction interface is used to connect OR1200 core to memory subsystem for purpose of fetching instructions or instruction cache lines.

PortWidthDirectionDescriptioniwb_CLK_I1InputClock inputiwb_RST_I1InputReset inputiwb_CYC_O1OutputIndicates valid bus cycle (core select)iwb_ADR_O32OutputsAddress outputsiwb_DAT_I32InputsData inputsiwb_DAT_O32OutputsData outputsiwb_SEL_O4OutputsIndicates valid bytes on data bus (during valid cycle it must be 0xf)iwb_ACK_I1InputAcknowledgment input (indicates normal transaction termination)iwb_ERR_I1InputError acknowledgment input (indicates an abnormal transaction termination)iwb_RTY_I1InputIn OR1200 treated same way as iwb_ERR_I.iwb_WE_O1OutputWrite transaction when asserted highiwb_STB_O1OutputsIndicates valid data transfer cycleTable  SEQ "Table" \*Arabic 27. Instruction WISHBONE Master Interface  Signals

Data WISHBONE Master Interface

OR1200 has two master WISHBONE Rev B compliant interfaces. Data interface is used to connect OR1200 core to external peripherals and memory subsystem for purpose of reading and writing data or data cache lines.

PortWidthDirectionDescriptiondwb_CLK_I1InputClock inputdwb_RST_I1InputReset inputdwb_CYC_O1OutputIndicates valid bus cycle (core select)dwb_ADR_O32OutputsAddress outputsdwb_DAT_I32InputsData inputsdwb_DAT_O32OutputsData outputsdwb_SEL_O4OutputsIndicates valid bytes on data bus (during valid cycle it must be 0xf)dwb_ACK_I1InputAcknowledgment input (indicates normal transaction termination)dwb_ERR_I1InputError acknowledgment input (indicates an abnormal transaction termination)dwb_RTY_I1InputIn OR1200 treated same way as dwb_ERR_I.dwb_WE_O1OutputWrite transaction when asserted highdwb_STB_O1OutputsIndicates valid data transfer cycleTable  SEQ "Table" \*Arabic 28. Data WISHBONE Master Interface  Signals

System Interface

System interface connects reset, clock and other system signals to the OR1200 core.

PortWidthDirectionDescriptionRst1InputAsynchronous resetclk_cpu1InputMain clock input to the RISCclk_dc1InputData cache clockclk_ic1InputInstruction cache clockclk_dmmu1InputData MMU clockclk_immu1InputInstruction MMU clockclk_tt1InputTick timer clockTable  SEQ "Table" \*Arabic 29. System Interface Signals

Development Interface

Development interface connects external development port to the RISC s internal debug facility. Debug facility allows control over program execution inside RISC, setting of breakpoints and watchpoints, and tracing of instruction and data flows.

PortWidthDirectionDescriptiondbg_dat_o32OutputTransfer of data from RISC to external development interfacedbg_dat_i32InputTransfer of data from external development interface to RISCdbg_adr_i32InputAddress of special-purpose register to be read or writtendbg_op_I3InputOperation select for development interfacedbg_lss_o4OutputStatus of load/store unitdbg_is_o2OutputStatus of instruction fetch unitdbg_wp_o11OutputStatus of watchpointsdbg_bp_o1OutputStatus of the breakpointdbg_stall_i1InputStalls RISC CPU coredbg_ewt_i1InputExternal watchpoint triggerTable  SEQ "Table" \*Arabic 30. Development Interface

Power Management Interface

Power management interface provides signals for interfacing RISC core with external power management circuitry. External power management circuitry is required to implement functions that are technology specific and cannot be implemented inside OR1200 core.

PortWidthDirectionGenerationDescriptionpm_clksd4OutputStatic (in SW)Slow down outputs that control reduction of RISC clock frequencypm_cpustall1Input-Synchronous stall of the RISC s CPU corepm_dc_gate1OutputDynamic (in HW)Gating of data cache clockpm_ic_gate1OutputDynamic (in HW)Gating of instruction cache clockpm_dmmu_gate1OutputDynamic (in HW)Gating of data MMU clockpm_immu_gate1OutputDynamic (in HW)Gating of instruction MMU clockpm_tt_gate1OutputDynamic (in HW)Gating of tick timer clockpm_cpu_gate1OutputStatic (in SW)Gating of main CPU clockpm_wakeup1OutputDynamic (in HW)Activate all clockspm_lvolt1OutputStatic (in SW)Lower voltageTable  SEQ "Table" \*Arabic 31. Power Management Interface

Interrupt Interface

Interrupt interface has interrupt inputs for interfacing external peripheral s interrupt outputs to the RISC core. All interrupt inputs are evaluated on positive edge of main RISC clock.

PortWidthDirectionDescriptionpic_intsPIC_INTSInputExternal interruptsTable  SEQ "Table" \*Arabic 32. Interrupt Interface
A
Core HW Configuration

This section describes parameters that are set by the user of the core and define configuration of the core. Parameters must be set by the user before actual use of the core in simulation or synthesis.

Variable NameRangeDefaultDescriptionEADDR_WIDTH3232Effective address widthVADDR_WIDTH3232Virtual address widthPADDR_WIDTH24   3632Physical address widthDATA_WIDTH3232Data width / Operation widthDC_IMPL0   11Data cache implementationDC_SETS256-1024512Data cache number of setsDC_WAYS11Data cache number of waysDC_LINE16 - 3216Data cache line sizeIC_IMPL0   11Instruction cache implementationIC_SETS32-1024512Instruction cache number of setsIC_WAYS11Instruction cache number of waysIC_LINE16-3216Instruction cache line size in bytesDMMU_IMPL0   11Data MMU implementationDTLB_SETS6464Data TLB number of setsDTLB_WAYS11Data TLB number of waysIMMU_IMPL0   11Instruction MMU implementationITLB_SETS6464Instruction TLB number of setsITLB_WAYS11Instruction TLB number of waysPIC_INTS2   3220Number of interrupt inputsTable  SEQ "Table" \*Arabic 33: Core HW configuration table



OpenCores        TITLE OpenRISC 1200 IP Core  DATE \@"M/D/YY" 1/19/11

 HYPERLINK "http://www.opencores.org/"www.opencores.org       Rev 0.11 Preliminary        PAGE 62 of  NUMPAGES \*Arabic 62







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 !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~€ўџџџƒ„…†‡ˆ‰Š‹ŒŽ‘’“”•–—˜™š›œžŸ ЁЂЃЄЅІЇЈЉЊЋЌ­ЎЏАБВГДЕЖЗИЙКўџџџМНОПРСТУФХЦЧШЩЪЫЬЭЮЯабвгдежзийклмнопрстуфхцчшщъыьэюўџџџ№ёђѓєѕіїјљњћќ§ўџanagement scheme that provides memory access protection and effective-to-physical address translation. Protection granularity is as defined by OpenRISC 1000 architecture - 8-Kbyte and 16-Mbyte pages.

Direct mapped16 entries per way16 DTLB entries32 entries per way32 DTLB entries64 entries per way64 DTLB entries (default)128 entries per way128 DTLB entriesTable  SEQ "Table" \*Arabic 3. Possible Data TLB Configurations of OR1200

Features:
data MMU is separate from instruction MMU
page size 8-Kbyte
comprehensive page protection scheme
direct mapped hash based translation lookaside buffer (DTLB) with the default of 1 way and the following features:
miss and fault exceptions
software tablewalk
high performance because of hashed based design
variable number DTLB entries with default of 64 per each way

 EMBED Microsoft Visio Drawing 

The MMU hardware supports two-level software tablewalk.

Instruction MMU

The OR1200 implements a virtual memory management scheme that provides memory access protection and effective-to-physical address translation. Protection granularity is as defined by OpenRISC 1000 architecture - 8-Kbyte and 16-Mbyte pages.

Direct mapped16 entries per way16 DTLB entries32 entries per way32 DTLB entries64 entries per way64 DTLB entries (default)128 entries per way128 DTLB entriesTable  SEQ "Table" \*Arabic 4. Possible Instruction TLB Configurations of OR1200

Features:
instruction MMU is separate from data MMU
pages size 8-Kbyte
comprehensive page protection scheme
1 way direct-mapped hash based translation lookaside buffer (ITLB) with the following features:
miss and fault exceptions
software tablewalk
high performance because of hashed based design
Variable number of ITLB entries with default of 64 entries per way

 EMBED Microsoft Visio Drawing 

The MMU hardware supports two-level software tablewalk.

Programmable Interrupt Controller

The interrupt controller receives interrupts from external sources and forwards them as low or high priority interrupt exception to the CPU core.


 EMBED Microsoft Visio Drawing 
Table  SEQ "Table" \*Arabic 5. Block Diagram of the Interrupt Controller

Programmable interrupt controller has three special-purpose registers and 32 interrupt inputs. Interrupt input 0 and 1 are always enabled and connected to high and low priority interrupt input, respectively.
30 other interrupt inputs can be masked and assigned low or high priority through programming special-purpose registers.

Tick Timer

OR1200 implements tick timer facility. Basically this is a timer that is clocked by RISC clock and is used by the operating system to precisely measure time and schedule system tasks.

OR1200 precisely follow architectural definition of the tick timer facility:
Maximum timer count of 2^32 clock cycles
Maximum time period of 2^28 clock cycles between interrupts
Maskable tick timer interrupt
Single run, restartable or continues timer

Tick timer operates from independent clock source so that doze power management mode can be implemented.

Power Management Support

To optimize power consumption, the OR1200 provides low-power modes that can be used to dynamically activate and deactivate certain internal modules.

OR1200 has three major features to minimize power consumption:
Slow and Idle Modes (SW controlled clock freq reduction)
Doze and Sleep Modes (interrupt wake-up)

Power Minimization FeatureApprox Power Consumption ReductionSlow and Idle mode2x   10xDoze mode100xSleep mode200xDynamic clock gatingN/ATable  SEQ "Table" \*Arabic 6. Power Consumption

Slow down mode takes advantage of the low-power dividers in external clock generation circuitry to enable full functionality, but at a lower frequency so that a power consumption is reduced.
PMR[SDF] 4 bits are broadcasted on pm_clksd and external clock generation for the RISC should adapt RISC clock frequency according to the value on pm_clksd.

When software initiates the doze mode, software processing on the core suspends. The clocks to the RISC internal modules are disabled except to the tick timer. However any other on-chip blocks can continue to function as normal.
The OR1200 will leave doze mode and enter normal mode when a pending interrupt occurs.

In sleep mode, all OR1200 internal units are disabled and clocks gated. Optionally implementation may choose to lower the operating voltage of the OR1200 core.
The OR1200 should leave sleep mode and enter normal mode when a pending interrupt occurs.

Dynamic Clock gating (unit clock gating on clock by clock basis) is not supported by OR1200.

Debug unit

Debug unit assists software developers to debug their systems. It provides support only for basic debugging and does not have support for more advanced debug features of OpenRISC 1000 architecture such as watchpoints, breakpoints and program-flow control registers.

 EMBED Microsoft Visio Drawing 
Figure  SEQ "Figure" \*Arabic 3. Block Diagram of Debug Unit

Watchpoints and breakpoints are events triggered by program- or data-flow matching the conditions programmed in the debug registers. Breakpoints unlike watchpoints also suspend execution of the current program-flow and start breakpoint exception.

Clocks & Reset

The OR1200 core has a clock input each for the instruction and data Wishbone interface logic, and for the CPU core. Clock input clk_cpu clocks everything inside the Wishbone interfaces. Data Wishbone interface is clocked by dwb_clk_i, instruction Wishbone interface is clocked by iwb_clk_i.

OR1200 has asynchronous reset signal. Reset signal rst, when asserted high, immediately resets all flip-flops inside OR1200. When deasserted, OR1200 will start reset exception.

WISHBONE Interfaces

Two WISHBONE interfaces connect OR1200 core to external peripherals and external memory subsystem. They are WISHBONE SoC Interconnection specification Rev. B3 compliant. The implementation implements a 32-bit bus width and does not support other bus widths.


3
Operation

This section describes the operation of the OR1200 core. For operations that pertain to the architectural definitions, see OpenRISC 1000 System Architecture Manual.

Reset

OR1200 has one asynchronous reset signal that can be used by a soft and hard reset on a higher system hierarchy levels.

 EMBED  
Figure  SEQ "Figure" \*Arabic 4. Power-Up and Reset Sequence

 REF _Ref513206810 \h Figure 4 shows how asynchronous reset is applied after powering up the OR1200 core. Reset is connected to asynchronous reset of almost all flip-flops inside RISC core. Special care must be taken to ensure hold and setup times of all flip-flops compared to main RISC clock.

If system implements gated clocks, then clock gating can be used to ensure proper reset timing.

 EMBED  
Figure  SEQ "Figure" \*Arabic 5. Power-Up and Reset Sequence w/ Gated Clock

The address the PC assumes at reset is definable at synthesis time. This is not to be confused with the ability to set the exception prefix address with the EPH bit.

CPU/FPU/DSP

CPU/FPU/DSP is implementation of the 32-bit part of the OpenRISC 1000 architecture and only a subset of all features is implemented.


Instructions

The following table lists the instructions implemented in the OR1200. Those optionally implemented are indicated as such.
Instruction 
mnemonicOpt.Instruction 
mnemonicOpt.Instruction 
mnemonicOpt.Instruction 
mnemonicOpt.l.addl.macrcYl.shlf.sflt.sYl.addcYl.msbYl.slllf.sfne.sYl.addil.mfsprl.sllilf.sub.sYl.andl.movhil.sral.andil.mtsprl.srail.bfl.mulYl.srll.bnfl.muliYl.srlil.divYl.nopl.subYl.ff1Yl.orl.swl.fl1Yl.oril.sysl.jl.rfel.trapl.jall.roril.xorl.jalrl.sbl.xoril.jrl.sfeqlf.add.sYl.lbsl.sfgeslf.div.sYl.lbzl.sfgeulf.ftoi.sYl.lhsl.sfgtslf.itof.sYl.lhzl.sfgtulf.mul.sYl.lwsl.sfleulf.sfeq.sYl.lwzl.sfltslf.sfge.sYl.macYl.sfltulf.sfgt.sYl.maciYl.sfnelf.sfle.sYTable  SEQ "Table" \*Arabic 7: Instructions implemented in OR1200
For a complete description of each instruction's format refer to the OpenRISC 1000 System Architecture Manual.

Instruction Unit

Instruction unit generates instruction fetch effective address and fetches instructions from instruction cache. Each clock cycle one instruction can be fetched. Instruction fetch EA is further translated into physical address by IMMU.

General-Purpose Registers

General-purpose register file can supply two read operands each clock cycle and store one result in a destination register.

GPRs can be also read and written through development interface.

Load/Store Unit

LSU can execute one load instruction every two clock cycles assuming load instruction have a hit in the data cache. Execution of store instructions takes one clock cycle assuming they have a hit in the data cache.

LSU performs calculation of the load/store effective address. EA is further translated into physical address by DMMU.

Load/store effective address and load and store data can be also accessed through development interface.

Integer Execution Pipeline

The core implements the following types of 32-bit integer instructions:
Arithmetic instructions
Compare instructions
Logical instructions
Rotate and shift instructions

Instruction GroupClock Cycles to ExecuteArithmetic except Multiply/Divide1Multiply3Divide2Compare1Logical1Rotate and Shift1Others1Table  SEQ "Table" \*Arabic 8. Execution Time of Integer Instructions

 REF _Ref513308588 \h Table 8 lists execution times for instructions executed by integer execution pipeline. Most instructions are executed in one clock cycle.


MAC Unit

MAC unit executes l.mac instructions. MAC unit implements 32x32 fully pipelined multiplier and 48-bit accumulator. MAC unit can accept one new l.mac instruction each clock cycle.
Care should be taken when executing l.macrc (MAC read and clear) too soon after the final l.mac instruction as the operation may still be underway and the result will not be valid in time. It is recommended at least 3 other instructions (or just l.nops) are inserted between the final l.mac and l.macrc.

Floating Point Unit
The floating point unit has a mechanism to stall the processor pipeline until processing has completed.
The following table indicates the number of cycles per operation

OperationCyclesAdd/subtract10Multiply38Divide37Compare2Convert7Table  SEQ "Table" \*Arabic 9: Execution time of floating point instructions

System Unit

System unit implements system control and status special-purpose registers and executes all l.mtspr/l.mfspr instructions.

Exceptions

The core implements a precise exception model. This means that when an exception is taken, the following conditions are met:
Subsequent instructions in program flow are discarded
Previous instructions finish and write back their results
The address of faulting instruction is saved in EPCR registers and the machine state is saved to ESR registers

Exception TypeVector Offsetcausing conditionsReset0x100Caused by reset.Bus Error0x200Caused by an attempt to access invalid physical address.Data Page Fault0x300Generated artificially by DTLB miss exception handler when no matching PTE found in page tables or page protection violation for load/store operations.Instruction Page Fault0x400Generated artificially by ITLB miss exception handler when no matching PTE found in page tables or page protection violation for instruction fetch.Low Priority External Interrupt0x500Low priority external interrupt asserted.Alignment0x600Load/store access to naturally not aligned location.Illegal Instruction0x700Illegal instruction in the instruction stream.High Priority External Interrupt0x800High priority external interrupt asserted.D-TLB Miss0x900No matching entry in DTLB (DTLB miss).I-TLB Miss0xA00No matching entry in ITLB (ITLB miss).System Call0xC00System call initiated by software.Floating point exception0xD00FP operation caused flags in FPCSR to become set.Trap0xE00Trap instruction was decodedTable  SEQ "Table" \*Arabic 10. List of Implemented Exceptions

The OR1200 exception support does not include support for fast context switching.

Data Cache Operation

Data Cache Load/Store Access

Load/store unit requests data from the data cache and stores them into the general-purpose register file and forwards them to integer execution units. Therefore LSU is tightly coupled with the data cache.

If there is no data cache line miss nor DTLB miss, load operations take two clock cycles to execute and store operations take one clock cycle to execute. LSU does all the data alignment work.

Data can be written to the data cache on a word, half-word or byte basis. Since data cache only operates in write-through mode, all writes are immediately written back to main memory or to the next level of caches.

 EMBED  
Figure  SEQ "Figure" \*Arabic 6. WISHBONE Write Cycle

 REF _Ref513193242 \h Figure 6 shows how a write-through cycle on data WISHBONE interface is performed when a store instruction hits in the data cache.
If dwb_ERR_I or dwb_RTY_I is asserted instead of usual dwb_ACK_I, bus error exception is invoked.

Data Cache Line Fill Operation

When executing load instruction and a cache miss occurs, depending on whether the cache uses write-through or write-back strategy and the line is clean or invalid, a 4 beat sequential read burst with critical word first is performed. If the strategy is write-back and the line is dirty, the line is first written back to memory. The critical word is forwarded to the load/store unit to minimize performance loss because of the cache miss.

 EMBED  
Figure  SEQ "Figure" \*Arabic 7. WISHBONE Block Read Cycle

 REF _Ref513194821 \h Figure 7 shows how a cache line is read in WISHBONE read block cycle composed out of four read transfers.
If dwb_ERR_I or dwb_RTY_I is asserted instead of usual dwb_ACK_I, bus error exception is invoked.

When executing a store instruction with the cache in write-through strategy, and a cache miss occurs, the write is simply put on the bus and no caching occurs. If it is a miss and the cache is in write back strategy and the line is valid and clean or invalid,  a 4 beat sequential read burst to fill the line is performed, and the the write to cache occurs. If storing and a cache miss occurs, and the desired line is valid and dirty, it is first written back to memory before the desired line is read.


 EMBED  
Figure  SEQ "Figure" \*Arabic 8. WISHBONE Block Read/Write Cycle

 REF _Ref513195072 \h Figure 8 shows how a cache line is read in WISHBONE read block cycle followed by a write transfer.
If dwb_ERR_I or dwb_RTY_I is asserted instead of usual dwb_ACK_I, bus error exception is invoked.

Cache/Memory Coherency

Data cache in OR1200 operates in either write-through or write-back mode, definable at synthesis time, for default use, and runtime when DMMU is used. There is currently no coherency support between local data cache and caches of other processors.

Data Cache Enabling/Disabling

Data cache is disabled at power up. Entire data cache can be enabled by setting bit SR[DCE] to one. Before data cache is enabled, it must be invalidated.

Data Cache Invalidation

Data cache in OR1200 does not support invalidation of entire data cache. Normal procedure to invalidate entire data cache is to cycle through all data cache lines and invalidate each line separately.

Data Cache Locking

Data cache implements way locking bits in data cache control register DCCR. Bits LWx lock individual ways when they are set to one.

Data Cache Line Prefetch

Data cache line prefetch is optional in the OpenRISC 1000 architecture and is not implemented in OR1200.

Data Cache Line Flush

Operation is performed by writing effective address to the DCBFR register.

When a cache line is valid and clean, or the cache is in write-through strategy, the line is invalidated and no write-back occurs.

Data Cache Line Invalidate

Data cache line invalidate invalidates a single data cache line. Operation is performed by writing effective address to the DCBIR register.
If cache is in write-back strategy, it is best to use the line flush function.

Data Cache Line Write-back

Operation is performed by writing effective address to the DCBWR register.

If cache is in write-through strategy, this operation is ignored as no lines will be cached and dirty, capable of being written back.

Data Cache Line Lock

Locking of individual data cache lines is not implemented in OR1200.

Data Cache inhibit with address bit 31 set

If DMMU is disabled, by default all addresses with bit 31 of the address asserted high will cause the data cache to be inhibited, meaning no reads or writes are cached.

If the DMMU is enabled, it is possible for any address to be inhibited or not, and in these modes the cache behaves accordingly.


Instruction Cache Operation

Instruction Cache Instruction Fetch Access

Instruction unit requests instruction from the instruction cache and forwards them to the instruction queue inside instruction unit. Therefore instruction unit is tightly coupled with the instruction cache.

If there is no instruction cache line miss nor ITLB miss, instruction fetch operation takes one clock cycle to execute.

Instruction cache cannot be explicitly modified like data cache can be with store instructions.

Instruction Cache Line Fill Operation

On a cache miss, a 4 beat sequential read burst with critical word first is performed. Critical word is forwarded to the instruction unit to minimize performance loss because of the cache miss.

 EMBED  
Figure  SEQ "Figure" \*Arabic 9. WISHBONE Block Read Cycle

 REF _Ref513197552 \h Figure 9 shows how a cache line is read in WISHBONE read block cycle composed out of four read transfers.
If iwb_ERR_I or iwb_RTY_I is asserted instead of usual dwb_ACK_I, bus error exception is invoked.

Cache/Memory Coherency

OR1200 is not intended for use in multiprocessor environments. Therefore no support for coherency between local instruction cache and caches of other processors or main memory is implemented.

Instruction Cache Enabling/Disabling

Instruction cache is disabled at power up. Entire instruction cache can be enabled by setting bit SR[ICE] to one. Before instruction cache is enabled, it must be invalidated.

Instruction Cache Invalidation

Instruction cache in OR1200 does not support invalidation of entire instruction cache. Normal procedure to invalidate entire instruction cache is to cycle through all instruction cache lines and invalidate each line separately.

Instruction Cache Locking

Instruction cache implements way locking bits in instruction cache control register ICCR. Bits LWx lock individual ways when they are set to one.

Instruction Cache Line Prefetch

Instruction cache line prefetch is optional in the OpenRISC 1000 architecture and is not implemented in OR1200.

Instruction Cache Line Invalidate

Instruction cache line invalidate invalidates a single instruction cache line. Operation is performed by writing effective address to the ICBIR register.

Instruction Cache Line Lock

Locking of individual instruction cache lines is not implemented in OR1200.

Data MMU

Translation Disabled

Load/store address translation can be disabled by clearing bit SR[DME]. If translation is disabled, then physical address used to access data cache and optionally provided on dwb_ADDR_O, is the same as load/store effective address.

Translation Enabled

Load/store address translation can be enabled by setting bit SR[DME]. If translation is enabled, it provides load/store effective address to physical address translation and page protection for memory accesses.

 EMBED Microsoft Visio Drawing 
Figure  SEQ "Figure" \*Arabic 10. 32-bit Address Translation Mechanism using Two-Level Page Table

In OR1200 case, page tables must be managed by operating system s virtual memory management subsystem.  REF _Ref513343227 \h Figure 10 shows address translation using two-level page table. Refer to OpenRISC 1000 System Architecture Manual for one-level page table address translation as well as for details about address translation and page table content.

DMMUCR and Flush of Entire DTLB

DMMUCR is not implemented in OR1200. Therefore page table base pointer (PTBP) must be stored in software variable. Flush of entire DTLB must be performed by software flush of every DTLB entry separately. Software flush is performed by manually writing  bits from the TLB entries back to PTEs.

Page Protection

After a virtual address is determined to be within a page covered by the valid PTE, the access is validated by the memory protection mechanism. If this protection mechanism prohibits the access, a data page fault exception is generated.

The memory protection mechanism allows selectively granting read access and write access for both supervisor and user modes. The page protection mechanism provides protection at all page level granularities.

Protection attributeMeaningDTLBWyTR[SREx]Enable load operations in supervisor mode to the page.DTLBWyTR[SWEx]Enable store operations in supervisor mode to the page.DTLBWyTR[UREx]Enable load operations in user mode to the page.DTLBWyTR[UWEx]Enable store operations in user mode to the page.Table  SEQ "Table" \*Arabic 11. Protection Attributes for Load/Store Accesses

 REF _Ref513346094 \h Table 11 lists page protection attributes defined in DTLBWyTR pregister. For the individual page appropriate strategy out of seven possible strategies programmed with the PPI field of the PTE. Because OR1200 does not implement DMMUPR, translation of PTE[PPI] into suitable set of protection bits must be performed by software and written into DTLBWyTR.

DTLB Entry Reload

OR1200 does not implement DTLB entry reloads in hardware. Instead software routine must be used to search page table for correct page table entry (PTE) and copy it into the DTLB. Software is responsible for maintaining accessed and dirty bits in the page tables.

When LSU computes load/store effective address whose physical address is not already cached by DTLB, a DTLB miss exception is invoked.

DTLB reload routine must load the correct PTE to correct DTLBWyMR and DTLBWyTR register from one of possible DTLB ways.

DTLB Entry Invalidation

Special-purpose register DTLBEIR must be written with the effective address and corresponding DTLB entry will be invalidated in the local DTLB.

Locking DTLB Entries

Since all DTLB entry reloads are performed in software, there is no hardware locking of DTLB entries. Instead it is up to the software reload routine to avoid replacing some of the entries if so desired.

Page Attribute   Dirty (D)

Dirty (D) attribute is not implemented in OR1200 DTLB. It is up to the operating system to generate dirty attribute bit with page protection mechanism.

Page Attribute   Accessed (A)

Accessed (A) attribute is not implemented in OR1200 DTLB. It is up to the operating system to generate accessed attribute bit with page protection mechanism.

Page Attribute   Weakly Ordered Memory (WOM)

Weakly ordered memory (WOM) attribute is not needed in OR1200 because all memory accesses are serialized and therefore this attribute is not implemented.

Page Attribute   Write-Back Cache (WBC)

Write-back cache (WBC) attribute is not implemented as the data cache cannot be configured at run time to be write-back enabled if write-through strategy was selected at synthesis-time.

Page Attribute   Caching-Inhibited (CI)

Caching-inhibited (CI) attribute is not implemented in OR1200 DTLB. Cached and uncached regions are divided by bit 30 of data effective address.

Effective AddressRegion0x00000000 - 0x3FFFFFFFCached0x40000000 - 0x7FFFFFFFUncached0x80000000 - 0xBFFFFFFFCached0xC0000000 - 0xFFFFFFFFUncachedTable  SEQ "Table" \*Arabic 12.  Cached and uncached regions

Uncached accesses must be performed when I/O registers are memory mapped and all reads and writes must be always performed directly to the external interface and not to the data cache.

Page Attribute   Cache Coherency (CC)

Cache coherency (CC) attribute is not needed in OR1200 because it doesn t implement support for multiprocessor environments and because data cache operates only in write-through mode and therefore this attribute is not implemented.

Instruction MMU

Translation Disabled

Instruction fetch address translation can be disabled by clearing bit SR[IME]. If translation is disabled, then physical address used to access instruction cache and optionally provided on iwb_ADDR_O, is the same as instruction fetch effective address.

Translation Enabled

Instruction fetch address translation can be enabled by setting bit SR[IME]. If translation is enabled, it provides instruction fetch effective address to physical address translation and page protection for instruction fetch accesses.

 EMBED Microsoft Visio Drawing 
Figure  SEQ "Figure" \*Arabic 11. 32-bit Address Translation Mechanism using Two-Level Page Table

In OR1200 case, page tables must be managed by operating system s virtual memory management subsystem.  REF _Ref513343227 \h Figure 10 shows address translation using two-level page table. Refer to OpenRISC 1000 System Architecture Manual for one-level page table address translation as well as for details about address translation and page table content.

IMMUCR and Flush of Entire ITLB

IMMUCR is not implemented in OR1200. Therefore page table base pointer (PTBP) must be stored in software variable. Flush of entire ITLB must be performed by software flush of every ITLB entry separately. Software flush is performed by manually writing bits from the TLB entries back to PTEs.

Page Protection

After a virtual address is determined to be within a page covered by the valid PTE, the access is validated by the memory protection mechanism. If this protection mechanism prohibits the access, an instruction page fault exception is generated.

The memory protection mechanism allows selectively granting execute access for both supervisor and user modes. The page protection mechanism provides protection at all page level granularities.

Protection attributeMeaningITLBWyTR[SXEx]Enable execute operations in supervisor mode of the page.ITLBWyTR[UXEx]Enable execute operations in user mode of the page.Table  SEQ "Table" \*Arabic 13. Protection Attributes for Instruction Fetch Accesses

 REF _Ref513346094 \h Table 11 lists page protection attributes defined in ITLBWyTR pregister. For the individual page appropriate strategy out of seven possible strategies programmed with PPI field of the PTE. Because OR1200 does not implement IMMUPR, translation of PTE[PPI] into suitable set of protection bits must be performed by software and written into ITLBWyTR.


ITLB Entry Reload

OR1200 does not implement ITLB entry reloads in hardware. Instead software routine must be used to search page table for correct page table entry (PTE) and copy it into the ITLB. Software is responsible for maintaining accessed bit in the page tables.

When LSU computes instruction fetch effective address whose physical address is not already cached by ITLB, an ITLB miss exception is invoked.

ITLB reload routine must load the correct PTE to correct ITLBWyMR and ITLBWyTR register from one of possible ITLB ways.

ITLB Entry Invalidation

Special-purpose register ITLBEIR must be written with the effective address and corresponding ITLB entry will be invalidated in the local ITLB.

Locking ITLB Entries

Since all ITLB entry reloads are performed in software, there is no hardware locking of ITLB entries. Instead it is up to the software reload routine to avoid replacing some of the entries if so desired.

Page Attribute   Dirty (D)

Dirty (D) attribute resides in the PTE but it is not used by the IMMU.

Page Attribute   Accessed (A)

Accessed (A) attribute is not implemented in OR1200 ITLB. It is up to the operating system to generate accessed attribute bit with page protection mechanism.

Page Attribute   Weakly Ordered Memory (WOM)

Weakly ordered memory (WOM) attribute is not needed in OR1200 because all instruction fetch accesses are serialized and therefore this attribute is not implemented.

Page Attribute   Write-Back Cache (WBC)

Write-back cache (WBC) attribute resides in the PTE but it is not used by the IMMU.

Page Attribute   Caching-Inhibited (CI)

Caching-inhibited (CI) attribute is not implemented in OR1200 ITLB. Cached and uncached regions are divided by bit 30 of instruction effective address.

Effective AddressRegion0x00000000 - 0x3FFFFFFFCached0x40000000 - 0x7FFFFFFFUncached0x80000000 - 0xBFFFFFFFCached0xC0000000 - 0xFFFFFFFFUncachedTable  SEQ "Table" \*Arabic 14.  Cached and uncached regions

Page Attribute   Cache Coherency (CC)

Cache coherency (CC) attribute resides in the PTE but it is not used by the IMMU.

Programmable Interrupt Controller

PICMR special-purpose register is used to mask or unmask up to 30 programmable interrupt sources. PICPR special-purpose register is used to assign low or high priority to maximum of 30 interrupt sources.

PICSR special-purpose register is used to determine status of each interrupt input. Bits in PICSR represent status of the interrupt inputs and the actual interrupt must be cleared in the device that is the source of a pending interrupt.

The PIC implementation in the OR1200  differs from the architecture specification. The PIC instead offers a latched level-sensitive interrupt.

Once an interrupt line is latched (i.e. its value appears in PICSR), no new interrupts can be triggered for that line until its bit in PICSR is cleared. The usual sequence for an interrupt handler is then as follows.

Peripheral asserts interrupt, which is latched and triggers handler. 
Handler processes interrupt.
Handler notifies peripheral that the interrupt has been processed (typically via a memory mapped register).
 Peripheral deasserts interrupt.
Handler clears corresponding bit in PICSR and returns.

It is assumed that the peripheral will de-assert its interrupt promptly (within 1-2 cycles). Otherwise on exiting the interrupt handler, having cleared PICSR, the level sensitive interrupt will immediately retrigger.

Tick Timer

Tick timer facility is enabled with TTMR[M]. TTCR is incremented with each clock cycle and a high priority interrupt can be asserted whenever lower 28 bits of TTCR match TTMR[TP] and TTMR[IE] is set.

TTCR restarts counting from zero when match event happens and TTMR[M] is 0x1. If TTMR[M] is 0x2, TTCR is stoped when match event happens and TTCR must be changed to start counting again. When TTMR[M] is 0x3, TTCR keeps counting even when match event happens.

Power Management

Clock Gating and Frequency Changing Versus CPU Stalling

If system doesn t support clock gating and if changing clock frequency in slow down mode is not possible, CPU can be stalled for certain number of clock cycles. This is much lower benefit on power consumption however it still reduces power consumption.

Slow Down Mode

Slow down mode is software controlled with the 4-bit value in PMR[SDF]. Lower value specifies higher expected performance from the processor core. Usually PMR[SDF] is dynamically set by the operating system s idle routine, that monitors the usage of the processor core.

PMR[SDF] is broadcasted on pm_clksd. External clock generator should adjust clock frequency according to the value of pm_clksd. Exact slow down factors are not defined but 0xF should go all the way down to 32.768 KHz.

With pm_clksd equal to 0xF, pm_lvolt is asserted. This is an indication for the external power supply to lower the voltage.

Doze Mode

To switch to doze mode, software should set the PMR[DME]. Once an interrupt is received by the programmable interrupt controller (PIC), pm_wakeup is asserted and external clock generation circuitry should enable all clocks. Once clocks are running RISC is switched back again to the normal mode and PMR[DME] is cleared.

When doze mode is enabled, pm_dc_gate, pm_ic_gate, pm_dmmu_gate, pm_immu_gate and pm_cpugate are asserted. As a result all clocks except clk_tt should be gated by external clock generation circuitry.

Sleep Mode

To switch to sleep mode, software should set the PMR[SME]. Once an interrupt is received by the programmable interrupt controller (PIC), pm_wakeup is asserted and external clock generation should enable all clocks. Once clocks are running, RISC is switched back again to the normal mode and PMR[SME] is cleared.

When sleep mode is enabled, pm_dc_gate, pm_ic_gate, pm_dmmu_gate, pm_immu_gate, pm_cpu_gate and pm_tt_gate are asserted. As a result all clocks including clk_tt should be gated by external clock generation circuitry.

In sleep mode, pm_lvolt is asserted. This is an indication for the external power supply to lower the voltage.

Clock Gating

Clock gating feature is not implemented in OR1200 power management. 

Disabled Units Force Clock Gating

Units that are disabled in special-purpose register SR, have their clock gate signals asserted. Cleared bits SR[DCE], SR[ICE], SR[DME] and SR[IME] directly force assertion of pm_dc_gate, pm_ic_gate, pm_dmmu_gate and pm_immu_gate.

Debug Unit

Debug unit can be controlled through development interface or it can operate independently programmed and handled by the RISC s resident debug software.

Watchpoints

OR1200 debug unit does not implement OR12000 architecture watchpoints.

Breakpoint Exception

Which breakpointDMR2[WGB] bits specify which watchpoints invoke breakpoint exception. By invoking breakpoint exception, target resident debugger can be built.

Breakpoint is broadcasted on development interface on dbg_bp_o.

Development Interface

NOTE: The information in this section is to be reviewed. It is the author's opinion that the debug interface is now largely provided by the SPR mappings, and no special sideband functions exist aside from stalling and resetting the core.

An additional development and debug interface IP core may be used to connect OpenRISC 1200 to standard debuggers using IEEE.1149.1 (JTAG) protocol.

Debugging Through Development Interface

The DSR special-purpose register specifies which exceptions cause the core to stop the execution of the exception handler and turn over control to development interface. It can be programmed by the resident debug software or by the development interface.

The DRR special-purpose register is specifies which event caused the core to stop the execution of program flow and turned over control to the development interface. It should be cleared by the resident debug software or by the development interface.

The DIR special-purpose register is not implemented.

Reading PC, Load/Store EA, Load Data, Store Data, Instruction

Crucial information like program counter (PC), load/store effective address (LSEA), load data, store data and current instruction in execution pipeline can be asynchronously read through the development interface.

dbg_op_i[2:0]Meaning0x0Reading Program Counter (PC)0x1Reading Load/Store Effective Address0x2Reading Load Data0x3Reading Store Data0x4Reading SPR0x5Writing SPR0x6Reading Instruction in Execution Pipeline0x7ReservedTable  SEQ "Table" \*Arabic 15. Development Interface Operation Commands

 REF _Ref513329306 \h Table 15 lists operation commands that control what is read or written through development interface. All reads except reads and writes of SPRs are asynchronous.

Reading and Writing SPRs Through Development Interface

For reads and write to SPRs dbg_op_i must be set to 0x4 and 0x5, respectively.

 EMBED  
Figure  SEQ "Figure" \*Arabic 12. Development Interface Cycles

 REF _Ref513329852 \h Figure 12 shows development interface cycles. Writes must be synchronous to the main RISC clock positive edge and should take one clock cycle. Reads must take two clock cycles because access to synchronous cache lines or to TLB entries introduces one clock cycle of delay.

If required, external debugger can stop the CPU core by asserting dbg_stall_i. This way it can have enough time to read all interesting registers from the RISC or guarantee that writes into SPRs are performed without RISC writing to the same registers.

Tracking Data Flow

An external debugger can monitor and record data flow inside the RISC for debugging purposes and profiling analysis. This is accomplished by monitoring status of the load/store unit, load/store effective address and load/store data, all available at the development interface.

dbg_lss_o[3:0]Load/Store Instruction in Execution0x0No load/store instruction in execution0x1Reserved for load doubleword0x2Load byte and zero extend0x3Load byte and sign extend0x4Load halfword and zero extend0x5Load halfword and sign extend0x6Load singleword and zero extend0x7Load singleword and sign extend0x8Reserved for store doubleword0x9Reserved0xAStore byte0xBReserved0xCStore halfword0xDReserved0xEStore singleword0xFReservedTable  SEQ "Table" \*Arabic 16. Status of the Load/Store Unit

External trace buffer can capture all interesting data flow events by analyzing status of the load/store unit available on dbg_lss_o.  REF _Ref513326484 \h Table 16 lists different status encoding for the load/store unit.

Tracking Program Flow

An external debugger can monitor and record program flow inside the RISC for debugging purposes and profiling analysis. This is accomplished by monitoring status of the instruction unit, PC and fetched instruction word, all available at the development interface.

dbg_is_o[1:0]Instruction Fetch Status0x0No instruction fetch in progress0x1Normal instruction fetch0x2Executing branch instruction0x3Fetching instruction in delay slotTable  SEQ "Table" \*Arabic 17. Status of the Instruction Unit

External trace buffer can capture all interesting program flow events by analyzing status of the instruction unit available on dbg_is_o.  REF _Ref513326219 \h Table 17 lists different status encoding for the instruction unit.

Triggering External Watcpoint Event

 REF _Ref513324670 \h Figure 13 shows how development interface can assert dbg_ewt_I and cause watchpoint event. If programmed, external watchpoint event will cause a breakpoint exception.

 EMBED  
Figure  SEQ "Figure" \*Arabic 13. Assertion of External Watchpoint Trigger
4
Registers

This section describes all registers inside the OR1200 core. Shifting GRP number 11 bits left and adding REG number computes the address of each special-purpose register. All registers are 32 bits wide from software perspective. USER MODE and SUPV MODE specify the valid access types for each register in user mode and supervisor mode of operation. R/W stands for read and write access and R stands for read only access.

Registers list

Grp
#Reg #Reg NameUSER MODESUPV
MODEDescription00VR RVersion Register01UPR RUnit Present Register02CPUCFGR RCPU Configuration Register03DMMUCFGR RData MMU Configuration Register04IMMUCFGR RInstruction MMU Configuration Register05DCCFGR RData Cache Configuration Register06ICCFGR RInstruction Cache Configuration Register07DCFGR RDebug Configuration Register016PC R/WPC mapped to SPR space017SR R/WSupervision Register020FPCSR-R/WFP Control Status Register032EPCR0 R/WException PC Register048EEAR0 R/WException EA Register064ESR0 R/WException SR Register01024-1055GPR0-GPR31 R/WGPRs mapped to SPR space12DTLBEIR WData TLB Entry Invalidate Register11024-1151DTLBW0MR0-DTLBW0MR127 R/WData TLB Match Registers Way 011536-1663DTLBW0TR0-DTLBW0TR127 R/WData TLB Translate Registers Way 022ITLBEIR WInstruction TLB Entry Invalidate Register21024-1151ITLBW0MR0-ITLBW0MR127 R/WInstruction TLB Match Registers Way 021536-1663ITLBW0TR0-ITLBW0TR127 R/WInstruction TLB Translate Registers Way 030DCCR R/WDC Control Register32DCBFRWWDC Block Flush Register33DCBIRWWDC Block Invalidate Register34DCBWRWWDC Block Write-back register40ICCR R/WIC Control Register4256ICBIRWWIC Block Invalidate Register5256MACLOR/WR/WMAC Low5257MACHIR/WR/WMAC High616DMR1 R/WDebug Mode Register 1617DMR2 R/WDebug Mode Register 2620DSR R/WDebug Stop Register621DRR R/WDebug Reason Register80PMR R/WPower Management Register90PICMR R/WPIC Mask Register92PICSR R/WPIC Status Register100TTMR R/WTick Timer Mode Register101TTCRR*R/WTick Timer Count RegisterTable  SEQ "Table" \*Arabic 18. List of All Registers

 REF _Ref513309410 \h Table 18 lists all OpenRISC 1000 special-purpose registers implemented in OR1200. Registers VR and UPR are described below. For description of other registers refer to OpenRISC 1000 System Architecture Manual document.

Register VR description

Special-purpose register VR identifies the version (model) and revision level of the OpenRISC 1000 processor. It also specifies possible standard template on which this implementation is based.

Bit #AccessResetDescription5:0RRevisionREV
Revision number of this document.15:6R0x0Reserved23:16R0x00CFG
Configuration should be read from UPR and configuration registers31:24R0x12VER
Version number for OR1200 is fixed at 0x1200.Table  SEQ "Table" \*Arabic 19. VR Register

Register UPR description

Special-purpose register UPR identifies the units present in the processor. It has a bit for each implemented unit or functionality. Lower sixteen bits identify present units defined in the OpenRISC 1000 architecture. Upper sixteen bits define present custom units.

Bit #AccessResetDescription0R1UP
UPR present1R1DCP
Data cache present*2R1ICP
Instruction cache present*3R1DMP
Data MMU present*4R1IMP
Instruction MMU present*5R1MP
MAC present*6R1DUP
Debug unit present*7R0PCUP
Performance counters unit not present*8R1PMP
Power Management Present*9R1PICP
Programmable interrupt controller present10R1TTP
Tick timer present11R1FPP
Floating point present*23:12RXReserved31:24R0xXXXXCUP
The user of the OR1200 core adds custom units.Table  SEQ "Table" \*Arabic 20. UPR Register
* if enabled at synthesis time

Register CPUCFGR description

Special-purpose register CPUCFGR identifies the capabilities and configuration of the CPU. 

Bit #AccessResetDescription3:0R0x0NSGF
Zero number of shadow GPR files4R0HGF
No half GPR files*5R1OB32S
ORBIS32 supported6R0OB64S
ORBIS64 not supported7R1OF32S
ORFPX32 supported**8R0OF64S
ORFPX64 not supported9R0OV64S
ORVDX64 not supportedTable  SEQ "Table" \*Arabic 21. CPUCFGR Register
* If disabled at synthesis time
** If FPU enabled at synthesis time

Register DMMUCFGR description

Special-purpose register DMMUCFGR identifies the capabilities and configuration of the DMMU. 

Bit #AccessResetDescription1:0R0x0NTW
One DTLB way4:2R0x4   0x7NTS
16, 32, 64 or 128 DTLB sets7:5R0x0NAE
No ATB Entries8R0CRI
No DMMU control register implemented9R0PRI
No protection register implemented10R1TEIRI
DTLB entry invalidate register implemented11R0HTR
No hardware DTLB reloadTable  SEQ "Table" \*Arabic 22. DMMUCFGR Register

Register IMMUCFGR description

Special-purpose register IMMUCFGR identifies the capabilities and configuration of the IMMU. 

Bit #AccessResetDescription1:0R0x0NTW
One ITLB way4:2R0x4   0x7NTS
16, 32, 64 or 128 ITLB sets7:5R0x0NAE
No ATB Entries8R0CRI
No IMMU control register implemented9R0PRI
No protection register implemented10R1TEIRI
ITLB entry invalidate register implemented11R0HTR
No hardware ITLB reloadTable  SEQ "Table" \*Arabic 23. IMMUCFGR Register

Register DCCFGR description

Special-purpose register DCCFGR identifies the capabilities and configuration of the data cache. 

Bit #AccessResetDescription2:0R0x0NCW
One DC way6:3R0x4   0x7NCS
16, 32, 64 or 128 DC sets7R0x0CBS
16-byte cache block size8R0CWS
Cache write-through strategy*9R1CCRI
DC control register implemented10R1CBIRI
DC block invalidate register implemented11R0CBPRI
DC block prefetch register not implemented12R0CBLRI
DC block lock register not implemented13R1CBFRI
DC block flush register implemented14R1CBWBRI
DC block write-back register  implemented**Table  SEQ "Table" \*Arabic 24. DCCFGR Register
*If Write-through enabled at synthesis time
**If Write-through disabled at synthesis time


Register ICCFGR description

Special-purpose register ICCFGR identifies the capabilities and configuration of the instruction cache. 

Bit #AccessResetDescription2:0R0x0NCW
One IC way6:3R0x4   0x7NCS
16, 32, 64 or 128 IC sets7R0x0CBS
16-byte cache block size8R0CWS
Cache write-through strategy9R1CCRI
IC control register implemented10R1CBIRI
IC block invalidate register implemented11R0CBPRI
IC block prefetch register not implemented12R0CBLRI
IC block lock register not implemented13R1CBFRI
IC block flush register implemented14R0CBWBRI
IC block write-back register not implementedTable  SEQ "Table" \*Arabic 25. ICCFGR Register

Register DCFGR description

Special-purpose register DCFGR identifies the capabilities and configuration of the debut unit. 

Bit #AccessResetDescription3:0R0x0NDP
Zero DVR/DCR pairs*4R0 WPCI
Watchpoint counters not implementedTable  SEQ "Table" \*Arabic 26. DCFGR Register
* If hardware breakpoints disabled at synthesis time
      


5
IO ports

OR1200 IP core has several interfaces.  REF _Ref507257694 \h Figure 14 below shows all interfaces:
Instruction and data WISHBONE host interfaces
Power management interface
Development interface
Interrupts interface

 EMBED Microsoft Visio Drawing 

Figure  SEQ "Figure" \*Arabic 14. Core s Interfaces

Instruction WISHBONE Master Interface

OR1200 has two master WISHBONE Rev B compliant interfaces. Instruction interface is used to connect OR1200 core to memory subsystem for purpose of fetching instructions or instruction cache lines.

PortWidthDirectionDescriptioniwb_CLK_I1InputClock inputiwb_RST_I1InputReset inputiwb_CYC_O1OutputIndicates valid bus cycle (core select)iwb_ADR_O32OutputsAddress outputsiwb_DAT_I32InputsData inputsiwb_DAT_O32OutputsData outputsiwb_SEL_O4OutputsIndicates valid bytes on data bus (during valid cycle it must be 0xf)iwb_ACK_I1InputAcknowledgment input (indicates normal transaction termination)iwb_ERR_I1InputError acknowledgment input (indicates an abnormal transaction termination)iwb_RTY_I1InputIn OR1200 treated same way as iwb_ERR_I.iwb_WE_O1OutputWrite transaction when asserted highiwb_STB_O1OutputsIndicates valid data transfer cycleTable  SEQ "Table" \*Arabic 27. Instruction WISHBONE Master Interface  Signals

Data WISHBONE Master Interface

OR1200 has two master WISHBONE Rev B compliant interfaces. Data interface is used to connect OR1200 core to external peripherals and memory subsystem for purpose of reading and writing data or data cache lines.

PortWidthDirectionDescriptiondwb_CLK_I1InputClock inputdwb_RST_I1InputReset inputdwb_CYC_O1OutputIndicates valid bus cycle (core select)dwb_ADR_O32OutputsAddress outputsdwb_DAT_I32InputsData inputsdwb_DAT_O32OutputsData outputsdwb_SEL_O4OutputsIndicates valid bytes on data bus (during valid cycle it must be 0xf)dwb_ACK_I1InputAcknowledgment input (indicates normal transaction termination)dwb_ERR_I1InputError acknowledgment input (indicates an abnormal transaction termination)dwb_RTY_I1InputIn OR1200 treated same way as dwb_ERR_I.dwb_WE_O1OutputWrite transaction when asserted highdwb_STB_O1OutputsIndicates valid data transfer cycleTable  SEQ "Table" \*Arabic 28. Data WISHBONE Master Interface  Signals

System Interface

System interface connects reset, clock and other system signals to the OR1200 core.

PortWidthDirectionDescriptionRst1InputAsynchronous resetclk_cpu1InputMain clock input to the RISCclk_dc1InputData cache clockclk_ic1InputInstruction cache clockclk_dmmu1InputData MMU clockclk_immu1InputInstruction MMU clockclk_tt1InputTick timer clockTable  SEQ "Table" \*Arabic 29. System Interface Signals

Development Interface

Development interface connects external development port to the RISC s internal debug facility. Debug facility allows control over program execution inside RISC, setting of breakpoints and watchpoints, and tracing of instruction and data flows.

PortWidthDirectionDescriptiondbg_dat_o32OutputTransfer of data from RISC to external development interfacedbg_dat_i32InputTransfer of data from external development interface to RISCdbg_adr_i32InputAddress of special-purpose register to be read or writtendbg_op_I3InputOperation select for development interfacedbg_lss_o4OutputStatus of load/store unitdbg_is_o2OutputStatus of instruction fetch unitdbg_wp_o11OutputStatus of watchpointsdbg_bp_o1OutputStatus of the breakpointdbg_stall_i1InputStalls RISC CPU coredbg_ewt_i1InputExternal watchpoint triggerTable  SEQ "Table" \*Arabic 30. Development Interface

Power Management Interface

Power management interface provides signals for interfacing RISC core with external power management circuitry. External power management circuitry is required to implement functions that are technology specific and cannot be implemented inside OR1200 core.

PortWidthDirectionGenerationDescriptionpm_clksd4OutputStatic (in SW)Slow down outputs that control reduction of RISC clock frequencypm_cpustall1Input-Synchronous stall of the RISC s CPU corepm_dc_gate1OutputDynamic (in HW)Gating of data cache clockpm_ic_gate1OutputDynamic (in HW)Gating of instruction cache clockpm_dmmu_gate1OutputDynamic (in HW)Gating of data MMU clockpm_immu_gate1OutputDynamic (in HW)Gating of instruction MMU clockpm_tt_gate1OutputDynamic (in HW)Gating of tick timer clockpm_cpu_gate1OutputStatic (in SW)Gating of main CPU clockpm_wakeup1OutputDynamic (in HW)Activate all clockspm_lvolt1OutputStatic (in SW)Lower voltageTable  SEQ "Table" \*Arabic 31. Power Management Interface

Interrupt Interface

Interrupt interface has interrupt inputs for interfacing external peripheral s interrupt outputs to the RISC core. All interrupt inputs are evaluated on positive edge of main RISC clock.

PortWidthDirectionDescriptionpic_intsPIC_INTSInputExternal interruptsTable  SEQ "Table" \*Arabic 32. Interrupt Interface
A
Core HW Configuration

This section describes parameters that are set by the user of the core and define configuration of the core. Parameters must be set by the user before actual use of the core in simulation or synthesis.

Variable NameRangeDefaultDescriptionEADDR_WIDTH3232Effective address widthVADDR_WIDTH3232Virtual address widthPADDR_WIDTH24   3632Physical address widthDATA_WIDTH3232Data width / Operation widthDC_IMPL0   11Data cache implementationDC_SETS512512Data cache number of setsDC_WAYS11Data cache number of waysDC_LINE1616Data cache line sizeIC_IMPL0   11Instruction cache implementationIC_SETS512512Instruction cache number of setsIC_WAYS11Instruction cache number of waysIC_LINE1616Instruction cache line size in bytesDMMU_IMPL0   11Data MMU implementationDTLB_SETS6464Data TLB number of setsDTLB_WAYS11Data TLB number of waysIMMU_IMPL0   11Instruction MMU implementationITLB_SETS6464Instruction TLB number of setsITLB_WAYS11Instruction TLB number of waysPIC_INTS2   3230Number of interrupt inputs


OpenCores        TITLE OpenRISC 1200 IP Core  DATE \@"M/D/YY" 11/1/10

 HYPERLINK "http://www.opencores.org/"www.opencores.org       Rev 0.10 Preliminary        PAGE 61 of  NUMPAGES \*Arabic 61







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вйрWЅ0Щ=с“Б5"“]цПAa5œПooЮВзПщПєЩџиппїGYLЯђяpЧџ!їDЯЯOџaџАє“Яцюџ џЋљ14бчd4юV$6№HZlжорЙЮoq:я?=“Iїе)ђЈ…џжтЈ…Р4­гх‚ы‚чцћ‰‹™\* šFркјц4@ѕGŸСVЖ™ЕьŸф‹јїПьIЁ;šУАН"ЅЏ*Џ<Џ` ?ф_љџЕA=ц/ХэнmЏП‘ЏЃЏЕЏЧЋп€и aмЏюЏМЮ$ŒNAПTЎ       `ПrПC5‹ПEЯБ
VerboseFileInput        0
1ЯDiДГйіIОяаяˆ§эђџwЯI''џЅХРўа?§џє?{џї€/ŸтџВ'С)O;O uCс6дЙqM,+sЙqEсOiЂх‘ЃЕќЧкк\"з9N'•<•!їеБ…џжБ…+=OЙq™чVLunUЇxX5“xW€­ЙqЖ™@gЯЅХ›X@?S—лdЈApўdм/ /6э/Ъ=сS/ј/w/‰/›/ЪЏП/б/у/эo?ЋбPaЋ3?Ю}PaY9$„ч‘ЋЙЖхПНœ?Ў?ˆџЁR}Oщ?7чXOЅХP‰V\O5щ…ЈЉгўУѕD & A aџttribute‡sjBXЈпКпRt•тЌИI~wУtWŸ!3u’ѓП0Уѕ}–ўд@4v,СPЮВ,Ÿ”аOдŸiu
VerboseSequenceVerification     0
__._Ш@_R_„R“ѓФ'bЮЖdщ їд€ŠU6ŠT€ŠUўПІ_И_;@ўЈЂu
НQfp@ФUсSЂ‘`мІjИjZ­e$@ххЃ/@)‘Вp•upю5З€fp@z3ШQ/В5ПGОжЇDi‡МыЂУвfЗ!ЊДZoЅХ§ŠUюП@ЅOњ‡ЄOњ†iчØoЊo`џ F]tбEчЦќвмouIХdЯ"04FXj+~„RQчІ“ж•TЂ‘,пОOнЂ‘Y5HЁƒя•ъИХo  €1Ы‘#5Gэџ`kОљь0ŒдоюПчпљп;ЧЭџjD{Ї8яС\эUtя€ЄяŸяpїп‰туўё†TLB SET? INDEXЉ’ЭУЈŸ„ROпџџУ•lљ†?oЅa7’p? ›]1s’]Yтэ#Зїримж’V™Њˆ}-Љ­фbХЈvF€РР@ў"Z1)ХЈЛYЛІРRЛRFОЃЪЂХЂ”ттИo[0ЮmсSЭСRЛВfфiЖмTН‰ђ#И№qЬТ2“фу7уFXф„PѓŽX~С8ХЕŠЯœЪ
\0ЏТqqIХ}ƒSY1…№ЏмH€џЌпОн*"яБ$тяБ@J‚+        ›/ђуCё8!HЁCќSZџЩСХ“%5|џ€ИХ–џЈџКџŠшq]_UЊ#ї#Двф“U
IncludeDelayTime        1
ЊUд“UњЅV€ЊСЯВФжыSъ F(~СeгNB‘DдщФћХЕ
ExecuteFromTopLevel     1
/b8!Ћ€LШQ‡ZШGР#27ЧqД@Ќ?ГOХFЌcDдр?эррЧяАСЊСџup!%HЁ}‘u䈑n9HЁншq пf*Рп†/фпЊ&јяЏ-˜‹Т6~_№яЂ]яО<г_х_4ghяm^$o_HmПяq_|oŽoЇTпХЕ:ь‹-ё0э
TimeOutInDiagramLengths 0
-ё1
DefaultCycleClock       Unclocked
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DefaultCycleEdge        neg
и*'е„ŸAпšып,Ÿ‰псmзŸНпћŸвhЏўпg…RQшINV№/бЬqё8o/'/і˜D)ЙЫt,Јг…/оы§ іхєџюфЪ/м/ю/??$?`6?H?Z?l?~?/бнљKЦЋ?UП
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1CЁ/Г/Х/‹_Э92_ /пh_Ю:‡_™_4/Н_X&и_D_…/o'_2oDo%о*г><жWAY 0Wжяя@џњH—пI?0$сrэЂСљг~A,‘!шф,Ÿ=t5ѕA%?ssi›_eщAe?аw?‰?›?ЩрEчљЇџ@@р‹јПьIщћ}Uђ–шќžи?Q’h™}BLE+‹OLBВ[Ђ/:ц`†ЄшC‰LCўРт1‘LEб<7г]uИј
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CORGROUP        $$CLK_I_BufferRising
Лk0GrpС ЯЯэіибћ§JЯ\ЭЏ+ЏљишбШdƒУЃЩ>РД7@џ@Рёй“юђ|хјМО{ЈP-DпTћ!љП]СˆЕ-Ђвu{Р`uЙ№`џфbu
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Percent 100
!
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CORGROUP        $$CLK_I_BufferFalling
ФМŒ>“~СВEЃЁгБУ7бPEЇ
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Percent 100
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ШhZŸУaєa‚Я
CORGROUP        $$CLK_I_BufferRisingFalling
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Percent 100
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!
!“у’Я_ч_пŸƒп•пAŸŸeŸ/ЮћєН/д_ч[PROTџECTION
CORGROUP        $$CLK_I_BufferRising
џATTRIBUTESђ/џџ$џ6џ€HџZџlџ~џџЂџе
Percent 100
€ЅшЖеђЩnЗXхo$6HZl~ ™wH1ЇyѕFХ
!
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CORGROUP        $$CLK_I_BufferFalling
FџAULT EXCEP31O2ксСP?b?t?†?‹xЃ9#СїСxфј—РCЇщСц?Џќёј"џў/{  @@?К  л6АbuЩƒбј7OIO[OmOO‘OЃOЕOЧOйOЂксА   Њ–ХД‰ds@ыТѕ§Њ–ЇЉ—"ЏЎЯРe1ЏiKЏЉ*o
Percent 100
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ЛЏЋ/пЏ?(џ:џT?^џx?Пџ ”џVyлNsАГŒxВs§TіFADDR[3?1:13]
CORGROUP        $$CLK_I_BufferRisingFalling
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Percent 100
!
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CORGROUP        $$CLK_I_BufferRising
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CORGROUP        $$CLK_I_BufferFalling
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Percent 100
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CORGROUP        $$CLK_I_BufferFalling
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CORGROUP        $$CLK_I_BufferRisingFalling
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CORGROUP        $$CLK_RISC_BufferRising
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Percent 100
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CORGROUP        $$CLK_RISC_BufferFalling
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Percent 100
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CORGROUP        $$CLK_RISC_BufferRisingFalling
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Percent 100
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CORGROUP        $$CLK_I_BufferRising
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Percent 100
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CORGROUP        $$CLK_I_BufferFalling
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Percent 100
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CORGROUP        $$CLK_I_BufferRisingFalling
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CORGROUP        $$CLK_RISC_BufferRising
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CORGROUP        $$CLK_RISC_BufferFalling
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Percent 100
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RectangleDynamic connectorф ”0lx„€Œ_VPID_ALTERNATENAMESўB`_PID_LINKBASEAф     ўџ
CORGROUP        $$CLK_RISC_BufferRisingFalling
џџџџQН…<ѓбЅ=Kuy›Timing DiagramTiming.Document.1є9ВqTimingDiagramўџ
Percent 100
џџџџQН…<ѓбЅ=Kuy›Timing DiagramTiming.Document.1є9ВqTiming DiagramTiming Diagram Editor v7.1g - Output File
!
PROJECT
CORGROUP        $$CLK_I_BufferRising
BaseTimeUnit    1
Percent 100
DisplayTimeUnit 2
!
TextGridX       250.000000
TextGridY       6
CORGROUP        $$CLK_I_BufferFalling
EdgeGridX       250.000000
Percent 100
ImportStartTime 0.000000
!
ImportEndTime   281474976710656.000000
TimePerPixel    5.428571
CORGROUP        $$CLK_I_BufferRisingFalling
Visible DELAYS  SETUPS  HOLDS   SAMPLES TEXT    HIDDENATTACHMENTS       CRITICALPATHS   GRIDLINES       UNCERTAINTY
Percent 100
ColWidths       144,216,288,423,488
!
ScrollPos       0.000000,0.000000,0.000000
DefDelayRule    1
CORGROUP        $$CLK_RISC_BufferRising
NoEventOverlap  NO
Percent 100
SigLabelFontHeight      10
!
LabelHeight     12
LoadLibsToMem   1
CORGROUP        $$CLK_RISC_BufferFalling
UseFullPathNames        1
Percent 100
LibPath
!
EntireTime      YES
PrintTimeSpecified      NO
CORGROUP        $$CLK_RISC_BufferRisingFalling
FromTime        0
Percent 100
ToTime  4.75
!
AllSignals      YES
CurrSelSigs     NO
CORGROUP        $$CLK_I_BufferRising
PrintTo 2
Percent 100
PrintFileName   C:\DOCS\untitled1.wmf
!
PreviewInterchange      YES
PreviewTIFF5    NO
CORGROUP        $$CLK_I_BufferFalling
UseMargins      NO
Percent 100
PrintTimeLine   NO
!
PrintBorderBox  YES
PrintSigNames   YES
CORGROUP        $$CLK_I_BufferRisingFalling
PrintSigNamesOnEachPage YES
Percent 100
AddPreviewToEPS NO
!
PreviewRes      150
MarginLR        1.25
CORGROUP        $$CLK_RISC_BufferRising
MifImageWidth   6.00
Percent 100
MarginTB        Auto
!
Header  %d %t;%f;%p
Footer
CORGROUP        $$CLK_RISC_BufferFalling
ScaleHorz       100
Percent 100
ScaleVert       100
!
ScaleHPage      1
PrintImage      DIAGRAM
CORGROUP        $$CLK_RISC_BufferRisingFalling
DefaultTimingModel      minmax
Percent 100
DefaultClock    Unclocked
!
DefaultEdgeLevel        neg
DefaultSet      Not Used
CORGROUP        $$CLK_I_BufferRising
DefaultClear    Not Used
Percent 100
DefaultClockEnable      Not Used
!
DefaultClockToOutLH     0
DefaultClockToOutHL     0
CORGROUP        $$CLK_I_BufferFalling
DefaultSetup    0
Percent 100
DefaultHold     0
!
DefaultRegStartupState  unknown
DefaultPodSize  8
CORGROUP        $$CLK_I_BufferRisingFalling
DefaultActiveLowSetClear        True
Percent 100
DefaultAsyncSetClear    True
!
DefaultActiveLowClockEnable     True
SigLabelFontHeight      10
CORGROUP        $$CLK_RISC_BufferRising
PROPS!
Percent 100
!
!
STYLE
CORGROUP        $$CLK_RISC_BufferFalling
DefaultFont     USER    {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
Percent 100
DrawWndFont     DEFAULT
!
DrawWndColor    DEFAULT
GridWndFont     DEFAULT
CORGROUP        $$CLK_RISC_BufferRisingFalling
GridWndColor    DEFAULT
Percent 100
LabelWndFont    USER    {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
!
LabelWndColor   DEFAULT
ParamDispPref   0
CORGROUP        $$CLK_I_BufferRising
ParamWndCellDisplay     0
Percent 100
CustDispString  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
!
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
MarkerDispPref  4
CORGROUP        $$CLK_I_BufferFalling
MarkerCustDispString    %n v=%mv,%Mv d=%md %t
Percent 100
MarkerCustomDisplayStringRTF    {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
!
SignalColor     2
LabelOffset     2
CORGROUP        $$CLK_I_BufferRisingFalling
BusDisplay      0
Percent 100
WaveFormWidth   1.000000
!
WaveFormColor   0
InputWaveFormColor      16711680
CORGROUP        $$CLK_RISC_BufferRising
SlantedEdges    1
Percent 100
SlantAngle      75
!
RightJustifySigNames    1
AutosplitEnabled        1
CORGROUP        $$CLK_RISC_BufferFalling
AutosplitChar   _
Percent 100
DynamSizedSignals       1
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
DIAGRAMTESTBENCHSETTINGS
Percent 100
FilesBeforeDiagramModel
!
FilesInsideDiagramModelDeclarationSection
AbortHdlCodeEnabled     1
CORGROUP        $$CLK_I_BufferRising
DelayHdlCodeEnabled     1
Percent 100
SampleHdlCodeEnabled    1
!
MarkerHdlCodeEnabled    1
VerboseSamples  0
CORGROUP        $$CLK_I_BufferFalling
VerboseDelays   0
Percent 100
VerboseFileInput        0
!
VerboseSequenceVerification     0
IncludeDelayTime        1
CORGROUP        $$CLK_I_BufferRisingFalling
ExecuteFromTopLevel     1
Percent 100
TimeOutInDiagramLengths 0
!
DefaultCycleClock       Unclocked
DefaultCycleEdge        neg
CORGROUP        $$dwb_CLK_RISC_BufferRising
!
Percent 100
!
MACROS
!
CORGROUP        $$dwb_CLK_RISC_BufferFalling
Percent 100
CORGROUP        $$CLK_I_BufferRising
!
Percent 100
!
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferRising
Percent 100
CORGROUP        $$CLK_I_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferFalling
Percent 100
CORGROUP        $$CLK_I_BufferRising
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_RISC_BufferRising
Percent 100
CORGROUP        $$CLK_I_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_RISC_BufferFalling
Percent 100
CORGROUP        $$CLK_I_BufferRising
!
Percent 100
!
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferRising
Percent 100
CORGROUP        $$CLK_I_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferFalling
Percent 100
CORGROUP        $$CLK_I_BufferRising
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_RISC_BufferRising
Percent 100
CORGROUP        $$CLK_I_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_RISC_BufferFalling
Percent 100
CORGROUP        $$CLK_I_BufferRising
!
Percent 100
!
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferRising
Percent 100
CORGROUP        $$CLK_I_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferFalling
Percent 100
CORGROUP        $$CLK_I_BufferRising
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_RISC_BufferRising
Percent 100
CORGROUP        $$CLK_I_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_RISC_BufferFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRising
!
Percent 100
!
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferRising
Percent 100
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRising
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_RISC_BufferRising
Percent 100
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_RISC_BufferFalling
Percent 100
CORGROUP        $$CLK_I_BufferRising
!
Percent 100
!
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferRising
Percent 100
CORGROUP        $$CLK_I_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRising
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_RISC_BufferRising
Percent 100
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_RISC_BufferFalling
Percent 100
CORGROUP        $$CLK_I_BufferRising
!
Percent 100
!
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferRising
Percent 100
CORGROUP        $$CLK_I_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRising
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
CORGROUP        $$CLK_I_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferRising
Percent 100
CORGROUP        $$CLK_I_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRising
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferFalling
!
Percent 100
!
CLOCK   CLK_RISC
PERIODE 2.5
CORGROUP        $$CLK_RISC_BufferRisingFalling
DUTY    50
Percent 100
OFFSETE 0
!
INITIAL HIGH
MAXUNCERTRISE   0
CORGROUP        $$CLK_RISC_BufferRising
MAXUNCERTFALL   0
Percent 100
MINUNCERTRISE   0
!
MINUNCERTFALL   0
JRISEE  0
CORGROUP        $$CLK_RISC_BufferFalling
JFALLE  0
Percent 100
GRID    0        1       0        2       0        16711680        0        0
!
ENDGRID -1
DIRECTION       internal
CORGROUP        $$CLK_RISC_BufferRisingFalling
MASTERCLOCK     None
Percent 100
Clock   Unclocked
!
EdgeLevel       neg
Set     Not Used
CORGROUP        $$CLK_RISC_BufferRising
Clear   Not Used
Percent 100
ClockEnable     Not Used
!
ActiveLowSetClear       True
AsyncSetClear   True
CORGROUP        $$CLK_RISC_BufferFalling
ActiveLowClockEnable    True
Percent 100
VhdlType        std_logic
!
VerilogType     wire
SystemCType     sc_logic
CORGROUP        $$CLK_RISC_BufferRisingFalling
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Percent 100
StateEquation   Hex(Inc(0,2,5))
!
HighVoltageThreshold    5
LowVoltageThreshold     0
CORGROUP        $$CLK_RISC_BufferRising
MSB     0
Percent 100
LSB     0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
CORGROUP        $$CLK_RISC_BufferFalling
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$CLK_RISC_BufferRisingFalling
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
PROPS!
CORGROUP        $$CLK_RISC_BufferRising
!
Percent 100
!
CLOCK   dwb_CLK_I
PERIODE 5
CORGROUP        $$CLK_RISC_BufferFalling
DUTY    50
Percent 100
OFFSETE 0
!
INITIAL LOW
MAXUNCERTRISE   0
CORGROUP        $$CLK_RISC_BufferRisingFalling
MAXUNCERTFALL   0
Percent 100
MINUNCERTRISE   0
!
MINUNCERTFALL   0
JRISEE  0
CORGROUP        $$CLK_RISC_BufferRising
JFALLE  0
Percent 100
GRID    1       1       1       2       2       16711680        0        0
!
ENDGRID -1
DIRECTION       input
CORGROUP        $$CLK_RISC_BufferFalling
MASTERCLOCK     None
Percent 100
Clock   Unclocked
!
EdgeLevel       neg
Set     Not Used
CORGROUP        $$CLK_RISC_BufferRisingFalling
Clear   Not Used
Percent 100
ClockEnable     Not Used
!
ActiveLowSetClear       True
AsyncSetClear   True
CORGROUP        $$CLK_RISC_BufferRising
ActiveLowClockEnable    True
Percent 100
VhdlType        std_logic
!
VerilogType     wire
SystemCType     sc_logic
CORGROUP        $$CLK_RISC_BufferFalling
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Percent 100
StateEquation   Hex(Inc(0,2,5))
!
HighVoltageThreshold    5
LowVoltageThreshold     0
CORGROUP        $$CLK_RISC_BufferRisingFalling
MSB     0
Percent 100
LSB     0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   True
CORGROUP        $$CLK_RISC_BufferRising
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$CLK_RISC_BufferFalling
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
PROPS!
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
SIGNAL  dwb_ADR_O
DIRECTION       output
CORGROUP        $$CLK_RISC_BufferRising
RADIX   hex
Percent 100
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock
CORGROUP        $$CLK_RISC_BufferFalling
EdgeLevel       neg
Percent 100
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
CORGROUP        $$CLK_RISC_BufferRisingFalling
ActiveLowSetClear       True
Percent 100
AsyncSetClear   True
!
ActiveLowClockEnable    True
VhdlType        std_logic
CORGROUP        $$clk_risc_BufferRising
VerilogType     wire
Percent 100
SystemCType     sc_logic
!
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
CORGROUP        $$clk_risc_BufferFalling
HighVoltageThreshold    5
Percent 100
LowVoltageThreshold     0
!
LSB     0
MSB     31
CORGROUP        $$clk_risc_BufferRisingFalling
SignalActionType        0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   True
DrawAnalog      0
CORGROUP        $$clk_risc_BufferRising
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$clk_risc_BufferFalling
VerilogCode
Percent 100
VHDLCode
!
VhdlMapping     DefaultVhdlMapping
PROPS!
CORGROUP        $$clk_risc_BufferRisingFalling
E0      V       -1      -1              1       0        DR      0
Percent 100
E1      X       3123    3123            1       0        DR      0
!
E2      V       13125   13125     A0    1       0        DR      0
E3      X       13625   13625           1       0        DR      0
CORGROUP        $$clk_risc_BufferRising
E4      V       23125   23125     A4    1       0        DR      0
Percent 100
E5      X       23625   23625           1       0        DR      0
!
E6      V       33125   33125     A8    1       0        DR      0
E7      X       33625   33625           1       0        DR      0
CORGROUP        $$clk_risc_BufferFalling
E8      V       43125   43125     A12   1       0        DR      0
Percent 100
E9      X       43750   43750           1       0        DR      0
!
E10     V       53125   53125    A0     1       0        DR      0
E11     X       53750   53750           1       0        DR      0
CORGROUP        $$clk_risc_BufferRisingFalling
!
Percent 100
!
SIGNAL  dwb_DAT_I
DIRECTION       input
CLOCK   clk_risc
RADIX   hex
PERIODE 1
GRID    0        1       0        1       0        16711680        0        0
DUTY    50
ENDGRID -1
OFFSETE 0
Clock
INITIAL LOW
EdgeLevel       neg
MAXUNCERTRISE   0
Set     Not Used
MAXUNCERTFALL   0
Clear   Not Used
MINUNCERTRISE   0
ClockEnable     Not Used
MINUNCERTFALL   0
ActiveLowSetClear       True
JRISEE  0
AsyncSetClear   True
JFALLE  0
ActiveLowClockEnable    True
GRID    1       1       1       2       2       16711680        0        0
VhdlType        std_logic
ENDGRID -1
VerilogType     wire
DIRECTION       input
SystemCType     sc_logic
MASTERCLOCK     None
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Clock   Unclocked
StateEquation   Hex(Inc(0,2,5))
EdgeLevel       neg
HighVoltageThreshold    5
Set     Not Used
LowVoltageThreshold     0
Clear   Not Used
LSB     0
ClockEnable     Not Used
MSB     31
ActiveLowSetClear       True
SignalActionType        0
AsyncSetClear   True
isFallingEdgeSensitive  False
ActiveLowClockEnable    True
isRisingEdgeSensitive   False
VhdlType        std_logic
DrawAnalog      0
VerilogType     wire
BooleanEquation
SystemCType     sc_logic
NegTolerance    0
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
PosTolerance    0
StateEquation   Hex(Inc(0,2,5))
UserSpecifiedSizeRatio  1
HighVoltageThreshold    5
VerilogCode
LowVoltageThreshold     0
VHDLCode
MSB     0
VhdlMapping     DefaultVhdlMapping
LSB     0
PROPS!
isFallingEdgeSensitive  False
E0      X       11250   11250           1       0        DR      0
isRisingEdgeSensitive   True
E1      V       13125   13125   D0      1       0        DR      0
DrawAnalog      0
E2      X       21250   21250           1       0        DR      0
BooleanEquation
E3      V       23125   23125   D4      1       0        DR      0
NegTolerance    0
E4      X       31250   31250           1       0        DR      0
PosTolerance    0
E5      V       33125   33125   D8      1       0        DR      0
UserSpecifiedSizeRatio  1
E6      X       41250   41250           1       0        DR      0
Verilog§џџџ‚ƒ„…ўџџџ‡ˆ‰Š‹ŒŽ‘’“”•–—˜™š›ўџџџžŸ ЁЂЃЄЅІЇЈЉЊЋЌ­ЎЏАБВГДЕЖЗИЙКЛМНОПРСТУФХЦЧШЩЪЫЬЭЮЯабвгдўџџџ3зийклмнопрстуфхцчшщъыьэюя№ёђѓєѕіїјљњћќ§ўџCode
E7      V       43125   43125   D12     1       0        DR      0
VHDLCode
E8      X       53750   53750           1       0        DR      0
PROPS!
!
!
SIGNAL  dwb_DAT_O
SIGNAL  dbg_wp_o[11]
DIRECTION       output
DIRECTION       output
RADIX   hex
RADIX   hex
GRID    0        1       0        1       0        16711680        0        0
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
ENDGRID -1
Clock   Unclocked
Clock   Unclocked
EdgeLevel       neg
EdgeLevel       neg
Set     Not Used
Set     Not Used
Clear   Not Used
Clear   Not Used
ClockEnable     Not Used
ClockEnable     Not Used
ActiveLowSetClear       True
ActiveLowSetClear       True
AsyncSetClear   True
AsyncSetClear   True
ActiveLowClockEnable    True
ActiveLowClockEnable    True
VhdlType        std_logic
VhdlType        std_logic
VerilogType     wire
VerilogType     wire
SystemCType     sc_logic
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
HighVoltageThreshold    5
LowVoltageThreshold     0
LowVoltageThreshold     0
LSB     0
SignalActionType        0
MSB     31
MSB     0
SignalActionType        0
LSB     0
isFallingEdgeSensitive  False
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
isRisingEdgeSensitive   False
DrawAnalog      0
DrawAnalog      0
BooleanEquation
BooleanEquation
NegTolerance    0
NegTolerance    0
PosTolerance    0
PosTolerance    0
UserSpecifiedSizeRatio  1
UserSpecifiedSizeRatio  1
VerilogCode
VerilogCode
VHDLCode
VHDLCode
PROPS!
PROPS!
E0      X       3125    3125            1       0        DR      0
E0      0        1750    1750            1       0        DR      0
E1      V       3126    3126    D0      1       0        DR      0
E1      1       3750    3750            1       0        DR      0
E2      X       43125   43125           1       0        DR      0
E2      0        4750    4750            1       0        DR      0
E3      V       53124   53124     D0    1       0        DR      0
!
E4      X       53750   53750           1       0        DR      0
!
SIGNAL  dbg_bp_o
DIRECTION       output
SIGNAL  dwb_WE_O
RADIX   hex
DIRECTION       output
GRID    0        1       0        1       0        16711680        0        0
RADIX   hex
ENDGRID -1
GRID    0        1       0        1       0        16711680        0        0
Clock   Unclocked
ENDGRID -1
EdgeLevel       neg
Clock   Unclocked
Set     Not Used
EdgeLevel       neg
Clear   Not Used
Set     Not Used
ClockEnable     Not Used
Clear   Not Used
ActiveLowSetClear       True
ClockEnable     Not Used
AsyncSetClear   True
ActiveLowSetClear       True
ActiveLowClockEnable    True
AsyncSetClear   True
VhdlType        std_logic
ActiveLowClockEnable    True
VerilogType     wire
VhdlType        std_logic
SystemCType     sc_logic
VerilogType     wire
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
SystemCType     sc_logic
StateEquation   Hex(Inc(0,2,5))
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
HighVoltageThreshold    5
StateEquation   Hex(Inc(0,2,5))
LowVoltageThreshold     0
HighVoltageThreshold    5
SignalActionType        0
LowVoltageThreshold     0
MSB     0
SignalActionType        0
LSB     0
MSB     0
isFallingEdgeSensitive  False
LSB     0
isRisingEdgeSensitive   False
isFallingEdgeSensitive  False
DrawAnalog      0
isRisingEdgeSensitive   False
BooleanEquation
DrawAnalog      0
NegTolerance    0
BooleanEquation
PosTolerance    0
NegTolerance    0
UserSpecifiedSizeRatio  1
PosTolerance    0
VerilogCode
UserSpecifiedSizeRatio  1
VHDLCode
VerilogCode
PROPS!
VHDLCode
E0      0        2750    2750            1       0        DR      0
PROPS!
E1      1       4750    4750    If Enabled      1       0        DR      0
E0      X       3126    3126            1       0        DR      0
!
E1      0        13125   13125           1       0        DR      0
E2      X       13625   13625           1       0        DR      0
SIGNAL  dbg_ewt_i
E3      0        23125   23125           1       0        DR      0
DIRECTION       input
E4      X       23625   23625           1       0        DR      0
RADIX   hex
E5      0        33125   33125           1       0        DR      0
GRID    0        1       0        1       0        16711680        0        0
E6      X       33750   33750           1       0        DR      0
ENDGRID -1
E7      0        43125   43125           1       0        DR      0
Clock   Unclocked
E8      1       53125   53125           1       0        DR      0
EdgeLevel       neg
E9      0        53750   53750           1       0        DR      0
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
SIGNAL  dwb_SEL_O
ActiveLowSetClear       True
DIRECTION       output
AsyncSetClear   True
RADIX   hex
ActiveLowClockEnable    True
GRID    0        1       0        1       0        16711680        0        0
VhdlType        std_logic
ENDGRID -1
VerilogType     wire
Clock   Unclocked
SystemCType     sc_logic
EdgeLevel       neg
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Set     Not Used
StateEquation   Hex(Inc(0,2,5))
Clear   Not Used
HighVoltageThreshold    5
ClockEnable     Not Used
LowVoltageThreshold     0
ActiveLowSetClear       True
SignalActionType        0
AsyncSetClear   True
MSB     0
ActiveLowClockEnable    True
LSB     0
VhdlType        std_logic
isFallingEdgeSensitive  False
VerilogType     wire
isRisingEdgeSensitive   False
SystemCType     sc_logic
DrawAnalog      0
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
BooleanEquation
StateEquation   Hex(Inc(0,2,5))
NegTolerance    0
HighVoltageThreshold    5
PosTolerance    0
LowVoltageThreshold     0
UserSpecifiedSizeRatio  1
LSB     0
VerilogCode
MSB     3
VHDLCode
SignalActionType        0
PROPS!
isFallingEdgeSensitive  False
E0      0        1250    1250            1       0        DR      0
isRisingEdgeSensitive   False
E1      1       3750    3750            1       0        DR      0
DrawAnalog      0
E2      0        4750    4750            1       0        DR      0
BooleanEquation
!
NegTolerance    0
PosTolerance    0
MARKER  MARK10
UserSpecifiedSizeRatio  1
ATTACH  dbg_wp_o[11]    NULL    S1
VerilogCode
TIME    1610.903040
VHDLCode
RELATIVETIME    0.000000
PROPS!
DISPLAYAS       5
E0      X       3123    3123            1       0        DR      0
MARKERTYPE      Timebreak(Curved)
E1      V       13125   13125       Valid       1       0        DR      0
WHILERETURN
E2      X       13625   13625           1       0        DR      0
REPEATNUMBER
E3      V       23125   23125     Valid 1       0        DR      0
SNAPTO  0
E4      X       23625   23625           1       0        DR      0
COMPRESSTIME    0.000000
E5      V       33125   33125     Valid 1       0        DR      0
COMMENT aaa
E6      X       33625   33625           1       0        DR      0
!
E7      V       43125   43125     Valid 1       0        DR      0
E8      X       43750   43750           1       0        DR      0
MARKER  MARK20
E9      V       53124   53124      Valid        1       0        DR      0
ATTACH  dbg_bp_o        NULL    S2
E10     X       53750   53750           1       0        DR      0
TIME    2644.928640
!
RELATIVETIME    0.000000
DISPLAYAS       5
SIGNAL  dwb_STB_O
MARKERTYPE      Timebreak(Curved)
DIRECTION       output
WHILERETURN
RADIX   hex
REPEATNUMBER
GRID    0        1       0        1       0        16711680        0        0
SNAPTO  0
ENDGRID -1
COMPRESSTIME    0.000000
Clock   Unclocked
COMMENT
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
Timing Diagram Editor v7.1g - Output File
ClockEnable     Not Used
ActiveLowSetClear       True
PROJECT
AsyncSetClear   True
BaseTimeUnit    1
ActiveLowClockEnable    True
DisplayTimeUnit 2
VhdlType        std_logic
TextGridX       250.000000
VerilogType     wire
TextGridY       6
SystemCType     sc_logic
EdgeGridX       250.000000
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
ImportStartTime 0.000000
StateEquation   Hex(Inc(0,2,5))
ImportEndTime   281474976710656.000000
HighVoltageThreshold    5
TimePerPixel    6.571429
LowVoltageThreshold     0
Visible DELAYS  SETUPS  HOLDS   SAMPLES TEXT    HIDDENATTACHMENTS       CRITICALPATHS   GRIDLINES       UNCERTAINTY
SignalActionType        0
ColWidths       144,216,288,423,488
MSB     0
ScrollPos       0.000000,0.000000,0.000000
LSB     0
DefDelayRule    1
isFallingEdgeSensitive  False
NoEventOverlap  NO
isRisingEdgeSensitive   False
SigLabelFontHeight      10
DrawAnalog      0
LabelHeight     12
BooleanEquation
LoadLibsToMem   1
NegTolerance    0
UseFullPathNames        1
PosTolerance    0
LibPath
UserSpecifiedSizeRatio  1
EntireTime      YES
VerilogCode
PrintTimeSpecified      NO
VHDLCode
FromTime        0
PROPS!
ToTime  5.75
E0      0        3750    3750            1       0        DR      0
AllSignals      YES
E1      1       13125   13125           1       0        DR      0
CurrSelSigs     NO
E2      0        13625   13625           1       0        DR      0
PrintTo 2
E3      1       23125   23125           1       0        DR      0
PrintFileName   C:\DOCS\dbg_readwritespr.wmf
E4      0        23625   23625           1       0        DR      0
PreviewInterchange      YES
E5      1       33125   33125           1       0        DR      0
PreviewTIFF5    NO
E6      0        33625   33625           1       0        DR      0
UseMargins      NO
E7      1       43124   43124           1       0        DR      0
PrintTimeLine   NO
E8      0        44466   44466           1       0        DR      0
PrintBorderBox  YES
E9      1       53124   53124           1       0        DR      0
PrintSigNames   YES
E10     X       53750   53750           1       0        DR      0
PrintSigNamesOnEachPage YES
!
AddPreviewToEPS NO
PreviewRes      150
SIGNAL  dwb_ACK_I
MarginLR        1.25
DIRECTION       input
MifImageWidth   6.00
RADIX   hex
MarginTB        Auto
GRID    0        1       0        1       0        16711680        0        0
Header  %d %t;%f;%p
ENDGRID -1
Footer
Clock   Unclocked
ScaleHorz       100
EdgeLevel       neg
ScaleVert       100
Set     Not Used
ScaleHPage      1
Clear   Not Used
PrintImage      DIAGRAM
ClockEnable     Not Used
DefaultTimingModel      minmax
ActiveLowSetClear       True
DefaultClock    Unclocked
AsyncSetClear   True
DefaultEdgeLevel        neg
ActiveLowClockEnable    True
DefaultSet      Not Used
VhdlType        std_logic
DefaultClear    Not Used
VerilogType     wire
DefaultClockEnable      Not Used
SystemCType     sc_logic
DefaultClockToOutLH     0
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
DefaultClockToOutHL     0
StateEquation   Hex(Inc(0,2,5))
DefaultSetup    0
HighVoltageThreshold    5
DefaultHold     0
LowVoltageThreshold     0
DefaultRegStartupState  unknown
SignalActionType        0
DefaultPodSize  8
MSB     0
DefaultActiveLowSetClear        True
LSB     0
DefaultAsyncSetClear    True
isFallingEdgeSensitive  False
DefaultActiveLowClockEnable     True
isRisingEdgeSensitive   False
SigLabelFontHeight      10
DrawAnalog      0
PROPS!
BooleanEquation
!
NegTolerance    0
PosTolerance    0
STYLE
UserSpecifiedSizeRatio  1
DefaultFont     USER    {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
VerilogCode
DrawWndFont     DEFAULT
VHDLCode
DrawWndColor    DEFAULT
PROPS!
GridWndFont     DEFAULT
E0      0        11250   11250           1       0        DR      0
GridWndColor    DEFAULT
E1      1       13125   13125           1       0        DR      0
LabelWndFont    USER    {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
E2      0        21250   21250           1       0        DR      0
LabelWndColor   DEFAULT
E3      1       23125   23125           1       0        DR      0
ParamDispPref   0
E4      0        31250   31250           1       0        DR      0
ParamWndCellDisplay     0
E5      1       33125   33125           1       0        DR      0
CustDispString  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
E6      0        41250   41250           1       0        DR      0
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
E7      1       43124   43124           1       0        DR      0
MarkerDispPref  4
E8      0        51875   51875           1       0        DR      0
MarkerCustDispString    %n v=%mv,%Mv d=%md %t
E9      1       53124   53124           1       0        DR      0
MarkerCustomDisplayStringRTF    {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
E10     X       53750   53750           1       0        DR      0
SignalColor     2
!
LabelOffset     4
BusDisplay      0
SIGNAL  dwb_CYC_O
WaveFormWidth   0.500000
DIRECTION       output
WaveFormColor   0
RADIX   hex
InputWaveFormColor      16711680
GRID    0        1       0        1       0        16711680        0        0
SlantedEdges    1
ENDGRID -1
SlantAngle      75
Clock   Unclocked
RightJustifySigNames    1
EdgeLevel       neg
AutosplitEnabled        1
Set     Not Used
AutosplitChar   _
Clear   Not Used
DynamSizedSignals       1
ClockEnable     Not Used
!
ActiveLowSetClear       True
AsyncSetClear   True
DIAGRAMTESTBENCHSETTINGS
ActiveLowClockEnable    True
FilesBeforeDiagramModel
VhdlType        std_logic
FilesInsideDiagramModelDeclarationSection
VerilogType     wire
AbortHdlCodeEnabled     1
SystemCType     sc_logic
DelayHdlCodeEnabled     1
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
SampleHdlCodeEnabled    1
StateEquation   Hex(Inc(0,2,5))
MarkerHdlCodeEnabled    1
HighVoltageThreshold    5
VerboseSamples  0
LowVoltageThreshold     0
VerboseDelays   0
SignalActionType        0
VerboseFileInput        0
MSB     0
VerboseSequenceVerification     0
LSB     0
IncludeDelayTime        1
isFallingEdgeSensitive  False
ExecuteFromTopLevel     1
isRisingEdgeSensitive   False
TimeOutInDiagramLengths 0
DrawAnalog      0
DefaultCycleClock       Unclocked
BooleanEquation
DefaultCycleEdge        neg
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
MACROS
VerilogCode
!
VHDLCode
PROPS!
CORGROUP        $$CLK_I_BufferRising
E0      0        3125    3125            1       0        DR      0
Percent 100
E1      1       43125   43125           1       0        DR      0
!
E2      0        44375   44375           1       0        DR      0
E3      1       53125   53125           1       0        DR      0
CORGROUP        $$CLK_I_BufferFalling
E4      0        53750   53750           1       0        DR      0
Percent 100
!
!
SIGNAL  dwb_ERR_I
CORGROUP        $$CLK_I_BufferRisingFalling
DIRECTION       input
Percent 100
RADIX   hex
!
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
CORGROUP        $$CLK_I_BufferRising
Clock   Unclocked
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$CLK_I_BufferFalling
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$CLK_I_BufferRisingFalling
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$CLK_I_BufferRising
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
SignalActionType        0
CORGROUP        $$CLK_I_BufferFalling
MSB     0
Percent 100
LSB     0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
CORGROUP        $$CLK_I_BufferRisingFalling
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$CLK_I_BufferRising
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
PROPS!
CORGROUP        $$CLK_I_BufferFalling
E0      0        53125   53125           1       0        DR      0
Percent 100
E1      X       53750   53750           1       0        DR      0
!
!
CORGROUP        $$CLK_I_BufferRisingFalling
SIGNAL  dwb_RTY_I
Percent 100
DIRECTION       input
!
RADIX   hex
GRID    0        1       0        1       0        16711680        0        0
CORGROUP        $$CLK_I_BufferRising
ENDGRID -1
Percent 100
Clock   Unclocked
!
EdgeLevel       neg
Set     Not Used
CORGROUP        $$CLK_I_BufferFalling
Clear   Not Used
Percent 100
ClockEnable     Not Used
!
ActiveLowSetClear       True
AsyncSetClear   True
CORGROUP        $$CLK_I_BufferRisingFalling
ActiveLowClockEnable    True
Percent 100
VhdlType        std_logic
!
VerilogType     wire
SystemCType     sc_logic
CORGROUP        $$CLK_I_BufferRising
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Percent 100
StateEquation   Hex(Inc(0,2,5))
!
HighVoltageThreshold    5
LowVoltageThreshold     0
CORGROUP        $$CLK_I_BufferFalling
SignalActionType        0
Percent 100
MSB     0
!
LSB     0
isFallingEdgeSensitive  False
CORGROUP        $$CLK_I_BufferRisingFalling
isRisingEdgeSensitive   False
Percent 100
DrawAnalog      0
!
BooleanEquation
NegTolerance    0
CORGROUP        $$CLK_RISC_BufferRising
PosTolerance    0
Percent 100
UserSpecifiedSizeRatio  1
!
VerilogCode
VHDLCode
CORGROUP        $$CLK_RISC_BufferFalling
PROPS!
Percent 100
E0      0        53125   53125           1       0        DR      0
!
E1      X       53750   53750           1       0        DR      0
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
MARKER  MARK1
!
ATTACH  dwb_SEL_O       NULL    S6
TIME    17500.000000
CORGROUP        $$CLK_RISC_BufferRising
RELATIVETIME    0.000000
Percent 100
DISPLAYAS       5
!
MARKERTYPE      Timebreak(Curved)
WHILERETURN
CORGROUP        $$CLK_RISC_BufferFalling
REPEATNUMBER
Percent 100
SNAPTO  0
!
COMPRESSTIME    0.000000
COMMENT
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
MARKER  MARK2
ATTACH  dwb_STB_O       NULL    S7
CORGROUP        $$CLK_I_BufferRising
TIME    27500.000000
Percent 100
RELATIVETIME    0.000000
!
DISPLAYAS       5
MARKERTYPE      Timebreak(Curved)
CORGROUP        $$CLK_I_BufferFalling
WHILERETURN
Percent 100
REPEATNUMBER
!
SNAPTO  0
COMPRESSTIME    0.000000
CORGROUP        $$CLK_I_BufferRisingFalling
COMMENT
Percent 100
!
!
MARKER  MARK3
CORGROUP        $$CLK_RISC_BufferRising
ATTACH  dwb_STB_O       NULL    S7
Percent 100
TIME    37500.000000
!
RELATIVETIME    0.000000
DISPLAYAS       5
CORGROUP        $$CLK_RISC_BufferFalling
MARKERTYPE      Timebreak(Curved)
Percent 100
WHILERETURN
!
REPEATNUMBER
SNAPTO  0
CORGROUP        $$CLK_RISC_BufferRisingFalling
COMPRESSTIME    0.000000
Percent 100
COMMENT
!
!
CORGROUP        $$CLK_I_BufferRising
MARKER  MARK0
Percent 100
ATTACH  dwb_CLK_I       NULL    S1
!
TIME    7500.000000
RELATIVETIME    0.000000
CORGROUP        $$CLK_I_BufferFalling
DISPLAYAS       5
Percent 100
MARKERTYPE      Timebreak(Curved)
!
WHILERETURN
REPEATNUMBER
CORGROUP        $$CLK_I_BufferRisingFalling
SNAPTO  0
Percent 100
COMPRESSTIME    0.000000
!
COMMENT
!
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
MARKER  MARK4
!
ATTACH  dwb_ADR_O       NULL    S2
TIME    47500.000000
CORGROUP        $$CLK_RISC_BufferFalling
RELATIVETIME    0.000000
Percent 100
DISPLAYAS       5
!
MARKERTYPE      Timebreak(Curved)
WHILERETURN
CORGROUP        $$CLK_RISC_BufferRisingFalling
REPEATNUMBER
Percent 100
SNAPTO  0
!
COMPRESSTIME    0.000000
COMMENT
CORGROUP        $$CLK_I_BufferRising
!
Percent 100
!
Timing Diagram Editor v7.1g - Output File
CORGROUP        $$CLK_I_BufferFalling
PROJECT
Percent 100
BaseTimeUnit    1
!
DisplayTimeUnit 2
TextGridX       250.000000
CORGROUP        $$CLK_I_BufferRisingFalling
TextGridY       6
Percent 100
EdgeGridX       250.000000
!
ImportStartTime 0.000000
ImportEndTime   281474976710656.000000
CORGROUP        $$CLK_RISC_BufferRising
TimePerPixel    6.571429
Percent 100
Visible DELAYS  SETUPS  HOLDS   SAMPLES TEXT    HIDDENATTACHMENTS       CRITICALPATHS   GRIDLINES       UNCERTAINTY
!
ColWidths       144,216,288,423,488
ScrollPos       0.000000,0.000000,0.000000
CORGROUP        $$CLK_RISC_BufferFalling
DefDelayRule    1
Percent 100
NoEventOverlap  NO
!
SigLabelFontHeight      10
LabelHeight     12
CORGROUP        $$CLK_RISC_BufferRisingFalling
LoadLibsToMem   1
Percent 100
UseFullPathNames        1
!
LibPath
EntireTime      YES
CORGROUP        $$CLK_RISC_BufferRising
PrintTimeSpecified      NO
Percent 100
FromTime        0
!
ToTime  5.75
AllSignals      YES
CORGROUP        $$CLK_RISC_BufferFalling
CurrSelSigs     NO
Percent 100
PrintTo 2
!
PrintFileName   C:\DOCS\dbg_readwritespr.wmf
PreviewInterchange      YES
CORGROUP        $$CLK_RISC_BufferRisingFalling
PreviewTIFF5    NO
Percent 100
UseMargins      NO
!
PrintTimeLine   NO
PrintBorderBox  YES
CORGROUP        $$CLK_RISC_BufferRising
PrintSigNames   YES
Percent 100
PrintSigNamesOnEachPage YES
!
AddPreviewToEPS NO
PreviewRes      150
CORGROUP        $$CLK_RISC_BufferFalling
MarginLR        1.25
Percent 100
MifImageWidth   6.00
!
MarginTB        Auto
Header  %d %t;%f;%p
CORGROUP        $$CLK_RISC_BufferRisingFalling
Footer
Percent 100
ScaleHorz       100
!
ScaleVert       100
ScaleHPage      1
CORGROUP        $$CLK_RISC_BufferRising
PrintImage      DIAGRAM
Percent 100
DefaultTimingModel      minmax
!
DefaultClock    Unclocked
DefaultEdgeLevel        neg
CORGROUP        $$CLK_RISC_BufferFalling
DefaultSet      Not Used
Percent 100
DefaultClear    Not Used
!
DefaultClockEnable      Not Used
DefaultClockToOutLH     0
CORGROUP        $$CLK_RISC_BufferRisingFalling
DefaultClockToOutHL     0
Percent 100
DefaultSetup    0
!
DefaultHold     0
DefaultRegStartupState  unknown
CORGROUP        $$CLK_RISC_BufferRising
DefaultPodSize  8
Percent 100
DefaultActiveLowSetClear        True
!
DefaultAsyncSetClear    True
DefaultActiveLowClockEnable     True
CORGROUP        $$CLK_RISC_BufferFalling
SigLabelFontHeight      10
Percent 100
PROPS!
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
STYLE
Percent 100
DefaultFont     USER    {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
!
DrawWndFont     DEFAULT
DrawWndColor    DEFAULT
CORGROUP        $$CLK_RISC_BufferRising
GridWndFont     DEFAULT
Percent 100
GridWndColor    DEFAULT
!
LabelWndFont    USER    {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
LabelWndColor   DEFAULT
CORGROUP        $$CLK_RISC_BufferFalling
ParamDispPref   0
Percent 100
ParamWndCellDisplay     0
!
CustDispString  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
CORGROUP        $$CLK_RISC_BufferRisingFalling
MarkerDispPref  4
Percent 100
MarkerCustDispString    %n v=%mv,%Mv d=%md %t
!
MarkerCustomDisplayStringRTF    {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
SignalColor     2
CORGROUP        $$CLK_RISC_BufferRising
LabelOffset     4
Percent 100
BusDisplay      0
!
WaveFormWidth   0.500000
WaveFormColor   0
CORGROUP        $$CLK_RISC_BufferFalling
InputWaveFormColor      16711680
Percent 100
SlantedEdges    1
!
SlantAngle      75
RightJustifySigNames    1
CORGROUP        $$CLK_RISC_BufferRisingFalling
AutosplitEnabled        1
Percent 100
AutosplitChar   _
!
DynamSizedSignals       1
!
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
DIAGRAMTESTBENCHSETTINGS
!
FilesBeforeDiagramModel
FilesInsideDiagramModelDeclarationSection
CORGROUP        $$CLK_RISC_BufferFalling
AbortHdlCodeEnabled     1
Percent 100
DelayHdlCodeEnabled     1
!
SampleHdlCodeEnabled    1
MarkerHdlCodeEnabled    1
CORGROUP        $$CLK_RISC_BufferRisingFalling
VerboseSamples  0
Percent 100
VerboseDelays   0
!
VerboseFileInput        0
VerboseSequenceVerification     0
CORGROUP        $$CLK_RISC_BufferRising
IncludeDelayTime        1
Percent 100
ExecuteFromTopLevel     1
!
TimeOutInDiagramLengths 0
DefaultCycleClock       Unclocked
CORGROUP        $$CLK_RISC_BufferFalling
DefaultCycleEdge        neg
Percent 100
!
!
MACROS
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
CORGROUP        $$CLK_RISC_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_I_BufferFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
CORGROUP        $$CLK_RISC_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_I_BufferFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
CORGROUP        $$clk_risc_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_I_BufferFalling
Percent 100
CORGROUP        $$clk_risc_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$clk_risc_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
CORGROUP        $$clk_risc_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_I_BufferFalling
Percent 100
CORGROUP        $$clk_risc_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$clk_risc_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
CLOCK   clk_risc
!
PERIODE 1
DUTY    50
CORGROUP        $$CLK_I_BufferFalling
OFFSETE 0
Percent 100
INITIAL LOW
!
MAXUNCERTRISE   0
MAXUNCERTFALL   0
CORGROUP        $$CLK_I_BufferRisingFalling
MINUNCERTRISE   0
Percent 100
MINUNCERTFALL   0
!
JRISEE  0
JFALLE  0
CORGROUP        $$CLK_I_BufferRising
GRID    1       1       1       2       2       16711680        0        0
Percent 100
ENDGRID -1
!
DIRECTION       input
MASTERCLOCK     None
CORGROUP        $$CLK_I_BufferFalling
Clock   Unclocked
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$CLK_I_BufferRisingFalling
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$CLK_RISC_BufferRising
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$CLK_RISC_BufferFalling
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
MSB     0
CORGROUP        $$CLK_RISC_BufferRisingFalling
LSB     0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   True
DrawAnalog      0
CORGROUP        $$CLK_RISC_BufferRising
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$CLK_RISC_BufferFalling
VerilogCode
Percent 100
VHDLCode
!
PROPS!
E5      1       2500    2500            1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRisingFalling
E6      0        3000    3000            1       0        DR      0
Percent 100
!
!
SIGNAL  dbg_adr_i
CORGROUP        $$CLK_I_BufferRising
DIRECTION       input
Percent 100
RADIX   hex
!
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
CORGROUP        $$CLK_I_BufferFalling
Clock   Unclocked
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$CLK_I_BufferRisingFalling
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$CLK_RISC_BufferRising
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$CLK_RISC_BufferFalling
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
LSB     0
CORGROUP        $$CLK_RISC_BufferRisingFalling
MSB     31
Percent 100
SignalActionType        0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
CORGROUP        $$CLK_I_BufferRising
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$CLK_I_BufferFalling
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
PROPS!
CORGROUP        $$CLK_I_BufferRisingFalling
E0      X       750     750             1       0        DR      0
Percent 100
E1      V       1750    1750    A20     1       0        DR      0
!
E2      V       3750    3750    A100    1       0        DR      0
E3      X       5750    5750            1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRising
!
Percent 100
!
SIGNAL  dbg_dat_i
DIRECTION       input
CORGROUP        $$CLK_RISC_BufferFalling
RADIX   hex
Percent 100
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock
CORGROUP        $$CLK_RISC_BufferRisingFalling
EdgeLevel       neg
Percent 100
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
CORGROUP        $$CLK_I_BufferRising
ActiveLowSetClear       True
Percent 100
AsyncSetClear   True
!
ActiveLowClockEnable    True
VhdlType        std_logic
CORGROUP        $$CLK_I_BufferFalling
VerilogType     wire
Percent 100
SystemCType     sc_logic
!
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
CORGROUP        $$CLK_I_BufferRisingFalling
HighVoltageThreshold    5
Percent 100
LowVoltageThreshold     0
!
LSB     0
MSB     31
CORGROUP        $$CLK_RISC_BufferRising
SignalActionType        0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   False
DrawAnalog      0
CORGROUP        $$CLK_RISC_BufferFalling
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$CLK_RISC_BufferRisingFalling
VerilogCode
Percent 100
VHDLCode
!
VhdlMapping     DefaultVhdlMapping
PROPS!
CORGROUP        $$CLK_RISC_BufferRising
E0      X       750     750             1       0        DR      0
Percent 100
E1      V       1750    1750    D20     1       0        DR      0
!
E2      X       5750    5750            1       0        DR      0
!
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
SIGNAL  dbg_dat_o
!
DIRECTION       output
RADIX   hex
CORGROUP        $$CLK_RISC_BufferRisingFalling
GRID    0        1       0        1       0        16711680        0        0
Percent 100
ENDGRID -1
!
Clock
EdgeLevel       neg
CORGROUP        $$CLK_RISC_BufferRising
Set     Not Used
Percent 100
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CORGROUP        $$CLK_RISC_BufferFalling
AsyncSetClear   True
Percent 100
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
CORGROUP        $$CLK_RISC_BufferRisingFalling
SystemCType     sc_logic
Percent 100
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
CORGROUP        $$CLK_RISC_BufferRising
LowVoltageThreshold     0
Percent 100
LSB     0
!
MSB     31
SignalActionType        0
CORGROUP        $$CLK_RISC_BufferFalling
isFallingEdgeSensitive  False
Percent 100
isRisingEdgeSensitive   True
!
DrawAnalog      0
BooleanEquation
CORGROUP        $$CLK_RISC_BufferRisingFalling
NegTolerance    0
Percent 100
PosTolerance    0
!
UserSpecifiedSizeRatio  1
VerilogCode
CORGROUP        $$CLK_RISC_BufferRising
VHDLCode
Percent 100
VhdlMapping     DefaultVhdlMapping
!
PROPS!
E0      V       -1      -1              1       0        DR      0
CORGROUP        $$CLK_RISC_BufferFalling
E1      V       750     750     PC      1       0        DR      0
Percent 100
E2      X       2750    2750            1       0        DR      0
!
E3      V       3750    3750    D100    1       0        DR      0
E4      V       4750    4750    L/S EA  1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRisingFalling
E5      V       5750    5750    LOAD DATA       1       0        DR      0
Percent 100
!
!
SIGNAL  dbg_op_i
CORGROUP        $$CLK_RISC_BufferRising
DIRECTION       input
Percent 100
RADIX   hex
!
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
CORGROUP        $$CLK_RISC_BufferFalling
Clock   Unclocked
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$CLK_RISC_BufferRisingFalling
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$CLK_RISC_BufferRising
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$CLK_RISC_BufferFalling
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
SignalActionType        0
CORGROUP        $$CLK_RISC_BufferRisingFalling
MSB     3
Percent 100
LSB     0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
CORGROUP        $$CLK_RISC_BufferRising
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$CLK_RISC_BufferFalling
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
PROPS!
CORGROUP        $$CLK_RISC_BufferRisingFalling
E0      V       750     750     READ PC 0x0     1       0        DR      0
Percent 100
E1      V       1750    1750    WRITE SPR 0x5   1       0        DR      0
!
E2      V       3750    3750    READ SPR == 0x4 1       0        DR      0
E3      V       4750    4750    READ LSEA 0x1   1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRising
E4      V       5750    5750    READ LDAT 0x2   1       0        DR      0
Percent 100
!
!
SIGNAL  dbg_stall_i
CORGROUP        $$CLK_RISC_BufferFalling
DIRECTION       input
Percent 100
RADIX   hex
!
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
CORGROUP        $$CLK_RISC_BufferRisingFalling
Clock   Unclocked
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$CLK_RISC_BufferRising
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$CLK_RISC_BufferFalling
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$CLK_RISC_BufferRisingFalling
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
SignalActionType        0
CORGROUP        $$CLK_RISC_BufferRising
MSB     0
Percent 100
LSB     0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
CORGROUP        $$CLK_RISC_BufferFalling
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$CLK_RISC_BufferRisingFalling
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
PROPS!
CORGROUP        $$clk_risc_BufferRising
E0      0        5750    5750            1       0        DR      0
Percent 100
!
!
вFQ/  %8&" WMFCcR P3PSxU>вFQ/ EMFPSЦXРьЫVISIODrawing
CORGROUP        $$clk_risc_BufferFalling
 Y=&%%€V0JJJJ%€(%€RLѓџџџ Arialdxі	фі	ф№П№П№П_VarMemberFlagsџџџџоОџVB_Var@?>=<;:98%Tˆ+.g=Ћ*ЉAЋ*ЉA+.
Percent 100
L`Context ID          T|5>\MЋ*ЉAЋ*ЉA5>L\(4 bits)&%%€V0}JJ}J}J%€(%€RLѓџџџ Arialџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџ%TИа.<=Ћ*ЉAЋ*ЉAа.LpPage Index Level 1	T|ђ>MЋ*ЉAЋ*ЉAђ>L\(8 bits)&%%€V0}iJ}JiJi}}J%€(%€RLѓџџџ Arialџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџ%TИМ.(=Ћ*ЉAЋ*ЉAМ.LpPage Index Level 2  T„л> MЋ*ЉAЋ*ЉAл>     L`(11 bits)џџ&%%€V0iUJiJUJUiiJ%€(%€RLѓџџџ Arialџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџ%TО.=Ћ*ЉAЋ*ЉAО.LdPage Offsetџџ     
!
T„Ч>ѕMЋ*ЉAЋ*ЉAЧ>     L`(13 bits)џџRLѓџџџ Arialџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџ%TX"Ћ*ЉAЋ*ЉALP35RLѓџџџ Arialџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџ%(%TX™І"Ћ*ЉAЋ*ЉA™LP31%
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CORGROUP        $$clk_risc_BufferRisingFalling

Percent 100

!


CORGROUP        $$clk_risc_BufferRising
H
Percent 100
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€(RLѓџџџ ArialrialArialЏG@ЏGџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџ%TXЋ*ЉAЋ*ЉALP34RLѓџџџ Arialџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџ%(%TXO\Ћ*ЉAЋ*ЉAOLP13%
€(RLѓџџџ Arialџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџ%TXu‚Ћ*ЉAЋ*ЉAuLP12%
€(RLѓџџџ Arialџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџ%TTFLЋ*ЉAЋ*ЉAFLP0џџ&%W$пJпўпJпў%€(%€%€V,л§фф§пл§ф§&%%€Vˆ&иœM&(-ї5ы@тLлZиhиvлƒты•їšœš!•.:ƒCvJhMZMLJ@C5:-.(!&%€(RLѓџџџ Arialџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџ%(%€RLѓџџџ Arialџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџ%TˆAџЋ*ЉAЋ*ЉAAџ
CORGROUP        $$clk_risc_BufferFalling
L`Page Table     T”8‰Ћ*ЉAЋ*ЉA8LdBase Address          T”;‡.Ћ*ЉAЋ*ЉA;Lddepending onTA/>Ћ*ЉAЋ*ЉAA/Ldcurrent CIDџџ      &%%€VXіŸПіЏјЈќЂŸ
Percent 100
ŸЂЈЏЖМ
!
ППќМјЖіЏ%€(%
€(%€RLьџџџМ Arialџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџ%TTЕЬЋ*ЉAЋ*ЉAЕLP+&%W(aЏщзaзaЏщЏ%€(%€%€V,шЋіДшЋіЏшДшЋ&%%€V0MРЌяMяЌяЌРMРMя%€(&%%€V0MяЌMЌЌяMяM%€(%
€(%€RLѓџџџ Arial&џByValџџџџKt(џCallџџџџGu*џCaseџџџџtL,џCBoolџџџџ~џDirџџџџge?€џDir$џџџџј\@‚џDoџџџџ4–A„џDoEventsDoџџџџ™
B†џDoubleџџџџuўˆџEachџџџџV;DŠџElseџџџџ%TTэнјєЋ*ЉAЋ*ЉAэнLP+f&%W,ЌзжћЌћбћбзжз%€(%€%€V,егтмегтземег&%%€W$J’J’%€(%€%€V,‘Ÿ‘Ÿ‘‘&%%€W$ѓJѓКѓJѓК%€(%€%€V,юЙјЧјЙѓЧюЙјЙ&%%€V0:я˜:˜˜я:я:%€(О     &rWMFCPPS&%%€V0:˜6:6˜6˜::6%€(RLѓџџџ Arial !"#$%&'()*+,./01234%(%€RLѓџџџ ArialFGHIJKLMNOPQRSTUVWXial,%TdY.x=Ћ*ЉAЋ*ЉAY.LTPTE2   &     %     %€V0:6˜Ф:Ф˜Ф˜6:6:Ф%€(     %
€(%€RLѓџџџ Arial,,,,,,,,%c,,,,є,є
     
                         
CORGROUP        $$clk_risc_BufferRisingFalling
      %Tœ@ч’іЋ*ЉAЋ*ЉA@ч
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Percent 100
%
!
W,IJIаIJI[I[Iа%€(
%€%€V,EЯNнNЯIнEЯNЯ&
CLOCK   clk_risc
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€(RLѓџџџ Arialџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџ%(%
€(%€%T`ДШœЋ*ЉAЋ*ЉAДLT255џџRLѓџџџ Arialџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџ%TTИаОпЋ*ЉAЋ*ЉAИаLP0џџ%
€(RLѓџџџ Arialџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџ%TT џІЋ*ЉAЋ*ЉA џLP0џџ%
€(%
€(RLѓџџџ Arialџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџ@?>=<:987543210/.-,+ri%TdЁММЫЋ*ЉAЋ*ЉAЁМLT2047<Yњ-ќџџџ-$JJJњџџџ-№.ќ-ћ
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--$,&:*,/,&њ-
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--$:§61§:§-ћ
 Arial   -
.2
VhdlType        std_logic
q+Virtual Page Number  (VPN)                                   њ-%IJI[I[Iа-№--$NЯIнEЯNЯњ--%ayiyia-№-№ћ
 Arial?????????????????????????-№-№       --2
VerilogType     wire
Д255ћ
 Arial?????????????????????????-      2
SystemCType     sc_logic
аИ0-№ћ
 Arial?????????????????????????-             2
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
џ 0-№-№ћ
 Arial?????????????????????????-
2
StateEquation   Hex(Inc(0,2,5))
МЁ2047ўџ
HighVoltageThreshold    5
џџџџРFMicrosoft Visio DrawingVISIO 6.0 ShapesVisio.Drawing.6є9ВqўџўџеЭеœ.“—+,љЎDеЭеœ.“—+,љЎN
LowVoltageThreshold     0
@€HP\ht
Ќф     PagesMastersPageVisio (TM) Drawing
LSB     0
цg„THїjf|Rэdъёщђџџџƒџіђџѓћ№јё‰€ъё€ €џРРРцццџЭЭЭГГГяššš!€fџffMMM333$ы№мџ
MSB     31
$ы№мџ
SignalActionType        0
Uы№џђ№Sы№8шѓ@њєсњіёъёуј§ы№Tdџ Arialъ@$чєN@џMonotџype Sort•s@>чєNuWOingdЂ†Rчєѕ
NtSymbol5Tы№?шѓа?ђџкъё шѓY@-1Uы№џђ№
isFallingEdgeSensitive  False
ы№шѓ њєы№іёъёJчє:ы№Dы№T1шѓ€ђёEWђёрћ-ъёhъчєы№Pы№T…ы№8пќŒŒцѕЎ‘*ы№Њы№ы№ы№        Њы№ы№
ы№“уј.žРUКіё_bў      љлaўщ…Иъё‰ќ0zПЎGсz„?Ж@цѕП3‘CЩfRbU|||% †МъёUќВ
isRisingEdgeSensitive   False
Pч     }     |Љ‡РъёйќKы№јG/Y&4?Й\.—џЫхт? р†ђ№яAуfY&‰Š”,”,”' /ˆDq&‰z&С}     |
DrawAnalog      0
| yрќЙ   }{})}ЉЛЈ        ?2     ||
Њ||||*|||ЄШъёEэ-?§k4'-Š'CECE,'*CECECE-›?H­>в?ф:`}'CEUCECECECEUCECE-„Ь’ъё O4ЃаъёFќ2AJY;;   ЧAnVnVЧAЇдbGTвfYЗиъёїќ  RШ_Rк_ї_ѕ `Ў#Šf:/lb6p`ЈfэW‰    /l
BooleanEquation
/lъНБ Y№?ˆ‡ˆ5?(\ ž#!&4№$
|
tFf-|•-|-|-w…GОръёQќUюoDЁOM`EбtoAПфъёв _3=OOOaO€sO…O­?П?ЇOу?ѕ7РФшъёмЛѕuЛ@L&“Щd2Й?цЩЩїˆr#в   ˜чŽsU/‘х-–OŸ%7I[m‘Џ„Rf–‰Ќј†J‰+Ќ
NegTolerance    0
–‰KЌ5ЌЌ .•‰Љ‹Ї ||i€ИЛњё”|Г    пЫ”ујМђd'
0/’UХKјiR?d?v4Gz№tŒ2ђ#Ж&Us•       s•
PosTolerance    0
s•s•)-Ѓ0‘jМСЏгЏуј•ујШ§ЇY/Ц›!3)ТѓПЕЖЕЖ1D‡/™/Ћ/ўQ+p)Ф?HdЕЗYcЕЗ‡4„НЧAkРЧПйПујˆујYfU|%Л1Iп€OвУ]нрћа„-(‘fp
шЩЛ я%щђ-=§Y[:ЗЬ!#йу:З4)›A/›ятљq/ƒ/YЯkЯЙ/p?‚2 ПБНЏчЯчПхіSЯ€џ'Я9Ч}FЩ‡7%УЕ8п@эџ\пnп1„У$‘щuеУ ЛЮпрпђпяя(я:яLя^яpя)деХмџBH>Z‡йкЫрšе”Uв\n€р’Є4!'4#U2Чq Ќ?/%&k/ Юя˜в%&юф`,`,`',б“б4п?ќџ|пвQЕБ›дžбЙQ–yТй“бAПбуЄвG
$ЊйбX&ћbp6эџƒыq
/#Šџу3=/дэU™ЬЉЬНqЄГи@T0ЏЙѓ'v”фr@1бN!T0;UцOaŸаu„ШA”ИЏDџVџюЋ=§ЉЖеБгРМа2rД|UўЩЭHEЇ#аE6Ве$2@1@1пB…q…q›       яTІБ,б$1“бІ,Ж/"dпA0mЄп+=Oa
д/Q?c?u4DЗњЏ        3МOшДNkЪЇ?нхђf„ту5/:0/WOT/f/x/Š- _2_D_яЊыdОJtМЗrГ†ОПатєЛIwџ‰0џ(7ЙѕвбЯN`кDa‡,бDaЂ/šа"oTfэ/do€voˆošoЌdБ`ЖoШo@о‘ЏСŠWь7ь=FHн™AКПсѓяЊЄПП1Ж,б›(ŸД/Ц/и/pŸ‚Ÿ”ŸІŸИŸP?0мŸt?ycT2Nєo ‚qєЕВХ‚фу5Q2FЯVtу2bјH)є–@ŠЏœЏЎЏѕвЏ0˜S3†,бS*ŸП/ПAПSПeПwП‰Л@…ОŸаŸУПє™п1'LЄљG]ЏЬбШ7вnу5ЏўП0­”ЯІЯИЯРЏмЯфЏ5Ј§”ы№Acrobaџt PDFWriwterо§юё$        щђ}dx)3EWi{§<ы№#џwinspoџolAcrobџat PDFWrџiterLPT1:мџUFы№џђ№ы№DшѓfњєёђџџъёP
рћіёъёhчєы№-RTы№пќUдUцѕ’ујUџUFпяїћ§~ћ@—Чуёxї<О?ЉПF
UserSpecifiedSizeRatio  1
…ПBЁP(Є?Л 3тєh
ы№Љ—ў ДЉ)Вў
VerilogCode
wbYbbїbb    b R)Л)ˆeqШYkчєƒујZUы№Hu§щђ ѓ№ящђџ˜џP№р№(:њџџŒˆџџ№{ŒW‹џ№_€qƒ•ЇЙЫеŒтџ§Qы№Rectanџgle. wiџth text џand connўѓ№ion poiџnts. Canџ be streџtched toўy dimenss.§bщђL&“Щd2џщПИ\.—ЫхЗт?Pѕѓ?К§ѓПџhHKГMщПџдDуу?эl?жП№їПћ§~ПР4р
я5їПD•Hы№џђ№ыєы№DBы№ы№іё№ѓ
яє$# фї?hчєіё-$>Tы№пќіёTE=ы№›ујcAџUFряїћя§~џ?ЃM&“џЩd2љ?FК\_.—ЫхђДщН—т?Q6‰ЃўJшюЕїОлў‰uŒ` nшѓр?'uі№Д2шйў
VHDLCode
‰Ubaj      jB›>ˆˆіёšŒšAšVъё‚ˆ’œнЊнДнОS„>ъё‰U5
ўg€L@SўЃ‰ъё{#§ђ№вI!ўN$5Aљ`7џCopyrighџt 1999 Vџisio Corџporation.  All s"џs reservПed.ў‰`§~ _Sba.cџhm!#2243O0ўl>#0>Uddтљ#3      ˆіёдˆ‰уј$]      ‰aў%2+5U+0Š(T#FцѕBS6ч.jRDRr6›ˆ
PROPS!
чн‘2‹7(4M4Ж]?
E0      X       750     750             1       0        DR      0
o1t?ўЇ1EГ>ПЬ?w9к1Ї1і9T6OHo?/GК2M?;‰НrA
E1      V       1750    1750    A20     1       0        DR      0
РўЃBžЉCРўq‰ˆ,B^пќ5ѓ/™ујбVД:Юцѕ@%^ќV"A(aCI|8Q
E2      V       3750    3750    A100    1       0        DR      0
%[Мт?-_?YM(|33Q:%^П–_?_Q_nKQEUIL”_ І_`IФ_жU9E\ч_botoo:›nеРы№Hы№lы№'ї-щђC{ѕы№џН!џРOyŽa§§єYEгЏйбqнтљчєFўы№„їлЛЪы№ж#ы№Tџ†їЅ       Jюы№B
E3      X       5750    5750            1       0        DR      0
ы№\‡їЋя][aДkJКfы№@+ы№МЪkKfMaђё$ˆзї˜fŸў№ж•8ы№ы№ѓєщђЌђё

ъёњђUlы№4ы№,чєчєџ(9
D,mџ@ЧаиrѓЅ@ујъёыё2љю
ы№•A-d3є7"AљіUlы№4ы№,чєћєџ(9
D,mџ@ЧаиrѓЅ@ујъёы№$џ3љ<*ы№A-43B7њѕ
Ulы№4ы№,чєчєџ(9
D,mџ@ЧаиrѓЅ@ујъёы№фџ3љ‹*ы№A-м3‘7"AљіUlы№4ы№,чєы№§ы№(9
D,џm@Чаиr‡ѓ@ујўёўёъёўы№œ4љкЋ
!
ы№A-Ќ3ф7;ъёUžы№ы№~пќчє§@ы№Ь1љі
Fы№Rмџ0Bў
|2љHѓCD3љU“_Gcєmъ_MHы№<мџ(
Hы№<мџ(
SIGNAL  dbg_dat_i
Hы№<мџ(
DIRECTION       input
Hы№<мџ(
RADIX   hex
Užы№ы№~пќчє§Eяё2љ
ы№Rмџ0B
хФŽŒ3љћ›_
GRID    0        1       0        1       0        16711680        0        0
<4љЈUFы№џђ№ы№Dшѓfњєёђџџъёа
рћіёъёh-Tы№пќUдUцѕ’уј”ы№џU@ряїћ§~ћ@—?Чуёяx<О?ЉПF
ENDGRID -1
…BЁP(Є?ЛАd
мюїb:‘ЉўoqYTkчєЈујQ‘§ђ№4u23uѕќі№‘`       Coџnnectorћў
Clock
‘`ў
EdgeLevel       neg
–
Set     Not Used
œe‘1Cw
Clear   Not Used
ЙƒујЉUы№HыЄъё ѓ№–ўяђџ^€џџџПџўџќњј№єџїєїїЕŸ  €-џ}|5pїџ`Iоџџ`V?џпџ}ƒџ`Сџџјƒx‹їџїaŠџџѓ833џŠџџƒџ‰џџѓџџџя‰џ‡Ž‡‡џƒџљо…џ Ÿ™џЊŸџ™љ]ЉџŽЗ№ўТџ№ƒ3Яƒƒ3‚Й†“Уu…Ыџ‚ŸЉОпџ3“3?,№     ї™?№џŸ№ўG‡xpџџ№хx“^мŠџ№ƒ‹џ&яŒџŒџ
ƒДџ§Cы№This cџonnectorџ automatџically rџoutes beџtween thПe shapi
tіѕs.•Hы№џђ№ыєы№DŠы№ы№щђђё
@яє#        фї      іё=hчєZ#8Tы№ пќH#3               Bы№Uы№ы№›ујF    џU@‹ХbяБXќ?ЗЙ\.Џ—ЫхђШПЩтnШтПP6
ClockEnable     Not Used
‰u
ActiveLowSetClear       True
`uџфb€Aя@ўќu*
  ‰E.#DB˜     ˜­‰uŒ`hрЋ?\hrІ|uі№†‰Дэ‰aкКчŽ‰UіЩ
@-ђ?b—l;'bE-$ho'—y(œ‰ъёљБм@rЧqџЧс?@ŸєIжЭ Я?У$бЫ%П?Nэ
AsyncSetClear   True
@§ƒўі"­Зў*5Lz -brъё_РŒ      ^Јvœvі"(2uM€.і"q2в8˜vі"uh9 BdД&<ž/MЃъёz
ActiveLowClockEnable    True
#§ђ№і1ўћ45|џ`Vis_SџE.chm!#2Э0)@ў`7џCopyright 1999 @џio Corpoџration. п All ;Bs џreserved.ўЄ•ъё4ЧUŒЂ#ў1?#ЇъёM№7A,@     „™ъё+Х4о§j'v*Q8l>$UdvтљіёE„    ‰\ДŠў4
VhdlType        std_logic
$цѕdU'€’1њ$b–‘24ƒR‹Ÿ(]UЪv[D ‡ZЫQi‰      ќaч5д9       Ь9”уј3ЫOя'0Х"qМ?.g;2шGеРы№Hы№lы№uw-щђ‘*щђ§џЎO`ЩѕЉы№ў­увEW
VerilogType     wire
)їтљчєFы№џd‘їѓнмы№ж#ы№”їЯ7їB
SystemCType     sc_logic
ы№Ќ•їGы№dъёIMoъё@мџёђєk€йў№жUFы№џђ№ы№DшѓfњєёђџџъёP
рћіёъёhчєы№-RTы№пќUдUцѕ’ујUџUFпяїћ§~ћ@—Чуёxї<О?ЉПF
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
…ПBЁP(Є?Л 3тєh
ы№Љ—ў ДЉ)Вў
StateEquation   Hex(Inc(0,2,5))
wbYbbїbb    b R)Л)ˆeqШYkчєƒујZUы№HыCъё ѓ№5ўяђ•џVјџџџ№џџРџџџ€џџўo?ќј)>§ыџјƒџˆŒџƒˆџŠџџџpџˆџ№…џї№ˆp…џ/ї†q‡uƒэ‡їƒˆџЏ„u™pў№ƒџwџѕїj№№џџїџїГ   ЬДlЈ p•ŒŒ†№yќsopŠџi‹`жџ§;ы№Generiџc circleџ with teџxt and cџonnectioџn points.§bщђL&“Щd2—щПPѕѓ?ќѕєѕhџHKГMщПlъ?j№їћп§~ПР4ря5їПD•Hы№џђ№ыєы№DDы№іёщђђё
яєЄ#  фї=hчєZы№,>Tы№пќHYY9  іё›уј§лAUFряПїћ§~џ?ЋMП&“Щd2љМщJЮQ6‰Ћў№ЅіНџЖ‰uŒ` шѓр?/u    :№mсў
HighVoltageThreshold    5
‰biUr      r~YA|XAЂ@ŒЂ     ЂіёЌ
LowVoltageThreshold     0
BаИдфп>јŠпžЄ!"В!"М!"Ц+&
LSB     0

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ўї€L@ў ‰ъё"“'Š%9        ~lbўœ7љ“#FRбџ&џ…С`0і?џFЛ\.—Ыхђ:5ц5т?P60)6К#ьCLК#EшC6	BLP{7№Žј0N„#јF;P46ў•ЃB{“#§ђ№
MSB     31
AўєD5A`7Coџpyright џ1999 Visџio Corpoџration. п All 4Bs џreservedo.ў‰`?@џ_Sba.chmџ!#22426+ўl>(>Ud№PтљіёE„
‰уј“$w       ‰aўоBUфEф@Š‡(Zј$цѕЯя6rƒ;З<ъЗ
SignalActionType        0
я5&
isFallingEdgeSensitive  False
"З(Єј$Чаљ37;№\-_?H4R^3@МRс$iF76RМR€fQя%ы! _ˆZцѕ_k‰rн#Рўhb
ncРж_ш^,Q§_‚kqYkБO™’ујVsZ’X@цѕ8vќBAo9RŠ3МRqŠ%\ в8J6У_zsК%u
^ЁГy _зzsя%~ŽМe9‚qE{€Xy"З_Ч{еРы№Hы№lы№Уї-щђ_{ѕы№џН!џРOyŽa§§єYEгЏебqнтљчєFўы№$žїБЛЪы№ж#ы№ќџ ї{пюы№B
isRisingEdgeSensitive   False
ы№|ŸїПZы№DЂї—oђё5Ќгo)PUFы№џђ№ы№DшѓfњєёђџџъёP
рћіёъёhчєы№-RTы№пќUдUцѕ’уј+UџUFряїћ§~ћ@—Чуёxї<О?ЉПF
DrawAnalog      0
…ПBЁP(Є?Л 3тєh
ы№Љ—ў ДЉ)Вў
BooleanEquation
wbYbbїbb    b в)Л)ˆЕђЈeqYkчєƒујZUЈH‹.ъё ѓ№ђ№яђџџ\ў?џџќoџџј   ќ     _#џџёу љџќџџћўџћыџ?.Ÿ.Яџ§ћџч:ѓџўј?ўќўх№ў?зџџ№ŽџџџŒџ№џџ§№jџџџˆ‹џј€№н†ˆџŒј§ˆn‹џˆƒџџŠџј„`‰Ј…ЄА­UˆЈ†ЕМХџˆџј„џп№€†сЊy…eьјˆ„k_ˆџ‚ˆ‚kŠг€|f`гџ§cы№Connecџt two ob§jі№s togeПther. ђєoџr can beї ei
NegTolerance    0
 a cпurve a џstraightџ line. Џshap.f).§bщђˆ]ю^џЄџйПP&“Щd2ый?ќѕL§ѓПtвџQ"~рПшіќЬiй? ћџ
•Hы№џђ№ыєы№DŠы№ы№щђђё
ˆяє#        фїы№іё=hTчє#8>T      пќЈ#3        Aы№ы№Њы№ы№›ујЇўAUFЬп…џћ<@Fряџїћ§~џ?FДџ}ќбё?FєцѕЩсбPв!3Ÿ|йР@Aў‰u
PosTolerance    0
`uўфbўvќuі№`u
       Ѕ-‰
ј:€з@ў‰вўж‰uŒ`hр?mVu”`bšЫў"‰@0€мSˆў#ъ‰           €eAЋ  Е]œ&Aœъё       ›њdыъё›A№W+ь"œW"4,4'щ>ъёБ–DИџ”ib@FК\џ.—Ых@FџіІФ +њ?FџM&“Щd2љ?M"q&Vz&bVƒ&V%ў.‘ ьм'ыS"№з"ыц/ј/ь87?5#'ЄB?T:Є‰ъё_‰UUщb$ўђ№@[мЎ
UserSpecifiedSizeRatio  1
;ў‰tNœ“zsSЭ2г<ЏŸbў ‘ъё, œ3a&G@Џ§1У4’ў0„ъёQD6!468"ы8"dB#"ЎR„F8!—€LSœ™ъё-ўБ!]{eEцў‹%Щ?@rЧqџЧс?@ŸєIjг@ЯШEббEП?эj?‰rњРўќB=SРў*+Ÿ@s`A*@bS_РŒ	SZg Ru€з bBTORrguhВq4Ž`u#`­€@Ђ	 ъ§0Ѓіё“§0uŽ `ўdBsH4&L'8"Ѓъё{œ3A§ђ№їQЎ1Ў15‰џ`Vis_Sbџa.chm!#2?2447ўзџ`7Copyriџght 1999§ `io Corџporation.  All =bџs reserv?ed.ў‡ъёuGœ32ЫBqЌ?…oк—f“2?Й|"т?Jhрђ№я1aцѕl>
VerilogCode
(>U  Wтљ(DE„     ”‰ујœ3І0м?P‹aў%ra-s4pŠ_(†RЕ@г9—$^Ї$^Ѕ8§†MtŽ<њЌЙЭъ‹%й?мџъё№?"В1‰Umчў-CUРЂЎЕї4џu2F
VHDLCode
Щ1ІHBMtЪ9˜Bmїxw}n‰Œha3w‡9   ЉујqєXсќђ№h
VhdlMapping     DefaultVhdlMapping
AШs`Cџhange Arџrowhead.ё.o`1fшƒthe Нaя… siz
nўtyle fo§r
PROPS!
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A R`ЃPPџ“`_Setџ As Straў>bLineўЮ
B`"П‘1– l~а to be!АШ“o`јsГў
E0      X       750     750             1       0        DR      0
(рRВiG82fВ86№iPPЏbЏуј”уј3MO.с`'0cМЋrb".,jЅH     a-Яфї!kхX#ЯgЯы№qЂП”ДПуј™ујP-Šт@бЮЫ?—#іЌ|xy%qaхі
A#г^?б=ЊDујСЃ       TОŸа‘g)ESЯ5ЩујˆArаѓХWb"ДВ_(9oгh№?ЫЮcBtL@ГtRфўЃл#SеРы№Hы№lы№'ї‡щђ?    {ѕ ы№џН!џРOyŽaчы№YEг_ъбqнтљчє§Fы№Ь­ї‘wжы№ж#ы№џDАїgнєы№B
E1      V       1750    1750    D20     1       0        DR      0
ы№|Бї[ca_ќЏїОoы№W@+ы№фkПoљ:aђёLВїљot:ж•Ты№(ы№Žмџсњъы№чєы№<ƒїП7
˜ы№SћЩы№ь}їЯК+ы№B?ы№,Н~(Jы№R{DGїЕOљ>S"œї&Я‹/"\їќ•wџ­їm$)/ы№ ы№мџUы№џђ№Ѓы№Pшѓјњєёђмџ№?ЅџRЉT*@‡УсpИ@ЈтљіёъёFчєы№DNы№Teъёёђ@yŠ
рћaъёhmї$ы№TBы№пќРРцѕХз’ујДqUFџ(9
D,m@џFЧаиrѓџ@?Чуёx<ћО?ПF
E2      X       5750    5750            1       0        DR      0
…BЁP(Є?.у     KX]oыї`Х]ўq|Jž|›ьъё‘2б№?уиыуЯžѓюЖХuѓ` цѕhу "&"uР0)Р№ъёэѓџ@L&“Щd2Йѕ?~-Щ(Й\.—gЫхвЁ(.sUЧ!схХ&tч/ы:џ—eь(Шœ’пќ'
!
4ъёы№1!!Rы№"шРы№ы№Uы№&)4ы№       ы№•Ь
ы№ы№0Tžюёы№ы№ы№R&!ы№Ыы№ы№•ы№ы№ы№Њ^#С%ы№ƒуј
\1Hщђд1Тр4`1ы7f%р4l1ы7ур4p1ы7Ар4X1ы7X1м8р1ы7\1м8t1ы7`1м8Яы7l1м8žы7p1м8ы7t1м81ы7Яр4”1ы7|1м8˜1ы7€1м8юёы7„1м8&!ы7žм8 1ы7м8Ыы71м8Р1ы7”1м8И1ы7˜1м881ы7юём8Д1Gь6&!м81!ы7 1м8@1ы7Ым8D1ы7Ј1м8Ш1/gЌ1м8,1ы7А1м8
1ы7Д1м8)ш:Р1м8*ш:И1м8+ш:81м8яы71%р4ѓы7@1м8Ры7D5р4aы7Ш1м8,ш:Фм8-ш:а1м8.ш:d1м8@|1ы7,1м8€1ы3Щc(A“Хl1\1\1я`1D`1Рl1l1a˜1D˜1|1р1р1€1ЯDЯ˜1|1|1юё 81ЈUФрћoНя@Д1ШАч ТъёЈујEQ§ђ№/‘я“/‘ыќР”1џ`   ConneПctorўр1_`ўP’
SIGNAL  dbg_dat_o
Všы1я[EiaiCТђёX1|ˆщiEѓИЪамюОцѕEЫџMЗ7у?@XџЧЫV@@НЗЄ"ђ?@Z€"й5?GЄтOЅЩ?(‘ч„П5o%Ћю’Kј…Ѓ2ЈЂЗ—ЁЄc( 1ŠІТў›ˆ;1
1Т<№“™цѕMЮ€"љ?КIЄЗŸџџяl№\10№’ЖRse цѕV…ч
ы‘—•‰џžŒЁ!ŠП˜1Ющђ‹c(ЈЕHІЙЛЅЯОQЅСГАЈОЫiEЈПхіqQ8Сqѓ”pџU2&fHnП™ујdаК` вфїсЃъёЌ1б­Ї­ЈщТяЯІСТGБњП–!ЬЯоШІСf%)л`ІW CпUмЅ)е%Ь@п•пАlпСпгп2№Аё„цѕXtextџ ID
DIRECTION       output
(4 bits)ъ2ѓˆŸhDf%ЉŸЛŸЭŸпŸёŸЏЏў'Ќhим+ g§@>Їпяїћ§~Џџ?@ERЅо!ђя@'ѕiЏП0qŠЏчФ@1ЈЃ|іТЏдЏцЏјЄf%ППѓљѓ;ПMП_ПqПƒП•ПCЯЙПђЙ2ѓ&№рП™&јЯz
RADIX   hex
е<ЯNЯ`ЯrЯ„Я–ЯЈЯ2іУЯячХ|џеНпШязпcо2ќƒп /Їпѕ
GRID    0        1       0        1       0        16711680        0        0
/c/ънР2ў–/я№ГЧфи5Paџge Indexџ Level 1
ENDGRID -1
(8QшT5dяушя€“яЅяЗяЩяляэяџь,Пhь”O“јсB!ўр3џEџWџiџ‚aЈЃRFџЁџГџїЅМ9йџыџЩE™1   -?Qc‡ђЙCЋl_ЯсѓQ_);M_qvXŽр/фШROе“oщž_ж/Ѕ/1.LQ/іou/‡/,Ћ/
мot%эјьq?72
Clock
(11Qш—•:?‹xW?i?{??№Ÿ?Б?У?џь$dъsы?§?O!O3OoњaЈЃ)–eOwO‰OїЅъеЋOНO ™"QпOёO__'_9_ч_]_–__CЏЅ_З_Щ_л_(Џџ_o#oшŸGoYoko}osЁ)ŸеjППouЏЌ{ПП=OaЯ…шП=ЯOЯњї)к Offsetњp3Qш2љ‘Œ“ƒ ŸџџБйЃKБ@ъеБh…dw…ЮœаЭљБЇ‰‘ЅДqŠџ}нsЅ
@@фџѓљ|>Ÿї?@џИѕЋ'Ьд?г@€Х™гФ еЙ?uPИЄ€ёЯuЫu`Dбn р?›ўЫвup€ейВЅБ2БївŠ§жџ‰ŸОђ€LІ ўЖ‘БОŸ0аŸПєŸЌЉŸЁˆУЏђЫвбйŒррг€чйсс>ЉДх™жХягз№оеъяˆўЂе џ2џїŒЉДюkџзяџГЉДяџРбџ=ўї!пЕ;тоw25'5im„Бu‡zдтcш”cш#$я'2ЧqТМА нФбnснЯяЯпп%п7пIп[пmпеџЅW—GТ?џ@$­>дk„џ@@РУм‚oџOа?@@Х—Рž@КоїгnсуЫпѓжЯспнбя)я;яMя_яqяƒя•яЇя)яяЌ+—У/}џч/Nџ8 ?0?—џЎ/І i?е/?@єџИ/?е?<КЂБЫ3dvˆšЌОмиъќ 2DјVh|иZQJЏ.ѕ?@#ЂжЉДпЦпиптдAщјVя&/8/J/\/n/€/’/Є/OO&Oь/Q??u?оoF?~Оџ%р?Ÿ?Гџmйoч?ЃМoЧйAOSK1bOtO†O˜OЊOМOкCJQиOъOќO_ _2_№D_V_h_ее"0њ@ŠW™пЋпЛG‘гхЩ–ў/Є1oCoUogoyo‹ooћ
8їoџХЏ€?ћЏhџПк™ЋgПгЏ‹ПѓЖЏСПгП;PM24_qƒ•ЇЙЫƒ	вфіŸŸ,Ÿ№>ŸPŸbŸz› Ѓ/жV
EdgeLevel       neg
@а˜ŽгЏО_а_т_ЫЮСќYђжo Џ2ЏDЏVЏhЏzЏŒЏžЏќПЯ ЯцЏЂьŽжКяuПояFПјМ?џкП™ПБ?gџгясПџЖяСџгџ;ЯMЫ3\ЯnЯ€Я’ЯЄЯЖЯЫƒ
Set     Not Used
ЯЯсЯѓЯппр)п;пMп_пt˜џЈАяgі№ƒиЅWO—Gв•и‹ТЇпЙпЫпнпяаЫќYяяя/яAяSяeяwя‰я›яљџуяŸ,‹З/rџл/Cџџ(Гџ?зџ–џЈџd?а/оџš?Г/О?а?8PŠ1Xj|Ž ВЪ„NЯсѓ)№;M_w•ЬŽ#!їSƒи@—'y„г•иˆSУЄЖШкяаNійьV//,/>/P/b/t/†/˜/і?OOр/œlˆVДoo?иo@?ќhА?д?“?Ѕ?aЭoл?—АoЛЭ5OGK2VOhOzOŒOžOАOЮC*aЬOоO№O__&_8_јJ_\_tе†C@%_ў@@"€U0›•	Р’U…“ЙŒ•Љ_Л_Э_хк*a№Yщ–oo)o;oMo_oqoƒo•oѓнo™Ќ…–БЏlеЏ=љЈŽ•ПП†œЏ/ WПУЏ{ПуІЏПУП+Ї‚ЫL0Sew‰›­Ыƒ
wЄЭŒфГССо…zЁ€фєУ`ЋфЕ,‘$•rЁ$@1—'ЁNЉŠЃ`Џ_™El”џ2=Хl@@ ЦfаžŸ—PЧуёxƒ•бйƒеyа…•QLйRЉ+”ЯЂ§в)sЄ[сжЄ7ˆФйЊЃўв/‘(Ј<ш1“оХNЉMЋВљ?К\.—Ыхђ?єЯџџСС3Ё,‘;ЏMЏLп,qЏƒЌ”ЉэПхчЉлх…жьы•ўŽеєу@•лю:ћфЕляŒцqЊфЕс,1—wё‰щЕсфЕЁя™ŠшzсїyаєОышуЄСйёЅхћ‹жИжє:…dц§ŽжBZлвсплвЈйё•хѕXќ?Q0•хўѓ6•§'FKPhysicџal Page џNumber
Clear   Not Used
(џ22 bits)Ь‚6ХЯуД6тЯЬпрп*п<пNп`п@$dџъs@@‹піќЬi—Pмяџїћ§~џ?@ŒV"”а^#яe%ІпИпЪпїRwёхгК&єпяя*хЗ:яLя196nя€я’яЄяЖяШяvџьяА9^&џз?d(BџИ:Koџџ“џЅџЗџЩџлџp&іџHOZ!иOTf
ClockEnable     Not Used
p,‚”OBО-М_д-O_@)_p.д_PЂУiўOffset
ActiveLowSetClear       True
(13у‘Щлэ€џŸ#Ÿ5ŸGŸYŸk•ЎџѕЋ'ЬФ?@џ РaџšЕп?K@fRu€•*sУ1uІžу“у‘э“ЗŸп–[r§“ЭŸЩ‘ЏЂ/'ЏM?_?q?ƒ?Џ“ЏUOЯЯлЏ?‹*vViПz:Пžˆ3uБУƒПAдpќh ŸрП KАhŸ(ЯЃТ@Ы34OЯaЯsЯ…Я—ЯЉЯpcko}ooЁoГoХoзoјщoћo
xzfЮ_м@@"uˆrд?@P7'Гp0ГK]rgЁfx}_Ж‘Ѓ:ЏЧйы§!3‘ŸЃŸЕŸЮ&ЗSЯŸwЯп›Ш0ЕЎЯРЯ(Ÿ>ЯбАљЯeЯп…ŸHЯ­Яeп<ЭŸпŸ13ѕŸЏ Џ+Џ=ЏOЏmЃhЏzЏŒЏžЏАЏТЏдЏцЏјЏ
xџЬŽ#!S@@"uP+u0Ж$ѓBp@BПWriП~qП~vdсcГ‚sˆіЅПЗПЩПлПэПџПЯ#Я5Я“пЅпЗп}Я9$іPпtмߘLпЕpп/пAп§iwп@3LWiбпул2ђп@яя(я:яLяjуeяwя‰я›я­яПябяуяѕяў
x…C@%ў"И0.і1Е!3Й=џOџaџsџ_pa!Œљ…6ЁџГџХџзџщџћџ
1ЁГy5L!6MOqOй•HIВOm,>њO€fOt0_IOT_f_Ю
AsyncSetClear   True
Bk0я//%/7/I/g#Di,ы#]aAž!A€/cќ;Ђ%Ш!Р%з!4Э'јQъ9д,AE№уaі1Aћ/U@$dџъs@@џ§N#@@§L1ЕzН^Џзыг
Р0t90{;r§ПdJЕDФ20v€AЫ1]Э!u
nPuфУ`rs3]aУ1ЌГ•v 8ъ}&.є{Œ@wŒіќЬiйMPХ)Э"pД%у`юw€ф@z3Ы1шrюФ2pв A†-A@RŽŸwbXГ’‡Ѕœш(qь„Cv|Mt@§rHbс?@ŸєIVл€Я?б„бй…ПIЖ@DЃ_e6kTЃ3{1ПзH1&0oNŸœt…Б(/dџ2NшДNkvS"V
Я "Š’Її8gЁщ§—"ф“`0ЄВуa@aS!@Ÿ. vѓcэ–Ё‚Xѓb”rѓb( 8<Э#ќ]a*­Й\.—Ыхkђ?<ЄПoџџ]aЯ1
ActiveLowClockEnable    True
E$м7У1ъ9&Cќ?OU@0OОˆ™_ŸН\€OМŠ:uоЏ№ЏrWi!cqAi,€ScЕ‚o”oG€UAР%AЁа$d’шlшiIyEцžоБџNP„щ?@ђ/џш]2Ж@@ияїћ§~я?*Чбр,Т!№=ХQюЙbŸ95аŸЃ2pЁxqdѓc‡Цг!Ћ‘Ќ‰ђХц>ХЙЧёx<џы?@ъѓљ|W>ŸчЩХлвХзєŠBA`ЄзHxqmЦЃ3ўŸbIЫ!ЏTcq<нMGR3љ?Nе–Пџџcqв§9тлPage Tџable
VhdlType        std_logic
Basџe Addresџs
VerilogType     wire
dependџing on
SystemCType     sc_logic
cџurrent CIDcЂEЮГс2йПыП€
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
EЃЏoСЙЉ]cŽX=Хш(8ц=У:ЯCЦяє‡V@уЂ%Nх/юЉч‰жzяЗ‚E,Э'(­A\€UO™ы8dOъnш_е@aц‡Я5bђhџёЃ5л1/џИщMџєы%ЂѕЁяМџЮќЂ%Ђў^єД%Ђћ\щBWјi!S1і1i,њ3S1„Пићњ5AТП№дПцпјП
StateEquation   Hex(Inc(0,2,5))
Ьhим+џ g@@šвџвlS
HighVoltageThreshold    5
@@4OFЃъ€nС~ЄNЯЂ6SjЯЃ2B‚Ыf‚і№fо!ІШђЋŠХ“&ўлџэvЛнЮ?@кПNЇгщtЪ*%О3%КэЯџЯп#пЮ"S1>пPпС-S1ьQzє_oPo*o
LowVoltageThreshold     0
ѕDaU32ХOcŸ1ЯQкEл\+cЂ,Юп#5яя‰]€@яМw€бxяŠяЩ?KМяЮыџхфяія‘?џю:
H˜„Vџђ|ѓ_–џаNXHьOжќ+ѕ@O[_WџЫTС_3S 
•_ž_TХOњ:oА^оzѕ{okБj#ЌГ‚ѕ€Ырkx7І0Ezu04ф'у!’IЧ‘q€9а›ЅЧ‘НD“Й„ЦЌџЗжџ­і?@Фџ˜xПќ@@§я)Вѓ?@`­VЋеjе?@№)ВхуˆuХє‚ёuі{ `uP0`€A_Гru
Лq€ТuРŒ‚г{Ёb“…УыrђЛ8
LSB     0
І€Ъю-gџІ@@5oУыLcc‚ƒp:еrA†Š:‚@RДrp3Гpƒ“†!’ЄŽсwў"сr‹ђшˆ†Тў"сrђ“)ќwAБ4ŸЯчѓљ§мˆxrЧqЧПс?@ŸєIMЯШB•tM“ПЃ}3ЙзuQ]‚‘FПXДП-H&­ЬРŸюt…‰842NПшДNk:2Wf
ц ќ’ЇhіŸСА§чжp>ц `0ў 3q8L1:1ВŸ.‚Яє–л_ˆ/T_Ёœ­Й\.—Ыхђ?ЎЄ
Прoџџ_ЁТбKqi?р{?ЃLА1KqЄ?UК9WaщњІGv™–F‹ŸBgВ‹wи;Е“s‡p\‹tPTЛО3ž‘lЙњРЂяŸ‚Б0E;ОŸП^ПУПЕaъ!Бoyдъ%вoфoіo}Nсч$Ц
x7yAG}мсW}§‘+”Y-oR/ў™p=BЄщ†4ї@@LА"ЩП@4hh§У‘ѓПдЭЙеуПЄ|rб€жФж~ъ!ыyhжŠ˜~+”MЗ7™pџ%.є{Œ@@ІEНСэ&™pџ0(JъP@ƒ:„О5rТжЈРСпЭsж™чŸU@Пфcв3Šuа|€ P_‰уПCŸјUŸgŸy–ЫŽNGЃћ*р‰œуяZxFђпŸŸDЏУŸьЃ^!Œ5ƒA.Kpўсz$
MSB     31
 œL16вtNРpvzsGбл‘ЂEчŸљŸЏЏ‚/Џ+ОяЖWwвCs­і‡Џщ"žЏАЏњ§ъ!жЅG€шЂŽO OЖEП'ПпЗДшS_?яИПKП~}’jтbqЙЊ­сlП€€П=ъ
ењЛ‘я(”›еПРщђТф ў~‘=ьЫцО€Œ5Ь0яT4Сb44Ьт"НL1QЯ№ЄKŒ5yKq!Aч$7yƒХШх5ЊE[y­+”Џ#й?›@NА$@GА"€hpl%}#q †#Щ?QЃI€Žbt}‘у! ˜№бБЏ"t“‘К"6UсqЬЦ%Е'0C—с*Џ"Я'к"ьЎр@1О5kєзыпЄ‹Ќк+        k#gљ?Кщє№џџНжЅcёAQцЄд§cёcѕЊO}CW•ёm '?ПŽТР ї5}&KѓUN†%Cюхї>VKЂEї?.9у	гђ'9Х95QЭEAU&o ao0c5[ƒ&Щ_%nG%^†&^_'lѓ]tL[_А_юх‡_м_ю_3ТuaеAХЄєоzoлK-ѕyБ$ЮїыqЩIcлOW/Uћ@Hl%Чуё_xє?@>~%@eHsq sЙŸ/Б+ѓР/ŠИ$к"Мр/Ељ/ Тл!ч
SignalActionType        0
xQ…cЗQƒт.@RЛ!‹RUдСхo“vTдТе?Е8?аёдЕ=OnйЗБqƒ•ЇЙЫyŸя(ŸŸяzЫEŸЮZPыrŸ„Ÿ–ŸЈŸКŸЬŸоŸ№Ÿ•яЏія|ЧtРџp_9џŽЧ†РXџЮЏХ_sч@UџЊџTП‹ЬнџяљGЛ`К!ѓ!ЬУДŸeтПaѓ!€o
РoЇбЯ(Я:ЯLЮ     ќMРЮQ`дкЊпFџ    @@§Nч#@dФƒ ‹ХŸbБXќ?dЧьЛ?PдщЯLЫQLК!MСН:@@GbDTЖВDhЃЃuЖ!ьШ06B@ЂЎ"ІTh5h|u“qьШ јqеŠДˆeбЏo,СoдяƒФш
isFallingEdgeSensitive  False
ЫSЂПБ[#еi$Щ!t'Ui$ЗБt#ЩvјбЃАMСЋе
isRisingEdgeSensitive   True
ЂПБИПJБ•aџџMС     9ƒЩMСШЏСLЮ‘ЫTьˆљџLЫ
DrawAnalog      0
@@р?яїћ§~яuЊœ3пЃ5Й €*@1м!:|ѓСЮ2д6оѓСйм!!п3#€0@ў„бЧ%п0ЂпияЦпиихй Є‘яw‚Эрўо2€ффAщЗEœ7ЩO…№ЃpшOњE•
BooleanEquation
_t#_5_„WZщЗOo_лO“_ашА_€_д_@^“БyѕнУЅЖLџ1 Page DџirectoryiкЄMСДСK4^хj9деmA”Фш#'O'2žqlqЂУс$<Б•ПМyѓ<ЕмП{Ю1l7•ЩR14H7ДСУщO<шs†гnquA•QЩ§“цЄЄu+гѓPџ@@љВЉОbџЮ@@8ŸЯчџѓљм?@…B_ЁP(фПЛtЬУusдП!ƒu5 {`ui `€AFAvюruŸА`uћw˜Ю3<Б5!є3"†љ{)хБ{Ў”T§ћšввlSў™0˜oЈ“ џ@@XbЊXI_@) Вpо1ИJБnp{‡€€@z3FAu‚{ЊТ!pbЃЋƒЮ†КЭпŽ‡DЮ2!В#˜1‚ІЮ2Ф;ВІœvјЈуPp8џ‡г?@Чџуёx<ЮП@r~гbс?@ŸєIˆЋЯ?~”б†•П ~j\ШBВйСT4i•и@ПкЈ&ЛoЬћŸ)„…[шКd2NПшДNkкbU
NegTolerance    0
fžА6ЃЇrHтд§
PosTolerance    0
2€ЂА`0СBnqmAкaэŸ.-†~s<Ж;ПMА5пTЄЎЁLнЙФщЄПџџЎЁ„еАч\BПябя‰Eˆб•OUЉOoo+o’žЗ€ќOДQ4Н}“ЛќКЦЋП UU]мn•‹П„XОŸДОЈ](ЦоПCЯЯф!ODф,uCОСuёЧwKuEМЁ;5МЁТЁWt -wxwŽiпщи     EБT+џhь”O“@@Пь-gІЙpŸ4FЃ—†мСZ–зQIйIS}ЏТrВBѕ2G1ВЃтж" ЏІіжСЂ~s
UserSpecifiedSizeRatio  1
цY™lељ“™е2цўлэvЛџнЮ?@кNЇгWщtЪBхОKхК €2 є•*rГ(ТЏT4ОС„­MТRљ?ЧхёЯџџОСwaБo‘oЃo(Еom5ЯaUKђХкcAJa•i!Zh+ВDе)г\B4пFп…EXП!nЙ(Б\ДZ˜еKh8БTп˜мб ƒVїѓ•цў`0Е0c“8ЕГM2((П:П…I™Ћd
VerilogCode
%˜П%ReіпО
жrЕVAцo        гNeтXsтп1йKUUY‚ОО€г/5т -/
VHDLCode
я3“/ф!G1ьoMdѓуЯ1CUgјy‹z3Š‚Ыџ<@@"HєcЋЕwh€ Нu ъЂвW?@0ЯuъЂТЁюьQ&‰џ6;ЕP(9
D,mi‡@†–ƒ`5zи@s†Vaїсџ…]BуXO@jOШƒОСc4ЊG—OЊOŸњ6#™ќLсвC™WYŸЗU@лn•@5ˆбБp•…Ÿ—ŸЉŸ` h›Я.ZРrпнВPЭкŸЏўŸЏ"Џ4ЏFЏXЏjЏ|ЏŽЉѓиђПЏkё ЖоЏ№Џиh	СП#ПГGПНџ@kП}П5ЯЁПz{СПU˜?pУˆЯD\h–_Œ@gЯHXЛ пЭ!!Ц/и'›ц/Э?.?@?шR?d?v‘Xthимџ+ g@@˜ЏQ’LC0LШтЩџ?@ЄеjЕZ­ЫцПn”Й 0y’жПМ<Ь2n–м?ю>›Iєг–JъV&.єѓ{Œzа]–уІЃ;ЁmOG:UŠA-ІРO,Џ>ЏЅCZЅІkЏ~ЏхOо– YаЇ6_U€—x“жП[_m__u|р~QДК__oо_№_o€o&o8oJo}ПnfИ…ТЗ†пЂцг+ЦžoT€›ЖoШoŒЭ›юeѕq$ћgч‘      yШѓМ5Gpбњ Wu–JП2Œ€œњЏ}п.п‹9Ÿ9T9РвфіŸŸ,Ÿ>Ÿ~Pš+hь”O“E@?Р–›7Ÿь3@o–.‹ХbБ№˜0тр‘ŸЃŸЕŸѓ99IйцьŸ\p,dх
VhdlMapping     DefaultVhdlMapping
І*ўdх5б8†FР OGѕuŠA3і”Џ2џDџЅGZЅ…іqџвC‰џОЏ9  YжїъЏќЈ~урП П2Пsп…пhПzП‘žПАПТПдПцПјП
PROPS!
ЯЬCНжaхђн1RЯTЁбjЯ|Я’ЁбЂЯДЯЦЯиЯъЯOппJ\Dп     .~хh"/4/чwGЖд!б$јеЬпЦ!ѕqд-С‚qхђaцqф+щје:U!uњs9  &D)fkT/џƒ@@ˆ19№П~љ§?@HЏтщЗ?@€сXќa5йZj5ьЛ;Я"}/Šжd
LЮ’ЙъђДъђГS%в6х6Ј€е3љ6С2Ч6Њб6б6х6х6љ6љ6ЄZМс+уўувbe"xДт(Пбђaƒ
E0      V       -1      -1              1       0        DR      0
x
E1      V       750     750     PC      1       0        DR      0
XsДЉбРCOuЮDх1йG:UЮD€йCЩёј+
уѕqGсŒGсДF0=Qх1F0JQ€ЉбДSЉмИДР%Ъпмп#s@Бќй
E2      X       2750    2750            1       0        DR      0
??.?v­XtѕMv5NЏтљ?@GТd5hv5c{0$cЩ?]QЏI€ђtyqЪЙ ŽSяŠ MbtД5Xb6qЬdePSgѕs‰!MbmgxbьŠ OuяšF0YqTxU    y       cљ?КFŽ_џџДЈGс0Е–AžI0UзѕqnSхb§Ћt/хЯP)•ufІ{ѕuМ~$eЎsБ€•~є{„QЃzіЃms,Р
ч1žI„Q)…[™,ш4qРw{09ŽЅxxC3с“нeŸ‹!fuЙЫŒєѕŸŽ$fќЫŒxŸ…ŒљNŸБ%ŸzŸŒŸЈвх1„Qc_BT|_Џy‹)…ќйР‹OOxє_6€u6џЧуёxє?@>Bd5@vхЊЃ{0ГЃЙ=oROkѓ^oVdxbМ~o4i›mТyaчВl мc%УйaCУnЖ,ё7у‚ЖYAєѕeJнcxHйoTЅєoљЙх1(:L^p‚0ІxЩЊІЭŸЯАЈќ€ЪлЫ);M_qƒ•МІАЮŸ‚д‹dЫЯ,ЈпF0Mah‹З‹ИтяŸŒиГІупQŸФкљЬрпђпaПВrНуРяŸŸ(FюšяiыЎ
@гыPTE2R€__qT€Џ‡џ _В_Ф_ж_ш_‰Џx3МтЈЈяЕїТяГтЬЏоЏ№ЏYaRUЂrх
ППnfTrеВoSПжoBбrѕлПэПOAЯ!Я3ЯEЯWЯiЯпЯЦЯБЯЏуЯ“юп"п4пFпXпjп|пŽп3/Вп”/Г/Ÿз/,$і/lяcŸ'ѓ/H?ђя){?ж'VџЮслsџџ|Ё
IpЉЂћ|ЁаДџЦџиџъў‘d(fџkT/ƒ@@Кџ”ї~м@@ряїћ§~яХtRх CпЇEЙ?PFЄн€yЁЯ}Ёu˜TaŠвBunaŠВzр1|ЁўBŠVЏ        Мнb\Ё€L€ў"|Ё*0<r/`rƒЧ1ˆ//yЂвBиI“PчC€юIшQЊЛU GЭ_лF№хEё_вoЊD'o9oˆgјЛ_soп_—o (Дo oРиoDn1ё•"sCіL2џ Page TaŸbleiв|Ё S'ќtЉк…IЁ”šXR~.\'2<Б
E3      V       3750    3750    D100    1       0        DR      0
Б@х4ге]ќ“кх€zџ‹ўAvЇеAЉVA4S'ƒq`ЉSL†Г~ЃnшyQеяљ“ќєЪЖ“џh9@@Мџ[ф@@`џŸЯчѓљм?@џ€С`0цПоЛ„Ь?@xЦ‚жПИУErDЂБu\ `;u
E4      V       4750    4750    L/S EA  1       0        DR      0
O€AJQю‚;u=№`uћ‡ўCЬг\ЁS"–ђд
E5      V       5750    5750    LOAD DATA       1       0        DR      0
| qЯ9UЩџi @@ь-gџІ@@Х3яв   №А€Œ§Nп#@ŠГуpЫфn€{—€N@z3JQu’{ŸŸHpЁе­‘Ю–КŸ!ЭŸпž—RўBвˆ'ЄmВRўBйтCЃœ\8F#U@•ТХџcБX,лП@§rгrс?@ŸєIVˆ Я?~Єб†ЅПТFќrD"yozг›о§дlБ:Јƒ:ЈуAАПвrёО~щ*“ѓ…љКt2NшoДNkкrЧ6•<№6ГЇvXЛ§xBB€`0ЎpnЁQкqэЏ.:І
!
укцйябргTТБщ
iЙщДПџџТБ"N'`R]/o/U!™_ƒU­_/žЧ€o~СgН“ЫќŽo i"YmІnІŒЯл@ ОЏДЮЌm(жоЯCпп]ё сь4 х
1CUgјy‹Š“Ц†џ.@@YœюJџ,Pѕ?@шѓљџ|>ŸР@~Нџ^Џзы§П@ъ“тїПšфэо№ŸР›Об&™јц;Ÿ˜пЁUi—@2п=ХlЙ€hіќЬiйЬ`u”ї‘Xсџ•VђуŸQџcџШ“тр[хЃїџЃџЏѓц€#ЉѕќђCЉYЏNтГЯЄсП@П€рЇуЏ‘ЏЃЏ€e+СятpцЧЁм2”зP^CщкЏ-V!KПП'П9ПKП]ПoПП“Длеs“ЈГpїтМПЮДОбйПыПбОбХV_h_=ЯVTЯfЯxЯ0пœЩОРЄпНЯо#щ“эm+"SњЯпўR'‹ЕUПŽиќ/пиCœ]ЧЅЂРПж/aпњ.L?%?€Љћo­(^?Ъ/‚?Цб*фЦпшп
BсM{_rE х‘3(lщ‘Еd8іџДv>М@џ@Чуёx‡@@@ЦdІDЙ€АCЙŠwЯы1SЧЂЂu)рА,“пFЧЂ19ћANUЯ+Я/OŒV2/D/ЖlАEm/ЅЯёkm\/Ј_К_LoоXЇFђ_„oo@A?:hŸ_WoУ_ѓ1+ЏДѓ<у
SIGNAL  dbg_op_i
O7эcu,OaEFIA61ZDHщх>EBEўOU@`дкЊпыF        œHN™bљ?@        `БE’sщ™uШGрqжFвaуOѕMЪv_њBF@•ёS@’ё€L€зс%Uя/§џџџ    
DIRECTION       input
ўџџџ
 !"#$%&'()*+,-./012ўџџџm56789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklўџџџЫopqrstuvwxyz{|}~Q_!*l_U€_х_Jo   onХЭ’vОЊoт(o˜›uŸ+Ÿф+kн–VdŸаˆŸ”?ГŸаŸЈ;HјZ@џVirtual џPage Numџber  (VPN)iфROdOŒˆё”Œˆјз'2VqМНqѓ11Qжoшoњo0BTќfEжBEЧmџ
@@FЃбџh@@—агK;жЖ@€БEЇГЙЎЕ Г~д!QњћF1QЮsџCЦ"4FXj|Ž ўŸЏ"Џшš;ЇЖгЯvŸїЯGŸиАЕ.п@пŸОЯž0yпхЯп€эŸШЯ-пхп5ЏѓMЋ0€uЏ‡Џ™ЏЋЏНЏЯЏэЃ-шЏњЏПП0ПBПTПfПќxПŠИоАqs§p(
RADIX   hex
…BЅПЗПЩПлПэПџЙусЩ$Я6ЯHЯZЯlЯ~ЯЯЂЯДЯя$я6яќЯaп п…пэVпhпЭп5ёпАпТп}щјпГЬзCRяdяvяˆяšяЌяОяая.фяіяџџ,џ>џ№PџbџtџŠИДZ­VћЋе—№Q*•JЅ_Rё?@PЩйЊјŸ3ЉіФџжџшџўКп!ЩF 2DVhzŒžА/ /2/јГLŸ6ЫO‡яOXXШ0_ьЋНx_фOѓЎ_ЧOв_єф_<­
MЋ2047Рm//‘/Ѓ/Е/Ч/U.щђы№ы№ы№Uы№
GRID    0        1       0        1       0        16711680        0        0
ы№ы№
ы№Uы№ы№ы№м№Ulы№4ы№,чєы№§ы№(9
D,џm@Чаиr—ѓ@ујњѕ<џ7љwV'њы№C§ђl0љž
ENDGRID -1
7ы№AщђU2ы№ы№пќчє§@ы№1љЄV7Kы№RHы№<мџ(
Clock   Unclocked
U2ы№ы№пќчє§Eы№L1љW7
ы№RUlы№ы№Lујы№ѕчєы№ЬФїџ—%Я0їгЩы№УїпfVы№@U?ы№4%я)ы№gRD3W<U$ы№мџ
EdgeLevel       neg
ѕ4ы№(чєєюмџU1ы№џђ№ы№(шѓы№мџіёіёцѕUы№ы№O"D&aU=шѓђёQџџJf        рћ)ъёh"Tы№y‡ъёМуј+U,оЈ
_Щ…>-З
Set     Not Used
лH*9(TYіёgЉŒžА
Clear   Not Used
щђ›ујEдпё/+GuideTheDocPage-1ѕы№ы№Gestџure FormatBasicVisio 00RectangleRectangle.3Rectangle.4Rectangle.14Connectorѕы№ы№Dynaџmic conn?ectorCircleVisio 90ѕы№ы№Lineџ-curve cџonnectorScaleFactorCircle.31Rectangle.26Rectangle.27Rectangle.13_ђы№Юя№Ѕ        ујъё3ы№МџЯјBX
ClockEnable     Not Used
Њы№EЬLЊмW-
ActiveLowSetClear       True
ьbєђёGајUz
AsyncSetClear   True
_„
U,_‘D_UŸ\_Џ™
ActiveLowClockEnable    True
Ut_Пы№AUŒ_УЄ_Uд‡
VhdlType        std_logic
М_тUeм_§?_Yv   _бјUЅ$%4œ<%D”ŠT%Rвlњ%c_œкјtX_ъёя№ы№[Њы№ы№ы№ы№ы№њё0ы№xŠQы№œвы№mм№ ы№мџUхіы№ы№ы№м№Ulы№4ы№,чєы№§ы№(9
D,џm@Чаиr—ѓ@ујъёўы№d5љZЋы№C-T3Ў
VerilogType     wire
7ы№AщђUlы№4ы№,чємџшнўўёўѕы№T0љП[
SystemCType     sc_logic
ы№AJ-L37ўёAщђ_ы№ќпќмџ*<Nчє@ўы№М4љДZMы№RVŠœЎ№РвфgL+љ
[6uHы№<мџ(
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Hы№<мџ(
StateEquation   Hex(Inc(0,2,5))
_ы№ќпќмџ*<NчєEўы№5љŠ[
ы№RVŠœЎ№Рвфgь+љ—qџ аЯряЁБсп§>Пўџ       фјМъђўџџџчѕ7DVhzŒžАТдцј
HighVoltageThreshold    5
.@Rdvˆ šЌОар§7   J3ь№ь№ь№ь№
LowVoltageThreshold     0
33!/3/E/W/i/{//Ÿ/Б/У/е/ч/љ/??/?A?S?e?w?‰?›?­?П?б?р;зRoѓ0tю№Enї0ryмџOціс р5     IO€џ‚уА‹ХРњ[AщѓVBALOˆOšOъђр5.ќСO\@žcх_МРŸ jуBbAуљTџhisDўѓ0cume№§2   __ыё@ўfAр1 _S_ыёйfAњь№_qD_PR/OJћ0Cё@‰_Р›_.TA
SignalActionType        0
 _г_+3`
MSB     3
!.fAўі”!!ь№
ь№kAЊ3ь№ь№ь№Кь№/Bь№Кь№/Rь№Њь№ь№ь№ьѓU!ь№"ь№#ь№$ь№U%ь№&ь№'ь№(ь№U)ь№*ь№+ь№,3U.ь№/ь№0ь№1ь№Љ2365ь№6ь№7
LSB     0
ь№8ь№9/фoіo,>Pbt†˜АЊМЮр~№Šь№Ф.дыё.рqЫђ.kTкЅиЅT@zaˆь№ЖA"ОUМ_N`рWfA!
isFallingEdgeSensitive  False
!ъv!рqx$ЂфјF8ME;‰7…/ƒпП„AќŸ Ÿ2ŸDŸVŸМ7ŽaSL?ƒзSt–?…<\?ƒ-…N­`{­`ЊЈ‘2Б`A­’-Ї”0RЗšCЛžк™4Х`}=[Юa€жcы€‚l’8ыёba‚aZ‘HЛ†хGЖ]ZŸRЏК]dЏЏТ=‰пЎЮЏрЏщѓўЪјt”ААAtџtributeП VB_NaP п= "Thі@Doџcument"џ
isRisingEdgeSensitive   False
DrawAnalog      0
ŒBasџŒ0{0002џ1PA21-џ0Cџ$0046}џ
|GlobaџlаSpacџ’FalseџdCreatџablPreџdeclaџIdБTruП
BExpo~АџTemplaџteDerivџ’BustomizDЖa$ЭПпПЬ*АГA       ўPњБыфхG?*\GЅ˜ъ‘‡EFЗŸЩŸлŸэ’#Њы.­`#б`#…P:tР|SG}PAMю№_FILћ0SР•CPM‡РOЁŠЫMЊРC}RSPFё@ *“РHu@Rћ0DРrCЊвХ6бФEХ`.љ@LђР#q@іAuaUlю№BџРsѕ@c‰ТUo@ u@pаlвaї0iѓ0nї@эЊ•`ЫА‘9Э`.Я@ЯRЯdЧЁ8y`nСvЯˆЭVРSъРOПжLРB3HЕ`юЭ*б #ТЈ‘ ё@Uyаeю№Lѕ@b@]aB [“Рe@)vвсRPlPб.с1]тњИ?оъ‘3_мdпvп^ЩмбnСœз•WРNљ@OБр”СSЋY“РTћ0MПтtЃdP.смбTаbRy`OТбuї0oPt&зуљ-._.
BooleanEquation
№ћЪ‹SЬ<@—ЏLџ_Ќф|рП€M`TђOS­`1йаcБ`еaџРdџР4;№Œ”џUџџ-R.%f@‹… „(:L^p‚\ўўџЗЩлэџ#5GYk}ЁГХзщўя$FcnB1еџ•vF"Щ№xѕя`[A-R
NegTolerance    0
пџd‚`џVisioџVBAїт§0 Win16СН~C$32:!MacГВ=!џ6­#
Fџigure2Damjanъп`џstdole“`Я2А6Еt<яž        ! џџџ_EvaluВАПй“%jwг'№<•Ќ&ѓДQО@:ѕ3P(Јо Јb5b?оћ=Б€§Rџ0*      pџH‚odф!`p%н@x"@Щ№@џ
PosTolerance    0
=
UserSpecifiedSizeRatio  1
џ+xП     SЬ 8ёџJ<
VerilogCode
ћrƒ"e>хsбс@ѓ0.сrfџ%\*\G§{Ј020430л-;Г C!№ћ0ъ6}#2.§0šа#C:\WI~ЖрOWS\SYЦрEM\StdOгрiрї?  OOЎCД_EOJ$[-k`A>Є|[wPˆƒO•O(W3OФOЃ\3 dnOџO_k/‚a(ОOO_$Ё4k`N|џ|_РŽ_ _EЏФ_ж_ЉFleп2.TlbцрLEџ AutoРmaяtionЉ`"џt‚к_Ѕ‚F#•#ПG€Ъѓіа№€QЂёЊm€Sџn€YŽ2šяЂ€‚`H‚я1‚Ž`ёё‚џ
VHDLCode
,Q‚CиЅџ"‚+‚K0so…o—oЊE)ЩџЇєќжoЉFID="{Cџ81BE968-џ281E-11Dџ5-80A9-E8D506C1MАг0}@А“%=)/&йHqq
PROPS!
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CORGROUP        $$CLK_I_BufferRising
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CORGROUP        $$CLK_I_BufferFalling
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CORGROUP        $$CLK_I_BufferRisingFalling
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CORGROUP        $$CLK_I_BufferRising
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CORGROUP        $$CLK_I_BufferFalling
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CORGROUP        $$CLK_I_BufferRising
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Percent 100
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Percent 100
LibPath
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Percent 100
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!
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Percent 100
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Percent 100
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CORGROUP        $$CLK_I_BufferRising
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Percent 100
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Percent 100
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!
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Percent 100
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Percent 100
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!
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!
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Percent 100
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!
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Percent 100
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!
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CustDispString  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
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Percent 100
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Percent 100
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!
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CORGROUP        $$CLK_I_BufferRisingFalling
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!
!
CORGROUP        $$CLK_RISC_BufferRising
DIAGRAMTESTBENCHSETTINGS
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FilesBeforeDiagramModel
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FilesInsideDiagramModelDeclarationSection
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CORGROUP        $$CLK_RISC_BufferFalling
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Percent 100
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!
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CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
!
MACROS
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_I_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
CORGROUP        $$CLK_I_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_I_BufferRising
!
Percent 100
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CORGROUP        $$CLK_I_BufferRising
Percent 100
CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
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CORGROUP        $$CLK_I_BufferFalling
Percent 100
CORGROUP        $$CLK_I_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_I_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
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CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
CORGROUP        $$CLK_I_BufferRisingFalling
!
Percent 100
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CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_I_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
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CORGROUP        $$CLK_I_BufferFalling
Percent 100
CORGROUP        $$CLK_I_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_I_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
CORGROUP        $$CLK_I_BufferRisingFalling
!
Percent 100
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CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_I_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
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CORGROUP        $$CLK_I_BufferFalling
Percent 100
CORGROUP        $$CLK_I_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRising
!
Percent 100
!
CORGROUP        $$dwb_CLK_RISC_BufferRising
Percent 100
CORGROUP        $$CLK_RISC_BufferFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_RISC_BufferFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRisingFalling
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Percent 100
!
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRising
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferRising
Percent 100
CORGROUP        $$CLK_RISC_BufferFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_I_BufferRising
!
Percent 100
!
CORGROUP        $$dwb_CLK_RISC_BufferRising
Percent 100
CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_RISC_BufferFalling
Percent 100
CORGROUP        $$CLK_I_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRising
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferRising
Percent 100
CORGROUP        $$CLK_RISC_BufferFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_I_BufferRising
!
Percent 100
!
CORGROUP        $$dwb_CLK_RISC_BufferRising
Percent 100
CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_RISC_BufferFalling
Percent 100
CORGROUP        $$CLK_I_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRising
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferRising
Percent 100
CORGROUP        $$CLK_RISC_BufferFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_I_BufferRising
!
Percent 100
!
CORGROUP        $$dwb_CLK_RISC_BufferRising
Percent 100
CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_RISC_BufferFalling
Percent 100
CORGROUP        $$CLK_I_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRising
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferRising
Percent 100
CORGROUP        $$CLK_RISC_BufferFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_I_BufferRising
!
Percent 100
!
CORGROUP        $$dwb_CLK_RISC_BufferRising
Percent 100
CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_RISC_BufferFalling
Percent 100
CORGROUP        $$CLK_I_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRising
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferRising
Percent 100
CORGROUP        $$CLK_RISC_BufferFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_I_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
CORGROUP        $$CLK_I_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRising
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferRising
Percent 100
CORGROUP        $$CLK_RISC_BufferFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_I_BufferRising
!
Percent 100
!
CLOCK   CLK_RISC
PERIODE 2.5
CORGROUP        $$CLK_I_BufferFalling
DUTY    50
Percent 100
OFFSETE 0
!
INITIAL HIGH
MAXUNCERTRISE   0
CORGROUP        $$CLK_I_BufferRisingFalling
MAXUNCERTFALL   0
Percent 100
MINUNCERTRISE   0
!
MINUNCERTFALL   0
JRISEE  0
CORGROUP        $$CLK_RISC_BufferRising
JFALLE  0
Percent 100
GRID    0        1       0        2       0        16711680        0        0
!
ENDGRID -1
DIRECTION       internal
CORGROUP        $$CLK_RISC_BufferFalling
MASTERCLOCK     None
Percent 100
Clock   Unclocked
!
EdgeLevel       neg
Set     Not Used
CORGROUP        $$CLK_RISC_BufferRisingFalling
Clear   Not Used
Percent 100
ClockEnable     Not Used
!
ActiveLowSetClear       True
AsyncSetClear   True
CORGROUP        $$CLK_I_BufferRising
ActiveLowClockEnable    True
Percent 100
VhdlType        std_logic
!
VerilogType     wire
SystemCType     sc_logic
CORGROUP        $$CLK_I_BufferFalling
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Percent 100
StateEquation   Hex(Inc(0,2,5))
!
HighVoltageThreshold    5
LowVoltageThreshold     0
CORGROUP        $$CLK_I_BufferRisingFalling
MSB     0
Percent 100
LSB     0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
CORGROUP        $$CLK_RISC_BufferRising
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$CLK_RISC_BufferFalling
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
PROPS!
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
CLOCK   dwb_CLK_I
PERIODE 5
CORGROUP        $$CLK_I_BufferRising
DUTY    50
Percent 100
OFFSETE 0
!
INITIAL LOW
MAXUNCERTRISE   0
CORGROUP        $$CLK_I_BufferFalling
MAXUNCERTFALL   0
Percent 100
MINUNCERTRISE   0
!
MINUNCERTFALL   0
JRISEE  0
CORGROUP        $$CLK_I_BufferRisingFalling
JFALLE  0
Percent 100
GRID    1       1       1       2       2       16711680        0        0
!
ENDGRID -1
DIRECTION       input
CORGROUP        $$CLK_RISC_BufferRising
MASTERCLOCK     None
Percent 100
Clock   Unclocked
!
EdgeLevel       neg
Set     Not Used
CORGROUP        $$CLK_RISC_BufferFalling
Clear   Not Used
Percent 100
ClockEnable     Not Used
!
ActiveLowSetClear       True
AsyncSetClear   True
CORGROUP        $$CLK_RISC_BufferRisingFalling
ActiveLowClockEnable    True
Percent 100
VhdlType        std_logic
!
VerilogType     wire
SystemCType     sc_logic
CORGROUP        $$CLK_I_BufferRising
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Percent 100
StateEquation   Hex(Inc(0,2,5))
!
HighVoltageThreshold    5
LowVoltageThreshold     0
CORGROUP        $$CLK_I_BufferFalling
MSB     0
Percent 100
LSB     0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   True
CORGROUP        $$CLK_I_BufferRisingFalling
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$CLK_RISC_BufferRising
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
PROPS!
CORGROUP        $$CLK_RISC_BufferFalling
!
Percent 100
!
SIGNAL  dwb_ADR_O
DIRECTION       output
CORGROUP        $$CLK_RISC_BufferRisingFalling
RADIX   hex
Percent 100
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock
CORGROUP        $$CLK_I_BufferRising
EdgeLevel       neg
Percent 100
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
CORGROUP        $$CLK_I_BufferFalling
ActiveLowSetClear       True
Percent 100
AsyncSetClear   True
!
ActiveLowClockEnable    True
VhdlType        std_logic
CORGROUP        $$CLK_I_BufferRisingFalling
VerilogType     wire
Percent 100
SystemCType     sc_logic
!
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
CORGROUP        $$CLK_RISC_BufferRising
HighVoltageThreshold    5
Percent 100
LowVoltageThreshold     0
!
LSB     0
MSB     31
CORGROUP        $$CLK_RISC_BufferFalling
SignalActionType        0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   True
DrawAnalog      0
CORGROUP        $$CLK_RISC_BufferRisingFalling
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$CLK_I_BufferRising
VerilogCode
Percent 100
VHDLCode
!
VhdlMapping     DefaultVhdlMapping
PROPS!
CORGROUP        $$CLK_I_BufferFalling
E0      V       -1      -1              1       0        DR      0
Percent 100
E1      X       3125    3125            1       0        DR      0
!
E2      V       3126    3126    A0      1       0        DR      0
E3      X       3750    3750            1       0        DR      0
CORGROUP        $$CLK_I_BufferRisingFalling
E4      V       13125   13125     A0    1       0        DR      0
Percent 100
E5      X       13625   13625           1       0        DR      0
!
E6      V       23125   23125     A4    1       0        DR      0
E7      X       23625   23625           1       0        DR      0
CORGROUP        $$dwb_CLK_RISC_BufferRising
E8      V       33125   33125     A8    1       0        DR      0
Percent 100
E9      X       33625   33625           1       0        DR      0
!
E10     V       43125   43125     A12   1       0        DR      0
E11     X       43750   43750           1       0        DR      0
CORGROUP        $$dwb_CLK_RISC_BufferFalling
!
Percent 100
!
SIGNAL  dwb_DAT_I
DIRECTION       input
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
RADIX   hex
Percent 100
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock
CORGROUP        $$dwb_CLK_I_BufferRising
EdgeLevel       neg
Percent 100
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
CORGROUP        $$dwb_CLK_I_BufferFalling
ActiveLowSetClear       True
Percent 100
AsyncSetClear   True
!
ActiveLowClockEnable    True
VhdlType        std_logic
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
VerilogType     wire
Percent 100
SystemCType     sc_logic
!
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
CORGROUP        $$dwb_CLK_RISC_BufferRising
HighVoltageThreshold    5
Percent 100
LowVoltageThreshold     0
!
LSB     0
MSB     31
CORGROUP        $$dwb_CLK_RISC_BufferFalling
SignalActionType        0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   False
DrawAnalog      0
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$dwb_CLK_I_BufferRising
VerilogCode
Percent 100
VHDLCode
!
VhdlMapping     DefaultVhdlMapping
PROPS!
CORGROUP        $$dwb_CLK_I_BufferFalling
E0      X       11250   11250           1       0        DR      0
Percent 100
E1      V       13125   13125   D0      1       0        DR      0
!
E2      X       21250   21250           1       0        DR      0
E3      V       23125   23125   D4      1       0        DR      0
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
E4      X       31250   31250           1       0        DR      0
Percent 100
E5      V       33125   33125   D8      1       0        DR      0
!
E6      X       41250   41250           1       0        DR      0
E7      V       43125   43125   D12     1       0        DR      0
CORGROUP        $$dwb_CLK_RISC_BufferRising
E8      X       43750   43750           1       0        DR      0
Percent 100
!
!
SIGNAL  dwb_DAT_O
CORGROUP        $$dwb_CLK_RISC_BufferFalling
DIRECTION       output
Percent 100
RADIX   hex
!
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
Clock   Unclocked
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$dwb_CLK_I_BufferRising
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$dwb_CLK_I_BufferFalling
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
LSB     0
CORGROUP        $$dwb_CLK_RISC_BufferRising
MSB     31
Percent 100
SignalActionType        0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
CORGROUP        $$dwb_CLK_RISC_BufferFalling
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
PROPS!
CORGROUP        $$dwb_CLK_I_BufferRising
E0      X       43750   43750           1       0        DR      0
Percent 100
!
!
SIGNAL  dwb_WE_O
CORGROUP        $$dwb_CLK_I_BufferFalling
DIRECTION       output
Percent 100
RADIX   hex
!
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
Clock   Unclocked
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$dwb_CLK_RISC_BufferRising
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$dwb_CLK_RISC_BufferFalling
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
SignalActionType        0
CORGROUP        $$dwb_CLK_I_BufferRising
MSB     0
Percent 100
LSB     0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
CORGROUP        $$dwb_CLK_I_BufferFalling
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
PROPS!
CORGROUP        $$CLK_RISC_BufferRising
E0      X       3125    3125            1       0        DR      0
Percent 100
E1      1       3126    3126            1       0        DR      0
!
E2      0        13125   13125           1       0        DR      0
E3      X       13625   13625           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferFalling
E4      0        23125   23125           1       0        DR      0
Percent 100
E5      X       23625   23625           1       0        DR      0
!
E6      0        33125   33125           1       0        DR      0
E7      X       33625   33625           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRisingFalling
E8      0        43125   43125           1       0        DR      0
Percent 100
E9      X       43625   43625           1       0        DR      0
!
!
CORGROUP        $$iwb_CLK_I_BufferRising
SIGNAL  dwb_SEL_O
Percent 100
DIRECTION       output
!
RADIX   hex
GRID    0        1       0        1       0        16711680        0        0
CORGROUP        $$iwb_CLK_I_BufferFalling
ENDGRID -1
Percent 100
Clock   Unclocked
!
EdgeLevel       neg
Set     Not Used
CORGROUP        $$iwb_CLK_I_BufferRisingFalling
Clear   Not Used
Percent 100
ClockEnable     Not Used
!
ActiveLowSetClear       True
AsyncSetClear   True
CLOCK   CLK_RISC
ActiveLowClockEnable    True
PERIODE 2.5
VhdlType        std_logic
DUTY    50
VerilogType     wire
OFFSETE 0
SystemCType     sc_logic
INITIAL HIGH
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
MAXUNCERTRISE   0
StateEquation   Hex(Inc(0,2,5))
MAXUNCERTFALL   0
HighVoltageThreshold    5
MINUNCERTRISE   0
LowVoltageThreshold     0
MINUNCERTFALL   0
LSB     0
JRISEE  0
MSB     3
JFALLE  0
SignalActionType        0
GRID    0        1       0        2       0        16711680        0        0
isFallingEdgeSensitive  False
ENDGRID -1
isRisingEdgeSensitive   False
DIRECTION       internal
DrawAnalog      0
MASTERCLOCK     None
BooleanEquation
Clock   Unclocked
NegTolerance    0
EdgeLevel       neg
PosTolerance    0
Set     Not Used
UserSpecifiedSizeRatio  1
Clear   Not Used
VerilogCode
ClockEnable     Not Used
VHDLCode
ActiveLowSetClear       True
PROPS!
AsyncSetClear   True
E0      V       0        0           Valid        1       0        DR      0
ActiveLowClockEnable    True
E1      X       3750    3750            1       0        DR      0
VhdlType        std_logic
E2      V       13125   13125       Valid       1       0        DR      0
VerilogType     wire
E3      X       13625   13625           1       0        DR      0
SystemCType     sc_logic
E4      V       23125   23125     Valid 1       0        DR      0
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
E5      X       23625   23625           1       0        DR      0
StateEquation   Hex(Inc(0,2,5))
E6      V       33125   33125     Valid 1       0        DR      0
HighVoltageThreshold    5
E7      X       33625   33625           1       0        DR      0
LowVoltageThreshold     0
E8      V       43125   43125     Valid 1       0        DR      0
MSB     0
E9      X       43750   43750           1       0        DR      0
LSB     0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
SIGNAL  dwb_STB_O
DrawAnalog      0
DIRECTION       output
BooleanEquation
RADIX   hex
NegTolerance    0
GRID    0        1       0        1       0        16711680        0        0
PosTolerance    0
ENDGRID -1
UserSpecifiedSizeRatio  1
Clock   Unclocked
VerilogCode
EdgeLevel       neg
VHDLCode
Set     Not Used
PROPS!
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CLOCK   iwb_CLK_I
AsyncSetClear   True
PERIODE 5
ActiveLowClockEnable    True
DUTY    50
VhdlType        std_logic
OFFSETE 0
VerilogType     wire
INITIAL LOW
SystemCType     sc_logic
MAXUNCERTRISE   0
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
MAXUNCERTFALL   0
StateEquation   Hex(Inc(0,2,5))
MINUNCERTRISE   0
HighVoltageThreshold    5
MINUNCERTFALL   0
LowVoltageThreshold     0
JRISEE  0
SignalActionType        0
JFALLE  0
MSB     0
GRID    1       1       1       2       2       16711680        0        0
LSB     0
ENDGRID -1
isFallingEdgeSensitive  False
DIRECTION       input
isRisingEdgeSensitive   False
MASTERCLOCK     None
DrawAnalog      0
Clock   Unclocked
BooleanEquation
EdgeLevel       neg
NegTolerance    0
Set     Not Used
PosTolerance    0
Clear   Not Used
UserSpecifiedSizeRatio  1
ClockEnable     Not Used
VerilogCode
ActiveLowSetClear       True
VHDLCode
AsyncSetClear   True
PROPS!
ActiveLowClockEnable    True
E0      0        3750    3750            1       0        DR      0
VhdlType        std_logic
E1      1       13125   13125           1       0        DR      0
VerilogType     wire
E2      0        13625   13625           1       0        DR      0
SystemCType     sc_logic
E3      1       23125   23125           1       0        DR      0
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
E4      0        23625   23625           1       0        DR      0
StateEquation   Hex(Inc(0,2,5))
E5      1       33125   33125           1       0        DR      0
HighVoltageThreshold    5
E6      0        33625   33625           1       0        DR      0
LowVoltageThreshold     0
E7      1       43125   43125           1       0        DR      0
MSB     0
E8      X       43750   43750           1       0        DR      0
LSB     0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   True
SIGNAL  dwb_ACK_I
DrawAnalog      0
DIRECTION       input
BooleanEquation
RADIX   hex
NegTolerance    0
GRID    0        1       0        1       0        16711680        0        0
PosTolerance    0
ENDGRID -1
UserSpecifiedSizeRatio  1
Clock   Unclocked
VerilogCode
EdgeLevel       neg
VHDLCode
Set     Not Used
PROPS!
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
SIGNAL  iwb_ADR_O
AsyncSetClear   True
DIRECTION       output
ActiveLowClockEnable    True
RADIX   hex
VhdlType        std_logic
GRID    0        1       0        1       0        16711680        0        0
VerilogType     wire
ENDGRID -1
SystemCType     sc_logic
Clock
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
EdgeLevel       neg
StateEquation   Hex(Inc(0,2,5))
Set     Not Used
HighVoltageThreshold    5
Clear   Not Used
LowVoltageThreshold     0
ClockEnable     Not Used
SignalActionType        0
ActiveLowSetClear       True
MSB     0
AsyncSetClear   True
LSB     0
ActiveLowClockEnable    True
isFallingEdgeSensitive  False
VhdlType        std_logic
isRisingEdgeSensitive   False
VerilogType     wire
DrawAnalog      0
SystemCType     sc_logic
BooleanEquation
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
NegTolerance    0
StateEquation   Hex(Inc(0,2,5))
PosTolerance    0
HighVoltageThreshold    5
UserSpecifiedSizeRatio  1
LowVoltageThreshold     0
VerilogCode
LSB     0
VHDLCode
MSB     31
PROPS!
SignalActionType        0
E0      0        11250   11250           1       0        DR      0
isFallingEdgeSensitive  False
E1      1       13125   13125           1       0        DR      0
isRisingEdgeSensitive   True
E2      0        21250   21250           1       0        DR      0
DrawAnalog      0
E3      1       23125   23125           1       0        DR      0
BooleanEquation
E4      0        31250   31250           1       0        DR      0
NegTolerance    0
E5      1       33125   33125           1       0        DR      0
PosTolerance    0
E6      0        41250   41250           1       0        DR      0
UserSpecifiedSizeRatio  1
E7      1       43125   43125           1       0        DR      0
VerilogCode
E8      X       43750   43750           1       0        DR      0
VHDLCode
!
VhdlMapping     DefaultVhdlMapping
PROPS!
SIGNAL  dwb_CYC_O
E0      V       -1      -1              1       0        DR      0
DIRECTION       output
E1      X       3125    3125            1       0        DR      0
RADIX   hex
E2      V       3126    3126    A0      1       0        DR      0
GRID    0        1       0        1       0        16711680        0        0
E3      X       3750    3750            1       0        DR      0
ENDGRID -1
E4      V       13125   13125     A0    1       0        DR      0
Clock   Unclocked
E5      X       13625   13625           1       0        DR      0
EdgeLevel       neg
E6      V       23125   23125     A4    1       0        DR      0
Set     Not Used
E7      X       23625   23625           1       0        DR      0
Clear   Not Used
E8      V       33125   33125     A8    1       0        DR      0
ClockEnable     Not Used
E9      X       33625   33625           1       0        DR      0
ActiveLowSetClear       True
E10     V       43125   43125     A12   1       0        DR      0
AsyncSetClear   True
E11     X       43750   43750           1       0        DR      0
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
SIGNAL  iwb_DAT_I
SystemCType     sc_logic
DIRECTION       input
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
RADIX   hex
StateEquation   Hex(Inc(0,2,5))
GRID    0        1       0        1       0        16711680        0        0
HighVoltageThreshold    5
ENDGRID -1
LowVoltageThreshold     0
Clock
SignalActionType        0
EdgeLevel       neg
MSB     0
Set     Not Used
LSB     0
Clear   Not Used
isFallingEdgeSensitive  False
ClockEnable     Not Used
isRisingEdgeSensitive   False
ActiveLowSetClear       True
DrawAnalog      0
AsyncSetClear   True
BooleanEquation
ActiveLowClockEnable    True
NegTolerance    0
VhdlType        std_logic
PosTolerance    0
VerilogType     wire
UserSpecifiedSizeRatio  1
SystemCType     sc_logic
VerilogCode
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
VHDLCode
StateEquation   Hex(Inc(0,2,5))
PROPS!
HighVoltageThreshold    5
E0      0        3125    3125            1       0        DR      0
LowVoltageThreshold     0
E1      1       43125   43125           1       0        DR      0
LSB     0
E2      0        43750   43750           1       0        DR      0
MSB     31
!
SignalActionType        0
isFallingEdgeSensitive  False
SIGNAL  dwb_ERR_I
isRisingEdgeSensitive   False
DIRECTION       input
DrawAnalog      0
RADIX   hex
BooleanEquation
GRID    0        1       0        1       0        16711680        0        0
NegTolerance    0
ENDGRID -1
PosTolerance    0
Clock   Unclocked
UserSpecifiedSizeRatio  1
EdgeLevel       neg
VerilogCode
Set     Not Used
VHDLCode
Clear   Not Used
VhdlMapping     DefaultVhdlMapping
ClockEnable     Not Used
PROPS!
ActiveLowSetClear       True
E0      X       11250   11250           1       0        DR      0
AsyncSetClear   True
E1      V       13125   13125   D0      1       0        DR      0
ActiveLowClockEnable    True
E2      X       21250   21250           1       0        DR      0
VhdlType        std_logic
E3      V       23125   23125   D4      1       0        DR      0
VerilogType     wire
E4      X       31250   31250           1       0        DR      0
SystemCType     sc_logic
E5      V       33125   33125   D8      1       0        DR      0
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
E6      X       41250   41250           1       0        DR      0
StateEquation   Hex(Inc(0,2,5))
E7      V       43125   43125   D12     1       0        DR      0
HighVoltageThreshold    5
E8      X       43750   43750           1       0        DR      0
LowVoltageThreshold     0
!
SignalActionType        0
MSB     0
SIGNAL  iwb_DAT_O
LSB     0
DIRECTION       output
isFallingEdgeSensitive  False
RADIX   hex
isRisingEdgeSensitive   False
GRID    0        1       0        1       0        16711680        0        0
DrawAnalog      0
ENDGRID -1
BooleanEquation
Clock   Unclocked
NegTolerance    0
EdgeLevel       neg
PosTolerance    0
Set     Not Used
UserSpecifiedSizeRatio  1
Clear   Not Used
VerilogCode
ClockEnable     Not Used
VHDLCode
ActiveLowSetClear       True
PROPS!
AsyncSetClear   True
E0      0        43125   43125           1       0        DR      0
ActiveLowClockEnable    True
E1      X       43750   43750           1       0        DR      0
VhdlType        std_logic
!
VerilogType     wire
SystemCType     sc_logic
SIGNAL  dwb_RTY_I
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
DIRECTION       input
StateEquation   Hex(Inc(0,2,5))
RADIX   hex
HighVoltageThreshold    5
GRID    0        1       0        1       0        16711680        0        0
LowVoltageThreshold     0
ENDGRID -1
LSB     0
Clock   Unclocked
MSB     31
EdgeLevel       neg
SignalActionType        0
Set     Not Used
isFallingEdgeSensitive  False
Clear   Not Used
isRisingEdgeSensitive   False
ClockEnable     Not Used
DrawAnalog      0
ActiveLowSetClear       True
BooleanEquation
AsyncSetClear   True
NegTolerance    0
ActiveLowClockEnable    True
PosTolerance    0
VhdlType        std_logic
UserSpecifiedSizeRatio  1
VerilogType     wire
VerilogCode
SystemCType     sc_logic
VHDLCode
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
PROPS!
StateEquation   Hex(Inc(0,2,5))
E0      X       43750   43750           1       0        DR      0
HighVoltageThreshold    5
!
LowVoltageThreshold     0
SignalActionType        0
SIGNAL  iwb_WE_O
MSB     0
DIRECTION       output
LSB     0
RADIX   hex
isFallingEdgeSensitive  False
GRID    0        1       0        1       0        16711680        0        0
isRisingEdgeSensitive   False
ENDGRID -1
DrawAnalog      0
Clock   Unclocked
BooleanEquation
EdgeLevel       neg
NegTolerance    0
Set     Not Used
PosTolerance    0
Clear   Not Used
UserSpecifiedSizeRatio  1
ClockEnable     Not Used
VerilogCode
ActiveLowSetClear       True
VHDLCode
AsyncSetClear   True
PROPS!
ActiveLowClockEnable    True
E0      0        43125   43125           1       0        DR      0
VhdlType        std_logic
E1      X       43750   43750           1       0        DR      0
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
MARKER  MARK1
StateEquation   Hex(Inc(0,2,5))
ATTACH  dwb_SEL_O       NULL    S6
HighVoltageThreshold    5
TIME    17500.000000
LowVoltageThreshold     0
RELATIVETIME    0.000000
SignalActionType        0
DISPLAYAS       5
MSB     0
MARKERTYPE      Timebreak(Curved)
LSB     0
WHILERETURN
isFallingEdgeSensitive  False
REPEATNUMBER
isRisingEdgeSensitive   False
SNAPTO  0
DrawAnalog      0
COMPRESSTIME    0.000000
BooleanEquation
COMMENT
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
MARKER  MARK2
VerilogCode
ATTACH  dwb_STB_O       NULL    S7
VHDLCode
TIME    27500.000000
PROPS!
RELATIVETIME    0.000000
E0      X       3125    3125            1       0        DR      0
DISPLAYAS       5
E1      1       3126    3126            1       0        DR      0
MARKERTYPE      Timebreak(Curved)
E2      0        13125   13125           1       0        DR      0
WHILERETURN
E3      X       13625   13625           1       0        DR      0
REPEATNUMBER
E4      0        23125   23125           1       0        DR      0
SNAPTO  0
E5      X       23625   23625           1       0        DR      0
COMPRESSTIME    0.000000
E6      0        33125   33125           1       0        DR      0
COMMENT
E7      X       33625   33625           1       0        DR      0
!
E8      0        43125   43125           1       0        DR      0
E9      X       43625   43625           1       0        DR      0
MARKER  MARK3
!
ATTACH  dwb_STB_O       NULL    S7
TIME    37500.000000
SIGNAL  iwb_SEL_O
RELATIVETIME    0.000000
DIRECTION       output
DISPLAYAS       5
RADIX   hex
MARKERTYPE      Timebreak(Curved)
GRID    0        1       0        1       0        16711680        0        0
WHILERETURN
ENDGRID -1
REPEATNUMBER
Clock   Unclocked
SNAPTO  0
EdgeLevel       neg
COMPRESSTIME    0.000000
Set     Not Used
COMMENT
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
MARKER  MARK0
AsyncSetClear   True
ATTACH  dwb_CLK_I       NULL    S1
ActiveLowClockEnable    True
TIME    7494.285714
VhdlType        std_logic
RELATIVETIME    0.000000
VerilogType     wire
DISPLAYAS       5
SystemCType     sc_logic
MARKERTYPE      Timebreak(Curved)
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
WHILERETURN
StateEquation   Hex(Inc(0,2,5))
REPEATNUMBER
HighVoltageThreshold    5
SNAPTO  0
LowVoltageThreshold     0
COMPRESSTIME    0.000000
LSB     0
COMMENT
MSB     3
!
SignalActionType        0
isFallingEdgeSensitive  False
ы1     h&&" WMFCC 8xZjы1 EMF8~XРьЫVISIODrawing
isRisingEdgeSensitive   False
 \l&%'мчр
DrawAnalog      0
%V0ZjjZjZj%€(%€(%€RLщџџџМ Arial§џџџ‚ƒ„…†‡ˆ‰Š‹ŒŽ‘’“”•–—˜™š›œžŸ ЁЂЃЄЅІўџџџЈЉЊЋЌ­ЎЏАБВГДЕЖЗИЙКЛМНОПРСТУФХЦЧШўџџџЪчЬЭЮЯабвгдежзийклмнопрстуфхцўџџџ%щъыьэюя№ёђѓєѕіїјљњћќўџџџўџdxі        фі ф№П№П№П%Tœиƒ8Ћ*ЉAЋ*ЉAи
LhOpenRISC 1200




&%'ќBр
BooleanEquation
%V0ъrrTъTrTrrъrъT%€(%€(%€RLщџџџМ ArialXІЇ<№„…КЎ(%Txћъ`Ћ*ЉAЋ*ЉAћъL\CPU/DSP&%'ќBр
NegTolerance    0
%V0—Х5—55Х—Х—%€(%€(%€RLщџџџМ Arial%TpЙміЋ*ЉAЋ*ЉAЙмLXDCache


T`ЮјќЋ*ЉAЋ*ЉAЮјLT8KB
&%'ќBр
PosTolerance    0
%V0—5T—T5T5——T%€(%€(%€RLщџџџМ Arialџџџџ№№CACA! €CA €CA0!@€CACA%TdТ=  WЋ*ЉAЋ*ЉAТ=LTDMMU&%'ќBр
UserSpecifiedSizeRatio  1
%V0'ХT'TХTХ''T%€(%€(%€RLщџџџМ Arialа?fџџџџџџџџџџџџАђb`АCAшfc`;@AA„a`Ађb`АCAјfc`<PAАђb`АCAgc`=@AA„a`Ађb`АCAgc`>@A„a`Ађb`АCAАec`RAA lŠCAИ2A%T`e=‰WЋ*ЉAЋ*ЉAe=LTPIC&%'ќBр
VerilogCode
%V0'ХХ'ХХХ'Х'%€(%€(%€RLщџџџМ ArialАђb`„CAшfc`;@AA„a`Ађb`„CAјfc`<PAb`„CAgc`=@AA„a`Ађb`„CAgc`>@AA„a`Ађb`„CAАec`RAAPр2Aр2A!№‚CA CACA0!ƒCA@ˆCAd‡CAP!CAˆCA%Tˆ5ъЗЋ*ЉAЋ*ЉA5ъ
VHDLCode
L`TICK TIMER&%'ќBр
PROPS!
%V0'rХЎ'ЎХЎХr'r'Ў%€(%€(%€RLщџџџМ ArialАђb`P†CAАec`RAAрApїb`0їb`A !€CA™CA€CA      РˆCA!@и2A™CATŠCA !CA@™CACA&CA€! ˆCA ˆCA !@ˆCA@ˆCA%TlL—ŸБЋ*ЉAЋ*ЉAL—LXDEBUG&%'     ќBр
E0      V       0        0           Valid        1       0        DR      0
%      V0' Х\'\Х\Х ' '\%€(%€( %
€(%€RLщџџџМ Arial№?№?№П№Пb`РˆCAиfc`CAA№CAœ€CA$pCAЄCAd‹CA1€№CAИ2AdŒCA !рvCAрvCAФŒCA@! vCA0ƒCAˆCA%А‹CA`!‹CA‹CA%TpAEЉ_Ћ*ЉAЋ*ЉAAELXPOWERM& %     'ќBр
E1      X       3750    3750            1       0        DR      0
%V0—r5Ў—Ў5Ў5r—r—Ў%€(      %€(RLщџџџМ Arial
E2      V       13125   13125       Valid       1       0        DR      0
E3      X       13625   13625           1       0        DR      0
Ађb`А‹CAАec`RAA@и2Aи2AЄŽ !РŠCAрvCACA@! vCA0ƒCAˆCA$№CA`!@CA@CA€!`CA`CA !€CA€CAРФіb`аѕb`%(%€RLщџџџМ ArialfџџџџџџџџџџџџАђb`№CAшfc`;@AA„a`Ађb`№CAјfc`<PAАђb`№CAgc`=@AA„a`Ађb`№CAgc`>@A„a`Ађb`№CAАec`RAAА! CA CACA%TpП‰
E4      V       23125   23125     Valid 1       0        DR      0
ЃЋ*ЉAЋ*ЉAП‰LXICache


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&     %     '
E5      X       23625   23625           1       0        DR      0
ќBр
E6      V       33125   33125     Valid 1       0        DR      0
%
E7      X       33625   33625           1       0        DR      0
V0— 5\—\5\5 — —\%€( %€(
E8      V       43125   43125     Valid 1       0        DR      0
RL
E9      X       43750   43750           1       0        DR      0
щџџџМ ArialџџџџџџџџvМ'       hx@@Р@ў ш@@  @ў(x@@а?ўx(LЬШРџџџџџџ@v”%        Р%
!
(%€RLщџџџМ ArialPX0X@
ќ"   @ќ$       @XXbbb@Р?@Р?@Р?@Р?a@а?@а@и?@и?aabbх?%TdШE_Ћ*ЉAЋ*ЉAШELTIMMU&	%	W$oš“—r%€(	&	&&WMFC8%	%€W$oрšц—уrу%€(	&	%	%€W$o3š9—6r6%€(	&	%	%€W$Z;šA—>]>%€( &	%	%€W$Z;`u]r]>%€( &	%	%€W$Т3э9ъ6Х6%€(	&	%	%€W$Т;A>Х>%€( &	%	%€W$ТрэцъуХу%€(	&	%	%€W$Тэ“ъХ%€(	&	%	%€W$ў;ur>%€( & %     'џџџ%V05 ZЎ5ЎZЎZ 5 5Ў%€(     %
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SIGNAL  iwb_STB_O
ьє@єѕ@
DIRECTION       output
Lі@ќTї@
RADIX   hex
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GRID    0        1       0        1       0        16711680        0        0
Ьќ@ќў@
ENDGRID -1
   @ќь       @
Clock   Unclocked
t   @ќ|       %TX<cQrЋ*ЉAЋ*ЉA<cLPWB
     TTFsI‚Ћ*ЉAЋ*ЉAFsLPIќ&%%V05ХZT5TZTZХ5Х5T%€(%
€(RLѓџџџМ Arialbbb@?@Р?@Р?@Р?a@а?@а?@и?@и?aabbbb sUUUUUх? sUUUUUх?b%(%€%TX<QЋ*ЉAЋ*ЉA<LPWB
     TTCK'Ћ*ЉAЋ*ЉACLPD     &%%V0r'ЎЎ'Ў'rrЎ%€(%
€(RLѓџџџМ Arial%(RLѓџџџМ Arial
       
EdgeLevel       neg
Set     Not Used
Clear   Not Used
ClockEnable     Not Used
ActiveLowSetClear       True

AsyncSetClear   True
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ActiveLowClockEnable    True
%€%TXŒ›Ћ*ЉAЋ*ЉAŒLPDB      T`
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VhdlType        std_logic
%
VerilogType     wire
%V0'TT'T'T%€(
SystemCType     sc_logic
%
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TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
2AЋ*ЉAЋ*ЉA
StateEquation   Hex(Inc(0,2,5))
2LTINTUU     T`
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BLTI/F&
HighVoltageThreshold    5
%
LowVoltageThreshold     0
%V0 '\\'\'  \%€(
SignalActionType        0
%
€(%€RLѓџџџМ ArialPџџџџџџџџ@œї р@@Р@ў№@@@@ўш№8ю?@џџџџџџџџџџ@@џџџџџџџџџџ%TX:IЋ*ЉAЋ*ЉA:LPPM     T`
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JLTI/F&
MSB     0
%
LSB     0
W$уYщuцrц\%€(
isFallingEdgeSensitive  False
&
isRisingEdgeSensitive   False
%
DrawAnalog      0
%€W$уўщцц%€(
BooleanEquation
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NegTolerance    0
%
PosTolerance    0
%V0І&І&&ІІ%€(
UserSpecifiedSizeRatio  1
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VerilogCode
L`System I/F     k\њ-ќмчр
VHDLCode
-$jZjZjњџџџ-№ќ-№.-ћМ Ariald??????П-2
PROPS!
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E0      0        3750    3750            1       0        DR      0
-$ъTrTrrъrъT-№-№-ћМ Arial-2
E1      1       13125   13125           1       0        DR      0
ъћCPU/DSPњ-ќќBр
E2      0        13625   13625           1       0        DR      0
-$—55Х—Х—-№-№-ћМ Arial-2
E3      1       23125   23125           1       0        DR      0
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E4      0        23625   23625           1       0        DR      0
јЮ8KB
њ-ќќBр
E5      1       33125   33125           1       0        DR      0
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2
E6      0        33625   33625           1       0        DR      0
=ТDMMUњ-ќќBр
E7      1       43125   43125           1       0        DR      0
-$'TХTХ''T-№-№-ћМ Arial-2
E8      X       43750   43750           1       0        DR      0
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SIGNAL  iwb_ACK_I
TICK TIMERњ-ќќBр
DIRECTION       input
-  $'ЎХЎХr'r'Ў-№-№     -ћМ Arial??????Œ??A????-2
RADIX   hex
—LDEBUGњ-  ќќBр
GRID    0        1       0        1       0        16711680        0        0
-
ENDGRID -1
$'\Х\Х ' '\-№     -№
Clock   Unclocked
ћ       М"SystemЮќєcФјПЯ -   №-ћМ Arial????-2
EdgeLevel       neg
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Set     Not Used
ќќBр
Clear   Not Used
-$—Ў5Ў5r—r—Ў-№
ClockEnable     Not Used
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ActiveLowSetClear       True
AsyncSetClear   True
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ActiveLowClockEnable    True
№-ћМ Arial-2
VhdlType        std_logic
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VerilogType     wire
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SystemCType     sc_logic
-$—\5\5 — —\-№-№ћМ Arial????-№-ћМ Arial??0?@
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
?c@ќ?c-
2
StateEquation   Hex(Inc(0,2,5))
EШIMMUњ-%—r-№њ--%—уrу-№њ--%—6r6-№њ--%—>]>-№њ--%]r]>-№њ--%ъ6Х6-№њ--%>Х>-№њ--%ъуХу-№њ--%ъХ-№њ--%r>-№њ-ќџџџ-
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HighVoltageThreshold    5
?C@-
LowVoltageThreshold     0
2
SignalActionType        0
c<WB
           2
MSB     0
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LSB     0
2
isFallingEdgeSensitive  False
<WB
           2
isRisingEdgeSensitive   False
CDК      њ--
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М Arial-№ћ
М Arial
      -№
DrawAnalog      0
- №--
BooleanEquation
2
NegTolerance    0
ŒDB             2
PosTolerance    0
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М Arial-2
UserSpecifiedSizeRatio  1
2
VerilogCode
INT     2
VHDLCode
B
I/Fњ--
$\'\'  \-№-    №-ћ
М ArialP?????-
PROPS!
2
E0      0        11250   11250           1       0        DR      0
:PM      2
E1      1       13125   13125           1       0        DR      0
J
I/Fњ-%цrц\-№њ--%цц-№њ--
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E2      0        21250   21250           1       0        DR      0
Х
E3      1       23125   23125           1       0        DR      0
System I/F   Visio (TM) Drawing
E4      0        31250   31250           1       0        DR      0
ГB„THї?AtRэxъёщђџџџƒџіђџѓћ№јё‰€ъё€ €џРРРцццџЭЭЭГГГяššš!€fџffMMM3џ33яџяяњњњ?мчќBa$ы№мџ
E5      1       33125   33125           1       0        DR      0
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E6      0        41250   41250           1       0        DR      0
Uы№џђ№,ы№8шѓ@њєсњіёъёуј§ы№Tdџ Arialъ@чєNПWingdzsЊ@чєN@tMџonotype ЏSort+чє
њNtSymbol5Tы№?шѓа?ђџкъё шѓY@-1ы№џђ№ы№іёїїTўјJчєы№Dы№T1шѓђёEWPђёрћ-ъёhчєы№НTы№Tы№<апќŒŒцѕ‘U*ы№ы№ы№Uы№       ы№
E7      1       43125   43125           1       0        DR      0
ы№ы№Uы№
ы№ы№“уј=/РUКпПbў
њbўщ…Иъё‰0zПЎGсz„?Ж@цѕП8‘HШ2!kWbU%Ѕ†МъёUВ
E8      X       43750   43750           1       0        DR      0
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‚+ŸЎ‡РъёйPы№L/^&œ9^$р? { ђ№яЁAшk^&Ž™,"™,™'%/v&ŽQ&Ц‚      
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1 yрЙ
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ЊJ1ЄШъёэ2?ё§k9лaUўBBHEHEHEUHEHEHEH@ ?В>з?щ:`2BBЊHEHEHEHEЊHEHEHEH@„$Ьъё%O9ЃаъёF7AOY@;
ЬA*sVsVЬAЇдgЄLTkYЗиъёї 1 WЭ_Wп_ќ_њ !`Г#•ku4l•b”6Pu`kђWŽ 4l
4lЅ•НмъёБ%Y№?ˆˆ:?-\
*Ѓ#!ю+|tKf*2|2|2|2wŠG)ОръёQUѓoˆІTMeEжttAПфъёв%_8BOTOfOxOŠOВ?Ф?ЌOш?њ7   РшъёмЛњuЛW+Р?ыаќŽиžђˆsU4‘х2–
SIGNAL  iwb_CYC_O
TŸ*<N`r„–HЂД„k!–ŽЌ)§†Ž0Ќ–ŽеPЌЌЌ Є3•ŽЇ
1’ьъёїмЏюЏрПП$П6Пуќ
nР[ЕiИРЛіё”|Г        фх”ујМЫЏi'04’UХP§iW?i?{4‚Lz№y‘2ї#ЩЖz“Њx•       x•
DIRECTION       output
x•x•x
RADIX   hex
Ѓ0–jМvПˆПŠуј•ујШВЗ^/ЫЦ!M3оТѓПjЦjЦ6DˆŒ/ž/А/ў$Q0pоФ?MdjЧ^cjЧŒ4ТBЬAk[Ж~ЯЯхіˆуј$YkU1%Л1ўпт@УэFЛе„-(‘ kp
йЛ   ѓ       .$–5-Bi`яЗBб#ошяЗ9)›F/Pџтљv/ˆ/п пО/u?@‡2tСrПœпœЯKЖSИЯ5мЯюЧ2ћЩŒ7сбxХ€эпЂя#я6@хhБ$MчюuLЕhБЪ        хеƒя•яЇяЙяЫяняяяџџ%џодŠе‘ї§ѓ)Й<щ€№Oх™U‡#Р5G‹˜:ём:ѓU27ЧqЩ Ќ?Ш/к&@мwџ‰ўк&Ѓє<<7сбHсщпєБУ1яOВQjСPфSсHЙQ›ywщHсAt/†/˜/YOВGТ$_щЅ4.Ыћb%FЂДЦ8ћqТ/д#?˜Cђ/Њ‰§Nм^мТqЄ€hшE!	@d)nм{” щrѕ1PБ1	@/ЋO0q•жt}Q„”ўnПњџЄК=ВЙkхЦБь…Љ{Ј…B'ФІЩ‚X/йPP\ьfцй2ѕ1ѕ1”Rе5P"”Q”Q[СO"P!ДЁq’[СŠrДЁДЁюrŠq€Šqг‚юqюqТЂггPБТЁТЁWт§a§a7бVтWсХе7бPБ$q$qZБ0r1qPБZБZБdБJrKqobdБdБХ2oaoaAPБС5TБ~rqPБсбй1W?Oрr?~??Ђ? ъќxХљ9/F
@@O$JљД]€”Aм7ЪкДIКHрЙq‡ƒаd˜Ep{y\O@fƒае_ч_љ_ЄКpИПЪПцЖсбЋaІИЂ–й1Ач<яNя`я†4F‰OdћЕ~‰аqŽЖGШ‰3qOшДNkуgLЂІ9њQзOыЏц$˜B_­XоєKPŸŸ,ŸЄК›ЄRžњЄМбЗ'У”ЖрвP!‡Ÿ™Ÿ//ЯŸ$ЏH?Џl~ІH›qЫ}EУеЎЏљ<ПNП`ПAŸSŸeŸw™КSРПвПфПіПЯЯ,Я>ЯPЯbЯtЯ†Я˜ЯЊЯМЯЮЯрЯђЯпп(п:пLп^пpп‚п‚OуЁпГпХпзпщпћп
яя1яCяUяgя€Ž№b{Џ.ВНяЯясяѓяџџ)џ;џMџ_џx˜Щa€џ’џЄџЖџШџкџьџўџ"4FX‰я›я­я ВФжшњ0Bz–Яas…—ЉЛЭпё//'/9/K/]/o//“/Ѕ/З/Щ/л/э/џ/?#?z–уaB?T?f?x?Š?œ?Ў?Р?в?ф?і?OOU§b§b7OжQлV.e_OqOƒO•OЇOЙOЫOнOяO_w™k#_5_G_Y_k_}__Ё_Г_0Х_з_щ_ћ_UlЄŠŒAoSoeowo‰o›o­oПoбoуox˜a(:L^p‚”ІИЪм
cяwo–…!3EWi{ŸБУйІВцј
GRID    0        1       0        1       0        16711680        0        0
ŸŸ.Ÿ@ŸRŸdŸvŸˆŸšŸЌŸОŸk}ЏЏ*Џ<Џ€NЏ`ЏrЏ„Џ–ЏЈЏ“еУЏеЏчЏљЏПП/ПAПSПeПwП‰П›П
ENDGRID -1
fЖПчŸкПьПўПЯ"Я4ЯFЯXЯjЯ|ЯŽЯв”ЇЯЙЯЫЯнЯяЯпп%п7пIп[пmппюsБЗў@ібЕФпжпшпњпяя0яBяTяfяQ…я—яЉяЛяЭяпяёяџџ'џ9џKџ]џЬŸџ№ŸЅџЗџЩџлџэџџџ #5G29fxŠœЎРвфі,>B'Cо–дkэћ# Чbсz„@Дп.`‹c­П.`Ыня/%b /Ї=QN3L/^/p/‚/”/І/И/Ъ/м/ю/?? От7?<цNШm??„?—г™?Пэ@€З?Щ?л?э?џ?O#L3OEOWOiO{OOŸOБO@УOеOчOљO?Žж'_lN2T4ы\9S_˜БГz_ПбА˜_Њ_М_Ю_ рUБВэ_t}нo&o8oJo\ono€o’oЄoЖoШoкo_V“3
ЗŠВе?„?cЈ?‡™ЋНЯсѓyx‘'9K]o“ЅЗЩлсS—п’ІKUКп(Ÿ LŸФpŸ‚Ÿ”Ÿ/ИŸ0/ŸСqфŸіŸЏЏ,Џ>ЏPЏbЏtЏ†Џ˜ЏЊЏМЏЮЏрЏђЏПП(П:ПLП^П@pП‚Пн‡žП‹Z€с;дЩМйПСдѓДгйЛ>еЯ.Я@Я*вб[ЯmСаŸƒЯпЩп…3єФOŸшДNkпжŒ
Clock   Unclocked
т‘цў‡ШФспP27ЧqирЌ?зящцўпƒ?Й\.—ЫхПт? рюАяQAqиДущцўДт$ќ$ќ$ї'п9пKп]кHŠфОщфМЉЗДтЙіCўjPШjџ|џxд•“ИaIмW™у&V03EЇѓП0<њїўџЙkPDФуџѕџ“Иˆ“ИЂњB!ЃпЕпт        Vс№
чпљпяя/яAяSяeяwя‰я›я­яПябяћѕяџџ+џ=џOџaџƒ…џ—џЉџЛџЭџпџ•/09K]o?!?ЅШ%§”ы№Acrobaџt PDFWriwterо§юёп$ъ
EdgeLevel       neg
wodx)3EWi{§<ы№#џwinspoџolAcrobџat PDFWrџiterLPT1:мџUFы№џђ№ы№DшѓfњєёђџџъёP
рћіёъёh> ы№/Tы№6DЊъёы№’ујƒUmAшѓ@›
Р?­лПIшѓ№?ПСYзщћ{џвъёЗъёO•1@цѕ3EEbOУe„ZЁцѕ
Set     Not Used
•ы№Hu§щђ ѓ№ящђџ˜џP№р№(:њџџŒˆџџ№{ŒW‹џ№_€qƒ•ЇЙЫеŒтџ§Qы№Rectanџgle. wiџth text џand connўѓ№ion poiџnts. Canџ be streџtched toўy dimenss.mbујшПшѓр?єєўрПшДNoшПр?kш?рћєР4
№ћє№П•Hы№џђ№ыєы№DBы№ы№іё№ѓ
яє$#        фї?hчє-(>Tы№пќT9   ›ујѕ‰›UAшѓј?ЇА№КЏшЏр?Q6 Ял‰uŒ` 6еўьuі№і        mB>іё0Œ0XA0ъё(2s@sJLsT„>ъёЁі5
‰€LO@ўЃ‰ъё{Ё‰§ђ№пўф5Аџ`7Copyrџight 199џ9 Visio џCorporatџion.  Alћl      "s resџerved.ўэ‰` _Sbџa.chm!#22430ў BЈdЌ9     l>ы№0>Uddтљ!!€Ф‰ујіёЌŠTЁ
Clear   Not Used
ќ<hЋђbЪ ў
2Є61
ClockEnable     Not Used
g,s72‹Э4Ё?`b?ўM1EY?Фr?9€1M1| ;6З==з5P2ш?;z‰rA
ActiveLowSetClear       True
РўIB=OCРўq‰…,^пќ35Д/™ТујVЁ:вШЫNќьAьCї=ЎA КKЗр?гOхIЛ=ь"3їЎAаКOФ<_хOїOKЎAEŒ[6:_ L_Ij_|U|\_ooУ_ўAnеРы№Hы№lы№&ї'щђћnѕы№џН!џРOyŽa§§єGEгЏ-szьтљчєFўы№фЌїƒЛЂы№ж#ы№ЏАї%Jы№Bћ
AsyncSetClear   True
ы№ЏїoЊ[atkЪЎы№@+ы№|kЫђ3aђёБї5ў\ў№ж•ы№ы№ѓєщђ&мёUlы№4ы№,чєчє-шѓ@шѓщђщъёы№ьpПы№AJ-ф3
ActiveLowClockEnable    True
7"Aљі&Ulы№4ы№,чєћє-шѓ@шѓщђщъё
VhdlType        std_logic
р_Jы№A-$3P7њѕUzы№ы№Zпќчє§@ы№\q>ы№Rмџ0B*
єV:Hы№<мџ(
VerilogType     wire
Hы№<мџ(
SystemCType     sc_logic
Uzы№ы№Zпќчє§Eы№ЄqР
ы№Rмџ0B>

TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
‘`ў–
StateEquation   Hex(Inc(0,2,5))
œe‘1Crw
HighVoltageThreshold    5
ƒујЉUы№HыЄъё ѓ№–ўяђџ^€џџџПџўџќњј№єџїєїїЕŸ  €-џ}|5pїџ`Iоџџ`V?џпџ}ƒџ`Сџџјƒx‹їџїaŠџџѓ833џŠџџƒџ‰џџѓџџџя‰џ‡Ž‡‡џƒџљо…џ Ÿ™џЊŸџ™љ]ЉџŽЗ№ўТџ№ƒ3Яƒƒ3‚Й†“Уu…Ыџ‚ŸЉОпџ3“3?,№      ї™?№џŸ№ўG‡xpџџ№хx“^мŠџ№ƒ‹џ&яŒџŒџ
ƒДџ§Cы№This cџonnectorџ automatџically rџoutes beџtween thПe shapi
tіѕs.•Hы№џђ№ыєы№DŠы№ы№щђђё
@яє#        фї      іё=hчєЕы№8Tы№ пќYY9    BTы№#ы№›ујF      oU@шѓј?З
е№ШПЗрПрПэP6
LowVoltageThreshold     0
‰u
SignalActionType        0
я`uфbџ€A@]ўќu
  Ѕ‰.(#DB˜     Ѓ˜‰uuŒ`hр?\еhr|u”і№†‰эV‰aкчЧŽ‰Жа@-№?b—l’;'bE-ho'$—y(œ‰ъёБ
MSB     0
тџ2rЧqЧсп?@ŸєIЭ Я?кУ$бЫ%П?э
LSB     0
@Љ§ƒўі"ЗўU*5L -яbrъёРŒ     ^vœvЕі"(2u€I.і"q28˜švі"uh9 РBdД&</MSЃъёz
isFallingEdgeSensitive  False
#§ђ№ті1ўћ45|`џVis_SE.cПhm!#20)@љў`7Copџyright 1я999 @io џCorporatџion.  Alћl ;Bs resџerved.ўёЄ•ъё4UјŒЂ#ў1#ЇЇъё№7)A,@„™ъёA+Х4о§j'vQ8l>$UdvтљіёEђ„       ‰\ДŠbў4
isRisingEdgeSensitive   False
*д’1Bњ$b–‘24ƒR‹Ÿ(@][аv[D ‡ZЫQi‰@       ќaч59        Ь9”уј§3ЫO'2Х"qМ?.g;2шGеРы№Hы№lы№sw'щђ‘*щђ§џЎO`ЩѕЉы№ў­увEW
DrawAnalog      0
)їтљчєFы№џмЙїнЮы№ж#ы№|МзїжK7B§
BooleanEquation
ы№$Ої
GGы№dъёToBъё@мџёѓk€Эў№ж•–ы№(ы№bмџсњъы№чєы№ЌїПZ—ы№SћЩы№ЉїёК+ы№B?ы№4ъ9@0ы№RDОы№фЊїк@.ќS"Йї!'‰/ъё ы№мџUы№џђ№™ы№Pшѓxњєёђмџ№Пђёoџџ@#ї?ЈтљіёъёFчєы№DNы№Teъёёђ@yŠ
рћaъёhчєѕы№$ы№TBы№пќРРцѕХз’ујўНUIЖшѓ@
NegTolerance    0
@2Р5?П
PosTolerance    0
№?.у  №K]oыїзХў%jН
яРђЈDŠЇЅaЈЅUЅ       Ѕ
UserSpecifiedSizeRatio  1
ЅЅ)›ьъё‘@цѕ-У№?--"(ыЯqНѓюХлuѓ` цѕўh`"уj"p"uРz)Р№ъёэяR?$Р5%Я&ай.иы.Я(sU1х6t1?ыe"gьЫШe?Ў'ЙЩујPяд–4"Д	(&НTшu§›ќђ№Хџ`
Black џ& Whiteўn№яХИ<;
VerilogCode
'ъёЉујК1)Eм{&ы0Щ3Cџolor Schџemes...ћў1Х`'Set the cNBэsTB fP@thiџs documesnt\@є`юы2`
MJ€QІ" ўeНы1ˆХpпќы1ы1ч РѓТaPжръєы№ ыєp!ИўЯ
ы№‚ы№ы№`!Ш1ЫHы№EA™1ƒујєUяHщђYQ%eTѓpWА%eTТpWуeTИpWі5eTРpWТaXapWАeTжpWжaXрpWрaXъpWъaXєpWєaXўpWўaXЯpWЯeT1QpW1QaX5QpW5QaX9QpW9QaX`!pW`!aXpWaXQpWQaXQpWQaXQpWQaXюёpWюёaXp!pWp!aXШ1pWШ1aXЫpWb5eTMQpWMQaXEApWEAaX™1pW™1aXы1pS‚1
VHDLCode
і5ЧХP9QEAEAяcы№ЉИы№ŒЖТы№Уa{!{!ж!ы№нрc"ы№ъъ#ы№ФїєФФў'ˆы№‘=R(ы№‘1)ы№+‘Q*ы№8‘FЫ+ы№E‘MQнE†ы1oіDч?љ?ујЈPујБ@%IС!К5уќРQЬ0    ConnectorŽD    –AЪ’
PROPS!
аšpQя§UiИА%ђёТ|ˆщАѓИИ‘Ш-u@цѕИv™эI!цѕE*Ћ@?$ј5%ЛЅpЛЅКЈЂ‘ч„      (XŽ3О х†­(.;‡јИ8ЗюёbbмbчzYPз@ў‡рG2ЧqqАЌ?pП‚Жшѓџ?Й\.—Ыхт5?{ рђ№яAщ`!D‘%<Х
E0      0        3125    3125            1       0        DR      0
Iрћј4s№?1ЏФ1l№a0Х‚b=aАы       HРИТ‰дЂ‘Š   (Q/щђ‹­(sЫЬІŠХуšЯŒУv•sЯгЪюU$шЯхіqНТ,ХЁu|&ыX9ЯOъёСАЏ!/ў›іё%}лЬІУІпLА%}паЋрпLуы”жзп,яv•яXяjя4Rьv•p"TцѕOpeџnRISC 1200i`ŸrŸ„Ÿ”№ујїЛя'2W8ŽуE№Ш2јЁpQ
E1      1       43125   43125           1       0        DR      0
ХЏ­(#Џ5ЏGЏИ@]ЏoЏЏ<Ъ Џюђ5%*ў5%т5%юшЏ
E2      0        43750   43750           1       0        DR      0
'H1П&Д1QИ0RR‚Q‚’Пј]‚3ПEЗќbBbVДЄБXШ1d#ЊггЗПTА%+фПРJYЁ5QА%`!ашCPU/DSPштЈѓяџџ)џ;џMіСЅЯ$ЯщџHЯZЯп~ЯЯБЯ†/.кЯa/С&ппNи6пHп /lпСк:”пoяXdЌ/?€?’9EAR–
с2‘ЃїйЊ;`:1Ъ?м8Jџџћ3`Oџџ:щЊ;~6С?JOa‡‡ћ3еO}яm>ЏO;pQ˜ЅbќwѓzOpCw]A?ьѕЙџЫџнџXЂd”Ѕќљ№№Фж€ќ)ем)д'^Ф'WPП-DTћ!    (QЗˆ-uЙ``§uн`фb›uШ``uœ`Sdm€Jp@ўъZhкJh€3@ўјqTObJbUa’c_bXZbЃdЬтuY `аnЛpр?Рcu.аlЫil‡эb­ѓfUљYЕџnњg‘†KwђgFrђgUguѓf“w_}wgp+‘pј№ёи€мww€@z3YБ’жrмю~…јиЦ06аi­“Г       (VYЁЃЫајЁaЕ@E‘dм7r–ˆ†№”Ѕ‘$K`
!
*G#_;/UQ)8‘œO—ЬуЧi5 ўx)§‹hŸDљ’єbџ—џ‘џ€ЃџЕџЗ_Щ_ыџ§џ“ Uѕ)р)х)аDVhzFц7Й–ЇІЅЗЩлэџTš4F”‘W1њ`ЭыDCache
8KB‚”ІИЪмю//H?6/     ЖQ/Ÿu/Уи=І›/žЯаbФ/yЯйЦё/??'?€9?K?%ЧЊ;OІ~?СOЇЏљ5МпCmЅ[=ІаŽп‘>wѕ[OІFІя(цO’к
яЈпх8œЈћ<œЈ_…о“я8_˜‘sŸС”	е”ŸІŸИŸЪŸмŸюŸЏЏ$­f=ЏOЏaЏsЏp чЁ‚RезЛзЛЏЭЏпЏёЏПП'ПWйEПWПрWёuЙљA…ЙMMUšПЌПОПаПтПєПЯЯ*Я`пNЯ`Яп„Я(/ЈЯКЯЬЯоЯ№ЯпІ/&п8пJпёV?єя’пџъпќпG? яuяDя˜?Ўпj
амopя‚яж?ш?[[ЭуrOхяТ?KOџч6џ~јSџeџwџ‰џ›џ­џПџбџХDяnќџ h)‚ГЏ„–ЈКЬо1ЕьУeЩuЙГ…ИPICSew‰›­Пбу?//Ч/=/Ьa/s/…/—/Љ/Л/Jп/ё/?•'?­OK?бOo95K‰?ќЎшoЮе\Ÿшг1яШ?;Ÿgяx>€COЖŸ(цЄOЖOѕŸ!њшOAїWЁ_‰Џ,_>_P_pb_З†_˜_ђ­_П_б_у_ѕ_a@кг{Ж€o0oBoTofoxoŠoT@tЅЯЗo3ЩWЁ4цkџTICK TIMERїo  -?Qcu‡НЋНkсCп);M_Спƒ•ЇпЫЏяAЏŸ%ŸbяIŸ?Нp“гяˆŸWяЌŸ{яаŸтŸ(џЏLџ*ЏpџоFXЏњGЮёxЏœЏЎЏРЏвЏ.яіЏП§П/ПAПSПeПa4ГђŽП ПВПФПжПшПњПTыѕ‹'ЯрЊЮёйiйcыfDEBUGnЯ€Я’ЯЄЯЖЯШЯкЯьЯўЯ4я"п4птпXпЕ/|пŽп пВпФпжп3?њпяя~/Bя”џfяИџŠяœяд?Ряиbі
p“EOџяЩ?#џэ?GџYџšO}џОOЁџтONІ       ЯџjЇ@Qяџr_%7I ?mі@?_ЙЫнxАхaГdf);M_qT]U§ožyє@QIЩЭPOWERMрђ//(/:/L/^/p/І?”/І/T?Ъ/(ю/??$?6?H?Іl?~??ёД?_и?*_ќ?OGŸ2OdoххИŸqO<Ÿ•O`ŸЙOЫO
ЏяO1Џ_UЏ7V
SIGNAL  iwb_ERR_I
A_сїГЁa_хЏ…_—_Љ_Л_Ÿп_8Ї e“o)oфhЗqJo‚dUСrbTТrbYAлГыЖxoŠoœoЎoРoвoфoаЅ„ЯЃЩ№ГЁ2yзБаICac?he
DIRECTION       input
8KBSew‰›­ПбуŸЧ=Гпas…—ЉЛ1япёŸ|п'ŸyЏKŸЏo™Уы‰Ÿуяj–ъ•{›Џ&џ­˜ыПщГъПшА)Љ{›CЏiџ­˜зϘѕ§џВѓpЏ‚Џмџ3ZДЏSWrдЏЄјЏ
RADIX   hex
ПП.ПžяRПdПoˆПšПˆЌПОПаД–Ÿї іwoЯ"Я4ЯFЯXЯjЯTC/—Яb)r2y
ЦЬMMUоЯ№Япп&п8пJп\пnпЄя’пЄпRяШпl?ьпўпя"я4яFяъ?jя|яŽя5?ВюIџея[§ГšќГњяџ‹O0џьOTџ_!ЏОџ_X_Џ––˜ѕЖ_):__Р_З’z.Sb/џџЬ‘XmVOбуѕ$ч}WўyЕ7ќM_hP-DTћ{!	Ч1ˆ-Ѕ!лuв`uГ `Пфbu„ `Йur4t€ћ"2Ѕ!;x+x€ћ!S0r+r6qssс@r;r„tаQuв`& EЁsuHh@ЌyЁaл’П"Юr­дv*(кj:/њшg$Г–П#дvгw'‚гw6H…б’@П"t‡@уw~H€)&rЛp	Н‡;€r@z3ћЗ‚ЩНЯŽ…Пл$0П6аi­W#„    fЛН01%+y­—уrж1Хe'4рi‘ 9\3poP?UЅf9*z_cЂrЈyJ0ў9о›љhїŸ\!ўz„#1oCoUogoРyo‹ooЏoСoгo€UќyЕђyЕдnФ0BTfxŠœЎР„!иyљЖэzхZкjџ
О†ђ?ˆ’ƒ"П#љЖјЗJ„RЯdЮљЖ™ЧeЭЧЃЯД…CpяуЦгтЯ@єЯИƒя€ъ†5ж!п4пј
GRID    0        1       0        1       0        16711680        0        0
ŸŸ.Ÿ(xФТрж™Тm“рж|ŸŽŸ ŸВŸФŸжŸшŸњŸЏlшИ‚яFЇx%XЏjЏ|ЏŽЏ Џ@ВЏФЏжЏшЏњЏЖ§П(П:ПLП^ПpП‚П”ПІПИПЪПмПЩxx!иy„э$Я і†§?%…„мƒJ„ня„$№
ˆ“.Д‡шˆnJпmoпп“пЅп@ŸRŸm“&яя+я=яOяaя@sя…я—яЉяЃ/Эымяюяџџ$џ6љ5';BD/АV+qѕ}џ@ёeм
ENDGRID -1
nЬМўљТбвџфџіџ,>PbФ}1ШиyЅF
Clock   Unclocked
Ж*…€ёeˆ'ƒЅF§GЄGJ„ўO^ЅFEW]ДGO_Д€ЙЫн-/?/ƒ?c/u/Ф/™/Ћ/Н/#gЪ88oбчQё?•aOї,1?Фfы[Јc_ѓ:џLџh^џN6y§E i`Й5ф†Љіѓ
ЕЛіу?Q‚yюЂ@ўЂ†ТQh cŠ7ЂЬtЁЄЗиEAџЂўгb~@ќaЂ<§c}
w1јЃSврФoџџqлхє…ёPЃTFeWB
EdgeLevel       neg
IidO1§geљK5ФЂ…ё”x”T{'_2Чqа€МЃRяОQЄe0ЫWqy•aфe#}јaКa§_!i oFePiN›Љјg“КеuŸctg“eѕNŸЎšКaПŸ\šq%”Кa,§gъ‘y       ЅŸs™xэю—Лј€hЏјu…ёLЁЂXЋЉіуgЏ‚ЎTeXЏc{ЛЏŠІКеоЋ-fВЏПeѕоЏ3ПEП2—q•oЇd—qВoбПжoРшoњo3Џ0BщЁўhzŒžАТдцј
Set     Not Used
‹МЕ-п2LйЅСTf‰Ds…—ЉЛЭпёŸ9Џ'Ÿ9ŸчŸ]ŸVяŸ“ŸЅŸЗŸЩŸлŸдяџŸЏ#ЏяGЏeПkЏ‰ПЏЁЏuџХЏЂџщЏЦџ
ППЙџUПяџD‹П@@ЂПІe­РПпфПіПЯЯAџ>ЯuW§eЮрwЮа‰Я›Я­ЯПЯбЯуЯѕЯпкЪ;/@пZ)­bй3f†
Dp€/Fп“пЅпЗпЩплпэпџпяGџ5яGяѕяkяf?яЁяvУяp?а6№яџџ&џ8џJџ\џ nџO’џqO 7а…OгџВOf„йO        OЬO!_f|NV_›іTЕTcZ/џџзTюYPOЕ%@0РRš!Kš †QЦР WurЂV„HP-DTћ!        Сяˆ-ОQuіJpu
Clear   Not Used
Jpфbwunа`uФfЛ€Г@ў"ОQДЭhНh€­@ў!ЉТbНbШas0вbЭbt3aНQЙ"[ОQuСP` Њє33s:vDrЉuV0Nya8liэzm€zg$5{9w:vЙrМRУ еz_wьѓЙr‰e)ОRpУ`U2Nˆw€г`@z3рa’I‚OaŽ…ёHе$06аi­O#9›VСQV1Ї‚7U+ДiвюQ^s$aМRџ‚џ!WeЙq4О`№6jV3oJ?UR`9*@_с$DrJy‚D0ў‡9p›Ё8‰ŸT!ўЕAС_г_х_ї_       o@o-o?oQocoujђƒo•oЇoЙoЫoнoяo %|DVqjVvA>sZs‹Ж€yZЃЉЋwCђ?лu‹ЖуЗŠЗЙsфПіО‹Ж+ЧїНšЗ5Я@єpI„IЁ}…uЦetЯ„†ЯнЂpxЅЧЦГЯЦЯŠœЎР4Xѕ!с.–Жџƒrж+Тџ‚ŠВџ‚Ÿ!Ÿ3ŸEŸWŸ€ІŸ{ŸŸŸŸБŸяеšуŸѕŸЏЏ+Џ=ЏOЏaЏsЏ…ЏrmмЈЏКЏЬЏоЏ№ЏПП&П8ПJП\ПnП€ИmсЙЄКŒ-њЋwмЖulтЙ#ФoЖ‚
%РkЧF1}…мЯџпп%п7пвф!џƒЋŸЋпНпЯпспѓпяя)я;я5/_ыx#sя…я—яЉяРЛяЭяпяёяџџ*yfzeпš^ЯNџ`џrџ„џ–џЈџКџЬџоџ№џw"Й;F/AW5 O7g;F“G:GФ”OІN;FлGЇMJGхO іЈ0|†%V$_:L^p‚”FFџƒаVОатє//*/љ‹Q‰?›?­?П?б?у?ѕ?OO+Mќq?Id\†ЄКЖFi€F€yO@ŽC\†Д‡[‡ФЕЧŽ\†ќ‡Шk‡Ÿіp_‚_”_ф_і_:o,o{oPobotoa'xяŸcч1МoLЁFЃаe5жo{ЃЂ›_Ѓ3ё/??Dv0=EзšMі2џр3ѕ.Mіа?QгЉЅRЉЕ(еpЕ]ЉВ†Јз“ —ЉГƒДЄЇXќqЖVЮ“ўŠЂ*@ГЁЮ•<ДЇвПFјZ“? {ЏџџКЁЈОЁЗ ЦЅџINT
ClockEnable     Not Used
I/F    i™”бДЇ9Ј•Ю•тF”УЈK”гЋ'Џ2ЧqŠРМZ’ІQu‘[Ѕ0‚—ЯНLЁ›Ѕк­ЏЁ5ДŸИQЪ™rбкŸEЉл;ј!гЊU/п7„€!г5пhк5yпкqпФ5,ДЇVбТЉУеЪЯЬЃ™УЈЇСњЏу™иБГ FсЮ•ы;іа!я<ю
ActiveLowSetClear       True
uяЛuяDцЊU˜ыф–lяСя5˜яэяџяОbrБLЏ^ЄrБiЏ‹џЏŸЏБЏУЏэпчЏ!џU8П(П:ПLП^ПpП‚П”ПІПИПЦђ@vѕчщПƒЩЫPM)Я;ЯMЯ_ЯqЯƒЯ•ЯЇЯЙЯшџнЯяЯпп%п7пIпD/mп/‘пŒ/ЕпЧпйпз§пџ6џ?џEяh/2џH?яŸя~?УяЂ?чяЦ?џЇ?ќ?OНcшaЛoЭoпoёoЗџЩџPлџKwї§a{puyuШ‚~И”ІИЪмРю$6HšA`‰fuŠZ_•Š%U/@€’hBнƒ fgв„ko}nfВgP~m!gМo)jBpЙPvlBњh€P'@z3ŒQѕbћo
‚dRpPЭ-qNv:M_~?ŸQŸcŸSЇДqcЭ.fаA—c§rВb§rb§ruŸ‡Ÿ™ŸЋŸНŸЏсŸѓŸЏi77X›>ЇjO|OŽO OВOФO жOшOњO_Qmщ:7_I_[_m__‘_Ѓ_Е_Ч_й_ы_§_`єiІ+o2ЇŸц:Wgь?ceІ ѕЇœЇˆdіЏОІ=З     НЌЇGПђgЌ!)u‡Жc†П˜ПHsуѕ-qйЖХПиПˆšЌОатЈІ§s„Ц=Вƒ„Ц 2DVhzŒžАТ"пц‹J]џЋєJzџБп€žџАџ]ŸoŸ§/јџЦЏЋ@ёКžс:ИCUgy‹ЏС€г
AsyncSetClear   True
œе
џњ,љJў)System :L^p‚”ІИЪяю/Ў/$/6/HыV/kП’/FІЌ/О/а/т/є/??Yь9?O]?Iъд˜n™?OРŸЖс?ХŸьO/^щ./wUFщђы№ы№ы№Uы№ы№ы№ы№U ы№!ы№"ы№#ы№U$ы№'ы№(ы№)ы№*ы№+м№Ulы№4ы№,чєы№Еы№шѓ@шѓЄщђъёы№џqю6;њы№C-ќp)/7ы№AщђU2ы№ы№пќчє§@ы№4p/77Gы№RHы№<мџ(
ActiveLowClockEnable    True
U2ы№ы№пќчє§Eы№„p•77
ы№RUlы№ы№Lујы№ѕчєы№\ШїџФїгЩы№œЦїпн6ы№@ѕ?ы№Д%v7ны№RDы№ФЧїЂ;U$ы№мџ
VhdlType        std_logic
!ы№§чєпЧsџ[ё№ъёя№"4FрXj|Žъёоџј“ЙхіC:\Prџogram Fiџles\Visiџo\Solutiћonф Extrџas\Backgџrounds.vss#ы№§чєёйsџ[ё№я№     #5GрYk}ы№Кџј“ЙхіC:\Prџogram Fiџles\Visiџo\Solutiџons\Blocпk Diaл\Bџasic Shaџpes.vss(ы№§чє€ыsџ[ё№ы№я№"4РFXj|ŽъёКџё“ЙхіC:\Pџrogram Fџiles\Visџio\Solutїionф Extџras\Bordџers and їTitт.vssеvы№(ы№Bы№є“юмџшѓъё*ўы№Д€ј8ыyы№C!мјы–+~/    ?9/ъё§ёU1ы№џђ№ы№(шѓы№мџіёіёцѕUы№ы№O"D&aU=шѓђёQџџJf       рћ)ъёh"Tы№y‡ъёМуј+UК
VerilogType     wire
ц"_Щ…&aQ-З
SystemCType     sc_logic
-H*9(TYяєkЉPŒžАщђ›ујEQю№/,GuideTheDocPage-1ѕы№ы№Gestџure FormatVisio 90ConnectorVisio 00Visio 01Visio 02Visio 03Visio 10Visio 11Visio 12Visio 13Visio 20Visio 21Visio 22Visio 23Visio 50Visio 51Visio 52Visio 53Visio 70Visio 80BasicBasic ShadowRectangleSchemeNameRectangle.28Rectangle.4Rectangle.5Rectangle.6Rectangle.7Rectangle.8Rectangle.9Rectangle.10Rectangle.11ѕы№ы№Dynaџmic conn?ectorRectangle.16Rectangle.17Rectangle.18Rectangle.24Rectangle.25_ьы№Шя№Ѕ%уј,ъё3ы№дџŠј:
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Њы№Eф‹ъє–-
StateEquation   Hex(Inc(0,2,5))
‹јSЁђёGMUЙ
4MЦULMдc
HighVoltageThreshold    5
dMUсc
LowVoltageThreshold     0
|Mюc
SignalActionType        0
”MЕћc
MSB     0
ЌM;d  ФЊMЯ
LSB     0
мM"Я
isFallingEdgeSensitive  False
єњM/Я
isRisingEdgeSensitive   False
Œј<ЊЯ
DrawAnalog      0
$IЯ
BooleanEquation
<VЊЯ
NegTolerance    0
TcЯ
PosTolerance    0
lpЊЯ
UserSpecifiedSizeRatio  1
„}Я
VerilogCode
œŠЊЯ
VHDLCode
Д—Я
PROPS!
ЬЄЊЯ
E0      0        43125   43125           1       0        DR      0
фБЯ
E1      X       43750   43750           1       0        DR      0
ќО|ЯјШЯIййЯx<йѕчЯгœјіњн\й<Њtй%*Œй'Њ%*Єй7%*МйGЊ%*дйW%*ьйg|% рŽјx‘*UŸ ‰% ы№AЊŸ % UDŸ ЈЊ‘*\Ÿ Й‘*tŸ ЪЊ‘*ŒŸ л‘*ЄŸ ь‘&ъёы№ы№я№З"Uы№ы№ы№ы№        ы№0ы№fxЈ!(!ры№ы№*ы№ы№ы№ы№ђёЅы№ы№Ъ!ы№Њы№ы№ы№ ы№!Šы№"ы№#!ы№њё&Њы№'ы№(ы№)ы№*ы№+м№U^хіы№ы№ы№Uы№ы№        ы№
!
ы№Uы№ы№
ы№ы№Uы№ы№ы№ы№Uы№ы№ы№ы№ы№ы№м№Ulы№4ы№,чєы№Еы№шѓ@шѓЄщђъёы№џтщ>Kњы№C-4р4/?ы№AщђUlы№4ы№,чємџшнўўёўѕы№ДuП?
ы№AJ-Ќ3‹7ўёAщђ_ы№ќпќмџ*<Nчє@ўы№”р:?Gы№RVŠœЎ№Рвфg
SIGNAL  iwb_RTY_I
Hы№<мџ(
DIRECTION       input
_ы№ќпќмџ*<NчєEўы№Дс       @
ы№RVŠœЎ№Рвфg„Pq ы№мџ&AM3'AM3(PPT)PPT1_(ы№я№*ујы№њљ'9K]o“ЅЗЩлэџ#5GYk}ЁГХзщћ
//1/C/U/g/y/ш‹//рћ/ы№М–јПo@
ы№AЊН"дУ |Ч*ьУ ‰ОЧ*—ј–Ч JЫ"&ы№'ыёы№)Ќ {†ы№zѓ№œцѕїѓы№
RADIX   hex
*ы№   ы№gѓ№"мџ4pFXпќїј„ќшѓ(S—›0џт@(9ŽуxqRЌЏА2Ьђ№^z     №Jїхічє}ы№$Qї:Ўы№Rы№ЄџЁT
GRID    0        1       0        1       0        16711680        0        0
дџЊЏRїГы№uы№вћ&ы№ЌOї(ъѓ№!ы№B  ЬUї[Iѓ№Ч>ы№џl8Bѕ>Oы№9BЕNo5OgЈ^$f$ы№ŸєХї
ENDGRID -1
'ўћЦїС7љSN€је8)ы№4Х•9зJ1г„јЋплЂ=џы№œЛ—јхі`2ы№мџ†ј§<ькѓ№V”?ы№МŽWјУ, FDы№_„‘ј#ЗC}=ы№\“јfЗЊ.ы№ŒU ЄЗ›ўџр…ŸђљOhЋ‘+'Гй0ф@`lx„амValued Sony CustomerAC:\Program Files\Visio\Solutions\Block Diagram\Basic Diagram.vstфўџеЭеœ.“—+,љЎDеЭеœ.“—+,љЎ(ф@LXd
œд€мPagesMastersPage-1
Clock   Unclocked
RectangleDynamic connectorф ”0lx„€Œ_VPID_ALTERNATENAMESўB`_PID_LINKBASEAф     ўџ
EdgeLevel       neg
џџџџQН…<ѓбЅ=Kuy›Timing DiagramTiming.Document.1є9ВqTiming DiagramTiming Diagram Editor v7.1g - Output File
Set     Not Used
Clear   Not Used
PROJECT
ClockEnable     Not Used
BaseTimeUnit    1
ActiveLowSetClear       True
DisplayTimeUnit 2
AsyncSetClear   True
TextGridX       625.000000
ActiveLowClockEnable    True
TextGridY       6
VhdlType        std_logic
EdgeGridX       625.000000
VerilogType     wire
ImportStartTime 0.000000
SystemCType     sc_logic
ImportEndTime   281474976710656.000000
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
TimePerPixel    17.543860
StateEquation   Hex(Inc(0,2,5))
Visible DELAYS  SETUPS  HOLDS   SAMPLES TEXT    HIDDENATTACHMENTS       CRITICALPATHS   GRIDLINES       UNCERTAINTY
HighVoltageThreshold    5
ColWidths       144,216,288,423,488
LowVoltageThreshold     0
ScrollPos       0.000000,0.000000,0.000000
SignalActionType        0
DefDelayRule    1
MSB     0
NoEventOverlap  NO
LSB     0
SigLabelFontHeight      8
isFallingEdgeSensitive  False
LabelHeight     10
isRisingEdgeSensitive   False
LoadLibsToMem   1
DrawAnalog      0
UseFullPathNames        1
BooleanEquation
LibPath
NegTolerance    0
EntireTime      YES
PosTolerance    0
PrintTimeSpecified      NO
UserSpecifiedSizeRatio  1
FromTime        0
VerilogCode
ToTime  15.625
VHDLCode
AllSignals      YES
PROPS!
CurrSelSigs     NO
E0      0        43125   43125           1       0        DR      0
PrintTo 2
E1      X       43750   43750           1       0        DR      0
PrintFileName   C:\DOCS\wb_writesingle.wmf
!
PreviewInterchange      YES
PreviewTIFF5    NO
MARKER  MARK1
UseMargins      NO
ATTACH  iwb_SEL_O       NULL    S6
PrintTimeLine   NO
TIME    17500.000000
PrintBorderBox  YES
RELATIVETIME    0.000000
PrintSigNames   YES
DISPLAYAS       5
PrintSigNamesOnEachPage YES
MARKERTYPE      Timebreak(Curved)
AddPreviewToEPS NO
WHILERETURN
PreviewRes      150
REPEATNUMBER
MarginLR        1
SNAPTO  0
MifImageWidth   6.00
COMPRESSTIME    0.000000
MarginTB        Auto
COMMENT
Header  %d %t;%f;%p
!
Footer
ScaleHorz       100
MARKER  MARK2
ScaleVert       100
ATTACH  iwb_STB_O       NULL    S7
ScaleHPage      1
TIME    27500.000000
PrintImage      DIAGRAM
RELATIVETIME    0.000000
DefaultTimingModel      minmax
DISPLAYAS       5
DefaultClock    Unclocked
MARKERTYPE      Timebreak(Curved)
DefaultEdgeLevel        neg
WHILERETURN
DefaultSet      Not Used
REPEATNUMBER
DefaultClear    Not Used
SNAPTO  0
DefaultClockEnable      Not Used
COMPRESSTIME    0.000000
DefaultClockToOutLH     0
COMMENT
DefaultClockToOutHL     0
!
DefaultSetup    0
DefaultHold     0
MARKER  MARK3
DefaultRegStartupState  unknown
ATTACH  iwb_STB_O       NULL    S7
DefaultPodSize  8
TIME    37500.000000
DefaultActiveLowSetClear        True
RELATIVETIME    0.000000
DefaultAsyncSetClear    True
DISPLAYAS       5
DefaultActiveLowClockEnable     True
MARKERTYPE      Timebreak(Curved)
SigLabelFontHeight      10
WHILERETURN
PROPS!
REPEATNUMBER
!
SNAPTO  0
COMPRESSTIME    0.000000
STYLE
COMMENT
DefaultFont     USER    {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
!
DrawWndFont     DEFAULT
DrawWndColor    DEFAULT
MARKER  MARK0
GridWndFont     DEFAULT
ATTACH  iwb_CLK_I       NULL    S1
GridWndColor    DEFAULT
TIME    7494.285714
LabelWndFont    USER    {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
RELATIVETIME    0.000000
LabelWndColor   DEFAULT
DISPLAYAS       5
ParamDispPref   0
MARKERTYPE      Timebreak(Curved)
ParamWndCellDisplay     0
WHILERETURN
CustDispString  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
REPEATNUMBER
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
SNAPTO  0
MarkerDispPref  4
COMPRESSTIME    0.000000
MarkerCustDispString    %n v=%mv,%Mv d=%md %t
COMMENT
MarkerCustomDisplayStringRTF    {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
!
SignalColor     2
LabelOffset     2
ўџ
BusDisplay      0
џџџџQН…<ѓбЅ=Kuy›Timing DiagramTiming.Document.1є9ВqTiming Diagramўџ
WaveFormWidth   0.500000
џџџџQН…<ѓбЅ=Kuy›Timing DiagramTiming.Document.1є9ВqTiming DiagramTiming Diagram Editor v7.1g - Output File
WaveFormColor   0
InputWaveFormColor      16711680
PROJECT
SlantedEdges    1
BaseTimeUnit    1
SlantAngle      75
DisplayTimeUnit 2
RightJustifySigNames    1
TextGridX       625.000000
AutosplitEnabled        1
TextGridY       6
AutosplitChar   _
EdgeGridX       625.000000
DynamSizedSignals       1
ImportStartTime 0.000000
!
ImportEndTime   281474976710656.000000
TimePerPixel    61.428571
DIAGRAMTESTBENCHSETTINGS
Visible DELAYS  SETUPS  HOLDS   SAMPLES TEXT    HIDDENATTACHMENTS       CRITICALPATHS   GRIDLINES       UNCERTAINTY
FilesBeforeDiagramModel
ColWidths       144,216,288,423,488
FilesInsideDiagramModelDeclarationSection
ScrollPos       0.000000,0.000000,0.000000
AbortHdlCodeEnabled     1
DefDelayRule    1
DelayHdlCodeEnabled     1
NoEventOverlap  NO
SampleHdlCodeEnabled    1
SigLabelFontHeight      10
MarkerHdlCodeEnabled    1
LabelHeight     12
VerboseSamples  0
LoadLibsToMem   1
VerboseDelays   0
UseFullPathNames        1
VerboseFileInput        0
LibPath
VerboseSequenceVerification     0
EntireTime      YES
IncludeDelayTime        1
PrintTimeSpecified      NO
ExecuteFromTopLevel     1
FromTime        0
TimeOutInDiagramLengths 0
ToTime  53.75
DefaultCycleClock       Unclocked
AllSignals      YES
DefaultCycleEdge        neg
CurrSelSigs     NO
!
PrintTo 2
PrintFileName   C:\DOCS\wb_writeblock_typ.wmf
MACROS
PreviewInterchange      YES
!
PreviewTIFF5    NO
UseMargins      NO
CORGROUP        $$CLK_I_BufferRising
PrintTimeLine   NO
Percent 100
PrintBorderBox  YES
!
PrintSigNames   YES
PrintSigNamesOnEachPage YES
CORGROUP        $$CLK_I_BufferFalling
AddPreviewToEPS NO
Percent 100
PreviewRes      150
!
MarginLR        1.25
MifImageWidth   6.00
CORGROUP        $$CLK_I_BufferRisingFalling
MarginTB        Auto
Percent 100
Header  %d %t;%f;%p
!
Footer
ScaleHorz       100
CORGROUP        $$CLK_I_BufferRising
ScaleVert       100
Percent 100
ScaleHPage      1
!
PrintImage      DIAGRAM
DefaultTimingModel      minmax
CORGROUP        $$CLK_I_BufferFalling
DefaultClock    Unclocked
Percent 100
DefaultEdgeLevel        neg
!
DefaultSet      Not Used
DefaultClear    Not Used
CORGROUP        $$CLK_I_BufferRisingFalling
DefaultClockEnable      Not Used
Percent 100
DefaultClockToOutLH     0
!
DefaultClockToOutHL     0
DefaultSetup    0
CORGROUP        $$CLK_I_BufferRising
DefaultHold     0
Percent 100
DefaultRegStartupState  unknown
!
DefaultPodSize  8
DefaultActiveLowSetClear        True
CORGROUP        $$CLK_I_BufferFalling
DefaultAsyncSetClear    True
Percent 100
DefaultActiveLowClockEnable     True
!
SigLabelFontHeight      10
PROPS!
CORGROUP        $$CLK_I_BufferRisingFalling
!
Percent 100
!
STYLE
DefaultFont     USER    {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
CORGROUP        $$CLK_I_BufferRising
DrawWndFont     DEFAULT
Percent 100
DrawWndColor    DEFAULT
!
GridWndFont     DEFAULT
GridWndColor    DEFAULT
CORGROUP        $$CLK_I_BufferFalling
LabelWndFont    USER    {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
Percent 100
LabelWndColor   DEFAULT
!
ParamDispPref   0
ParamWndCellDisplay     0
CORGROUP        $$CLK_I_BufferRisingFalling
CustDispString  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
Percent 100
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
!
MarkerDispPref  4
MarkerCustDispString    %n v=%mv,%Mv d=%md %t
CORGROUP        $$CLK_I_BufferRising
MarkerCustomDisplayStringRTF    {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
Percent 100
SignalColor     2
!
LabelOffset     2
BusDisplay      0
CORGROUP        $$CLK_I_BufferFalling
WaveFormWidth   0.500000
Percent 100
WaveFormColor   0
!
InputWaveFormColor      16711680
SlantedEdges    1
CORGROUP        $$CLK_I_BufferRisingFalling
SlantAngle      75
Percent 100
RightJustifySigNames    1
!
AutosplitEnabled        1
AutosplitChar   _
CORGROUP        $$CLK_I_BufferRising
DynamSizedSignals       1
Percent 100
!
!
DIAGRAMTESTBENCHSETTINGS
CORGROUP        $$CLK_I_BufferFalling
FilesBeforeDiagramModel
Percent 100
FilesInsideDiagramModelDeclarationSection
!
AbortHdlCodeEnabled     1
DelayHdlCodeEnabled     1
CORGROUP        $$CLK_I_BufferRisingFalling
SampleHdlCodeEnabled    1
Percent 100
MarkerHdlCodeEnabled    1
!
VerboseSamples  0
VerboseDelays   0
CORGROUP        $$CLK_RISC_BufferRising
VerboseFileInput        0
Percent 100
VerboseSequenceVerification     0
!
IncludeDelayTime        1
ExecuteFromTopLevel     1
CORGROUP        $$CLK_RISC_BufferFalling
TimeOutInDiagramLengths 0
Percent 100
DefaultCycleClock       Unclocked
!
DefaultCycleEdge        neg
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
MACROS
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_I_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_I_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferRising
CORGROUP        $$CLK_I_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferFalling
CORGROUP        $$CLK_I_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferRisingFalling
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_I_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_I_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferRising
CORGROUP        $$CLK_I_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferFalling
CORGROUP        $$CLK_I_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferRisingFalling
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_I_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_I_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferRising
CORGROUP        $$CLK_I_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferFalling
CORGROUP        $$CLK_I_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferRisingFalling
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferRising
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferFalling
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_I_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_I_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferRising
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferFalling
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_I_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_I_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$dwb_CLK_I_BufferRising
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$dwb_CLK_I_BufferFalling
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CLOCK   CLK_RISC
CORGROUP        $$CLK_I_BufferRising
PERIODE 2.5
Percent 100
DUTY    50
!
OFFSETE 0
INITIAL HIGH
CORGROUP        $$CLK_I_BufferFalling
MAXUNCERTRISE   0
Percent 100
MAXUNCERTFALL   0
!
MINUNCERTRISE   0
MINUNCERTFALL   0
CORGROUP        $$CLK_I_BufferRisingFalling
JRISEE  0
Percent 100
JFALLE  0
!
GRID    0        1       0        2       0        16711680        0        0
ENDGRID -1
CORGROUP        $$CLK_RISC_BufferRising
DIRECTION       internal
Percent 100
MASTERCLOCK     None
!
Clock   Unclocked
EdgeLevel       neg
CORGROUP        $$CLK_RISC_BufferFalling
Set     Not Used
Percent 100
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CORGROUP        $$CLK_RISC_BufferRisingFalling
AsyncSetClear   True
Percent 100
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
CORGROUP        $$CLK_I_BufferRising
SystemCType     sc_logic
Percent 100
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
CORGROUP        $$CLK_I_BufferFalling
LowVoltageThreshold     0
Percent 100
MSB     0
!
LSB     0
isFallingEdgeSensitive  False
CORGROUP        $$CLK_I_BufferRisingFalling
isRisingEdgeSensitive   False
Percent 100
DrawAnalog      0
!
BooleanEquation
NegTolerance    0
CORGROUP        $$CLK_RISC_BufferRising
PosTolerance    0
Percent 100
UserSpecifiedSizeRatio  1
!
VerilogCode
VHDLCode
CORGROUP        $$CLK_RISC_BufferFalling
PROPS!
Percent 100
!
!
CLOCK   dwb_CLK_I
CORGROUP        $$CLK_RISC_BufferRisingFalling
PERIODE 5
Percent 100
DUTY    50
!
OFFSETE 0
INITIAL LOW
CORGROUP        $$CLK_I_BufferRising
MAXUNCERTRISE   0
Percent 100
MAXUNCERTFALL   0
!
MINUNCERTRISE   0
MINUNCERTFALL   0
CORGROUP        $$CLK_I_BufferFalling
JRISEE  0
Percent 100
JFALLE  0
!
GRID    1       1       1       2       2       16711680        0        0
ENDGRID -1
CORGROUP        $$CLK_I_BufferRisingFalling
DIRECTION       input
Percent 100
MASTERCLOCK     None
!
Clock   Unclocked
EdgeLevel       neg
CORGROUP        $$CLK_RISC_BufferRising
Set     Not Used
Percent 100
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CORGROUP        $$CLK_RISC_BufferFalling
AsyncSetClear   True
Percent 100
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
CORGROUP        $$CLK_RISC_BufferRisingFalling
SystemCType     sc_logic
Percent 100
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
CORGROUP        $$CLK_I_BufferRising
LowVoltageThreshold     0
Percent 100
MSB     0
!
LSB     0
isFallingEdgeSensitive  False
CORGROUP        $$CLK_I_BufferFalling
isRisingEdgeSensitive   True
Percent 100
DrawAnalog      0
!
BooleanEquation
NegTolerance    0
CORGROUP        $$CLK_I_BufferRisingFalling
PosTolerance    0
Percent 100
UserSpecifiedSizeRatio  1
!
VerilogCode
VHDLCode
CORGROUP        $$CLK_RISC_BufferRising
PROPS!
Percent 100
!
!
SIGNAL  dwb_ADR_O
CORGROUP        $$CLK_RISC_BufferFalling
DIRECTION       output
Percent 100
RADIX   hex
!
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
CORGROUP        $$CLK_RISC_BufferRisingFalling
Clock
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$CLK_I_BufferRising
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$CLK_I_BufferFalling
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$CLK_I_BufferRisingFalling
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
LSB     0
CORGROUP        $$CLK_RISC_BufferRising
MSB     31
Percent 100
SignalActionType        0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   True
CORGROUP        $$CLK_RISC_BufferFalling
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$CLK_RISC_BufferRisingFalling
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
VhdlMapping     DefaultVhdlMapping
CORGROUP        $$CLK_I_BufferRising
PROPS!
Percent 100
E0      V       -1      -1              1       0        DR      0
!
E1      X       3125    3125            1       0        DR      0
E2      V       13125   13125   Valid   1       0        DR      0
CORGROUP        $$CLK_I_BufferFalling
E3      X       15625   15625           1       0        DR      0
Percent 100
!
!
SIGNAL  dwb_DAT_I
CORGROUP        $$CLK_I_BufferRisingFalling
DIRECTION       input
Percent 100
RADIX   hex
!
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
CORGROUP        $$CLK_RISC_BufferRising
Clock
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$CLK_RISC_BufferFalling
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$CLK_RISC_BufferRisingFalling
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$CLK_I_BufferRising
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
LSB     0
CORGROUP        $$CLK_I_BufferFalling
MSB     31
Percent 100
SignalActionType        0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
CORGROUP        $$CLK_I_BufferRisingFalling
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$CLK_RISC_BufferRising
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
VhdlMapping     DefaultVhdlMapping
CORGROUP        $$CLK_RISC_BufferFalling
PROPS!
Percent 100
E0      X       13125   13125           1       0        DR      0
!
E1      V       13126   13126   Valid   1       0        DR      0
E2      X       15625   15625           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
SIGNAL  dwb_DAT_O
DIRECTION       output
CORGROUP        $$CLK_I_BufferRising
RADIX   hex
Percent 100
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock   Unclocked
CORGROUP        $$CLK_I_BufferFalling
EdgeLevel       neg
Per§џџџ     
Set     Not Used

ўџџџ !"#$%&'()*+,-./0123456789:;<=>?@AўџџџtDEFGHIJKLMNOPQRSTUVWXYZ[\]^ўџџџ`abcdefghijklmnopqrsўџџџжvwxyz{|}~cent      100
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CORGROUP        $$CLK_I_BufferRisingFalling
AsyncSetClear   True
Percent 100
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
CORGROUP        $$CLK_RISC_BufferRising
SystemCType     sc_logic
Percent 100
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
CORGROUP        $$CLK_RISC_BufferFalling
LowVoltageThreshold     0
Percent 100
LSB     0
!
MSB     31
SignalActionType        0
CORGROUP        $$CLK_RISC_BufferRisingFalling
isFallingEdgeSensitive  False
Percent 100
isRisingEdgeSensitive   False
!
DrawAnalog      0
BooleanEquation
CORGROUP        $$CLK_I_BufferRising
NegTolerance    0
Percent 100
PosTolerance    0
!
UserSpecifiedSizeRatio  1
VerilogCode
CORGROUP        $$CLK_I_BufferFalling
VHDLCode
Percent 100
PROPS!
!
E0      X       3125    3125            1       0        DR      0
E1      V       13125   13125   Valid   1       0        DR      0
CORGROUP        $$CLK_I_BufferRisingFalling
E2      X       15625   15625           1       0        DR      0
Percent 100
!
!
SIGNAL  dwb_WE_O
CORGROUP        $$dwb_CLK_RISC_BufferRising
DIRECTION       output
Percent 100
RADIX   hex
!
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
CORGROUP        $$dwb_CLK_RISC_BufferFalling
Clock   Unclocked
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$dwb_CLK_I_BufferRising
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$dwb_CLK_I_BufferFalling
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
SignalActionType        0
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
MSB     0
Percent 100
LSB     0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
CORGROUP        $$dwb_CLK_RISC_BufferRising
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$dwb_CLK_RISC_BufferFalling
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
PROPS!
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
E0      X       3125    3125            1       0        DR      0
Percent 100
E1      0        3467    3467            1       0        DR      0
!
E2      1       13125   13125           1       0        DR      0
E3      0        13126   13126           1       0        DR      0
CORGROUP        $$dwb_CLK_I_BufferRising
E4      X       15625   15625           1       0        DR      0
Percent 100
!
!
SIGNAL  dwb_SEL_O
CORGROUP        $$dwb_CLK_I_BufferFalling
DIRECTION       output
Percent 100
RADIX   hex
!
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
Clock   Unclocked
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$dwb_CLK_RISC_BufferRising
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$dwb_CLK_RISC_BufferFalling
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
LSB     0
CORGROUP        $$dwb_CLK_I_BufferRising
MSB     3
Percent 100
SignalActionType        0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
CORGROUP        $$dwb_CLK_I_BufferFalling
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
PROPS!
CORGROUP        $$dwb_CLK_RISC_BufferRising
E0      X       3125    3125            1       0        DR      0
Percent 100
E1      V       13125   13125   Valid   1       0        DR      0
!
E2      X       15625   15625           1       0        DR      0
!
CORGROUP        $$dwb_CLK_RISC_BufferFalling
Percent 100
SIGNAL  dwb_STB_O
!
DIRECTION       output
RADIX   hex
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
GRID    0        1       0        1       0        16711680        0        0
Percent 100
ENDGRID -1
!
Clock   Unclocked
EdgeLevel       neg
CORGROUP        $$dwb_CLK_I_BufferRising
Set     Not Used
Percent 100
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CORGROUP        $$dwb_CLK_I_BufferFalling
AsyncSetClear   True
Percent 100
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
SystemCType     sc_logic
Percent 100
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
CORGROUP        $$dwb_CLK_RISC_BufferRising
LowVoltageThreshold     0
Percent 100
SignalActionType        0
!
MSB     0
LSB     0
CORGROUP        $$dwb_CLK_RISC_BufferFalling
isFallingEdgeSensitive  False
Percent 100
isRisingEdgeSensitive   False
!
DrawAnalog      0
BooleanEquation
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
NegTolerance    0
Percent 100
PosTolerance    0
!
UserSpecifiedSizeRatio  1
VerilogCode
CORGROUP        $$dwb_CLK_I_BufferRising
VHDLCode
Percent 100
PROPS!
!
E0      0        3125    3125            1       0        DR      0
E1      1       13125   13125           1       0        DR      0
CORGROUP        $$dwb_CLK_I_BufferFalling
E2      0        15625   15625           1       0        DR      0
Percent 100
!
!
SIGNAL  dwb_ACK_I
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
DIRECTION       input
Percent 100
RADIX   hex
!
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
CORGROUP        $$dwb_CLK_RISC_BufferRising
Clock   Unclocked
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$dwb_CLK_RISC_BufferFalling
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$dwb_CLK_I_BufferRising
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
SignalActionType        0
CORGROUP        $$dwb_CLK_I_BufferFalling
MSB     0
Percent 100
LSB     0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$CLK_RISC_BufferRising
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
PROPS!
CORGROUP        $$CLK_RISC_BufferFalling
E0      0        11250   11250           1       0        DR      0
Percent 100
E1      1       13125   13125           1       0        DR      0
!
E2      0        15625   15625           1       0        DR      0
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
SIGNAL  dwb_CYC_O
!
DIRECTION       output
RADIX   hex
CORGROUP        $$dwb_CLK_I_BufferRising
GRID    0        1       0        1       0        16711680        0        0
Percent 100
ENDGRID -1
!
Clock   Unclocked
EdgeLevel       neg
CORGROUP        $$dwb_CLK_I_BufferFalling
Set     Not Used
Percent 100
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
AsyncSetClear   True
Percent 100
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
CLOCK   CLK_RISC
SystemCType     sc_logic
PERIODE 2.5
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
DUTY    50
StateEquation   Hex(Inc(0,2,5))
OFFSETE 0
HighVoltageThreshold    5
INITIAL HIGH
LowVoltageThreshold     0
MAXUNCERTRISE   0
SignalActionType        0
MAXUNCERTFALL   0
MSB     0
MINUNCERTRISE   0
LSB     0
MINUNCERTFALL   0
isFallingEdgeSensitive  False
JRISEE  0
isRisingEdgeSensitive   False
JFALLE  0
DrawAnalog      0
GRID    0        1       0        2       0        16711680        0        0
BooleanEquation
ENDGRID -1
NegTolerance    0
DIRECTION       internal
PosTolerance    0
MASTERCLOCK     None
UserSpecifiedSizeRatio  1
Clock   Unclocked
VerilogCode
EdgeLevel       neg
VHDLCode
Set     Not Used
PROPS!
Clear   Not Used
E0      0        3125    3125            1       0        DR      0
ClockEnable     Not Used
E1      1       13125   13125           1       0        DR      0
ActiveLowSetClear       True
E2      0        15625   15625           1       0        DR      0
AsyncSetClear   True
!
ActiveLowClockEnable    True
VhdlType        std_logic
SIGNAL  dwb_ERR_I
VerilogType     wire
DIRECTION       input
SystemCType     sc_logic
RADIX   hex
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
GRID    0        1       0        1       0        16711680        0        0
StateEquation   Hex(Inc(0,2,5))
ENDGRID -1
HighVoltageThreshold    5
Clock   Unclocked
LowVoltageThreshold     0
EdgeLevel       neg
MSB     0
Set     Not Used
LSB     0
Clear   Not Used
isFallingEdgeSensitive  False
ClockEnable     Not Used
isRisingEdgeSensitive   False
ActiveLowSetClear       True
DrawAnalog      0
AsyncSetClear   True
BooleanEquation
ActiveLowClockEnable    True
NegTolerance    0
VhdlType        std_logic
PosTolerance    0
VerilogType     wire
UserSpecifiedSizeRatio  1
SystemCType     sc_logic
VerilogCode
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
VHDLCode
StateEquation   Hex(Inc(0,2,5))
PROPS!
HighVoltageThreshold    5
!
LowVoltageThreshold     0
SignalActionType        0
CLOCK   dwb_CLK_I
MSB     0
PERIODE 5
LSB     0
DUTY    50
isFallingEdgeSensitive  False
OFFSETE 0
isRisingEdgeSensitive   False
INITIAL LOW
DrawAnalog      0
MAXUNCERTRISE   0
BooleanEquation
MAXUNCERTFALL   0
NegTolerance    0
MINUNCERTRISE   0
PosTolerance    0
MINUNCERTFALL   0
UserSpecifiedSizeRatio  1
JRISEE  0
VerilogCode
JFALLE  0
VHDLCode
GRID    1       1       1       2       2       16711680        0        0
PROPS!
ENDGRID -1
E0      0        15625   15625           1       0        DR      0
DIRECTION       input
!
MASTERCLOCK     None
Clock   Unclocked
SIGNAL  dwb_RTY_I
EdgeLevel       neg
DIRECTION       input
Set     Not Used
RADIX   hex
Clear   Not Used
GRID    0        1       0        1       0        16711680        0        0
ClockEnable     Not Used
ENDGRID -1
ActiveLowSetClear       True
Clock   Unclocked
AsyncSetClear   True
EdgeLevel       neg
ActiveLowClockEnable    True
Set     Not Used
VhdlType        std_logic
Clear   Not Used
VerilogType     wire
ClockEnable     Not Used
SystemCType     sc_logic
ActiveLowSetClear       True
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
AsyncSetClear   True
StateEquation   Hex(Inc(0,2,5))
ActiveLowClockEnable    True
HighVoltageThreshold    5
VhdlType        std_logic
LowVoltageThreshold     0
VerilogType     wire
MSB     0
SystemCType     sc_logic
LSB     0
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
isFallingEdgeSensitive  False
StateEquation   Hex(Inc(0,2,5))
isRisingEdgeSensitive   True
HighVoltageThreshold    5
DrawAnalog      0
LowVoltageThreshold     0
BooleanEquation
SignalActionType        0
NegTolerance    0
MSB     0
PosTolerance    0
LSB     0
UserSpecifiedSizeRatio  1
isFallingEdgeSensitive  False
VerilogCode
isRisingEdgeSensitive   False
VHDLCode
DrawAnalog      0
PROPS!
BooleanEquation
!
NegTolerance    0
PosTolerance    0
SIGNAL  dwb_ADR_O
UserSpecifiedSizeRatio  1
DIRECTION       output
VerilogCode
RADIX   hex
VHDLCode
GRID    0        1       0        1       0        16711680        0        0
PROPS!
ENDGRID -1
E0      0        15625   15625           1       0        DR      0
Clock
!
EdgeLevel       neg
Set     Not Used
MARKER  MARK0
Clear   Not Used
ATTACH  dwb_DAT_O       NULL    S4
ClockEnable     Not Used
TIME    7500.000000
ActiveLowSetClear       True
RELATIVETIME    0.000000
AsyncSetClear   True
DISPLAYAS       5
ActiveLowClockEnable    True
MARKERTYPE      Timebreak(Curved)
VhdlType        std_logic
WHILERETURN
VerilogType     wire
REPEATNUMBER
SystemCType     sc_logic
SNAPTO  0
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
COMPRESSTIME    0.000000
StateEquation   Hex(Inc(0,2,5))
COMMENT
HighVoltageThreshold    5
!
LowVoltageThreshold     0
LSB     0
ўџ
MSB     31
џџџџQН…<ѓбЅ=Kuy›Timing DiagramTiming.Document.1є9ВqTiming Diagramўџ
SignalActionType        0
џџџџРFMicrosoft Visio DrawingVISIO 6.0 ShapesVisio.Drawing.6є9ВqTiming Diagram Editor v7.1g - Output File
isFallingEdgeSensitive  False
isRisingEdgeSensitive   True
PROJECT
DrawAnalog      0
BaseTimeUnit    1
BooleanEquation
DisplayTimeUnit 2
NegTolerance    0
TextGridX       250.000000
PosTolerance    0
TextGridY       6
UserSpecifiedSizeRatio  1
EdgeGridX       250.000000
VerilogCode
ImportStartTime 0.000000
VHDLCode
ImportEndTime   281474976710656.000000
VhdlMapping     DefaultVhdlMapping
TimePerPixel    6.497175
PROPS!
Visible DELAYS  SETUPS  HOLDS   SAMPLES TEXT    HIDDENATTACHMENTS       CRITICALPATHS   GRIDLINES       UNCERTAINTY
E0      V       -1      -1              1       0        DR      0
ColWidths       144,216,288,423,488
E1      X       3123    3123            1       0        DR      0
ScrollPos       0.000000,0.000000,0.000000
E2      V       13125   13125     A0    1       0        DR      0
DefDelayRule    1
E3      X       13625   13625           1       0        DR      0
NoEventOverlap  NO
E4      V       23125   23125     A4    1       0        DR      0
SigLabelFontHeight      10
E5      X       23625   23625           1       0        DR      0
LabelHeight     12
E6      V       33125   33125     A8    1       0        DR      0
LoadLibsToMem   1
E7      X       33625   33625           1       0        DR      0
UseFullPathNames        1
E8      V       43125   43125     A12   1       0        DR      0
LibPath
E9      X       43750   43750           1       0        DR      0
EntireTime      YES
E10     V       53125   53125    A0     1       0        DR      0
PrintTimeSpecified      NO
E11     X       53750   53750           1       0        DR      0
FromTime        0
!
ToTime  5.75
AllSignals      YES
SIGNAL  dwb_DAT_I
CurrSelSigs     NO
DIRECTION       input
PrintTo 2
RADIX   hex
PrintFileName   C:\DOCS\reset_gated.wmf
GRID    0        1       0        1       0        16711680        0        0
PreviewInterchange      YES
ENDGRID -1
PreviewTIFF5    NO
Clock
UseMargins      NO
EdgeLevel       neg
PrintTimeLine   NO
Set     Not Used
PrintBorderBox  YES
Clear   Not Used
PrintSigNames   YES
ClockEnable     Not Used
PrintSigNamesOnEachPage YES
ActiveLowSetClear       True
AddPreviewToEPS NO
AsyncSetClear   True
PreviewRes      150
ActiveLowClockEnable    True
MarginLR        1.25
VhdlType        std_logic
MifImageWidth   6.00
VerilogType     wire
MarginTB        Auto
SystemCType     sc_logic
Header  %d %t;%f;%p
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Footer
StateEquation   Hex(Inc(0,2,5))
ScaleHorz       100
HighVoltageThreshold    5
ScaleVert       100
LowVoltageThreshold     0
ScaleHPage      1
LSB     0
PrintImage      DIAGRAM
MSB     31
DefaultTimingModel      minmax
SignalActionType        0
DefaultClock    Unclocked
isFallingEdgeSensitive  False
DefaultEdgeLevel        neg
isRisingEdgeSensitive   False
DefaultSet      Not Used
DrawAnalog      0
DefaultClear    Not Used
BooleanEquation
DefaultClockEnable      Not Used
NegTolerance    0
DefaultClockToOutLH     0
PosTolerance    0
DefaultClockToOutHL     0
UserSpecifiedSizeRatio  1
DefaultSetup    0
VerilogCode
DefaultHold     0
VHDLCode
DefaultRegStartupState  unknown
VhdlMapping     DefaultVhdlMapping
DefaultPodSize  8
PROPS!
DefaultActiveLowSetClear        True
E0      X       11250   11250           1       0        DR      0
DefaultAsyncSetClear    True
E1      V       13125   13125   D0      1       0        DR      0
DefaultActiveLowClockEnable     True
E2      X       21250   21250           1       0        DR      0
SigLabelFontHeight      10
E3      V       23125   23125   D4      1       0        DR      0
PROPS!
E4      X       31250   31250           1       0        DR      0
!
E5      V       33125   33125   D8      1       0        DR      0
E6      X       41250   41250           1       0        DR      0
STYLE
E7      V       43125   43125   D12     1       0        DR      0
DefaultFont     USER    {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
E8      X       53750   53750           1       0        DR      0
DrawWndFont     DEFAULT
!
DrawWndColor    DEFAULT
GridWndFont     DEFAULT
SIGNAL  dwb_DAT_O
GridWndColor    DEFAULT
DIRECTION       output
LabelWndFont    USER    {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
RADIX   hex
LabelWndColor   DEFAULT
GRID    0        1       0        1       0        16711680        0        0
ParamDispPref   0
ENDGRID -1
ParamWndCellDisplay     0
Clock   Unclocked
CustDispString  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
EdgeLevel       neg
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
Set     Not Used
MarkerDispPref  4
Clear   Not Used
MarkerCustDispString    %n v=%mv,%Mv d=%md %t
ClockEnable     Not Used
MarkerCustomDisplayStringRTF    {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
ActiveLowSetClear       True
SignalColor     2
AsyncSetClear   True
LabelOffset     4
ActiveLowClockEnable    True
BusDisplay      0
VhdlType        std_logic
WaveFormWidth   0.500000
VerilogType     wire
WaveFormColor   0
SystemCType     sc_logic
InputWaveFormColor      16711680
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
SlantedEdges    1
StateEquation   Hex(Inc(0,2,5))
SlantAngle      75
HighVoltageThreshold    5
RightJustifySigNames    1
LowVoltageThreshold     0
AutosplitEnabled        1
LSB     0
AutosplitChar   _
MSB     31
DynamSizedSignals       1
SignalActionType        0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
DIAGRAMTESTBENCHSETTINGS
DrawAnalog      0
FilesBeforeDiagramModel
BooleanEquation
FilesInsideDiagramModelDeclarationSection
NegTolerance    0
AbortHdlCodeEnabled     1
PosTolerance    0
DelayHdlCodeEnabled     1
UserSpecifiedSizeRatio  1
SampleHdlCodeEnabled    1
VerilogCode
MarkerHdlCodeEnabled    1
VHDLCode
VerboseSamples  0
PROPS!
VerboseDelays   0
E0      X       3125    3125            1       0        DR      0
VerboseFileInput        0
E1      V       3126    3126    D0      1       0        DR      0
VerboseSequenceVerification     0
E2      X       43125   43125           1       0        DR      0
IncludeDelayTime        1
E3      V       53124   53124     D0    1       0        DR      0
ExecuteFromTopLevel     1
E4      X       53750   53750           1       0        DR      0
TimeOutInDiagramLengths 0
!
DefaultCycleClock       Unclocked
DefaultCycleEdge        neg
SIGNAL  dwb_WE_O
!
DIRECTION       output
RADIX   hex
MACROS
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock   Unclocked
CORGROUP        $$CLK_I_BufferRising
EdgeLevel       neg
Percent 100
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
CORGROUP        $$CLK_I_BufferFalling
ActiveLowSetClear       True
Percent 100
AsyncSetClear   True
!
ActiveLowClockEnable    True
VhdlType        std_logic
CORGROUP        $$CLK_I_BufferRisingFalling
VerilogType     wire
Percent 100
SystemCType     sc_logic
!
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
CORGROUP        $$CLK_I_BufferRising
HighVoltageThreshold    5
Percent 100
LowVoltageThreshold     0
!
SignalActionType        0
MSB     0
CORGROUP        $$CLK_I_BufferFalling
LSB     0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   False
DrawAnalog      0
CORGROUP        $$CLK_I_BufferRisingFalling
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$CLK_I_BufferRising
VerilogCode
Percent 100
VHDLCode
!
PROPS!
E0      X       3126    3126            1       0        DR      0
CORGROUP        $$CLK_I_BufferFalling
E1      0        13125   13125           1       0        DR      0
Percent 100
E2      X       13625   13625           1       0        DR      0
!
E3      0        23125   23125           1       0        DR      0
E4      X       23625   23625           1       0        DR      0
CORGROUP        $$CLK_I_BufferRisingFalling
E5      0        33125   33125           1       0        DR      0
Percent 100
E6      X       33750   33750           1       0        DR      0
!
E7      0        43125   43125           1       0        DR      0
E8      1       53125   53125           1       0        DR      0
CORGROUP        $$CLK_I_BufferRising
E9      0        53750   53750           1       0        DR      0
Percent 100
!
!
SIGNAL  dwb_SEL_O
CORGROUP        $$CLK_I_BufferFalling
DIRECTION       output
Percent 100
RADIX   hex
!
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
CORGROUP        $$CLK_I_BufferRisingFalling
Clock   Unclocked
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$CLK_I_BufferRising
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$CLK_I_BufferFalling
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$CLK_I_BufferRisingFalling
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
LSB     0
CORGROUP        $$CLK_I_BufferRising
MSB     3
Percent 100
SignalActionType        0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
CORGROUP        $$CLK_I_BufferFalling
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$CLK_I_BufferRisingFalling
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
PROPS!
CORGROUP        $$CLK_RISC_BufferRising
E0      X       3123    3123            1       0        DR      0
Percent 100
E1      V       13125   13125       Valid       1       0        DR      0
!
E2      X       13625   13625           1       0        DR      0
E3      V       23125   23125     Valid 1       0        DR      0
CORGROUP        $$CLK_RISC_BufferFalling
E4      X       23625   23625           1       0        DR      0
Percent 100
E5      V       33125   33125     Valid 1       0        DR      0
!
E6      X       33625   33625           1       0        DR      0
E7      V       43125   43125     Valid 1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRisingFalling
E8      X       43750   43750           1       0        DR      0
Percent 100
E9      V       53124   53124      Valid        1       0        DR      0
!
E10     X       53750   53750           1       0        DR      0
!
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
SIGNAL  dwb_STB_O
!
DIRECTION       output
RADIX   hex
CORGROUP        $$CLK_RISC_BufferFalling
GRID    0        1       0        1       0        16711680        0        0
Percent 100
ENDGRID -1
!
Clock   Unclocked
EdgeLevel       neg
CORGROUP        $$CLK_RISC_BufferRisingFalling
Set     Not Used
Percent 100
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CORGROUP        $$CLK_I_BufferRising
AsyncSetClear   True
Percent 100
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
CORGROUP        $$CLK_I_BufferFalling
SystemCType     sc_logic
Percent 100
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
CORGROUP        $$CLK_I_BufferRisingFalling
LowVoltageThreshold     0
Percent 100
SignalActionType        0
!
MSB     0
LSB     0
CORGROUP        $$CLK_RISC_BufferRising
isFallingEdgeSensitive  False
Percent 100
isRisingEdgeSensitive   False
!
DrawAnalog      0
BooleanEquation
CORGROUP        $$CLK_RISC_BufferFalling
NegTolerance    0
Percent 100
PosTolerance    0
!
UserSpecifiedSizeRatio  1
VerilogCode
CORGROUP        $$CLK_RISC_BufferRisingFalling
VHDLCode
Percent 100
PROPS!
!
E0      0        3750    3750            1       0        DR      0
E1      1       13125   13125           1       0        DR      0
CORGROUP        $$CLK_I_BufferRising
E2      0        13625   13625           1       0        DR      0
Percent 100
E3      1       23125   23125           1       0        DR      0
!
E4      0        23625   23625           1       0        DR      0
E5      1       33125   33125           1       0        DR      0
CORGROUP        $$CLK_I_BufferFalling
E6      0        33625   33625           1       0        DR      0
Percent 100
E7      1       43124   43124           1       0        DR      0
!
E8      0        44466   44466           1       0        DR      0
E9      1       53124   53124           1       0        DR      0
CORGROUP        $$CLK_I_BufferRisingFalling
E10     X       53750   53750           1       0        DR      0
Percent 100
!
!
SIGNAL  dwb_ACK_I
CORGROUP        $$CLK_RISC_BufferRising
DIRECTION       input
Percent 100
RADIX   hex
!
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
CORGROUP        $$CLK_RISC_BufferFalling
Clock   Unclocked
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$CLK_RISC_BufferRisingFalling
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$CLK_I_BufferRising
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$CLK_I_BufferFalling
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
SignalActionType        0
CORGROUP        $$CLK_I_BufferRisingFalling
MSB     0
Percent 100
LSB     0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
CORGROUP        $$CLK_RISC_BufferRising
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$CLK_RISC_BufferFalling
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
PROPS!
CORGROUP        $$CLK_RISC_BufferRisingFalling
E0      0        11250   11250           1       0        DR      0
Percent 100
E1      1       13125   13125           1       0        DR      0
!
E2      0        21250   21250           1       0        DR      0
E3      1       23125   23125           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRising
E4      0        31250   31250           1       0        DR      0
Percent 100
E5      1       33125   33125           1       0        DR      0
!
E6      0        41250   41250           1       0        DR      0
E7      1       43124   43124           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferFalling
E8      0        51875   51875           1       0        DR      0
Percent 100
E9      1       53124   53124           1       0        DR      0
!
E10     X       53750   53750           1       0        DR      0
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
SIGNAL  dwb_CYC_O
!
DIRECTION       output
RADIX   hex
CORGROUP        $$CLK_RISC_BufferRising
GRID    0        1       0        1       0        16711680        0        0
Percent 100
ENDGRID -1
!
Clock   Unclocked
EdgeLevel       neg
CORGROUP        $$CLK_RISC_BufferFalling
Set     Not Used
Percent 100
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CORGROUP        $$CLK_RISC_BufferRisingFalling
AsyncSetClear   True
Percent 100
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
CORGROUP        $$CLK_RISC_BufferRising
SystemCType     sc_logic
Percent 100
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
CORGROUP        $$CLK_RISC_BufferFalling
LowVoltageThreshold     0
Percent 100
SignalActionType        0
!
MSB     0
LSB     0
CORGROUP        $$CLK_RISC_BufferRisingFalling
isFallingEdgeSensitive  False
Percent 100
isRisingEdgeSensitive   False
!
DrawAnalog      0
BooleanEquation
CORGROUP        $$CLK_RISC_BufferRising
NegTolerance    0
Percent 100
PosTolerance    0
!
UserSpecifiedSizeRatio  1
VerilogCode
CORGROUP        $$CLK_RISC_BufferFalling
VHDLCode
Percent 100
PROPS!
!
E0      0        3125    3125            1       0        DR      0
E1      1       43125   43125           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRisingFalling
E2      0        44375   44375           1       0        DR      0
Percent 100
E3      1       53125   53125           1       0        DR      0
!
E4      0        53750   53750           1       0        DR      0
!
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
SIGNAL  dwb_ERR_I
!
DIRECTION       input
RADIX   hex
CORGROUP        $$CLK_RISC_BufferFalling
GRID    0        1       0        1       0        16711680        0        0
Percent 100
ENDGRID -1
!
Clock   Unclocked
EdgeLevel       neg
CORGROUP        $$CLK_RISC_BufferRisingFalling
Set     Not Used
Percent 100
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CORGROUP        $$CLK_RISC_BufferRising
AsyncSetClear   True
Percent 100
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
CORGROUP        $$CLK_RISC_BufferFalling
SystemCType     sc_logic
Percent 100
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
CORGROUP        $$CLK_RISC_BufferRisingFalling
LowVoltageThreshold     0
Percent 100
SignalActionType        0
!
MSB     0
LSB     0
CORGROUP        $$CLK_RISC_BufferRising
isFallingEdgeSensitive  False
Percent 100
isRisingEdgeSensitive   False
!
DrawAnalog      0
BooleanEquation
CORGROUP        $$CLK_RISC_BufferFalling
NegTolerance    0
Percent 100
PosTolerance    0
!
UserSpecifiedSizeRatio  1
VerilogCode
CORGROUP        $$CLK_RISC_BufferRisingFalling
VHDLCode
Percent 100
PROPS!
!
E0      0        53125   53125           1       0        DR      0
E1      X       53750   53750           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRising
!
Percent 100
!
SIGNAL  dwb_RTY_I
DIRECTION       input
CORGROUP        $$CLK_RISC_BufferFalling
RADIX   hex
Percent 100
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock   Unclocked
CORGROUP        $$CLK_RISC_BufferRisingFalling
EdgeLevel       neg
Percent 100
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
CORGROUP        $$CLK_RISC_BufferRising
ActiveLowSetClear       True
Percent 100
AsyncSetClear   True
!
ActiveLowClockEnable    True
VhdlType        std_logic
CORGROUP        $$CLK_RISC_BufferFalling
VerilogType     wire
Percent 100
SystemCType     sc_logic
!
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
CORGROUP        $$CLK_RISC_BufferRisingFalling
HighVoltageThreshold    5
Percent 100
LowVoltageThreshold     0
!
SignalActionType        0
MSB     0
CORGROUP        $$CLK_RISC_BufferRising
LSB     0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   False
DrawAnalog      0
CORGROUP        $$CLK_RISC_BufferFalling
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$CLK_RISC_BufferRisingFalling
VerilogCode
Percent 100
VHDLCode
!
PROPS!
E0      0        53125   53125           1       0        DR      0
CORGROUP        $$clk_risc_BufferRising
E1      X       53750   53750           1       0        DR      0
Percent 100
!
!
MARKER  MARK1
CORGROUP        $$clk_risc_BufferFalling
ATTACH  dwb_SEL_O       NULL    S6
Percent 100
TIME    17500.000000
!
RELATIVETIME    0.000000
DISPLAYAS       5
CORGROUP        $$clk_risc_BufferRisingFalling
MARKERTYPE      Timebreak(Curved)
Percent 100
WHILERETURN
!
REPEATNUMBER
SNAPTO  0
CORGROUP        $$clk_risc_BufferRising
COMPRESSTIME    0.000000
Percent 100
COMMENT
!
!
CORGROUP        $$clk_risc_BufferFalling
MARKER  MARK2
Percent 100
ATTACH  dwb_STB_O       NULL    S7
!
TIME    27500.000000
RELATIVETIME    0.000000
CORGROUP        $$clk_risc_BufferRisingFalling
DISPLAYAS       5
Percent 100
MARKERTYPE      Timebreak(Curved)
!
WHILERETURN
REPEATNUMBER
CORGROUP        $$clk_risc_BufferRising
SNAPTO  0
Percent 100
COMPRESSTIME    0.000000
!
COMMENT
!
CORGROUP        $$clk_risc_BufferFalling
Percent 100
MARKER  MARK3
!
ATTACH  dwb_STB_O       NULL    S7
TIME    37500.000000
CORGROUP        $$clk_risc_BufferRisingFalling
RELATIVETIME    0.000000
Percent 100
DISPLAYAS       5
!
MARKERTYPE      Timebreak(Curved)
WHILERETURN
CORGROUP        $$clk_risc_BufferRising
REPEATNUMBER
Percent 100
SNAPTO  0
!
COMPRESSTIME    0.000000
COMMENT
CORGROUP        $$clk_risc_BufferFalling
!
Percent 100
!
MARKER  MARK0
ATTACH  dwb_CLK_I       NULL    S1
CORGROUP        $$clk_risc_BufferRisingFalling
TIME    7500.000000
Percent 100
RELATIVETIME    0.000000
!
DISPLAYAS       5
MARKERTYPE      Timebreak(Curved)
CORGROUP        $$clk_risc_BufferRising
WHILERETURN
Percent 100
REPEATNUMBER
!
SNAPTO  0
COMPRESSTIME    0.000000
CORGROUP        $$clk_risc_BufferFalling
COMMENT
Percent 100
!
!
MARKER  MARK4
CORGROUP        $$clk_risc_BufferRisingFalling
ATTACH  dwb_ADR_O       NULL    S2
Percent 100
TIME    47500.000000
!
RELATIVETIME    0.000000
DISPLAYAS       5
CORGROUP        $$clk_risc_BufferRising
MARKERTYPE      Timebreak(Curved)
Percent 100
WHILERETURN
!
REPEATNUMBER
SNAPTO  0
CORGROUP        $$clk_risc_BufferFalling
COMPRESSTIME    0.000000
Percent 100
COMMENT
!
!
CORGROUP        $$clk_risc_BufferRisingFalling
Timing Diagram Editor v7.1g - Output File
Percent 100
!
PROJECT
BaseTimeUnit    1
CLOCK   clk_risc
DisplayTimeUnit 2
PERIODE 1
TextGridX       625.000000
DUTY    50
TextGridY       6
OFFSETE 4.5
EdgeGridX       625.000000
INITIAL HIGH
ImportStartTime 0.000000
MAXUNCERTRISE   0
ImportEndTime   281474976710656.000000
MAXUNCERTFALL   0
TimePerPixel    50.000000
MINUNCERTRISE   0
Visible DELAYS  SETUPS  HOLDS   SAMPLES TEXT    HIDDENATTACHMENTS       CRITICALPATHS   GRIDLINES       UNCERTAINTY
MINUNCERTFALL   0
ColWidths       144,216,288,423,488
JRISEE  0
ScrollPos       0.000000,0.000000,0.000000
JFALLE  0
DefDelayRule    1
GRID    1       1       0        2       2       16711680        0        0
NoEventOverlap  NO
ENDGRID -1
SigLabelFontHeight      10
DIRECTION       input
LabelHeight     12
MASTERCLOCK     None
LoadLibsToMem   1
Clock   Unclocked
UseFullPathNames        1
EdgeLevel       neg
LibPath
Set     Not Used
EntireTime      YES
Clear   Not Used
PrintTimeSpecified      NO
ClockEnable     Not Used
FromTime        0
ActiveLowSetClear       True
ToTime  43.75
AsyncSetClear   True
AllSignals      YES
ActiveLowClockEnable    True
CurrSelSigs     NO
VhdlType        std_logic
PrintTo 2
VerilogType     wire
PrintFileName   C:\DOCS\wb_readblock_typ.wmf
SystemCType     sc_logic
PreviewInterchange      YES
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
PreviewTIFF5    NO
StateEquation   Hex(Inc(0,2,5))
UseMargins      NO
HighVoltageThreshold    5
PrintTimeLine   NO
LowVoltageThreshold     0
PrintBorderBox  YES
MSB     0
PrintSigNames   YES
LSB     0
PrintSigNamesOnEachPage YES
isFallingEdgeSensitive  False
AddPreviewToEPS NO
isRisingEdgeSensitive   True
PreviewRes      150
DrawAnalog      0
MarginLR        1.25
BooleanEquation
MifImageWidth   6.00
NegTolerance    0
MarginTB        Auto
PosTolerance    0
Header  %d %t;%f;%p
UserSpecifiedSizeRatio  1
Footer
VerilogCode
ScaleHorz       100
VHDLCode
ScaleVert       100
PROPS!
ScaleHPage      1
E5      1       7000    7000            1       0        DR      0
PrintImage      DIAGRAM
E6      0        7500    7500            1       0        DR      0
DefaultTimingModel      minmax
E7      1       8000    8000            1       0        DR      0
DefaultClock    Unclocked
E9      1       9000    9000            1       0        DR      0
DefaultEdgeLevel        neg
!
DefaultSet      Not Used
DefaultClear    Not Used
SIGNAL  rst
DefaultClockEnable      Not Used
DIRECTION       input
DefaultClockToOutLH     0
RADIX   hex
DefaultClockToOutHL     0
GRID    0        1       0        1       0        16711680        0        0
DefaultSetup    0
ENDGRID -1
DefaultHold     0
Clock   Unclocked
DefaultRegStartupState  unknown
EdgeLevel       neg
DefaultPodSize  8
Set     Not Used
DefaultActiveLowSetClear        True
Clear   Not Used
DefaultAsyncSetClear    True
ClockEnable     Not Used
DefaultActiveLowClockEnable     True
ActiveLowSetClear       True
SigLabelFontHeight      10
AsyncSetClear   True
PROPS!
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
STYLE
SystemCType     sc_logic
DefaultFont     USER    {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
DrawWndFont     DEFAULT
StateEquation   Hex(Inc(0,2,5))
DrawWndColor    DEFAULT
HighVoltageThreshold    5
GridWndFont     DEFAULT
LowVoltageThreshold     0
GridWndColor    DEFAULT
SignalActionType        0
LabelWndFont    USER    {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
MSB     0
LabelWndColor   DEFAULT
LSB     0
ParamDispPref   0
isFallingEdgeSensitive  False
ParamWndCellDisplay     0
isRisingEdgeSensitive   False
CustDispString  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
DrawAnalog      0
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
BooleanEquation
MarkerDispPref  4
NegTolerance    0
MarkerCustDispString    %n v=%mv,%Mv d=%md %t
PosTolerance    0
MarkerCustomDisplayStringRTF    {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
UserSpecifiedSizeRatio  1
SignalColor     2
VerilogCode
LabelOffset     2
VHDLCode
BusDisplay      0
PROPS!
WaveFormWidth   0.500000
E0      0        1750    1750            1       0        DR      0
WaveFormColor   0
E1      1       3750    3750            1       0        DR      0
InputWaveFormColor      16711680
E2      0        5750    5750            1       0        DR      0
SlantedEdges    1
!
SlantAngle      75
RightJustifySigNames    1
SIGNAL  dbg_dat_o
AutosplitEnabled        1
DIRECTION       output
AutosplitChar   _
RADIX   hex
DynamSizedSignals       1
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock
DIAGRAMTESTBENCHSETTINGS
EdgeLevel       neg
FilesBeforeDiagramModel
Set     Not Used
FilesInsideDiagramModelDeclarationSection
Clear   Not Used
AbortHdlCodeEnabled     1
ClockEnable     Not Used
DelayHdlCodeEnabled     1
ActiveLowSetClear       True
SampleHdlCodeEnabled    1
AsyncSetClear   True
MarkerHdlCodeEnabled    1
ActiveLowClockEnable    True
VerboseSamples  0
VhdlType        std_logic
VerboseDelays   0
VerilogType     wire
VerboseFileInput        0
SystemCType     sc_logic
VerboseSequenceVerification     0
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
IncludeDelayTime        1
StateEquation   Hex(Inc(0,2,5))
ExecuteFromTopLevel     1
HighVoltageThreshold    5
TimeOutInDiagramLengths 0
LowVoltageThreshold     0
DefaultCycleClock       Unclocked
LSB     0
DefaultCycleEdge        neg
MSB     31
!
SignalActionType        0
isFallingEdgeSensitive  False
MACROS
isRisingEdgeSensitive   True
!
DrawAnalog      0
BooleanEquation
CORGROUP        $$CLK_I_BufferRising
NegTolerance    0
Percent 100
PosTolerance    0
!
UserSpecifiedSizeRatio  1
VerilogCode
CORGROUP        $$CLK_I_BufferFalling
VHDLCode
Percent 100
VhdlMapping     DefaultVhdlMapping
!
PROPS!
E0      X       1750    1750            1       0        DR      0
CORGROUP        $$CLK_I_BufferRisingFalling
E1      V       4750    4750    0x0     1       0        DR      0
Percent 100
E2      V       5750    5750    0x4     1       0        DR      0
!
!
CORGROUP        $$CLK_I_BufferRising
SIGNAL  dbg_op_i
Percent 100
DIRECTION       input
!
RADIX   hex
GRID    0        1       0        1       0        16711680        0        0
CORGROUP        $$CLK_I_BufferFalling
ENDGRID -1
Percent 100
Clock   Unclocked
!
EdgeLevel       neg
Set     Not Used
CORGROUP        $$CLK_I_BufferRisingFalling
Clear   Not Used
Percent 100
ClockEnable     Not Used
!
ActiveLowSetClear       True
AsyncSetClear   True
CORGROUP        $$CLK_I_BufferRising
ActiveLowClockEnable    True
Percent 100
VhdlType        std_logic
!
VerilogType     wire
SystemCType     sc_logic
CORGROUP        $$CLK_I_BufferFalling
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Percent 100
StateEquation   Hex(Inc(0,2,5))
!
HighVoltageThreshold    5
LowVoltageThreshold     0
CORGROUP        $$CLK_I_BufferRisingFalling
SignalActionType        0
Percent 100
MSB     3
!
LSB     0
isFallingEdgeSensitive  False
CORGROUP        $$CLK_I_BufferRising
isRisingEdgeSensitive   False
Percent 100
DrawAnalog      0
!
BooleanEquation
NegTolerance    0
CORGROUP        $$CLK_I_BufferFalling
PosTolerance    0
Percent 100
UserSpecifiedSizeRatio  1
!
VerilogCode
VHDLCode
CORGROUP        $$CLK_I_BufferRisingFalling
PROPS!
Percent 100
E0      V       5750    5750    READ PC 0x0     1       0        DR      0
!
!
CORGROUP        $$CLK_I_BufferRising
MARKER  MARK0
Percent 100
ATTACH  rst     NULL    S1
!
TIME    2750.000000
RELATIVETIME    0.000000
CORGROUP        $$CLK_I_BufferFalling
DISPLAYAS       5
Percent 100
MARKERTYPE      Timebreak(Curved)
!
WHILERETURN
REPEATNUMBER
CORGROUP        $$CLK_I_BufferRisingFalling
SNAPTO  0
Percent 100
COMPRESSTIME    0.000000
!
COMMENT
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
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Percent 100
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Percent 100
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Percent 100
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CORGROUP        $$CLK_RISC_BufferRisingFalling
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CORGROUP        $$CLK_I_BufferRisingFalling
Ѓ0–jPМvПˆПуј•ујШВЗl^/ЫЦ!3оТѓПjЦBjЦ6DŒ/ž/А/ў$Q0pоФ?MdjЧ^cjЧŒ4ТЬAk[Ж~ЯЯхіˆуј$YkU1%Л1ўптУэFЛе„-(‘kp
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Percent 100
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!
KЯџџя“ЯЅЯЗЯОCЯЯсЯNЩa\п"п4пFпXпjп пВпKжпГХзяћBяTяfя_/q/œяЎяРявяфяіяй/ы/,џк­ЩaRџdџvџˆџšџЌџОџаџтџєџу*<€+/`Ш§b§b‡iAnFUЏj?|?~/ї "CЖ?Ш?ВVуaР]ї?     I„a(G
rpl/YDE@a1LOзpOћŸ#Q/ˆ­ISПGQл„BQfQaЮIq_U‚ѕ…yjŸЕ(ŸШ„Bb_(_:_/^_Ѕ/З/ЦТдQ—_Љ_†a1и_      OO-OДFСZOQo~MЮA%ФъoCХЅŽAЕšOЌOОMgy ‹N_Џr_МЬO”7ш”ZіgŸ†˜@ЊМ:oЏ,K€o-ŸXyCХЎbУddpЭddpЧСсAЭŸпŸёŸЏЏ'Џ@9ЏKЏ]ЏФvЏAЧBЫ(ŽOГЏn–ЁlХУ=#юПм?ю?6HZl•ПЏДЦŽѕ'сЖПŸŸМЏ;ŸMŸ_ŸqŸƒŸ•ŸЇŸ Я2ЯDЯVЯhЯzЯŒЯžЯАЯТЯдЯцЯјЯ
CORGROUP        $$CLK_RISC_BufferRising
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Percent 100
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CORGROUP        $$CLK_RISC_BufferFalling
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Percent 100
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CORGROUP        $$CLK_RISC_BufferRisingFalling
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Percent 100
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CORGROUP        $$CLK_I_BufferRising
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Percent 100
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CORGROUP        $$CLK_I_BufferFalling
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Percent 100
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й"k†iF1"‡9v5GeOeЋU‘rtЊМEgaЪeф‹яV ћGјqa28ŸЬeЅbrоaД0ўЅ’ЦЋ“ъЪ›­PICSRiЮщoћoё”п(ќD™['25U@ЂХR€|dїУj/oЁoГoЖVЛ-bpqє”˜\bbТe?•в0vђ(~яVиE8-?DTћ!љПX?j?|?Ž? ?В?Ф?ж?r„їС]љіЖ&OП9v*Цш]FіЖNЧѕЗЯєOЯaЮіЖ–ЧbЭЧ Яэ@€_’_Є_Ж_Ш_к_ь_TŸo ЯPпFfa№“[ЏmЏЏ€‘ЏЃЏЕЏЧЏйЏыЏyмЧџŒTъwм?@rцV+ЩзИlуЧ.П@ПRПdПvПˆП`šПЌПОПаПтП№‘РIMіЯ|п26*РŽЉдя6а]FMіЅїLїƒDІџИўMіэїЙ§\їїџжЯшЯњЯпп0п€Bп‘пfп’lюЊЂзe/Ппбпуп­/П/б/у/Јѕ/Gя tя(xќ"пИЫЯE?W?ЉяЛяЭяРпяёяџџ'џ9џ€IЌ&fџxџ*Р"ѓ€=ЯЌ&7Ћ'ƒD?>Ќ&L7=Л'V?эOџO_#_5_н?Y_k_}_?Qcu‡™шНDЫ$™OIo    \k~b(:L^p‚”І@ўК,fBvкьў/"/4/F/X/j/|/Ž/@‹yQ›yЗfХ/СVч‚јь,фFЦЗfwЖgУє"~ЗfWw#}ЦgaŒ?ž?А?Т?д?шј?
CORGROUP        $$CLK_I_BufferRisingFalling
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Percent 100
Ѕ@ујъёы№|џРљ9**ы№A-Œ3?7њѕU2ы№ы№пќчє§@ы№$РљE*7Cы№RHы№<мџ(
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U2ы№ы№пќчє§Eы№TФљЇ*7
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CORGROUP        $$CLK_RISC_BufferRising
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Percent 100
Њы№EдшЊфѓ-
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CORGROUP        $$CLK_RISC_BufferFalling
l_RcЊT„_ju
Percent 100
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!
ЬЊ_’cUф_ЉЊcUќ_Тu
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CORGROUP        $$CLK_RISC_BufferRisingFalling
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Percent 100
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CORGROUP        $$CLK_I_BufferRising
ы№ы№ы№іђёEы№чы№њём№Ujхіы№ы№ы№Uы№ы№        ы№
Percent 100
ы№Uы№ы№
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!
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CORGROUP        $$CLK_I_BufferFalling
Hы№<мџ(
Percent 100
_ы№ќпќмџ*<NчєEўыёХљ&0
ы№RVŠœЎРјвфg\"љ3q ы№мџщђујм№Єt>{˜ы№Œѓ№œцѕїѓы№
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CORGROUP        $$CLK_I_BufferRisingFalling
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Percent 100
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LhMask Function
CORGROUP        $$CLK_RISC_BufferRising

Percent 100
!

CORGROUP        $$CLK_RISC_BufferFalling
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Percent 100
L`INT [31:2] &%WXАьˆАˆН‡Ъ‚е{пrцfъYьLъ?ц2п'еЪНА%€(&%%€WXАПˆАˆГ‡Ж‚Й{ЛrНfОYПLО?Н2М'КИЕВ%€(&%%€WXА\ьдАдНгЪЮеЧпНцВъЅь˜ъ‹ц~пsеiЪbН]А\%€(&%%€WXА\ПдАдГгЖЮЙЧЛННВОЅП˜О‹Н~МsКiИbЕ^В\%€(&%%€V0Яƒ>Я>ƒ>ƒЯЯ>%€(%€RLьџџџ Arialџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџ%Td&?<РЈAРЈA&LTICPR
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!

      
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CORGROUP        $$CLK_RISC_BufferRisingFalling
               
Percent 100
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CORGROUP        $$CLK_I_BufferRising
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Percent 100
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L`InstuctionTd˜YНpЋ*ЉAЋ*ЉA˜YLTUnit&%W$к]!c`н`%€(&%%V0k€ъЮkЮъЮъ€k€kЮ%€(%€RLьџџџМ Arial
CORGROUP        $$CLK_I_BufferFalling
Percent 100





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L`Exceptions
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”Z‘‘W%€(%€%€V,†TœjœT‘j†TœT&%%€W$о фmсjс#%€(%€%€V,жь&ж&сь&ж&%€RLѓџџџ Arialџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџ%T|šUзdЋ*ЉAЋ*ЉAšUL\Data MMU          Tx eбtЋ*ЉAЋ*ЉA eL\& Cacheџџ  RLѓџџџЬ Arialџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџ%(RLѓџџџ Arialџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџ%T|A<PЋ*ЉAЋ*ЉAAL\Insn MMU TxQ8`Ћ*ЉAЋ*ЉAQL\& Cache,  &%W$џџџџY[_\X\%€(%€%€V,UQkgUQk\UgUQ&%%V0kпъ.k.ъ.ъпkпk.%€(%€RLьџџџМ Arial
     
                         
CORGROUP        $$CLK_I_BufferRisingFalling
          
Percent 100
!
                
%Tp‡
Ь$Ћ*ЉAЋ*ЉA‡
LXSystem
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CORGROUP        $$CLK_RISC_BufferRising
     
Percent 100

!
                          
                               %Tp
6Ћ*ЉAЋ*ЉA
CORGROUP        $$CLK_RISC_BufferFalling
LXSystem     & %     W$[X%€(     %€%€V,!!!%€%€V,Uk"UkU"U&     %     %€W§џџџ‚ƒ„…†‡ˆ‰Š‹ŒŽўџџџ’“”•–—˜™š›œžŸ ЁЂЃЄЅІЇЈЉЊЋЌ­ЎЏАБўџџџГЕЖЗИЙКЛМНОПРСТУФХЦЧШЩЪЫЬЭЮЯабвгдежзийклмнопрстуфхцчшщъыьэюя№ёђѓєѕіїјљњћќ§ўџ$AЪiаfЭDЭ%€( &     %     %€W$AW“TD%€( &     %     %€W$QQWTTT%€( &     %     %€W$ghmцjуjk%€( &     %     %€W$ghnŒkjk%€( &     %     %€W$gГЙŒЖjЖ%€( &     %     %€W$gрцŒуjу%€( &     %     %€W$Q•y›v˜T˜%€( & %     %V0uBѕ~u~ѕ~ѕBuBu~%€(     %€RL     ьџџџМ ArialџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџF&‚
Percent 100
WMFC`
!
`*џџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџ%      Tˆ„ZхqЋ*ЉAЋ*ЉA„Z
L`Integer EX

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CORGROUP        $$CLK_RISC_BufferRisingFalling
%
Percent 100
%V0њVDњDDVњVњ%€(
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CORGROUP        $$CLK_I_BufferRising
%V0uдѕuѕѕдuдu%€(
Percent 100
%
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!
L`Load/Store
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%
CORGROUP        $$CLK_I_BufferFalling
%V0u‰ѕХuХѕХѕ‰u‰uХ%€(
Percent 100
%
€(%€RLьџџџМ Arialџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџ%T|Š­сФЋ*ЉAЋ*ЉAŠ­L\MAC Unit
&
!
%
W$FЕLIIИ%€(
CORGROUP        $$CLK_I_BufferRisingFalling
&
Percent 100
%
!
%€W$FГ[ЙIЖXЖ%€(
%€%€V,UЋkСUЋkЖUСUЋk\њ-ќќB0-$>=K=K>>=њџџџ-№ќ-№.-ћМ Ariald??????П-2
CORGROUP        $$CLK_RISC_BufferRising
/CPU/DSPњ-ќџџ-$koъoъ k ko-№-ћМ Arial%%?W$?--2
Percent 100
A|
!
Instuction
2
Y˜Unitњ-%`н`-№њ--$kЮъЮъ€k€kЮ-№-ћМ Arial
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
-2
!
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Exceptions
њ-%ђѕђ-№њ--%`ђ-№њ--%<ЇѕЇ-№њ--%<//-№њ--%<Ї<0-№њ--%C/-№-ќ-$*@V@*@њ--%TTuT-№њ--%ˆT-№њ--%‘‘W-№--$œT‘j†TœTњ--%сjс#-№--$ж&сь&ж&-ћ
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CORGROUP        $$CLK_RISC_BufferRisingFalling
UšData MMU           2
Percent 100
e & Cache             ћ
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!
AInsn MMU  2
Q& Cache             њ- %\X\-№ --$UQk\UgUQњ- -$k.ъ.ъпkпk.-№     -ћМ Arial
CORGROUP        $$CLK_I_BufferRising
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Percent 100

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!
       -
CORGROUP        $$CLK_I_BufferFalling
2
Percent 100

!
System     њ-%X-№--$!!--$UkU"Uњ--%fЭDЭ-№њ--%TD-№њ--%TTT-№њ--%jуjk-№њ--%Œkjk-№њ--%ŒЖjЖ-№њ--%Œуjу-№њ--%v˜T˜-№њ--$u~ѕ~ѕBuBu~-№-ћМ Arial?????????????????????????-2
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CORGROUP        $$CLK_I_BufferRisingFalling
Integer EX

2
Percent 100
rPipeline
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!
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CORGROUP        $$CLK_RISC_BufferRising
Load/Store

2
Percent 100
ЃUnitњ-
-$uХѕХѕ‰u‰uХ-№
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CORGROUP        $$CLK_RISC_BufferFalling
$ы№мџ
Percent 100
Uы№џђ№,ы№8шѓ@њєсњіёъёуј§ы№Tdџ Arialъ@чєNПWingdzsЊ@чєN@tMџonotype ЏSort+чє
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CORGROUP        $$CLK_RISC_BufferRisingFalling
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Percent 100
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*Ѓ#!ю+|tKf*2|2|2|2wŠG)ОръёQUѓoˆІTMeEжttAПфъёв%_8BOTOfOxOŠOВ?Ф?ЌOш?њ7   РшъёмЛњuЛW+Р?ыаќŽиžђˆsU4‘х2–
!
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cяwo–…!3EWi{ŸБУйІВцј
Percent 100
ŸŸ.Ÿ@ŸRŸdŸvŸˆŸšŸЌŸОŸk}ЏЏ*Џ<Џ€NЏ`ЏrЏ„Џ–ЏЈЏ“еУЏеЏчЏљЏПП/ПAПSПeПwП‰П›П
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CORGROUP        $$dwb_CLK_I_BufferFalling
О‡@ћXLTCOMP047-&%W$›щ­qЄђЄh%€(%€%€V,}^ЫгЫ^Єг}^Ы^&%%€W$‘
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CORGROUP        $$dwb_CLK_I_BufferRisingFalling
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CLOCK   CLK_RISC
О‡@‘ЄLP31%%RLЮџџџ Arial%T`ЊŸэз
PERIODE 2.5
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DUTY    50
О‡@ЊŸLTlogRLпџџџ Arial&" WMFC xg use. You my not copy or distribute this su%TTюАџе
OFFSETE 0
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INITIAL HIGH
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MAXUNCERTRISE   0
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MAXUNCERTFALL   0
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MINUNCERTRISE   0
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€(RLНџџџ Arial92. All Rights ReservedArialRegularMonotype:Arial lar:Version 2.76 (Microsoft)ArialVersion 2.76ArialMTArialЈ Trademark of The Monotype Corporation plc registered in the US Pat TM Off. and elsewhere.Monotype TypographyMonotype Type Drawing S%TXIЄ’ю
MINUNCERTFALL   0
О‡@
JRISEE  0
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JFALLE  0
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GRID    0        1       0        2       0        16711680        0        0
О‡@ЉЄLP0er%RL­џџџМ Arialserif faces.  Terminal strokes are cut on the diag which helps to give the face a less mechanical appearance.  Arial is an extremely versatile family of typefaces which can be ed with equal success for text setting in reports, presentatio u%Tl™о
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DIRECTION       internal
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MASTERCLOCK     None
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Clock   Unclocked
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EdgeLevel       neg
Set     Not Used
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Clear   Not Used
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О‡@•     L`DTLB MISS t0)%-7--T„l…эЯ
ActiveLowSetClear       True
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ActiveLowClockEnable    True
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VerilogType     wire
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О     МЙЗЕГБ§АћЏјЎѕЎѓЎ№ЎэЎъЏшАхБуГсЕпЗоЙмМлОкСкФкЦ&%%€W$ъ{ќІѓ„ѓ%€(%€%€V,Ь““ѓЬ““%
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TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
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StateEquation   Hex(Inc(0,2,5))
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HighVoltageThreshold    5
LowVoltageThreshold     0
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MSB     0
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isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
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DrawAnalog      0
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MAXUNCERTFALL   0
MINUNCERTRISE   0
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DIRECTION       input
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MASTERCLOCK     None
Clock   Unclocked
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EdgeLevel       neg

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VhdlType        std_logic
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E4      V       13125   13125     A0    1       0        DR      0
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E5      X       13625   13625           1       0        DR      0
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EdgeLevel       neg
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ActiveLowSetClear       True
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ActiveLowClockEnable    True
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VhdlType        std_logic
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TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
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StateEquation   Hex(Inc(0,2,5))
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HighVoltageThreshold    5
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LSB     0
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MSB     31
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SignalActionType        0
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isFallingEdgeSensitive  False
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DrawAnalog      0
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NegTolerance    0
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UserSpecifiedSizeRatio  1
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VHDLCode
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VhdlMapping     DefaultVhdlMapping
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E2      X       21250   21250           1       0        DR      0
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E3      V       23125   23125   D4      1       0        DR      0
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E4      X       31250   31250           1       0        DR      0
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E5      V       33125   33125   D8      1       0        DR      0
e-№-№        §џџџўџџџS   
E6      X       41250   41250           1       0        DR      0

 !"#$%&'()*+,-.ўџџџ0123456789:;<=>?@ABCDEFGHIJKLMNOPQRўџџџЭUVWXYZ[\]^_`abcdefghijklўџџџnopqrstuvwxyz{|}~-ћC Arialpe:Arial Regular:Version -        2
E7      V       43125   43125   D12     1       0        DR      0
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RADIX   hex
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AsyncSetClear   True
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ActiveLowClockEnable    True
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VhdlType        std_logic
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VerilogType     wire
If you have any questio-2
SystemCType     sc_logic
шё    DMMU PAGEђ0770--4-2
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
LQFAULT)-0%)2
StateEquation   Hex(Inc(0,2,5))
ѕ    EXCEPTIONђ-+0--)40њ-
HighVoltageThreshold    5
%Є§§ђ-№       --v$9‹§ŒŒŽ
LowVoltageThreshold     0
‘
“•—™œŸЁЄЇЊЌЏБДЖЗ
Й
LSB     0
КММНН§НћМјМѕКѓЙ№ЗюЖьДъБшЏчЌцЊхЇхЄхЁхŸхœц™ч—ш•ъ“ь‘ю№ŽѓѕŒјŒћ‹§ўџўџеЭеœ.“—+,љЎDеЭеœ.“—+,љЎ"о@€HP\ht
Ќф     PagesMastersPage-1BoxDynamic connectorМ8Œ€”œЈД_VPID_ALTERNATENAMESЬтПVisio (TM) Drawing
MSB     31
ЪN„THїGMƒRэlъёщђџџџƒџіђџѓћ№јё‰€ъё€ €џРРРцццџЭЭЭГГГяššš!€fџffMMM3џ33яяяњњњ$ы№мџ
SignalActionType        0
$ы№мџ
isFallingEdgeSensitive  False
Uы№џђ№3ы№8шѓ@њєсњіёъёуј§ы№Tdџ Arialъ@чєNПWingdzsЊ@чєN@tMџonotype ЏSort+чє
њNtSymbol5Tы№?шѓа?ђџкъё шѓY@-1Uы№џђ№ы№шѓ њєы№іёъёJчє:ы№Dы№T1шѓ€ђёEWђёрћ-ъёhъчєы№Tы№T…ы№<пќŒŒцѕЎ‘*ы№Њы№ы№ы№  ы№
isRisingEdgeSensitive   False
Њы№ы№ы№
ы№ъы№“уј/РUљКпbеў
bOў…Иъё‰џ0zЎGсz„Ѕ?Ж@цѕП8@‘H2!kWЎb*Ѕ†МъёUВ
DrawAnalog      0
ь
‚+Ÿ$Ў‡РъёйPры№L/^&9^$р? { ђ№яAшk^&Ž™,™,™'%/‰v&Ž&Ц‚       *
BooleanEquation
1 yрЙ
‚€‚ )‚ЎPР? 2
U
U1ЄШŠъёэ2?§k9лЏaўBBHEЊHEHEHEHE‚HEH@ ?В>з?щ:`T2BBHEHEHEUHEHEHEHE%H@„Ьъё%O9      ЃаъёF7AOY@;P
ЬAsVsVЬA!ЇдgLTkYЗиъёї  WЭ_Wп_ќ_њ !`Г#Ј•k4l•ƒb”6u`kђWŽ     *4l
NegTolerance    0
4l•Нмъё§Б%Y№?ˆˆP:?-\
Ѓ#!ю+|QtKf2|2|2|I2wŠGОръёQAUѓoІTMeE$жttAПфъёв%_8BOTOfOxOŠOВ?Ф?HЌOш?њ7РшъёмЛXњuЛWР?ыаќŽYиžђˆsU4‘х2–
PosTolerance    0
TŸ*<N`r@„–ЂД„k!–JŽЌ§†Ž0ЌЉ–ŽPЌЌ&Ќ 3•ŽЇ
•1’ьъёїмЏюЏПП$П6Пуќw
Р[ЕiИЛњё”|Г .ф”ујМЫЏi7'04’UХP§iW?i?{4Lz№y‘2ї#TЩЖz“x•       x•
UserSpecifiedSizeRatio  1
x•Ѕx•x
VerilogCode
Ѓ0–jPМvПˆПуј•ујШВЗl^/ЫЦ!3оТѓПjЦBjЦ6DŒ/ž/А/ў$Q0pоФ?MdjЧ^cjЧŒ4ТЬAk[Ж~ЯЯхіˆуј$YkU1%Л1ўптУэFЛе„-(‘kp
йЛ   ѓ       A.$–5-Bi`яЗб#ошяЗ9)›F/Pџтљv/ˆ/п пО/u?‡2tСrПœпœЯKЖSИЯ5мЯюЧ2ћЩŒ7сбxХэпЂя#я6@хhБ$MчюuLЕhБЪ        хеƒя•яЇяЙяЫяняяяџџ%џодŠе‘ї§ѓ)Й<щ€№Oх™U‡#5G‹˜:ёмО:ѓU2ЧqЩ Ќ?Ш/к&мwџ‰ўк&Ѓє
VHDLCode
<<7сбHсщпєБУ1яOВQjСPфSсHЙQ›ywщHсAt/†/˜/YOВGТ$_щpЅ4Ыћb%F!ЂДЦ8ћqТ/д#P?˜Cђ/‰§Nм^мТqЄhшE!	@d)nм{”щrѕ1PБ1	@/ЋOq•жt}Q„”!ўnПњџЄК=ВЙkх@ЦБь…Љ{…B'ФІЩ‚XVйP_0TБNJgхй2ѕ1ѕ1”Rе5P"”Q”Q[СO"P!ДЁq’[СŠrДЁДЁюrŠqŠqг‚юqюqТЂггPБТЁТЁWт§a§a7б$VтWсХе7бPБ$q"$qPБ1q1qPБ>q">qPБKqKqPБXqXqХ2eqeqZБФ2SсobZБZБdБSВTБсQcВdБPБсQсQPБсбй1Hс[<k?шtЋaі}Yя рђMД/OOш*DљЗd3qOш/ДNkS\O’ѕИ†9ђ˜EС/Ÿх/_      ??-??=е_ч_љ_ЄКБ„ИО”МбЗ'Ур–sЯ–ŸdЈŸЉЫI,OЏ0Rн7nOВ†пЏ&ЏМкЋaЬ—сбЋaW?Oрш  //Ђ?*<N`r„w€|rŽЄБdU0{yЦ?gЁ7ЁMЗFКHЃЙ}E ‚…ŸЇЏЙЏjpЯž0UЌТХ8nодP!ЭпъЦЌ!јЭ5/G/Y/k/lŸПБПЂДчПиOЯaЯsЯКŸ—ЯоŸ№ŸЏћп
я8ЏJЏ\ЏnЏ€Џ’Џuя‡яШЏк­КS№ЏуЯП&П8ПJП\ПnП€П’ПпЖПШПкПьПўПЦ$rм#Я
PROPS!
KЯџџя“ЯЅЯЗЯОCЯЯсЯNЩa\п"п4пFпXпjп пВпKжпГХзяћBяTяfя_/q/œяЎяРявяфяіяй/ы/,џк­ЩaRџdџvџˆџšџЌџОџаџтџєџу*<€+/`Ш§b§b‡iAnFUЏj?|?~/ї "CЖ?Ш?ВVуaР]ї?     I„a(G
E0      X       43750   43750           1       0        DR      0
rpl/YDE@a1LOзpOћŸ#Q/ˆ­ISПGQл„BQfQaЮIq_U‚ѕ…yjŸЕ(ŸШ„Bb_(_:_/^_Ѕ/З/ЦТдQ—_Љ_†a1и_      OO-OДFСZOQo~MЮA%ФъoCХЅŽAЕšOЌOОMgy ‹N_Џr_МЬO”7ш”ZіgŸ†˜@ЊМ:oЏ,K€o-ŸXyCХЎbУddpЭddpЧСсAЭŸпŸёŸЏЏ'Џ@9ЏKЏ]ЏФvЏAЧBЫ(ŽOГЏn–ЁlХУ=#юПм?ю?6HZl•ПЏДЦŽѕ'сЖПŸŸМЏ;ŸMŸ_ŸqŸƒŸ•ŸЇŸ Я2ЯDЯVЯhЯzЯŒЯžЯАЯТЯдЯцЯјЯ
!
пп.п@пRпdпvпˆпšпЌпОпаптп#}яя(я:яLя^яpя‚я ”яІяИяЪямяUЩ‘л’ј"џ4џFџXџjџ@|џŽџ џВџФџˆXтџєџ*<N`r„–ЈКыяоџ&8J\n€’Є‡YУечљ////A/S/e/w/‰/›/нFсёК/ќLм/ю/??$?6?H?Z?l?~??Є?Ж?Ш?к?ь?ў?O"O4OFOXOjO|OЬ O№ФOжOшOњO__ 0_B_T_f_Н™…_—_Љ_Л_Э_п_ё_oo'o9oKo]oŽFxoЉOœoЎoРoвoфoіo,>PPfxŠœЎРвфі,> nЁ—BsgcŽМE’f†˜ЊМЮрђŸŸ(ŸєйД‘JŸ\ŸnŸ€Ÿ’ŸЄŸЖŸШŸкŸьŸўŸЏ"Џ‘OeЕOjЏ|ЏŽЏ ЏВЏ@ФЏжЏшЏњЏПїж(П:ПLП^ПpП‚П”ПІПИПЪПмПюПЬBЋ#vбX„ИT‡+С„Sb ‰Рbсz„@v6РMЯ_ЧTƒoЯЦ6РЯŸЯБЯУЯеХТтЯiэнё      пп-п?пQпcпuп‡п™пЋпНпЯпЯ­,ыЪ/-я?яeСYƒ[яЦЏ№€yя‹яяЏяСягяхьѕяџџ+џ=џOџaџsџ…џ—џЉџЛџспЦбьџ1Х„RфыщZЬsc<Ц“`Zl~еХsbЏ6-Ÿ1R#лэџ#5GYk}ЁвџІЮx;6Х/Fя%/jяI/[/m//‘/Ѓ/Е)Т/д/ц/ј/
??.?@?R?d?v?ˆ?š? YTV
|ъ?bЯO†Я2ODOVOЮЯzOђЯaqЃOЕOЧOйOыO§O_!_3_E_W_i_{__Ÿ_Б_У_е_ч_љ_oo/oAo}x^oKџ€Acroџbat Distпillerо§џ”ъo€Џщђd7XXя№6њнўы№РШсфї  рћ$ь…џѓ)ѓ/ž@oр  .0ТВr
SIGNAL  dwb_WE_O
dtујџџв        гТ'9K]o“ЅЗЩлэўрћCustom ?page 0ќ,/FнўBN#/#1>/‚/?/Q/
*2”/и/•/Ї/
*3ъ/.?ы/§/d:§hы№#џwinspoџolAcrobџat Distiџllerc:\џProgram џFiles\Adяobe\4.0џ\PDF Outџput\*.pdfмџUFы№џђ№ы№DшѓfњєёђџџъёP
рћіёъёh> ы№/Tы№6DЊъёы№’ујƒUmAшѓ@›
Р?­лПIшѓ№?ПСYзщћ{џвъёЗъёO•1@цѕ3EEbOУe„ZЁцѕ
DIRECTION       output
•ы№Hu§щђ ѓ№ящђџ˜џP№р№(:њџџŒˆџџ№{ŒW‹џ№_€qƒ•ЇЙЫеŒтџ§Qы№Generiџc box wiџth text џand connџection pџoints. Cџan be stџretched ћtoy dimwenss.mbујшПшѓр?єєўрПшДNoшПр?kш?рћєР4
№ћє№П•Hы№џђ№ыєы№DDы№іёщђђё
яє$#       фї=hчєіё-(>Tы№пќіёTE=›ујѕ‰›UAшѓј?ЇА№КЏшЏр?Q6   Ял‰uŒ` 6еўьu   і      mB>ъё0Œ0       Ќ0іё(2s@sJs&T„>ъёЁ5
ћ‰€LЇ@ўЃ‰ъё{Ё§Фђ№пўф5Аџ`7Copyriџght 1999џ Visio Cџorporatiџon.  All§  "s reseџrved.ўі‰` _SBlџ.chm!#22П448ў ‘dЌ9   l>#0>Uddтљ#3     ˆ       Фіё‰уј        ЌŠTЁ
RADIX   hex
ќ<hЋђbЪ ў
2Є61
GRID    0        1       0        1       0        16711680        0        0
g,s72‹Э4Ё?`b?ўM1^%Y?Фr?9€1M1E ;6З==з5(2ш?;z‰rA
ENDGRID -1
РўIB=OCРўq‰…,^пќ35Д/™rујVЁ:в№?@цѕгFќьAьCїMЎA КOеMмOюO@_2ЎAа#[6рвO€MZMь"3їЎA^%\$_Ÿ_Б_Z_ўи_B#[@ЗoЕ_П9Boў[(љ
^цѕtextеРы№Hы№lы№&ї'щђдяњъёџН!џРOyŽaў§єGEгџЉГфїчєFы№єџБїЭЂюы№ж#ы№,ДїПoJы№Bћ
Clock   Unclocked
ы№4ЕїЙj]\aŒk_@+ы№”kЅ3aђёќkIkў№ж•ы№ы№ѓєщђ%мёUlы№4ы№,чєїѕџЊЂъДф< @.М%@ујъё§ы№Cњ]Wы№A-3        c7"Aљі%Ulы№4ы№,чєћѕџЊЂъДф< @.М%@ујъё§ы№DCњЇзы№A-”Dњ­7њѕUžы№ы№~пќчє}@ы№dCњeђ№Bы№Rмџ0BTfЪ
ќГђ№RHы№<мџ(
EdgeLevel       neg
Hы№<мџ(
Set     Not Used
Užы№ы№~пќчє§Eы№ЌCњ'
ы№Rмџ0BјTf
DDњ4UFы№џђ№ы№Dшѓfњєёђџџъёа
рћіёъёh-Tы№пќUдUцѕ’уј”ы№[U@шѓ@—?шѓлР?ЉПIшѓ№?`Лd
мюїbu‘ЉўoqЈYkчєЈујQ‘§hђ№u23uъќі№‘`   Cџonnectorїў
Clear   Not Used
‘`ў–
ClockEnable     Not Used
œe‘1Crw
ActiveLowSetClear       True
ƒујЉUы№HыЄъё ѓ№–ўяђџ^€џџџПџўџќњј№єџїєїїЕŸ  €-џ}|5pїџ`Iоџџ`V?џпџ}ƒџ`Сџџјƒx‹їџїaŠџџѓ833џŠџџƒџ‰џџѓџџџя‰џ‡Ž‡‡џƒџљо…џ Ÿ™џЊŸџ™љ]ЉџŽЗ№ўТџ№ƒ3Яƒƒ3‚Й†“Уu…Ыџ‚ŸЉОпџ3“3?,№      ї™?№џŸ№ўG‡xpџџ№хx“^мŠџ№ƒ‹џ&яŒџŒџ
ƒДџ§Cы№This cџonnectorџ automatџically rџoutes beџtween thПe shapi
tіѕs.­bујрПєє?ќќПџшДNрП?єџ•Hы№џђ№ыєы№DŠы№ы№щђђё
@яє#      фї      іё=hчєЕы№8Tы№ пќYY9    BЊы№ы№ы№›ујFо    U@шѓј?ЊЗ
№ШПЗрПрлПP6
AsyncSetClear   True
‰u
ActiveLowClockEnable    True
я`u#`фџb€AЛ@ўќu
J ‰.Q#DB˜ц     ˜#ж‰uŒ`hр?U\hr|Suі№†‰эZ‰aкчŽ‰Жа{@-№?bH—l;'bE-h’o'—y(œ‰ъёќБ
VhdlType        std_logic
т2rЧqЧс?@ŸєIЭ kЯ?У$бЫ%П?э
VerilogType     wire
Ї@§ƒўі"VЗў*5L Н-brъё/РŒ     ^vдœvі"(2u&€.і"q28i˜vі"uh9 BdД&<O/MЃъё{
SystemCType     sc_logic
#‰§ђ№і1ўћ45ќ`џVis_SBlџ.chm!#22Ÿ474ў`џ7Copyrigџht 1999 ў@io Corpџoration.П  All $AUd3CE„ ‰\^ДŠў4
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
*Lд’1њ$b–‘24„R‹Ÿ(^[аw[D ˆZЬQi‰       ќaЈч59       Ь9”уј3ЬOп'2Х"qМ?/g;2щGеРы№Hы№lы№sї'щђ$њѕы№џН!џРOyŽaїўѓGEгЇДфїчєFўы№єОїtЛЮы№ж#ы№ФџСїB7ПB
StateEquation   Hex(Inc(0,2,5))
ѓёУїy$ы№dъђ\oъё@+ы№Дkђ€"sђёФї5тoЯў№ж•Кы№(ы№†мџсњъы№чєы№,БїПД–ы№SћЩы№Ь­їJї+B?Њы№є9ѓ=4ы№RћD5ЏїA‡3Si{"ОїБ—/ъё| ы№мџUы№џђ№ы№Pшѓxњєёђмџ№ПP4фїіёъёFчєы№Dы№Teъё€ёђyŠ
рћaъёhjчєы№ НTы№ЁпќРРцѕы№’њујƒqUIЊЂъпДф< @М%л@?шѓР?ПI?*я?Qcтљ—џ`›ьъё‘2@цѕœ№?ЎЃыЯqуяЗНuР`ЌФщђўсч&ёu ћoшы№ЁХАч     <ЈујQЂ§ђ№w!яЉw!ыќ Н`џ        Connectпorў
HighVoltageThreshold    5
Н`Wў˜"
LowVoltageThreshold     0
ž*eНU0ы№ДХœпќ'Э$Pч    Р!aы№ы№ЅЬ        ы№Ћ!ы№Jы№ы№ыєёы№ЊЫы№6$ы№!Њы№"ы№#ы№$ы№%Њы№&ь$(ы№)ы№*Њы№+ы№,ы№-ы№.
SignalActionType        0
ы№/ы№
ќцѕЋ!+1Hњ<Ѓ4РЎ7уЃ4яЎ7" 7!Ў7АЃ4aЎ71Ÿ81Ў71Ÿ81Ў71Ÿ81Ў7ЯЃ4Ћ!Ў71Ÿ8'1Ў7Ћ!Ÿ8“1Ў7'1Ÿ8/1Ў7+1Ÿ8Ћ:“1Ÿ8ЯЎ7/1Ÿ8ЫЎ731Ÿ8G1Ў7юё Ÿ89!Ў7ёŸ8Ћ:?1Ÿ8Ћ:ЫŸ8[1Ў7G1Ÿ8ФЎ7K1Ÿ8c1Ў79!Ÿ8k1Ў7S1Ÿ8w1Ў7W1 Ÿ8а!Ў7[1Ÿ81Ћ:_1"Ÿ82Ћ:c1Ÿ83Ћ:g1"Ÿ84Ћ:k1Ÿ85Ћ:я!Ÿ8S1Ў7s1Ÿ81Ў7w1Ÿ8W1Ў7{1Ÿ8g1Ў71Ÿ8я!Ў7ƒ1Ÿ8s1Ў7‡1Ÿ8‡1Ў7‹1Ÿ8‹1Ў71ЈŸ81Ў3Щя8/яCPсS1S1яs1Ds1РДQДQ!_1D_1ac1c11g1Dg11—Q—QЯœaDœa1k1k1Ћ!ѓaDѓa“111Ы‡1D‡1W1‹1‹1я!ЙaDЙa‡1а!а!œaaaжapњŸŸ0Ÿ­2яuEiafC<ђё1|ˆщfEРИ!c1ШїEцѕ!ђ5ћ)‰њцѕE–ИDЎsœџN@@|џ—Џ=щ$@Р
MSB     0
ЅаЬП
LSB     0
ЅР?p!чa„Š1H-"d1a2lЂЄр(?1NІ<ў›Уs1Ђ<<Х<цѕј№-?{ŸџџяlН1а!>SТUцѕ1IEћ/R
3‰УžPЁŠŠ–цѕ‹рbЛІyЕђ5‰ПЄ{ГАbПТК,EзПхіq41ƒ1ШўБтљ1,E(П™уја!Ш@ЏqЙ›Ѓъё`СЙЅdmЯ@Ÿ‘ЯbЂqЇqЈbЂьЯC`СуlЬЄР„Я–Юђ5lЯ8пJп_ТАiлІ€п’л/1АbЁШъ–џFFECTIVEџ ADDRESSCj45/G/уј•уј *NЄ\яЮ 3zтѓЉПѓ&ѓ&˜ЦХбi4я*яуј”уј_1NЋўя'2Чq
isFallingEdgeSensitive  False
џрМEР#UT˜ЯуmŸŸщЯЃŸЕŸ№ЧŸйŸыŸ§“ј"ў/W{в
isRisingEdgeSensitive   False
ЅшЖ
DrawAnalog      0
BooleanEquation
ЅиЖњ.Џ@ЏRЏ    !Q,lЃ4‡рG–dџуУЌ?[mЙЃр?Фр9№яA|0ІЏTу ХЏзЏл.ѕЏПП+П=ПOП§ПsПZоі П‡фђЩПbТіПЯЯ,Я>ЯPЯbЯъќчіЬпžЯi/ТЯ/цУ4ўХш/пўј№Ф/Qп?юњ;?@”п_?мј|?еп 5;№лПVPN 0
NegTolerance    0
њ11
PosTolerance    0
F...Gџ2DџTLB_SETS-1Ђт=ёH*ƒ'"€HКщ.ёЁ{ёкяU8kUЄќэџoBЙЅцфкE‹OJ1ѕцфžјјя  G]5цф1НKU7RЕœGсЇяЙя8яЏФcяR›Z!zя[ї§—хїх„ЛБU?ўьa`™ kI”P_b_
1ˆ
_‘fa{ёџ*є]59џKџ]џoџџ@“џЅџЗџ§ч№Яќєпўфёџ[ЊрvЂkvHZš~ЂTеiСг…Вaё'9Kљo‘vœОР”фŸ//,/>/P/Ђ?%x/Ž?Ѓ/и#zТ/д/kгЏ?(?ёŸL?RЏ${rЏ?–ЏxГЏб?
UserSpecifiedSizeRatio  1
зЅJь;Pћ21БO<Г1Б!G2RМ+GВoФoYOpoOOџOЅOU)ЦПиПоO№OЭH_oo~__Ђ_Д_Ц_и_ъ_ZЯlЯ o2oDd^aEбSlEбеЇpo‚o”gnгЄoП‘Пкoўьn\"з9N'џ@@|џ—=щ%$
~а(u'vР1C`U0јС3wцЄ.ј1Zщк“Ь“ХpйTнќ|б^a(:L^p‚0ŸІmџЪ‘џыќuџеі)Ÿ;ŸMŸ_ŸqŸƒŸ•Ÿ!|*цџЏбŸ|ѕŸ Ѓwяњ%ћ?;рз„Џ/1ъNЧЏ rxПГ  ь;SТ €б
VerilogCode
пп€ЯI˜Я[/0ОЯо)q-AXЯ`$/6,ВП_щ<Я^aSaOSlSS|пŽп”g€SВпФпжпшпњпр
VHDLCode
юќ"юь4яFяXяjъ42FŠяœяЎяфuS   дяцяЉE;1џџ(џ:џLџ^џ‚џ(_м6ЏџU_гџ+_їџ_-?QcЕь8’ЁЖъ:еч;G;H3ЃЖo'Ь_б^ooщ=   Ѓ-к8JфіТS_бцAy1_мшcцE7?‹к+um9ХPаaБ$­!кIEб4@оE{уСCEбЭuА9“фПp‰\ч8ё€јП"ў/{вд6ПцяЄР:uЈ…   РPмkRAuˆ0`u^јР`€Ag ўг‚—u
лр‡YцAˆ1’–ыnhИфИDЎЏsœNфЉрРП%rуtк–„Rя@ћБpИ5%Eа`—€і€@z3цZ’`Ÿrž—‚5"’Є&К”’5"
PROPS!
’в—œхhуSYVЈ…яР2r
Тс?@ЗŸєI Я?ЄбVЅП?ФŒРBuУ@й`m@ЁCўDЂuўy0`
E0      X       3125    3125            1       0        DR      0
зЃp=+
E1      1       3126    3126            1       0        DR      0
зW П™8&Hœ9фК-‚…kxОД0Й…ыQИže#œ"У(
х€ЇчHчСркСѓі€Т@`0ўAЊеOя’{у-ЖЅpOTъIиK№žEПџџцAПIяSбBњ_8шOўOZ YЦёєo|тDЏ€XЋ ЧnYLљПУRиПЯ$ЯИОЂЎW •YLЫЇ†cЯRЏ‡ЭeŸЯЋ„ИЯЪЯз_бnбУAеї‡Жjнo]5q5Љ/Л/лHА9‘ˆšЄх*ц
E2      0        13125   13125           1       0        DR      0
їеvњ4ЋЯU
вйрWЅ0Щ=с“Б5"“]цПAa5œПooЮВзПщПєЩџиппїGYLЯђяpЧџ!їDЯЯOџaџАє“Яцюџ џЋљ14бчd4юV$6№HZlжорЙЮoq:я?=“Iїе)ђЈ…џжтЈ…Р4­гх‚ы‚чцћ‰‹™\* šFркјц4@ѕGŸСVЖ™ЕьŸф‹јїПьIЁ;šУАН"ЅЏ*Џ<Џ` ?ф_љџЕA=ц/ХэнmЏП‘ЏЃЏЕЏЧЋп€и aмЏюЏМЮ$ŒNAПTЎ       `ПrПC5‹ПEЯБ
E3      X       13625   13625           1       0        DR      0
1ЯDiДГйіIОяаяˆ§эђџwЯI''џЅХРўа?§џє?{џї€/ŸтџВ'С)O;O uCс6дЙqM,+sЙqEсOiЂх‘ЃЕќЧкк\"з9N'•<•!їеБ…џжБ…+=OЙq™чVLunUЇxX5“xW€­ЙqЖ™@gЯЅХ›X@?S—лdЈApўdм/ /6э/Ъ=сS/ј/w/‰/›/ЪЏП/б/у/эo?ЋбPaЋ3?Ю}PaY9$„ч‘ЋЙЖхПНœ?Ў?ˆџЁR}Oщ?7чXOЅХP‰V\O5щ…ЈЉгўУѕD & A aџttribute‡sjBXЈпКпRt•тЌИI~wУtWŸ!3u’ѓП0Уѕ}–ўд@4v,СPЮВ,Ÿ”аOдŸiu
E4      0        23125   23125           1       0        DR      0
__._Ш@_R_„R“ѓФ'bЮЖdщ їд€ŠU6ŠT€ŠUўПІ_И_;@ўЈЂu
НQfp@ФUсSЂ‘`мІjИjZ­e$@ххЃ/@)‘Вp•upю5З€fp@z3ШQ/В5ПGОжЇDi‡МыЂУвfЗ!ЊДZoЅХ§ŠUюП@ЅOњ‡ЄOњ†iчØoЊo`џ F]tбEчЦќвмouIХdЯ"04FXj+~„RQчІ“ж•TЂ‘,пОOнЂ‘Y5HЁƒя•ъИХo  €1Ы‘#5Gэџ`kОљь0ŒдоюПчпљп;ЧЭџjD{Ї8яС\эUtя€ЄяŸяpїп‰туўё†TLB SET? INDEXЉ’ЭУЈŸ„ROпџџУ•lљ†?oЅa7’p? ›]1s’]Yтэ#Зїримж’V™Њˆ}-Љ­фbХЈvF€РР@ў"Z1)ХЈЛYЛІРRЛRFОЃЪЂХЂ”ттИo[0ЮmсSЭСRЛВfфiЖмTН‰ђ#И№qЬТ2“фу7уFXф„PѓŽX~С8ХЕŠЯœЪ
\0ЏТqqIХ}ƒSY1…№ЏмH€џЌпОн*"яБ$тяБ@J‚+        ›/ђуCё8!HЁCќSZџЩСХ“%5|џ€ИХ–џЈџКџŠшq]_UЊ#ї#Двф“U
E5      X       23625   23625           1       0        DR      0
ЊUд“UњЅV€ЊСЯВФжыSъ F(~СeгNB‘DдщФћХЕ
E6      0        33125   33125           1       0        DR      0
/b8!Ћ€LШQ‡ZШGР#27ЧqД@Ќ?ГOХFЌcDдр?эррЧяАСЊСџup!%HЁ}‘u䈑n9HЁншq пf*Рп†/фпЊ&јяЏ-˜‹Т6~_№яЂ]яО<г_х_4ghяm^$o_HmПяq_|oŽoЇTпХЕ:ь‹-ё0э
E7      X       33625   33625           1       0        DR      0
-ё1
E8      0        43125   43125           1       0        DR      0
 v...д w-ёD)№_-№S-1iЁDЫ‘qг’|пЉgЭљNё9Q”o8гЎm:'ХDМ™Тџr>LЦ ЄЖЫ]ШхСtIХгЭС
E9      X       43625   43625           1       0        DR      0
л{rНBБК{‚Ь6™ƒU‹‚ЕКwŸŸ/ŸAšadOŸщsŸ…—ЧСк›ТїНФ•?]ўaб`• k‰дШЄЖo8ˆЌ
%CёзqЫ‘ќ/œ”
5AQ?в“€;Ћe5QS55Q3aZ” ,ЉzuХЕ†ѕ–9EЃ:§џ?@№Eќ_і$Q*КУитШ?QlЩќ_UфЯФ^SќУ†ЛІпTдз{n9јDе?вŸџџ€зqeй__*_<_NX[Y^qЗoЛТГ)‹ЛeІЂЕIХВПiЄЄГ‚Х‹ПыКЋeЯq6qHZlUН™o8*БУ'wІnІ™Кўс–‰С_Uп„p­СhЗЯВЅhФЇФЈЕЂп‰СВU•ЫСfШчЯПЮ4…•ЯaпsпˆТj…’лeІЉпЛл№ёj…зqјCOMPBђњeCџЩŸgџ2?‹џV? h?Сџгџхљ$јTЅјЌЯьиP-DTћ!љП/ASe@w‰›­ћ?
O0с ш       йі§ущ"ьхЄ
4йі1иїZ2DйіyE
шїƒФжшњ//0/B/T/f/x/Лoй/Ў/Р*ўшъ'1яCяUяgяyя‹я№яЏяСягя@ИDЎпsœN@В3’
!
]Ѕіџюцџ#џ5џGџ€Yџkџ}џџЁџГџХџ!щ$I’6ђњ˜/Г@ž'")VВpИ%ы7€C€@z3œAх2ы?§>,’6
и*'е„ŸAпšып,Ÿ‰псmзŸНпћŸвhЏўпg…RQшINV№/бЬqё8o/'/і˜D)ЙЫPt,г…/оы§ іхєџюфЪ/м/ю/??Р$?6?H?Z?l?~? /бнљKЦЋ?UП
SIGNAL  dwb_SEL_O
^ЖAт7сEЅЦOЄЯ&OжZKЦJЧOіЯоKЦ=з	нZЧGпФOжO€шOњO_!vžЁ+Sржѕ‡dˆGЃ2Чq†рЌ?яцЖ“ltр?$РрO`яюЁa_!;_M___q_ƒ_в_Ї_Й_Ы_ЇpИШяcВЖ•ѓОІHIT 0ЅЂŸЏБЏaљоСoљпЏёЏTщ PreяwяШqDЙ‘ЄРџ%rуtв?@|џ—=I%Џ%uа\ЅР
А?Pї
€ЁaЯЯ+Я„;BёD–9j€бuŒе˜!‘ltЂп№Ж•Упr‡Ђ€L
DIRECTION       output
ANх•ЇЭџЫн|Ёы‘ГяЁbџмсrT мэWneˆмх@…ЊУеgc‰W/{3/‹ˆP/РМt/рљеАŠЉ31IђЦo\џnџ€џљUё>qNtœ1МљUёg…јљмџЃ\"з9NWЇ@ќ§№
р1CU^@ЦOЩ8Fƒ•ЇЙЫн
RADIX   hex
єб@…я ЭOжDs1яџфџжРъќ 2DЂ/Д/Ц/и/žM•к6–_&/хЬ_и:ы_§_:/!o^/Ÿ_Wo@”/{oч_Ÿoм/Ж•ˆЋџlog2(DTLџB_SETS)+12iХј­џПџ-ИТоС”^XŒдЬљ€0'ы2UЄrЕѕBџ~rVL{Ё–Ј~„мЇхxCжВpj5ИBё
Д–9„ЃEўy•^XG”ёHm7!3‹‚ѓПQ?ІšЂD§/ЄїАФАЛŠ…?ўрА`, k!Д);b^Xˆ^XжРХжJё
??1?C?U?g?y?ј‹??Џ?@ИDЎsœN
Щ?л?э?џ?O#Og$‘OЩPІQOcOuO‡O™OЋOНOиOсOѓO__)_;_M___q_ЯoсoѓoЙ_Пн_BoЦПoъПŠoЯЎomooVЯТПЕo€ŒЯЅПАЯЯ!3x3?Qcu‡ЯЋНБпсѓзщM_qƒ•ЇЙЫGяYяŸž’є,œуCŸSŸeŸƒе™`пrпVПХŸП5'сž(є
ЏЏ1Џ+J<ё
GRID    0        1       0        1       0        16711680        0        0
НЯzЯѓžЯq)/дЯM/Йq/пх7лUа,‘==с,œƒг[џkџ}џЎ•—џЉџЛџhЭџЫŸнс”)!ъ•        фГВд'#5GEЈATЉ.F}ЁГХзщћ
1CЁ/Г/Х/‹_Э92_ /пh_Ю:‡_™_4/Н_X&и_D_…/o'_2oDo%о|*г<жWAY 0Wж€яяџњH—пI?0$сr"эЂСљг~A,‘!шф,Ÿ=t5ѕA%?ssi›_eщA e?w?‰?›?ЩрEчљЇџ@@р‹јПьгIћ}Uђ–шќžи?%Qh™}BLE+‹OLBe[Ђ/:ц`†Єш)C‰LCўРт1‘ЂLE<7г]uИј
Д№
?sџџ@qЎAщAЖOАШOЫьOўLYhoЂ•bYZ›јИs“ƒеŸ„s“цeZŸКš_eЯŸќF        q€д4‘,Ќwі‘Кy4‘_e Ÿ™9˜љћ††hš“ƒРЁXЁLE|ф€hH†ЏW…i‡iˆZ‚†фЏXЁхdЋX&иЖЏŽЎƒеdЏ0ПBПWЂцe@aЛKЦxПŠЛрбцe7лџPAGE FAULTGr"=џOџ+?=?Р…џa?­Пбпџ9NgѕўАѕ?OO+@Сh        -жGOYOkO}OGЁOђŸŸ(Ÿ:Ÿ
_"П}ooU_яЬЩ1яъ_Љ_gяЭЪ†я˜яў_МяX/:яђяXoџ‚я:џ o
ENDGRID -1
е
Clock   Unclocked
Лk0GrpС ЯЯэіибћ§JЯ\ЭЏ+ЏљишбdƒУЃЩ>РД7џ@@Рёй“хю|хјМО{ЈP-ПDTћ!љП]Сˆk-Ђвu{Р`uЙ№џ`фbuq
д№ л€ЉбfСтв€ЉбP€привнчт+ћЯ
п KpС,2I{Hи
ћvўˆ_ФџeOЪ/?)хвpФб>СЛг€№ @z3ЉбЮдцЮѓ{%'zЮђz//A%{m'9-Šw/A v]Тр/А"р/GбќеSеЙ…ыQИžbгiп{гХBиЈXŠdƒ 6‡јGСу2,rqЌ?G?Y6KгVbдр?Tрц€яyб]С(A­еlЧПв{ЯЯшб–јпUы*gџyєџ]эя; OыуЎi‰бўОhDTLB MIџSS
EdgeLevel       neg
Set     Not Used
EXCE_PTIONGr%Яџсџѓџ);M_qЄљu§Ž!іЕЈьХ{ђЪмю$6HZм‘A1й>f”IЖСфЉRXђsRWЮѓ>f–g=gC$—oЉn>fоgЊmMgшoA Р/в/ф/і)ЗP?иА4?F?–?гq?ƒ?•?Ї?Й?Ы?н?я?>OO/Œ›$OWO   ш˘B&’OЄO*Я<ЯкO`ЯrЯѕ–ЯЈЯ/9NОЮааЮиШьЯo!o"иФ1йь–FпXпD|пŽп пВпФпжпшпњпя:|џŽџZвЏ‹™№ЏщяЈя&ПŒšEПWП§я{П!џљЏБПWџеПAП`љПŸџ@ЅЋPlI12Ы‚'ФЬŒN“ŽСТEГЁу€СУ7бUЇХЇЁ#•А!80—ЖюША!ЛЅ+UГЁЇЁ€ sЂ3]n•llcVŽ–њэПъП€Z$aЂ†Ж€8 мTЅXЇг˜ц“ŽС:‘…ЪжB•FMпVTјжФдзЊЂц’#чœ=ЈqќСяƒг@й‚-и‚-ф?@ŸєIlр+Я?bфдjхПЊ–WЄ@ЯЬ–ЪЬ‘ХN•Фƒi<›вгЁЪЕ-?zN#7Ђ{qХ‡EџЋu@ЂИ’ЪxЇ”Јct§ђ‚xУ`0ў<Ё4б_ЙЇ(ЈvЬвёШкЙOўŸяO__˜%_7_t”‡[е:Fтd^вv_ˆ_š_Ќ_О_а_`т_є_oЦŸиŸвѕ0Fe„6WoHUЮ˜(~lјŽf„6м7ƒ7Дdн?я>„6$G№=“7.O    џBTНџx?џйOЎuџв0BTf,-ЯРbж
Clear   Not Used
Љ(•_žА)ЄЄпё//=Ј™ЪБвё3”гЧзWЇЁu/Д‡'јг}”)!†•рќЊ.:ИP-DTћ!љСсв/ф/і/??,?>?P?b?м
ClockEnable     Not Used
a№™Гvd?НnЉЯ`с| @е5@Гv‡Вwњ4ŽГvS‡Тw]dOvOˆOšOЌO_*_<_N_`_r_„_г_Ј_ж
ActiveLowSetClear       True
иhjŸУaq’Я”qЏЯѕŸгЯхЯїЯр    пп-п?пЏ9РёЏй“ыdоѕvохˆпšпЌпОйqЮйџІупЏ?  -Жэq'щXЗ=я*лхaхьjюм|яŽяћВяФя
AsyncSetClear   True
ЯшяњяЈџ0џгO€Яfџ      _ŠџœџЎџЯвџTqпћџ@нq!3СќšW&%/Ÿr€П–еПК–ЗпЅЄапртпђQM!њXACCџESS TYPE?Qcu‡™ЋНЯ.иo/oAo /2/`D/V/h/ЉoŒ'gЙ5ећЦеіЊ.цыhКш?Ђ‹.КНўo"4FXj|Ž СёЗyМЬŽ%Їч@@їгѕ‘"'@@Щгєе5МЛњ4'М\(Ыf “>ЯЗˆ$Х€aЩђЯОOtЯ/!ЃуЂЯ_їoпŸ“пЅпQŸ ŸuŸ­/шоћЭ/ф_ї[PROџTECTION
ActiveLowClockEnable    True
џ
VhdlType        std_logic
ATTRIBUTESђ/џ"џ4џFџXџjџ|џŽџ џВџхЅшЦеђйnЧXѕo"4FXj|Ž@ ЉwX1ЗyVе
VerilogType     wire
MЂ6ГѕњAHЖ
SystemCType     sc_logic
cpq!}фi ^W€r@'@z3A
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
b^_p^€VЏWW2А_Т^VїWУ]WoœЎЗв+то"V|уšfљ/Щo//A/S/e/w/‰/›/ъ/П/б/у/чр*H‚?FaaшDMMџU PAGE
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
џFAULT EXCEPC1_2ъсС`?r?„?–?›xГ93Сбˆф€ЇSЇщСі?Пќјџ"ў/{  @@К  лFАruйƒсјGOYOkO}OOЁOГOХOзOщOВъсР   0К–еФ‰ts@ћвѕ
К–ЇЙ—2Џ%ЎпРeAЏy[Џ%Љ:oLoч8Юр‘t,>PŸt†˜сйŽqПKу1$6HZl№~ЂД@ИDЎ/sœN
LowVoltageThreshold     0
Ю„RKQ•”_НађЯсŸŸ,Ÿ>ŸPŸbŸtŸ†Ÿ˜ŸЌ
ЪБР рsж_}Яї€Ь@
XRpBБŒUЭжt_Ьп™_YВsжчrз2я0юsжeч1э‚зoяšЏЌЏОЎloсЏgЪБђ2rвђ2їЏ   ПП-П?ПQПcПuП‡Пї˜Ш–џРЗ2Y?нЗяёћЕП1щП"P@ЧЇ9сБЗ50№4Ф74ќPUHЩSѕuСЪhЭ‘сšЈиІѓРvЃЭќПј$Р?Pœ;t*вЩЩ€ќ`@ў№в ЃЦџCяё3ё?Т'д™FсЊп^ƒ!ЃџBюђЃœВЏјq~њл2rЫbс_?@ŸєIЩЯОEбЧПх
еџSж]н„‘Gѕ&ышGљ5ћ/PЈсTХДяXjаРЭЃiЇ
лЈ§јАрР
LSB     0
рА`ˆ ўгЁuлЏ9ї5Си•
MSB     3
ІЬV $gЫW;ф%o7nЬVlg@8mлWvoЅяf/ОЉ
ЫЏЛ/яЏ.?8џJџd?nџˆ?@ЯџЄџfyыNƒРГœxњТsTVADDR[31:13]
SignalActionType        0
*BZ'O9DZ74F Xj|Ž'v“с™gџ@@|џ—=Ћi$ЄЕфUамдFUРПцјjT3X p+?–@Исš’Ю„Љж€њRЇюа‚)o$@Цвp.ње™–тп˜ŸЊž9—„(ъœN’ЉbжR
isFallingEdgeSensitive  False
Їš‚puШр‡ПбуХv3ˆЂгOПД/0/B/T/Оox(Я’йт/Ÿ/Б)ъяPќщp›ƒeЖе/TpПў/ВНp$9ŽCr™OM?TqDVƒ?ИТ—q’ЏВ1›yи;пˆFЯOЇЧ Ь?3Ю—ЯVЯп§56OHOZON~OOшПДOЦO~”†—Сє№ђHТўќŠ_-_?_Q_c_u_‡_™_Ћ_Н\баYЧцх_бж…˜єф†˜dЧцїЦчBd џ2ўЧцgї3§жчqџЌo№ЏаnБхoMП    -?Яcu№Я™iшьи~в!х}GE џOFFSET
isRisingEdgeSensitive   False
DrawAnalog      0
~ѓs12:0]UFщђы№ы№ы№Uы№#ы№$ы№%ы№U&ы№(ы№+ы№-ы№U.ы№0ы№1ы№2ы№3ы№5м№Ulы№4ы№,чєы№§џёЊЂъДф<Л @М%@ујєъёы№Fњ_]D;ы№C-_TCњ˜7ы№AщђU2ы№ы№пќчє§@ы№lBњžD7Jы№RHы№<мџ(
BooleanEquation
U2ы№ы№пќчє}Eы№ДBњ

ы№RUlы№ы№Lујы№ѕчєы№ЮїџМ(їгЩы№4ЬїпLDы№@Љ?ѓё%ш)ы№R§)tЭїE?U$ы№мџ
NegTolerance    0
ѕ4ы№(чєєюмџU1ы№џђ№ы№(шѓы№мџіёіёцѕUы№ы№O"D&aU=шѓђёQџџJf        рћ)ъёh"Tы№y‡ъёМуј+Uvы'_Щ…&aQ-З
PosTolerance    0
-H*9(TYіёgЉŒЈžАщђ›ујEQю№/,GuideTheDocPage-1ѕы№ы№Gestџure FormatBlock NormalVisio 10Block ShadowVisio 12ѕы№ы№Block Highl§№tVisio 11ConnectorVisio 90ѕы№ы№Dot џConnectorѕы№ы№Connџector ArrowVisio 00Visio 01Visio 02Visio 03Visio 13Visio 20Visio 21Visio 22Visio 23Visio 50Visio 51Visio 52Visio 53Visio 70Visio 80Boxѕы№ы№Dynaџmic connџector.8Box.3Box.4Box.5ѕы№ы№Dynaџmic conn?ectorѕы№ы№Dynaџmic connџector.10Box.2Box.24Box.33ѕы№ы№Dynaџmic connџector.39ѕы№ы№Dynaџmic connџector.50ѕы№ы№Dynaџmic connџector.52ѕы№ы№Dynaџmic connџector.9ѕы№ы№Dynaџmic connџector.45Box.13_Шы№Єя№Ѕ уј6ъё3ы№TџљAF
UserSpecifiedSizeRatio  1
Њы№EdKОLљV-
VerilogCode
\R;aђёGt;UyŒ;ŠU
Є;—c
VHDLCode
М;UЈu
PROPS!
д;ЕQ
E0      V       0        0           Valid        1       0        DR      0
ь;}Эu
E1      X       3750    3750            1       0        DR      0
љкUЫшu
E2      V       13125   13125       Valid       1       0        DR      0
4ЫеѕULЫGWUdЫ%Њx|Ы2”Ы?ЊЌЫLФЫYЊмЫfєЫsОљ€$Њ‘<‘šTЊ‘Їl‘Д„Њ‘Сœ‘ЮДЊ‘лЬ‘ш^c/љ№U­ф‘
H	є‘ЌI я№Aќ‘О[*љ[*Њ{ #I*{ -I*,J{ 7I ї{ RI UUl{ q[*|{ UuI*Œ{ [*œ{ •ƒ[*М{ ‡I 0ЬЊ{ ’[*ь{ –!:Џ љЁЧ*$S0РЊ[*DS0ФЧ*dS0уZЧ*„S0I8)ЄS0)Ÿ0Ъ'ФS0>Ÿ0^'EдS0BŸ00ъёы№Ѕы№Чы№ы№ы№ы№(!      ы№0Qы№xвы№ы№Њfы№ы№ы№Bы№ы№іђёы№И!ы№:!ы№Ъ!њё•!ы№"ы№#Ÿы№%Њы№&ы№'ы№(ы№)Jы№*ы№+­!ы№-ы№U.ы№/ы№0ы№1ы№24ы№5м№щђујм№Ujхіы№ы№ы№Uы№ы№    ы№
E3      X       13625   13625           1       0        DR      0
ы№Uы№ы№
ы№ы№Uы№ы№ы№ы№Uы№ы№ы№ы№Uы№ы№ы№ы№ы№м№Ulы№4ы№,чєы№§џёЊЂъДф<Л @М%@ујєъёыёјЏЏKUы№C-\О3Lы№AщђUlы№4ы№,чємџшнўўёўѕы№\BњПSL
E4      V       23125   23125     Valid 1       0        DR      0
ы№AJ-T3]7ўёAщђ_ы№ќпќмџ*<Nчє@ўы№ЄDњ
E5      X       23625   23625           1       0        DR      0
LIы№RVŠœЎ№Рвфgљљ_q6uHы№<мџ(
E6      V       33125   33125     Valid 1       0        DR      0
Hы№<мџ(
E7      X       33625   33625           1       0        DR      0
_ы№ќпќмџ*<NчєEўы№ьDњлL
ы№RVŠœЎ№Рвфgњшq ы№мџkЉ—{†ы№zѓ№œцѕїѓы№
E8      V       43125   43125     Valid 1       0        DR      0
*ы№   ы№gѓ№"мџ4pFXпќїј„ќшѓ(4№
Иџт@(?щ“ўЯaт@ЏА2ЙЬy
E9      X       43750   43750           1       0        DR      0
ы№№Jїхіњчєы№„Oї:Кы№]ы№RPЇї—
!
4 Њы№dЉы№uюы№в&ы№ЬSїыѓ№!ы№BоћTї?ѓ№Q
њ>ы№ Cяны№Fўы№ ŸCmы`sы№ФЌїЋHfk$ы№ŒOЫїГf'ы№}МЁ2EU>NDљ‡ЗU)ы№tХЗU1ы№ДХ ЗЁ=эџх%љхі`2ўы№,љMIЛXя№V<ы№ьџoїЅK
њO?ы№мї•щLtDы№l#љ+ѕ5 C=СћS8MJ!єџAY 
ы№@ўџр…ŸђљOhЋ‘+'Гй0Є@Hht€Œ˜фValued Sony CustomerG(Eџџџџxw
SIGNAL  dwb_STB_O
w
DIRECTION       output
 EMF EXиЂVISIODrawingM”D€€ Ь€?€?џџџl(”@€€(€€€€€€€€€€€РРРРмР№ЪІ№ћџЄ  €€€џџџџџџџџџџџџ_VPID_PREVIEWS@_PID_LINKBASEтПф        Aўџ
RADIX   hex
џџџџQН…<ѓбЅ=Kuy›Timing DiagramTiming.Document.1є9ВqTiming Diagramўџ
GRID    0        1       0        1       0        16711680        0        0
џџџџРFMicrosoft Visio DrawingVISITiming Diagram Editor v7.1g - Output File
ENDGRID -1
Clock   Unclocked
PROJECT
EdgeLevel       neg
BaseTimeUnit    1
Set     Not Used
DisplayTimeUnit 2
Clear   Not Used
TextGridX       250.000000
ClockEnable     Not Used
TextGridY       6
ActiveLowSetClear       True
EdgeGridX       250.000000
AsyncSetClear   True
ImportStartTime 0.000000
ActiveLowClockEnable    True
ImportEndTime   281474976710656.000000
VhdlType        std_logic
TimePerPixel    6.497175
VerilogType     wire
Visible DELAYS  SETUPS  HOLDS   SAMPLES TEXT    HIDDENATTACHMENTS       CRITICALPATHS   GRIDLINES       UNCERTAINTY
SystemCType     sc_logic
ColWidths       144,216,288,423,488
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
ScrollPos       0.000000,0.000009,0.000000
StateEquation   Hex(Inc(0,2,5))
DefDelayRule    1
HighVoltageThreshold    5
NoEventOverlap  NO
LowVoltageThreshold     0
SigLabelFontHeight      10
SignalActionType        0
LabelHeight     12
MSB     0
LoadLibsToMem   1
LSB     0
UseFullPathNames        1
isFallingEdgeSensitive  False
LibPath
isRisingEdgeSensitive   False
EntireTime      YES
DrawAnalog      0
PrintTimeSpecified      NO
BooleanEquation
FromTime        0
NegTolerance    0
ToTime  5.75
PosTolerance    0
AllSignals      YES
UserSpecifiedSizeRatio  1
CurrSelSigs     NO
VerilogCode
PrintTo 2
VHDLCode
PrintFileName   C:\DOCS\reset.wmf
PROPS!
PreviewInterchange      YES
E0      0        3750    3750            1       0        DR      0
PreviewTIFF5    NO
E1      1       13125   13125           1       0        DR      0
UseMargins      NO
E2      0        13625   13625           1       0        DR      0
PrintTimeLine   NO
E3      1       23125   23125           1       0        DR      0
PrintBorderBox  YES
E4      0        23625   23625           1       0        DR      0
PrintSigNames   YES
E5      1       33125   33125           1       0        DR      0
PrintSigNamesOnEachPage YES
E6      0        33625   33625           1       0        DR      0
AddPreviewToEPS NO
E7      1       43125   43125           1       0        DR      0
PreviewRes      150
E8      X       43750   43750           1       0        DR      0
MarginLR        1.25
!
MifImageWidth   6.00
MarginTB        Auto
SIGNAL  dwb_ACK_I
Header  %d %t;%f;%p
DIRECTION       input
Footer
RADIX   hex
ScaleHorz       100
GRID    0        1       0        1       0        16711680        0        0
ScaleVert       100
ENDGRID -1
ScaleHPage      1
Clock   Unclocked
PrintImage      DIAGRAM
EdgeLevel       neg
DefaultTimingModel      minmax
Set     Not Used
DefaultClock    Unclocked
Clear   Not Used
DefaultEdgeLevel        neg
ClockEnable     Not Used
DefaultSet      Not Used
ActiveLowSetClear       True
DefaultClear    Not Used
AsyncSetClear   True
DefaultClockEnable      Not Used
ActiveLowClockEnable    True
DefaultClockToOutLH     0
VhdlType        std_logic
DefaultClockToOutHL     0
VerilogType     wire
DefaultSetup    0
SystemCType     sc_logic
DefaultHold     0
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
DefaultRegStartupState  unknown
StateEquation   Hex(Inc(0,2,5))
DefaultPodSize  8
HighVoltageThreshold    5
DefaultActiveLowSetClear        True
LowVoltageThreshold     0
DefaultAsyncSetClear    True
SignalActionType        0
DefaultActiveLowClockEnable     True
MSB     0
SigLabelFontHeight      10
LSB     0
PROPS!
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   False
DrawAnalog      0
STYLE
BooleanEquation
DefaultFont     USER    {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
NegTolerance    0
DrawWndFont     DEFAULT
PosTolerance    0
DrawWndColor    DEFAULT
UserSpecifiedSizeRatio  1
GridWndFont     DEFAULT
VerilogCode
GridWndColor    DEFAULT
VHDLCode
LabelWndFont    USER    {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
PROPS!
LabelWndColor   DEFAULT
E0      0        11250   11250           1       0        DR      0
ParamDispPref   0
E1      1       13125   13125           1       0        DR      0
ParamWndCellDisplay     0
E2      0        21250   21250           1       0        DR      0
CustDispString  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
E3      1       23125   23125           1       0        DR      0
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
E4      0        31250   31250           1       0        DR      0
MarkerDispPref  4
E5      1       33125   33125           1       0        DR      0
MarkerCustDispString    %n v=%mv,%Mv d=%md %t
E6      0        41250   41250           1       0        DR      0
MarkerCustomDisplayStringRTF    {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
E7      1       43125   43125           1       0        DR      0
SignalColor     2
E8      X       43750   43750           1       0        DR      0
LabelOffset     4
!
BusDisplay      0
WaveFormWidth   0.500000
SIGNAL  dwb_CYC_O
WaveFormColor   0
DIRECTION       output
InputWaveFormColor      16711680
RADIX   hex
SlantedEdges    1
GRID    0        1       0        1       0        16711680        0        0
SlantAngle      75
ENDGRID -1
RightJustifySigNames    1
Clock   Unclocked
AutosplitEnabled        1
EdgeLevel       neg
AutosplitChar   _
Set     Not Used
DynamSizedSignals       1
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
DIAGRAMTESTBENCHSETTINGS
AsyncSetClear   True
FilesBeforeDiagramModel
ActiveLowClockEnable    True
FilesInsideDiagramModelDeclarationSection
VhdlType        std_logic
AbortHdlCodeEnabled     1
VerilogType     wire
DelayHdlCodeEnabled     1
SystemCType     sc_logic
SampleHdlCodeEnabled    1
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
MarkerHdlCodeEnabled    1
StateEquation   Hex(Inc(0,2,5))
VerboseSamples  0
HighVoltageThreshold    5
VerboseDelays   0
LowVoltageThreshold     0
VerboseFileInput        0
SignalActionType        0
VerboseSequenceVerification     0
MSB     0
IncludeDelayTime        1
LSB     0
ExecuteFromTopLevel     1
isFallingEdgeSensitive  False
TimeOutInDiagramLengths 0
isRisingEdgeSensitive   False
DefaultCycleClock       Unclocked
DrawAnalog      0
DefaultCycleEdge        neg
BooleanEquation
!
NegTolerance    0
PosTolerance    0
MACROS
UserSpecifiedSizeRatio  1
!
VerilogCode
VHDLCode
CORGROUP        $$CLK_I_BufferRising
PROPS!
Percent 100
E0      0        3125    3125            1       0        DR      0
!
E1      1       43125   43125           1       0        DR      0
E2      0        43750   43750           1       0        DR      0
CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
!
SIGNAL  dwb_ERR_I
DIRECTION       input
CORGROUP        $$CLK_I_BufferRisingFalling
RADIX   hex
Percent 100
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock   Unclocked
CORGROUP        $$CLK_I_BufferRising
EdgeLevel       neg
Percent 100
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
CORGROUP        $$CLK_I_BufferFalling
ActiveLowSetClear       True
Percent 100
AsyncSetClear   True
!
ActiveLowClockEnable    True
VhdlType        std_logic
CORGROUP        $$CLK_I_BufferRisingFalling
VerilogType     wire
Percent 100
SystemCType     sc_logic
!
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
CORGROUP        $$CLK_I_BufferRising
HighVoltageThreshold    5
Percent 100
LowVoltageThreshold     0
!
SignalActionType        0
MSB     0
CORGROUP        $$CLK_I_BufferFalling
LSB     0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   False
DrawAnalog      0
CORGROUP        $$CLK_I_BufferRisingFalling
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$CLK_I_BufferRising
VerilogCode
Percent 100
VHDLCode
!
PROPS!
E0      0        43125   43125           1       0        DR      0
CORGROUP        $$CLK_I_BufferFalling
E1      X       43750   43750           1       0        DR      0
Percent 100
!
!
SIGNAL  dwb_RTY_I
CORGROUP        $$CLK_I_BufferRisingFalling
DIRECTION       input
Percent 100
RADIX   hex
!
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
CORGROUP        $$CLK_I_BufferRising
Clock   Unclocked
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$CLK_I_BufferFalling
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$CLK_I_BufferRisingFalling
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$CLK_I_BufferRising
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
SignalActionType        0
CORGROUP        $$CLK_I_BufferFalling
MSB     0
Percent 100
LSB     0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
CORGROUP        $$CLK_I_BufferRisingFalling
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$CLK_RISC_BufferRising
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
PROPS!
CORGROUP        $$CLK_RISC_BufferFalling
E0      0        43125   43125           1       0        DR      0
Percent 100
E1      X       43750   43750           1       0        DR      0
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
MARKER  MARK1
Percent 100
ATTACH  dwb_SEL_O       NULL    S6
!
TIME    17500.000000
RELATIVETIME    0.000000
CORGROUP        $$CLK_RISC_BufferRising
DISPLAYAS       5
Percent 100
MARKERTYPE      Timebreak(Curved)
!
WHILERETURN
REPEATNUMBER
CORGROUP        $$CLK_RISC_BufferFalling
SNAPTO  0
Percent 100
COMPRESSTIME    0.000000
!
COMMENT
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
MARKER  MARK2
!
ATTACH  dwb_STB_O       NULL    S7
TIME    27500.000000
CORGROUP        $$CLK_I_BufferRising
RELATIVETIME    0.000000
Percent 100
DISPLAYAS       5
!
MARKERTYPE      Timebreak(Curved)
WHILERETURN
CORGROUP        $$CLK_I_BufferFalling
REPEATNUMBER
Percent 100
SNAPTO  0
!
COMPRESSTIME    0.000000
COMMENT
CORGROUP        $$CLK_I_BufferRisingFalling
!
Percent 100
!
MARKER  MARK3
ATTACH  dwb_STB_O       NULL    S7
CORGROUP        $$CLK_RISC_BufferRising
TIME    37500.000000
Percent 100
RELATIVETIME    0.000000
!
DISPLAYAS       5
MARKERTYPE      Timebreak(Curved)
CORGROUP        $$CLK_RISC_BufferFalling
WHILERETURN
Percent 100
REPEATNUMBER
!
SNAPTO  0
COMPRESSTIME    0.000000
CORGROUP        $$CLK_RISC_BufferRisingFalling
COMMENT
Percent 100
!
!
MARKER  MARK0
CORGROUP        $$CLK_I_BufferRising
ATTACH  dwb_CLK_I       NULL    S1
Percent 100
TIME    7494.285714
!
RELATIVETIME    0.000000
DISPLAYAS       5
CORGROUP        $$CLK_I_BufferFalling
MARKERTYPE      Timebreak(Curved)
Percent 100
WHILERETURN
!
REPEATNUMBER
SNAPTO  0
CORGROUP        $$CLK_I_BufferRisingFalling
COMPRESSTIME    0.000000
Percent 100
COMMENT
!
!
CORGROUP        $$CLK_RISC_BufferRising
ўџ
Percent 100
џџџџQН…<ѓбЅ=Kuy›Timing DiagramTiming.Document.1є9ВqTiming Diagramўџ
!
џџџџQН…<ѓбЅ=Kuy›Timing DiagramTiming.Document.1є9ВqTiming DiagramTiming Diagram Editor v7.1g - Output File
CORGROUP        $$CLK_RISC_BufferFalling
PROJECT
Percent 100
BaseTimeUnit    1
!
DisplayTimeUnit 2
TextGridX       625.000000
CORGROUP        $$CLK_RISC_BufferRisingFalling
TextGridY       6
Percent 100
EdgeGridX       625.000000
!
ImportStartTime 0.000000
ImportEndTime   281474976710656.000000
CORGROUP        $$CLK_I_BufferRising
TimePerPixel    17.543860
Percent 100
Visible DELAYS  SETUPS  HOLDS   SAMPLES TEXT    HIDDENATTACHMENTS       CRITICALPATHS   GRIDLINES       UNCERTAINTY
!
ColWidths       144,216,288,423,488
ScrollPos       0.000000,0.000000,0.000000
CORGROUP        $$CLK_I_BufferFalling
DefDelayRule    1
Percent 100
NoEventOverlap  NO
!
SigLabelFontHeight      8
LabelHeight     10
CORGROUP        $$CLK_I_BufferRisingFalling
LoadLibsToMem   1
Percent 100
UseFullPathNames        1
!
LibPath
EntireTime      YES
CORGROUP        $$CLK_RISC_BufferRising
PrintTimeSpecified      NO
Percent 100
FromTime        0
!
ToTime  15.625
AllSignals      YES
CORGROUP        $$CLK_RISC_BufferFalling
CurrSelSigs     NO
Percent 100
PrintTo 2
!
PrintFileName   C:\DOCS\wb_writesingle.wmf
PreviewInterchange      YES
CORGROUP        $$CLK_RISC_BufferRisingFalling
PreviewTIFF5    NO
Percent 100
UseMargins      NO
!
PrintTimeLine   NO
PrintBorderBox  YES
CORGROUP        $$CLK_RISC_BufferRising
PrintSigNames   YES
Percent 100
PrintSigNamesOnEachPage YES
!
AddPreviewToEPS NO
PreviewRes      150
CORGROUP        $$CLK_RISC_BufferFalling
MarginLR        1
Percent 100
MifImageWidth   6.00
!
MarginTB        Auto
Header  %d %t;%f;%p
CORGROUP        $$CLK_RISC_BufferRisingFalling
Footer
Percent 100
ScaleHorz       100
!
ScaleVert       100
ScaleHPage      1
CORGROUP        $$CLK_RISC_BufferRising
PrintImage      DIAGRAM
Percent 100
DefaultTimingModel      minmax
!
DefaultClock    Unclocked
DefaultEdgeLevel        neg
CORGROUP        $$CLK_RISC_BufferFalling
DefaultSet      Not Used
Percent 100
DefaultClear    Not Used
!
DefaultClockEnable      Not Used
DefaultClockToOutLH     0
CORGROUP        $$CLK_RISC_BufferRisingFalling
DefaultClockToOutHL     0
Percent 100
DefaultSetup    0
!
DefaultHold     0
DefaultRegStartupState  unknown
CORGROUP        $$CLK_RISC_BufferRising
DefaultPodSize  8
Percent 100
DefaultActiveLowSetClear        True
!
DefaultAsyncSetClear    True
DefaultActiveLowClockEnable     True
CORGROUP        $$CLK_RISC_BufferFalling
SigLabelFontHeight      10
Percent 100
PROPS!
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
STYLE
Percent 100
DefaultFont     USER    {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
!
DrawWndFont     DEFAULT
DrawWndColor    DEFAULT
CORGROUP        $$CLK_RISC_BufferRising
GridWndFont     DEFAULT
Percent 100
GridWndColor    DEFAULT
!
LabelWndFont    USER    {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
LabelWndColor   DEFAULT
CORGROUP        $$CLK_RISC_BufferFalling
ParamDispPref   0
Percent 100
ParamWndCellDisplay     0
!
CustDispString  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
CORGROUP        $$CLK_RISC_BufferRisingFalling
MarkerDispPref  4
Percent 100
MarkerCustDispString    %n v=%mv,%Mv d=%md %t
!
MarkerCustomDisplayStringRTF    {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
SignalColor     2
CORGROUP        $$CLK_RISC_BufferRising
LabelOffset     2
Percent 100
BusDisplay      0
!
WaveFormWidth   0.500000
WaveFormColor   0
CORGROUP        $$CLK_RISC_BufferFalling
InputWaveFormColor      16711680
Percent 100
SlantedEdges    1
!
SlantAngle      75
RightJustifySigNames    1
CORGROUP        $$CLK_RISC_BufferRisingFalling
AutosplitEnabled        1
Percent 100
AutosplitChar   _
!
DynamSizedSignals       1
!
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
DIAGRAMTESTBENCHSETTINGS
!
FilesBeforeDiagramModel
FilesInsideDiagramModelDeclarationSection
CORGROUP        $$CLK_RISC_BufferFalling
AbortHdlCodeEnabled     1
Percent 100
DelayHdlCodeEnabled     1
!
SampleHdlCodeEnabled    1
MarkerHdlCodeEnabled    1
CORGROUP        $$CLK_RISC_BufferRisingFalling
VerboseSamples  0
Percent 100
VerboseDelays   0
!
VerboseFileInput        0
VerboseSequenceVerification     0
CORGROUP        $$CLK_RISC_BufferRising
IncludeDelayTime        1
Percent 100
ExecuteFromTopLevel     1
!
TimeOutInDiagramLengths 0
DefaultCycleClock       Unclocked
CORGROUP        $$CLK_RISC_BufferFalling
DefaultCycleEdge        neg
Percent 100
!
!
MACROS
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
CORGROUP        $$CLK_RISC_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_I_BufferFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
CORGROUP        $$CLK_RISC_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_I_BufferFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
CORGROUP        $$CLK_RISC_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_I_BufferFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
CORGROUP        $$clk_risc_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_I_BufferFalling
Percent 100
CORGROUP        $$clk_risc_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$clk_risc_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
CORGROUP        $$clk_risc_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_I_BufferFalling
Percent 100
CORGROUP        $$clk_risc_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$clk_risc_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
CORGROUP        $$clk_risc_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_I_BufferFalling
Percent 100
CORGROUP        $$clk_risc_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$clk_risc_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
CORGROUP        $$clk_risc_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
CORGROUP        $$clk_risc_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
CORGROUP        $$clk_risc_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
CORGROUP        $$clk_risc_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
CORGROUP        $$clk_risc_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
CORGROUP        $$clk_risc_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
CLOCK   clk_risc
!
PERIODE 1
DUTY    50
CORGROUP        $$CLK_I_BufferFalling
OFFSETE 0
Percent 100
INITIAL LOW
!
MAXUNCERTRISE   0
MAXUNCERTFALL   0
CORGROUP        $$CLK_I_BufferRisingFalling
MINUNCERTRISE   0
Percent 100
MINUNCERTFALL   0
!
JRISEE  0
JFALLE  0
CORGROUP        $$CLK_RISC_BufferRising
GRID    1       1       1       2       2       16711680        0        0
Percent 100
ENDGRID -1
!
DIRECTION       input
MASTERCLOCK     None
CORGROUP        $$CLK_RISC_BufferFalling
Clock   Unclocked
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$CLK_RISC_BufferRisingFalling
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$CLK_I_BufferRising
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$CLK_I_BufferFalling
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
MSB     0
CORGROUP        $$CLK_I_BufferRisingFalling
LSB     0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   True
DrawAnalog      0
CORGROUP        $$CLK_RISC_BufferRising
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$CLK_RISC_BufferFalling
VerilogCode
Percent 100
VHDLCode
!
PROPS!
E5      1       2500    2500            1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRisingFalling
E6      0        3000    3000            1       0        DR      0
Percent 100
E7      0        3500    3500            1       0        DR      0
!
E9      1       4500    4500            1       0        DR      0
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
SIGNAL  rst
!
DIRECTION       input
RADIX   hex
CORGROUP        $$CLK_I_BufferFalling
GRID    0        1       0        1       0        16711680        0        0
Percent 100
ENDGRID -1
!
Clock   Unclocked
EdgeLevel       neg
CORGROUP        $$CLK_I_BufferRisingFalling
Set     Not Used
Percent 100
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CORGROUP        $$CLK_RISC_BufferRising
AsyncSetClear   True
Percent 100
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
CORGROUP        $$CLK_RISC_BufferFalling
SystemCType     sc_logic
Percent 100
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
CORGROUP        $$CLK_RISC_BufferRisingFalling
LowVoltageThreshold     0
Percent 100
SignalActionType        0
!
MSB     0
LSB     0
CORGROUP        $$CLK_I_BufferRising
isFallingEdgeSensitive  False
Percent 100
isRisingEdgeSensitive   False
!
DrawAnalog      0
BooleanEquation
CORGROUP        $$CLK_I_BufferFalling
NegTolerance    0
Percent 100
PosTolerance    0
!
UserSpecifiedSizeRatio  1
VerilogCode
CORGROUP        $$CLK_I_BufferRisingFalling
VHDLCode
Percent 100
PROPS!
!
E0      0        1750    1750            1       0        DR      0
E1      1       3750    3750            1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRising
E2      0        5750    5750            1       0        DR      0
Percent 100
!
!
SIGNAL  dbg_dat_o
CORGROUP        $$CLK_RISC_BufferFalling
DIRECTION       output
Percent 100
RADIX   hex
!
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
CORGROUP        $$CLK_RISC_BufferRisingFalling
Clock
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$CLK_I_BufferRising
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$CLK_I_BufferFalling
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$CLK_I_BufferRisingFalling
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
LSB     0
CORGROUP        $$CLK_RISC_BufferRising
MSB     31
Percent 100
SignalActionType        0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   True
CORGROUP        $$CLK_RISC_BufferFalling
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$CLK_RISC_BufferRisingFalling
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
VhdlMapping     DefaultVhdlMapping
CORGROUP        $$dwb_CLK_I_BufferRising
PROPS!
Percent 100
E0      X       1750    1750            1       0        DR      0
!
E1      V       4750    4750    0x0     1       0        DR      0
E2      V       5750    5750    0x4     1       0        DR      0
CORGROUP        $$dwb_CLK_I_BufferFalling
!
Percent 100
!
SIGNAL  dbg_op_i
DIRECTION       input
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
RADIX   hex
Percent 100
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock   Unclocked
CLOCK   CLK_RISC
EdgeLevel       neg
PERIODE 2.5
Set     Not Used
DUTY    50
Clear   Not Used
OFFSETE 0
ClockEnable     Not Used
INITIAL HIGH
ActiveLowSetClear       True
MAXUNCERTRISE   0
AsyncSetClear   True
MAXUNCERTFALL   0
ActiveLowClockEnable    True
MINUNCERTRISE   0
VhdlType        std_logic
MINUNCERTFALL   0
VerilogType     wire
JRISEE  0
SystemCType     sc_logic
JFALLE  0
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
GRID    0        1       0        2       0        16711680        0        0
StateEquation   Hex(Inc(0,2,5))
ENDGRID -1
HighVoltageThreshold    5
DIRECTION       internal
LowVoltageThreshold     0
MASTERCLOCK     None
SignalActionType        0
Clock   Unclocked
MSB     3
EdgeLevel       neg
LSB     0
Set     Not Used
isFallingEdgeSensitive  False
Clear   Not Used
isRisingEdgeSensitive   False
ClockEnable     Not Used
DrawAnalog      0
ActiveLowSetClear       True
BooleanEquation
AsyncSetClear   True
NegTolerance    0
ActiveLowClockEnable    True
PosTolerance    0
VhdlType        std_logic
UserSpecifiedSizeRatio  1
VerilogType     wire
VerilogCode
SystemCType     sc_logic
VHDLCode
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
PROPS!
StateEquation   Hex(Inc(0,2,5))
E0      V       5750    5750    READ PC 0x0     1       0        DR      0
HighVoltageThreshold    5
!
LowVoltageThreshold     0
MSB     0
PARM    Trs
LSB     0
MIN     NULL
isFallingEdgeSensitive  False
MAX     NULL
isRisingEdgeSensitive   False
COMMENT Reset Setup Time
DrawAnalog      0
NameRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont Trs}
BooleanEquation
MinRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont}
NegTolerance    0
MaxRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont}
PosTolerance    0
CommentRTF      {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont Reset Setup Time}
UserSpecifiedSizeRatio  1
CLOCKNAME       Unclocked
VerilogCode
CLOCKEDGE       neg
VHDLCode
IsApplyInput    False
PROPS!
PROPS!
!
!
CLOCK   dwb_CLK_I
PARM    Trh
PERIODE 5
MIN     NULL
DUTY    50
MAX     NULL
OFFSETE 0
COMMENT Reset Hold Time
INITIAL LOW
NameRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont Trh}
MAXUNCERTRISE   0
MinRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont}
MAXUNCERTFALL   0
MaxRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont}
MINUNCERTRISE   0
CommentRTF      {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont Reset Hold Time}
MINUNCERTFALL   0
CLOCKNAME       Unclocked
JRISEE  0
CLOCKEDGE       neg
JFALLE  0
IsApplyInput    False
GRID    1       1       1       2       2       16711680        0        0
PROPS!
ENDGRID -1
!
DIRECTION       input
MASTERCLOCK     None
SETUP   Trs
Clock   Unclocked
FROM    clk_risc        E9      S0
EdgeLevel       neg
TO      rst     E1      S1
Set     Not Used
OUTARROWS       0
Clear   Not Used
USERPLACED      0
ClockEnable     Not Used
DISPLAYAS       6
ActiveLowSetClear       True
CUSTDISPSTRING  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
AsyncSetClear   True
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
ActiveLowClockEnable    True
EnableHdlCodeGeneration False
VhdlType        std_logic
OrderIndex      1
VerilogType     wire
PROPS!
SystemCType     sc_logic
!
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
HOLD    Trh
HighVoltageThreshold    5
FROM    clk_risc        E7      S0
LowVoltageThreshold     0
TO      rst     E1      S1
MSB     0
OUTARROWS       0
LSB     0
USERPLACED      0
isFallingEdgeSensitive  False
DISPLAYAS       6
isRisingEdgeSensitive   True
CUSTDISPSTRING  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
DrawAnalog      0
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
BooleanEquation
EnableHdlCodeGeneration False
NegTolerance    0
OrderIndex      2
PosTolerance    0
PROPS!
UserSpecifiedSizeRatio  1
!
VerilogCode
VHDLCode
MARKER  MARK0
PROPS!
ATTACH  rst     NULL    S1
!
TIME    2750.000000
RELATIVETIME    0.000000
SIGNAL  dwb_ADR_O
DISPLAYAS       5
DIRECTION       output
MARKERTYPE      Timebreak(Curved)
RADIX   hex
WHILERETURN
GRID    0        1       0        1       0        16711680        0        0
REPEATNUMBER
ENDGRID -1
SNAPTO  0
Clock
COMPRESSTIME    0.000000
EdgeLevel       neg
COMMENT
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
ТQ&l   Ћ^&" WMFCћж ЈeЈ…xŸЬТQ&l EMFЈ…SXфПиVISIODrawingР
ActiveLowSetClear       True
 Q%€RLНџџџ Arialџџџџџџџџџџџџџџ%TlWQ›
AsyncSetClear   True
О‡@
ActiveLowClockEnable    True
О‡@WQLXSET 0--)%TlWЁы
VhdlType        std_logic
О‡@
VerilogType     wire
О‡@WЁLXSET 1--)%RLНџџџМ ArialBBd№dє
SystemCType     sc_logic
ШШuдЇJJS%T`˜С    а
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X

StateEquation   Hex(Inc(0,2,5))
О‡@
HighVoltageThreshold    5
О‡@˜С        LT...RLНџџџ ArialPCMШK%T`s1
ѕ{

LowVoltageThreshold     0
О‡@
LSB     0
О‡@s1
LTSET--)RLЮџџџ Arial%T„6r
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MSB     31
О‡@
SignalActionType        0
О‡@6r
     L`IC_SETS-1$!!!&%%€V0oћ3›
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%€(RLНџџџ Arial„„„ж…F††к‡Вˆn‰%(RLНџџџ Arial˜т˜є™™™(™:™L™^™p™‚š0šм›Šœ’œЬœі `Вž.žxžєŸHŸЬ  ” ьЁRЁЈЂЂdЂАЃЃrЃРЄЄfЄЎЄиЅЅ,Ѕ`ЅЅРІ€ІжЇBЇ–Ј
isFallingEdgeSensitive  False
ЈPЈИЈўЉZЉ€ЉЊЉаЊЊ&ЊL%(RLНџџџ ArialБšБЮБќВ0В`ВšВФВђГГ>ГjГЈГиД8ДpДЄДвЕЕ2ЕbЕ’ЕЦЖЖPЖАЖфЗ<ЗpЗЬИjЙ8КXЛ rif design, Arial contains more humanistharacteristics than many of its predecessors and as such is most%(RLНџџџМ Arialr and fuller than in most industrial style sans sefaces.  Terminal strokes are cut on the diagonal which helps to give the face a less mechanical appearance.  Arial is an extrely versatile family of typefaces which can be used with equal s,%(%€RLНџџџ Arialwww.monotype.com/html/mtname/ms_arial.htmlhttp://wonotype.com/html/mtname/ms_welcome.htmlNOTIFICATION OF LICENSE AGREEMENT
isRisingEdgeSensitive   True
DrawAnalog      0
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BooleanEquation
О‡@
NegTolerance    0
О‡@№oLXTAG 0pe)-4%Tl№ПБ 
PosTolerance    0
О‡@
UserSpecifiedSizeRatio  1
О‡@№ПLXTAG 1 y)-4%RLНџџџМ Arialishing use. You may not copy or distribute this sore.
VerilogCode
VHDLCode
If you have any question concerning your rights you should review the license agreement you received with the software  contact Monotype for a copy of the license agreement.
VhdlMapping     DefaultVhdlMapping
PROPS!
Mono (%T`5п       m,
E0      V       -1      -1              1       0        DR      0

E1      X       3125    3125            1       0        DR      0
О‡@
E2      V       13125   13125   Valid   1       0        DR      0
О‡@5п        LT...peRLНџџџ Arialypeface Љ The Monotype Cooration plc. Data Љ The Monotype Corporation plc/Type SolutionsInc. 1990-1992. All Rights Reseo%T`џ•I

E3      X       15625   15625           1       0        DR      0
О‡@
!
О‡@џLTTAGi)-4T„ЇO
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О‡@
SIGNAL  dwb_DAT_I
О‡@ЇO
     L`IC_SETS-1 0%--)-%&%%€V0 Е
DIRECTION       input
MЁL
RADIX   hex
L
GRID    0        1       0        1       0        16711680        0        0
ЖЁЖЁL%€(%
€(%
€(RLНџџџМ Arialorary sans serif design, ial contains more humanist characteristics than many of its preecessors and as such is more ino%(%
€(%€%TДэДb
ENDGRID -1
О‡@
Clock
О‡@эLpEFFECTIVE ADDRESSl-))-0(---000---&%%€V0|ћl    ›
}š
k š
k     ќ}ќ}š
%€(RLНџџџ Arial appearance.  Arial is anxtremely versatile family of typefaces which can be used with eual success for text seшBшbш‚шЈ%(RLНџџџ Arialю юbюІюьяHяdя€яœяИядёBєі‚іИіді№її(ї„їОј(јђљ’њhњшћpћрќvќд§§x§кўўpўœўјџ4 ”Ок>Šў.^ŽТђ"R‚ВтBrЂ%(RLНџџџ ArialB^ŽОŠ’Тќ,\ŒО&V†Иш Єд4d в4d˜Ъњ*œа ž! #0%`'Њ)<) ***Ш,r-P...Ъ/к1ž33т3ђ44і555&%(%€RLНџџџ ArialEОFТG„HЄIАKKFK~KДKкL
EdgeLevel       neg
L0MNpN€NNТNвOњPцQвQњR*RжRцSОSЮTTмTьWXlXђY"Z@ZоZюZў[[€[[ [А\’]Ь^B^№_”`VaaєbВbжcаcўde&fRf%Tp‡o`Й
Set     Not Used
О‡@
Clear   Not Used
О‡@‡oLXWord 0B%%%Tp‡П`     
ClockEnable     Not Used
О‡@
ActiveLowSetClear       True
О‡@‡ПLXWord 1B%%%%T`ип        ,
AsyncSetClear   True

ActiveLowClockEnable    True
О‡@&" WMFC ЈEЈ…
VhdlType        std_logic
О‡@ип        LT...RLНџџџ ArialЉьЋЋ<ЋŠЋИ­­H­О­ќЎ*ЎhЏ†ЏЎБzВ$ВІГbДzЕˆЕМЖBЗžИ ИjЙtЙМКРЛ<Л”ММєО
VerilogType     wire
ОјПЂР’СHТТіУІФ(Ц†ЦАЦкЧ’ШўЪЪюЫЫBЫlЫ–ЫРЭ@ЭjЭ”ЭОЭшЮЮ<%T №џїI

SystemCType     sc_logic
О‡@
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
О‡@№џLhWord IC_SETS-2B%%0%--)-%T №O
ї™

StateEquation   Hex(Inc(0,2,5))
О‡@
HighVoltageThreshold    5
О‡@№O
LhWord IC_SETS-1B%%0%--)-%%
€(&%%€V0
LowVoltageThreshold     0
ЕIM
LSB     0
LHLHЖ
MSB     31
Ж
SignalActionType        0
L%€(%
€(%
€(&%%€V0(ЕM)L
isFallingEdgeSensitive  False
L
isRisingEdgeSensitive   False
Ж)Ж)L%€(&%%€W,.CZ
DrawAnalog      0
QLQ-7-7
BooleanEquation
%€(&%%€W,јћ›
ќљќљš
š
%€(&§џџџ‚ƒ„…†‡ˆ‰Š‹ŒŽ‘’“”•–—˜™š›œžŸ ЁЂЃЄЅІЇЈЉЊЋЌ­ЎЏАБВГДЕЖЗИЙКЛМНОПРСТУФХЦЧШЩЪЫЬўџџџЯабвгдежзийклмнопрстуфхцчшщъыьэюя№ёђѓєѕўџџџїјљњћќ§ўџ%%€W$.
NegTolerance    0
@d7
PosTolerance    0
7[%€(%€%€V,Q^Ц^Q7ЦQ^Q%€%€V0ЦcccЦЦ&%%€666#6'+6/367;6?C6GK6OS6W[6_c6gk6os6w{6ƒ6‡‹6“6—›6ŸЃ6ЇЋ6ЏГ6ЗЛ6ПУ6ЧЫ6Яг6зл6пу6чы6яѓ6їћ6џ6666#6'+6/367;6?C6GK6OS6W[6_c6gk6os6w{6ƒ6‡‹6“6—›6ŸЃ6ЇЋ6ЏГ6ЗЛ6ПУ6ЧЫ6Яг6зл6пу6чы6яѓ6їћ6џ6666#6'+6/367;6?C6GK6OS6W[6_c6cc6cc6cc6ccџ6cћcї6cѓcя6cыcч6cуcп6cлcз6cгcЯ6cЫcЧ6cУcП6cЛcЗ6cГcЏ6cЋcЇ6cЃcŸ6c›c—6c“c6c‹c‡6cƒc6c{cw6csco6ckcg6ccc_6c[cW6cScO6cKcG6cCc?6c;c76c3c/6c+c'6c#c6cc6cc6cc6ccџ6cћcї6cѓcя6cыcч6cуcп6cлcз6cгcЯ6cЫcЧ6cУcП6cЛcЗ6cГcЏ6cЋcЇ6cЃcŸ6c›c—6c“c6c‹c‡6cƒc6c{cw6csco6ckcg6ccc_6c[cW6cScO6cKcG6cCc?6c;c76c3c/6c+c'6c#c6cc6cc6cc6ccџ6cћcї6cѓcя6cыcч6cуcп6cлcз6cгcЯ6cЫcЧ6cЦ6`Ц\Ц6XЦTЦ6PЦLЦ6HЦDЦ6@Ц<Ц68Ц4Ц60Ц,Ц6(Ц$Ц6 ЦЦ6ЦЦ6ЦЦ6ЦЦ6ЦќЦ6јЦєЦ6№ЦьЦ6шЦфЦ6рЦмЦ6иЦдЦ6аЦЬЦ6ШЦФЦ6РЦМЦ6ИЦДЦ6АЦЌЦ6ЈЦЄЦ6 ЦœЦ6˜Ц”Ц6ЦŒЦ6ˆЦ„Ц6€Ц|Ц6xЦtЦ6pЦlЦ6hЦdЦ6`Ц\Ц6XЦTЦ6PЦLЦ6HЦDЦ6@Ц<Ц68Ц4Ц60Ц,Ц6(Ц$Ц6 ЦЦ6ЦЦ6ЦЦ6ЦЦ6ЦќЦ6јЦєЦ6№ЦьЦ6шЦфЦ6рЦмЦ6иЦдЦ6аЦ&" WMFC Ј%Ј…ЬЦ6ШЦФЦ6РЦМЦ6ИЦДЦ6АЦЌЦ6ЈЦЄЦ6 ЦœЦ6˜Ц”Ц6ЦŒЦ6ˆЦ„Ц6€Ц|Ц6xЦtЦ6pЦlЦ6hЦdЦ6`Ц\Ц6XЦTЦ6PЦLЦ6HЦDЦ6@Ц<Ц68Ц4Ц60Ц,Ц6(Ц$Ц6 ЦЦ6ЦЦ6ЦЦ6Ц6ЩЭ6бе6йн6сх6щэ6ёѕ6љ§66        
666!%6)-61569=6AE6IM6QU6Y]6ae6im6qu6y}6…6‰6‘•6™6ЁЅ6Љ­6БЕ6ЙН6СХ6ЩЭ6бе6йн6сх6щэ6ёѕ6љ§66 
666!%6)-61569=6AE6IM6QU6Y]6ae6im6qu6y}6…6‰6‘•6™6ЁЅ6Љ­6БЕ6ЙН6СХ6ЩЭ6бе6йн6сх6щэ6ёѕ6љ§66 
666%€(%€RLœџџџМ ArialžŸ ЁЂЄЅІЇЈЉЊЋЌ­ЎЏАБВДЕЖЗИЙК%Tdœб‚
UserSpecifiedSizeRatio  1
О‡@
VerilogCode
О‡@œLTDMMUHSSH&%W,ФC­
VHDLCode
ЄLЄЭЭ
VhdlMapping     DefaultVhdlMapping
%€(&%%€W$Ф
PROPS!
—
E0      X       13125   13125           1       0        DR      0
Э
E1      V       13126   13126   Valid   1       0        DR      0
Ž
E2      X       15625   15625           1       0        DR      0
%€(%€%€V,„я       љ=
!
„я       љ
„=
SIGNAL  dwb_DAT_O
„я     &%%€V0CвшЖDЕчЕчгDгDЕ%€(%€RLНџџџ ArialДArialArialџџCCMSTT315b3b3a84tНџ Arial`ѓcˆ
DIRECTION       output
:Ÿўy№ˆгMS%Td1XјЂ
RADIX   hex
О‡@
GRID    0        1       0        1       0        16711680        0        0
О‡@1XLTCOMP047-&%W$щŸq–ђ–h%€(%€%€V,o^НгН^–гo^Н^&%%€W$H‘
ZqQš
Qh%€(%€%€V,*^xгx^Qг*^x^&%%€W,ZщŸ–§%§%ђcђ%€(&%%€W$ЌŸ’–Е–‰%€(%€%€V,o€НѕН€–ѕo€Н€%€RLНџџџŒ
ENDGRID -1
Œ
Clock   Unclocked
 Arial?CЏO№ˆгАMSTT315b3b3a84t#ѕXX>№C№'ˆ‹ƒ–,fЕЕџ(Qїˆ‹Arial%TlЫnL
EdgeLevel       neg
О‡@
Set     Not Used
О‡@ЫLXHIT 00)%%
€(%
€(RLНџџџ Arial ВArialArialџџCCMSTT316eafa793tНџМ ArialIOч?CЏO№дМг%TXЧЄю
Clear   Not Used
О‡@
ClockEnable     Not Used
О‡@ЧЄLP31%%%
€(RLпџџџ Arial#XX<KДƒгC+ЕЕCџ(Q%(RLЮџџџ Ariald в4d˜Ъњ*œа ž#0%`'Њ)<) ***:*Ш,r-P...Ъ/к1ž33т3ђ44і555&565F66(686Ќ6М707@8:8J8Z9f:Ђ:д;
ActiveLowSetClear       True
;@;p; ;ф<=R>(? %(RLЮџџџ ArialQњR*RжRцSОSЮTTмTьWXlXђY"ZоZюZў[[€[[ [А\’]М]Ь^B^№_”`VaaєbВbжcаcўde&fRfgXghizjфkІkжmцooИoШpRpbprpцpіrrr‚ssžtpu^%T`:Ÿ}з
AsyncSetClear   True
О‡@
ActiveLowClockEnable    True
О‡@:ŸLTlogRLпџџџ Arial’Ж“<“Ў”Є”к•`•ў–Ф—p˜B™™жšp›жœ–œф2~ДžžиŸHŸ€ŸЦŸі LЁЁ4ЁdЁ˜ЁШЁјЂ(ЃЖЃюЄ.ЄfЄžЅ(ІІ2ІМІъЇ ЇŒЇЮЈаЉьЋЋ<ЋŠЋИ­­H­О­ќЎ*ЎhЏ†%TT~Ае
VhdlType        std_logic
О‡@
VerilogType     wire
О‡@~АLP2RLЮџџџ ArialЮюЯЯBаМаЬбюбўв(вRв|вІдPж\зšйй&кlм8н>оОр^т‚умхОчш0шZш„шЎшищщ,щVщ€щЊщд&" WMFC ЈЈ…щўъ(ъRъ|ъІъаэюˆёДђќѓ&ѓPѓ€ѓАєєPєѕѕVѕДі
SystemCType     sc_logic
і@і‚%TŸК     з
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
О‡@
StateEquation   Hex(Inc(0,2,5))
О‡@ŸLd(IC_SETS)+4$!!!%
€(%TTЄAю
HighVoltageThreshold    5
О‡@
LowVoltageThreshold     0
О‡@ЄLP4%RLНџџџ Arial7 8`8p8€8:::(:8;Š<и=І>ŠAŒBŒC DфDєEтFМHXHhI†JŒL„L”LЄLДMўNNЦNжOфOєPрP№RRRМRЬRмSЪU>VjWtW„W”Y2Zђ[Р[а^0`zcehgьjbl2mь%TThЄŒю
LSB     0
О‡@
MSB     31
О‡@hЄLP3%RLНџџџ Arialu2u\u†uАuкvv.vXv‚vЌvжww*w~wЈwвwќx&xPxzxЄxЮxјy"yLyvzzZzаzњ{${N{x{Ђ{Ь{і| |J|t|ž|Ш|ђ}}F}š}Ф}ю~~B~l~–~Р~є(\€xz‚Jƒ.%TTпЄю
SignalActionType        0
О‡@
isFallingEdgeSensitive  False
О‡@пЄLP0%RL     ­џџџМ Arialœ6œ’œЬœі `Вž.žxžєŸHŸЬ  ьЁRЁЈЂЂdЂАЃЃrЃРЄЄfЄЎЄиЅЅ,Ѕ`ЅЅРІІ€ІжЇBЇ–Ј
isRisingEdgeSensitive   False
ЈPЈИЈўЉZЉ€ЉЊЉаЊ&ЊLЊ~ЊЎЋЋfЋМЌ"ЌvЌф­&­†­ШЎЎN%      TlЮво
DrawAnalog      0
О‡@
BooleanEquation
О‡@ЮLXWAY 0O98.&
NegTolerance    0
%
PosTolerance    0
%€V0GЕ*MHL)L)ЖHЖHL%€(
UserSpecifiedSizeRatio  1
%
€(%
€(%
€(%€RLНџџџ Arialserif faces.  Terminal strokes are cut on the diag which helps to give the face a less mechanical appearance.  Arial is an extremely versatile family of typefaces which can be ed with equal success for text setting in reports, presentatio u%TTўЄ"ю
VerilogCode
О‡@
VHDLCode
О‡@ўЄLP2ht%%
€(%
€(RLНџџџ Arialype ЈИЈўЉZЉ€ЉЊЉаЊЊ&ЊLЊ~ЊЎЋЋМЌ"ЌvЌф­&­†­ШЎЎNЎŠЎФЏЏ4ЏfЏ–ЏЦЏ№АА@АnА˜АфБ(Б^БšБЮБќВ0В`ВšВФГГ>ГjГЈГиДД8ДpДЄДвЕЕ2ЕbЕ’ЕЦ%TTIЄmю
PROPS!
О‡@
E0      X       3125    3125            1       0        DR      0
О‡@IЄLP1ec%&%W,
E1      V       13125   13125   Valid   1       0        DR      0
CСйИLИ::а%€(%
€(%€%€V0’‘
g’g‘
g‘
’’g%€RLНџџџ Arial versatile family of typefaces which can be used wequal success for text setting in reports, presentations, magazines etc, and for display use in newspapers, advertising and protions.http://www.monotype.com/html/mtname/ms_arial.htmlhttp:/el%TšN‡
˜
E2      X       15625   15625           1       0        DR      0
О‡@
!
О‡@šNLdWORD SELECT bB400--%-0)&%W$
Чšа‘%€(%€%€V,ь‡:ќ:‡ќь‡:‡&
SIGNAL  dwb_WE_O
%%€V0вž‰з„€ЃбЃz„з„%€(&
DIRECTION       output
%%€V0вž‰zЃб„€„зЃzЃ%€(&%%€W$ С2@)Ъ)7%€(%€%€V,.PЃP.)Ѓ.P.&%%€W$ы§
§ЯєЦє%€(%€%€V,Эš
Эєš
Э&%%€W$ыН2Я)ЦєЦ%€(%€%€VЎAп9ЦЩЬЯбджиклн о#п&п)п+п.п1о3н6л8к:и<ж>д?б@ЯAЬAЩAЦAФAС@О?М>Й<З:Е8Г6Б3А1Џ.Ў+Ў)Ў&Ў#Ў ЏАБГЕЗЙМОСФЦ&%%€W$ ц2І)я)%€(%€%€V,„Pљљ)„Pљљ%€%€V,“PP“)“P“%
€(RLНџџџŒ
RADIX   hex
Œ
GRID    0        1       0        1       0        16711680        0        0
 Arialesign, Arial contains morhumanist characteristics than many of its predecessors and as sch is more in tune with the mooa%(%
€(  %€RL     НџџџŒ
ENDGRID -1
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Clock   Unclocked
 Arial is softer and fuller thain most industrial style sans serif faces.  Terminal strokes ar cut on the diagonal which helpe%      Te\8І
EdgeLevel       neg
О‡@
Set     Not Used
О‡@e\LdTO/FROM CPUe)4)0470-0TДХKL
Clear   Not Used
О‡@
ClockEnable     Not Used
О‡@ХLpTO/FROM EXTEN I/Fr)4)047-+)-0)&%W(C^ы™L™тUт%€(&%%€W$LйiыUт`т%€(%€%€V,WЛЬ     WЛЬтW       WЛ%€RLНџџџ Arial#XX<K'ДƒгC+ЕЕCџ(QїДArialArialџџCC%TdИІg№
ActiveLowSetClear       True
О‡@
AsyncSetClear   True
О‡@ИІLTBYTE--)-TxwFЈ
ActiveLowClockEnable    True
О‡@
VhdlType        std_logic
О‡@wFL\SELECTS–--%-0)-%
€(%
€(RLпџџџ Arial#XX<K'ДƒгC+ЕЕCџ(QїДArial%(RLЮџџџ ArialНџalIOч?CЏO№ˆгMSTT315b3b3a84t#ѕXX>№C№'ˆ‹ƒ–,f%(RLъ&ЪWMFCЈЈ…Юџџџ Arial,,М                  џu…QЅЇ4№шшш2ЗrŽўњєєd22dr-%T`G
VerilogType     wire
ŸŠ
SystemCType     sc_logic
з
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
О‡@
StateEquation   Hex(Inc(0,2,5))
О‡@G
HighVoltageThreshold    5
ŸLTlogXRLпџџџ ArialXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX%TT‹
LowVoltageThreshold     0
Аœ
SignalActionType        0
е
MSB     0
О‡@
LSB     0
О‡@‹
isFallingEdgeSensitive  False
АLP2RLЮџџџ Arial%(      %T
isRisingEdgeSensitive   False
ŸЧз
DrawAnalog      0
О‡@
BooleanEquation
О‡@
NegTolerance    0
ŸLd(IC_SETS)+3$!!!ŒF.ќ-ћC Arial???????-2
PosTolerance    0
QWSET 0--)%2
UserSpecifiedSizeRatio  1
ЁWSET 1--)%ћCМ Arial??-2
VerilogCode
С       ˜...ћC Arial???-2
VHDLCode
1
sSET--)ћ2 Arial-2
PROPS!
r
6    IC_SETS-1м$!!!њ-ќџџџ-$pš
2š
2ќpќpš
њџџџ-№ћC Arial-№ћC Arial?????????????????????????-№ћC Arial?????????????????????????-№ћCМ Arial????????????4????????????-№-ћC Arial?????????????????????????-2
E0      X       3125    3125            1       0        DR      0
o№TAG 0)-4%2
E1      0        3467    3467            1       0        DR      0
П№TAG 1)-4%ћCМ Arial???????5???4?????????????-2
E2      1       13125   13125           1       0        DR      0
п       5...ћC Arialypeface Љ The Monotype Co-  2
E3      0        13126   13126           1       0        DR      0
џTAG)-42
E4      X       15625   15625           1       0        DR      0
O
Ї    IC_SETS-1м0%--)-%њ-
!
-$ЁL
L
SIGNAL  dwb_SEL_O
ЖЁЖЁL-№
DIRECTION       output
ћ       М"SystemЮќєcФјПЯ -
RADIX   hex
№-
GRID    0        1       0        1       0        16711680        0        0
№ћCМ Arialorary sans serif design, -№-
ENDGRID -1
№--!2
Clock   Unclocked
эEFFECTIVE ADDRESSс-))-0(---000---њ--$}š
k       š
k     ќ}ќ}š
-№ћC Arial appearance.  Arial is an-№ћC Arial?????????????-№ћC Arial?A?A?A?A?A?A?A?A?A?A?A?A?-№        -ћC Arial?A?A?A?A?A?A?A?A?A?A?A?A?-2
EdgeLevel       neg
o‡Word 0B%%%2
Set     Not Used
П‡Word 1B%%%-2
Clear   Not Used
п       и...ћC Arial?A?A?A?A?A?A?A?A?A?A?A?A?-2
ClockEnable     Not Used
џ№Word IC_SETS-2B%%0%--)-%2
ActiveLowSetClear       True
O
№Word IC_SETS-1B%%0%--)-%-
AsyncSetClear   True
№њ--$
ActiveLowClockEnable    True
LHLHЖ
VhdlType        std_logic
Ж
VerilogType     wire
L-№-
SystemCType     sc_logic
№-
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
№њ--$)L
StateEquation   Hex(Inc(0,2,5))
L
HighVoltageThreshold    5
Ж)Ж)L-№њ--%QLQ-7-7
LowVoltageThreshold     0
-№њ--%ќљќљš
š
-№њ--%7
LSB     0
7[-№-ќ-$^Q7ЦQ^Q--$ccЦЦњ--#'+/37;?CGKOSW[_cgkosw{ƒ‡‹“—›ŸЃЇЋЏГЗЛПУЧЫЯгзлпучыяѓїћџ#'+/37;?CGKOSW[_cgkosw{ƒ‡‹“—›ŸЃЇЋЏГЗЛПУЧЫЯгзлпучыяѓїћџ#'+/37;?CGKOSW[_ccccccccџcћcїcѓcяcыcчcуcпcлcзcгcЯcЫcЧcУcПcЛcЗcГcЏcЋcЇcЃcŸc›c—c“cc‹c‡cƒcc{cwcscockcgccc_c[cWcScOcKcGcCc?c;c7c3c/c+c'c#cccccccccџcћcїcѓcяcыcчcуcпcлcзcгcЯcЫcЧcУcПcЛcЗcГcЏcЋcЇcЃcŸc›c—c“cc‹c‡cƒcc{cwcscockcgccc_c[cWcScOcKcGcCc?c;c7c3c/c+c'c#cccccccccџcћcїcѓcяcыcчcуcпcлcзcгcЯcЫcЧcЦcЦ`Ц\ЦXЦTЦPЦLЦHЦDЦ@Ц<Ц8Ц4Ц0Ц,Ц(Ц$Ц ЦЦЦЦЦЦЦЦЦќЦјЦєЦ№ЦьЦшЦфЦрЦмЦиЦдЦаЦЬЦШЦФЦРЦМЦИЦДЦАЦЌЦЈЦЄЦ ЦœЦ˜Ц”ЦЦŒЦˆЦ„Ц€Ц|ЦxЦtЦpЦlЦhЦdЦ`Ц\ЦXЦTЦPЦLЦHЦDЦ@Ц<Ц8Ц4Ц0Ц,Ц(Ц$Ц ЦЦЦЦЦЦЦЦЦќЦјЦєЦ№ЦьЦшЦфЦрЦмЦиЦдЦаЦЬЦШЦФЦРЦМЦИЦДЦАЦЌЦЈЦЄЦ ЦœЦ˜Ц”ЦЦŒЦˆЦ„Ц€Ц|ЦxЦtЦpЦlЦhЦdЦ`Ц\ЦXЦTЦPЦLЦHЦDЦ@Ц<Ц8Ц4Ц0Ц,Ц(Ц$Ц ЦЦЦЦЦЦЩЭбейнсхщэёѕљ§  
!%)-159=AEIMQUY]aeimquy}…‰‘•™ЁЅЉ­БЕЙНСХЩЭбейнсхщэёѕљ§ 
!%)-159=AEIMQUY]aeimquy}…‰‘•™ЁЅЉ­БЕЙНСХЩЭбейнсхщэёѕљ§ 
-№-ћdМ Arial??????-
2
MSB     3
œDMMUHSSHњ-%ЄLЄЭЭ
SignalActionType        0
-№њ--%Э
isFallingEdgeSensitive  False
Ž
isRisingEdgeSensitive   False
-№--$„я     љ
DrawAnalog      0
„=
BooleanEquation
„я     њ--$DЕчЕчгDгDЕ-№-ћC Arial?????????-
2
NegTolerance    0
X1COMP047-њ-      %–ђ–h-№ --$Н^–гo^Н^њ- -%Qš
Qh-№ --$x^Qг*^x^њ- -%–§%§%ђcђ-№ њ- -%–Е–‰-№ --$Н€–ѕo€Н€-ћCŒ
PosTolerance    0
Œ
UserSpecifiedSizeRatio  1
 Arial?????гu???????t-        2
VerilogCode
ЫHIT 00)%-
VHDLCode
№-
PROPS!
№ћC Arial? ???????-
E0      X       3125    3125            1       0        DR      0
2
E1      V       13125   13125   Valid   1       0        DR      0
ЄЧ31%%-
E2      X       15625   15625           1       0        DR      0
№ћ! Arial-№ћ2 Arial?A?A?A?A?A?A?A?A?A?A?A?A?-№ћ2 Arial?A?A?A?A?A?A?A?A?A?A?A?A?-2
!
Ÿ:logћ! Arial?A?A?A?A?A?A?A?A?A?A?A?A?-      2
А~2Бћ2 Arial?A?A?A?A?A?A?A?A?A?A?A?A?-2
SIGNAL  dwb_STB_O
Ÿ(IC_SETS)+4$!!!-
DIRECTION       output
№ -       2
RADIX   hex
Є4Б%ћC Arial?????????????????????????-             2
GRID    0        1       0        1       0        16711680        0        0
Єh3Б%ћC Arial??????????????????????w??-    2
ENDGRID -1
Єп0Б%ћSМ Arial?????????????????????????-
2
Clock   Unclocked
ЮWAY 0O98.њ--$HL)L)ЖHЖHL-№-
EdgeLevel       neg
№-
Set     Not Used
№-
Clear   Not Used
№-ћC Arial??????†??????????????????-       2
ClockEnable     Not Used
Єў2Б%-
ActiveLowSetClear       True
№-
AsyncSetClear   True
№ћC Arial??????????????Њ?????????Ћ-       2
ActiveLowClockEnable    True
ЄI1Б%њ-%ИLИ::а-№-
VhdlType        std_logic
№--$’g‘
g‘
’’g-ћC Arial?????????????????????????-2
VerilogType     wire
NšWORD SELECTB400--%-0)њ-%а‘-№--$:‡ќь‡:‡њ
SystemCType     sc_logic
--$з„€ЃбЃz„з„-№њ
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
--$zЃб„€„зЃzЃ-№њ--%)Ъ)7-№--$P.)Ѓ.P.њ--%єЦє-№--$Эєš
Эњ--%)ЦєЦ-№--v$9ЦЩЬЯбджиклн о#п&п)п+п.п1о3н6л8к:и<ж>д?б@ЯAЬAЩAЦAФAС@О?М>Й<З:Е8Г6Б3А1Џ.Ў+Ў)Ў&Ў#Ў ЏАБГЕЗЙМОСФЦњ--%)я)-№--$љ)„Pљљ--$P“)“P“-
StateEquation   Hex(Inc(0,2,5))
№ ћCŒ
HighVoltageThreshold    5
Œ
LowVoltageThreshold     0
 Arialesign, Arial contains mor-№-
SignalActionType        0
№
-ћCŒ
MSB     0
Œ
LSB     0
 Arial is softer and fuller tha-2
isFallingEdgeSensitive  False
\eTO/FROM CPU)4)0470-0!2
isRisingEdgeSensitive   False
ХTO/FROM EXTEN I/Fс)4)047-+)-0)њ-
DrawAnalog      0
%™L™тUт-№       њ- -%Uт`т-№ --$WЛЬтW     WЛ-ћC Arial???<?K???-     
2
BooleanEquation
ІИBYTE--)-2
NegTolerance    0
FwSELECTS--%-0)--
PosTolerance    0
№-
UserSpecifiedSizeRatio  1
№ћ! Arial-№ћ2 Arial?џ?-№ћ2 Arial-2
VerilogCode
ŸG
VHDLCode
logћ! Arial?????????????????????????-  2
PROPS!
А‹
E0      0        3125    3125            1       0        DR      0
2Бћ2 Arial-№-2
E1      1       13125   13125           1       0        DR      0
Ÿ
E2      0        15625   15625           1       0        DR      0
(IC_SETS)+3$!!!O 6.0 ShapesVisio.Drawing.6є9ВqўџўџеЭеœ.“—+,љЎDеЭеœ.“—+,љЎ"о@€HP\ht
Ќф  PagesMastersPage-1BoxDynamic connectorМ8Œ€”Visio (TM) Drawing
!
:N„THїЗLƒRэlъёщђџџџƒџіђџѓћ№јё‰€ъё€ €џРРРцццџЭЭЭГГГяššš!€fџffMMM3џ33яяяњњњ$ы№мџ
$ы№мџ
SIGNAL  dwb_ACK_I
Uы№џђ№3ы№8шѓ@њєсњіёъёуј§ы№Tdџ Arialъ@чєNПWingdzsЊ@чєN@tMџonotype ЏSort+чє
њNtSymbol5Tы№?шѓа?ђџкъё шѓY@-1Uы№џђ№ы№шѓ њєы№іёъёJчє:ы№Dы№T1шѓ€ђёEWђёрћ-ъёhъчєы№Tы№T…ы№<пќŒŒцѕЎ‘*ы№Њы№ы№ы№  ы№
DIRECTION       input
Њы№ы№ы№
ы№ъы№“уј/РUљКпbеў
bOў…Иъё‰џ0zЎGсz„Ѕ?Ж@цѕП8@‘H2!kWЎb*Ѕ†МъёUВ
RADIX   hex
ь
‚+Ÿ$Ў‡РъёйPры№L/^&9^$р? { ђ№яAшk^&Ž™,™,™'%/‰v&Ž&Ц‚       *
GRID    0        1       0        1       0        16711680        0        0
1 yрЙ
‚€‚ )‚ЎPР? 2
U
U1ЄШŠъёэ2?§k9лЏaўBBHEЊHEHEHEHE‚HEH@ ?В>з?щ:`T2BBHEHEHEUHEHEHEHE%H@„Ьъё%O9      ЃаъёF7AOY@;P
ЬAsVsVЬA!ЇдgLTkYЗиъёї  WЭ_Wп_ќ_њ !`Г#Ј•k4l•ƒb”6u`kђWŽ     *4l
ENDGRID -1
4l•Нмъё§Б%Y№?ˆˆP:?-\
Ѓ#!ю+|QtKf2|2|2|I2wŠGОръёQAUѓoІTMeE$жttAПфъёв%_8BOTOfOxOŠOВ?Ф?HЌOш?њ7РшъёмЛXњuЛWР?ыаќŽYиžђˆsU4‘х2–
Clock   Unclocked
TŸ*<N`r@„–ЂД„k!–JŽЌ§†Ž0ЌЉ–ŽPЌЌ&Ќ 3•ŽЇ
•1’ьъёїмЏюЏПП$П6Пуќw
Р[ЕiИЛњё”|Г .ф”ујМЫЏi7'04’UХP§iW?i?{4Lz№y‘2ї#TЩЖz“x•       x•
EdgeLevel       neg
x•Ѕx•x
Set     Not Used
Ѓ0–jPМvПˆПуј•ујШВЗl^/ЫЦ!3оТѓПjЦBjЦ6DŒ/ž/А/ў$Q0pоФ?MdjЧ^cjЧŒ4ТЬAk[Ж~ЯЯхіˆуј$YkU1%Л1ўптУэFЛе„-(‘kp
йЛ   ѓ       A.$–5-Bi`яЗб#ошяЗ9)›F/Pџтљv/ˆ/п пО/u?‡2tСrПœпœЯKЖSИЯ5мЯюЧ2ћЩŒ7сбxХэпЂя#я6@хhБ$MчюuLЕhБЪ        хеƒя•яЇяЙяЫяняяяџџ%џодŠе‘ї§ѓ)Й<щ€№Oх™U‡#5G‹˜:ёмО:ѓU2ЧqЩ Ќ?Ш/к&мwџ‰ўк&Ѓє
Clear   Not Used
<<7сбHсщпєБУ1яOВQjСPфSсHЙQ›ywщHсAt/†/˜/YOВGТ$_щpЅ4Ыћb%F!ЂДЦ8ћqТ/д#P?˜Cђ/‰§Nм^мТqЄhшE!	@d)nм{”щrѕ1PБ1	@/ЋOq•жt}Q„”!ўnПњџЄК=ВЙkх@ЦБь…Љ{…B'ФІЩ‚XVйP_0TБNJgхй2ѕ1ѕ1”Rе5P"”Q”Q[СO"P!ДЁq’[СŠrДЁДЁюrŠqŠqг‚юqюqТЂггPБТЁТЁWт§a§a7б$VтWсХе7бPБ$q"$qPБ1q1qPБ>q">qPБKqKqPБXqXqХ2eqeqZБФ2SсobZБZБdБSВTБсQcВdБPБсQсQPБсбй1Hс[<k?шtЋaі}Yя рђMД/OOш*DљЗd3qOш/ДNkS\O’ѕИ†9ђ˜EС/Ÿх/_      ??-??=е_ч_љ_ЄКБ„ИО”МбЗ'Ур–sЯ–ŸdЈŸЉЫI,OЏ0Rн7nOВ†пЏ&ЏМкЋaЬ—сбЋaW?Oрш  //Ђ?*<N`r„w€|rŽЄБdU0{yЦ?gЁ7ЁMЗFКHЃЙ}E ‚…ŸЇЏЙЏjpЯž0UЌТХ8nодP!ЭпъЦЌ!јЭ5/G/Y/k/lŸПБПЂДчПиOЯaЯsЯКŸ—ЯоŸ№ŸЏћп
я8ЏJЏ\ЏnЏ€Џ’Џuя‡яШЏк­КS№ЏуЯП&П8ПJП\ПnП€П’ПпЖПШПкПьПўПЦ$rм#Я
ClockEnable     Not Used
KЯџџя“ЯЅЯЗЯОCЯЯсЯNЩa\п"п4пFпXпjп пВпKжпГХзяћBяTяfя_/q/œяЎяРявяфяіяй/ы/,џк­ЩaRџdџvџˆџšџЌџОџаџтџєџу*<€+/`Ш§b§b‡iAnFUЏj?|?~/ї "CЖ?Ш?ВVуaР]ї?     I„a(G
ActiveLowSetClear       True
rpl/YDE@a1LOзpOћŸ#Q/ˆ­ISПGQл„BQfQaЮIq_U‚ѕ…yjŸЕ(ŸШ„Bb_(_:_/^_Ѕ/З/ЦТдQ—_Љ_†a1и_      OO-OДFСZOQo~MЮA%ФъoCХЅŽAЕšOЌOОMgy ‹N_Џr_МЬO”7ш”ZіgŸ†˜@ЊМ:oЏ,K€o-ŸXyCХЎbУddpЭddpЧСсAЭŸпŸёŸЏЏ'Џ@9ЏKЏ]ЏФvЏAЧBЫ(ŽOГЏn–ЁlХУ=#юПм?ю?6HZl•ПЏДЦŽѕ'сЖПŸŸМЏ;ŸMŸ_ŸqŸƒŸ•ŸЇŸ Я2ЯDЯVЯhЯzЯŒЯžЯАЯТЯдЯцЯјЯ
AsyncSetClear   True
пп.п@пRпdпvпˆпšпЌпОпаптп#}яя(я:яLя^яpя‚я ”яІяИяЪямяUЩ‘л’ј"џ4џFџXџjџ@|џŽџ џВџФџˆXтџєџ*<N`r„–ЈКыяоџ&8J\n€’Є‡YУечљ////A/S/e/w/‰/›/нFсёК/ќLм/ю/??$?6?H?Z?l?~??Є?Ж?Ш?к?ь?ў?O"O4OFOXOjO|OЬ O№ФOжOшOњO__ 0_B_T_f_Н™…_—_Љ_Л_Э_п_ё_oo'o9oKo]oŽFxoЉOœoЎoРoвoфoіo,>PPfxŠœЎРвфі,> nЁ—BsgcŽМE’f†˜ЊМЮрђŸŸ(ŸєйД‘JŸ\ŸnŸ€Ÿ’ŸЄŸЖŸШŸкŸьŸўŸЏ"Џ‘OeЕOjЏ|ЏŽЏ ЏВЏ@ФЏжЏшЏњЏПїж(П:ПLП^ПpП‚П”ПІПИПЪПмПюПЬBЋ#vбX„ИT‡+С„Sb ‰Рbсz„@v6РMЯ_ЧTƒoЯЦ6РЯŸЯБЯУЯеХТтЯiэнё      пп-п?пQпcпuп‡п™пЋпНпЯпЯ­,ыЪ/-я?яeСYƒ[яЦЏ№€yя‹яяЏяСягяхьѕяџџ+џ=џOџaџsџ…џ—џЉџЛџспЦбьџ1Х„RфыщZЬsc<Ц“`Zl~еХsbЏ6-Ÿ1R#лэџ#5GYk}ЁвџІЮx;6Х/Fя%/jяI/[/m//‘/Ѓ/Е)Т/д/ц/ј/
ActiveLowClockEnable    True
??.?@?R?d?v?ˆ?š? YTV
|ъ?bЯO†Я2ODOVOЮЯzOђЯaqЃOЕOЧOйOыO§O_!_3_E_W_i_{__Ÿ_Б_У_е_ч_љ_oo/oAo}x^oKџ€Acroџbat Distпillerо§џ”ъo€Џщђd7XXя№6њнўы№РШсфї  рћ$ь…џѓ)ѓ/ž@oр  .0ТВr
VhdlType        std_logic
dtујџџв        гТ'9K]o“ЅЗЩлэўрћCustom ?page 0ќ,/FнўBN#/#1>/‚/?/Q/
*2”/и/•/Ї/
*3ъ/.?ы/§/d:§hы№#џwinspoџolAcrobџat Distiџllerc:\џProgram џFiles\Adяobe\4.0џ\PDF Outџput\*.pdfмџUFы№џђ№ы№DшѓfњєёђџџъёP
рћіёъёh> ы№/Tы№6DЊъёы№’ујƒUmAшѓ@›
Р?­лПIшѓ№?ПСYзщћ{џвъёЗъёO•1@цѕ3EEbOУe„ZЁцѕ
VerilogType     wire
•ы№Hu§щђ ѓ№ящђџ˜џP№р№(:њџџŒˆџџ№{ŒW‹џ№_€qƒ•ЇЙЫеŒтџ§Qы№Generiџc box wiџth text џand connџection pџoints. Cџan be stџretched ћtoy dimwenss.mbујшПшѓр?єєўрПшДNoшПр?kш?рћєР4
№ћє№П•Hы№џђ№ыєы№DDы№іёщђђё
яє$#       фї=hчєіё-(>Tы№пќіёTE=›ујѕ‰›UAшѓј?ЇА№КЏшЏр?Q6   Ял‰uŒ` 6еўьu   і      mB>ъё0Œ0       Ќ0іё(2s@sJs&T„>ъёЁ5
ћ‰€LЇ@ўЃ‰ъё{Ё§Фђ№пўф5Аџ`7Copyriџght 1999џ Visio Cџorporatiџon.  All§  "s reseџrved.ўі‰` _SBlџ.chm!#22П448ў ‘dЌ9   l>#0>Uddтљ#3     ˆ       Фіё‰уј        ЌŠTЁ
SystemCType     sc_logic
ќ<hЋђbЪ ў
2Є61
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
g,s72‹Э4Ё?`b?ўM1^%Y?Фr?9€1M1E ;6З==з5(2ш?;z‰rA
StateEquation   Hex(Inc(0,2,5))
РўIB=OCРўq‰…,^пќ35Д/™rујVЁ:в№?@цѕгFќьAьCїMЎA КOеMмOюO@_2ЎAа#[6рвO€MZMь"3їЎA^%\$_Ÿ_Б_Z_ўи_B#[@ЗoЕ_П9Boў[(љ
^цѕtextеРы№Hы№lы№&ї'щђдяњъёџН!џРOyŽaў§єGEгџЉГфїчєFы№ФџВїЭЂюы№ж#ы№ќДїПoJы№Bћ
HighVoltageThreshold    5
ы№ЖїЙj]\a\k_@+ы№dkЅ3aђёЬkIkў№ж•ы№ы№ѓєщђ%мёUlы№4ы№,чєїѕџў_€ђj @џЊЂъДфМ%@вујъёы№дљ]ы№•A-Ь3c7"Aљі%Ulы№4ы№,чєћѕџў_€ђj @џЊЂъДфМ%@вујъёы№|љЋы№A-”3Б7њѕUžы№ы№~пќчє}@ы№Lљeђ№Fы№Rмџ0BTf*
фЗђ№BHы№<мџ(
LowVoltageThreshold     0
Hы№<мџ(
SignalActionType        0
Užы№ы№~пќчє§Eы№”љ,
ы№Rмџ0BјTf
,љ9UFы№џђ№ы№Dшѓfњєёђџџъёа
рћіёъёh-Tы№пќUдUцѕ’уј”ы№[U@шѓ@—?шѓлР?ЉПIшѓ№?`Лd
мюїbu‘ЉўoqЈYkчєЈујQ‘§hђ№u23uъќі№‘`   Cџonnectorїў
MSB     0
‘`ў–
LSB     0
œe‘1Crw
isFallingEdgeSensitive  False
ƒујЉUы№HыЄъё ѓ№–ўяђџ^€џџџПџўџќњј№єџїєїїЕŸ  €-џ}|5pїџ`Iоџџ`V?џпџ}ƒџ`Сџџјƒx‹їџїaŠџџѓ833џŠџџƒџ‰џџѓџџџя‰џ‡Ž‡‡џƒџљо…џ Ÿ™џЊŸџ™љ]ЉџŽЗ№ўТџ№ƒ3Яƒƒ3‚Й†“Уu…Ыџ‚ŸЉОпџ3“3?,№      ї™?№џŸ№ўG‡xpџџ№хx“^мŠџ№ƒ‹џ&яŒџŒџ
ƒДџ§Cы№This cџonnectorџ automatџically rџoutes beџtween thПe shapi
tіѕs.­bујрПєє?ќќПџшДNрП?єџ•Hы№џђ№ыєы№DŠы№ы№щђђё
@яє#      фї      іё=hчєЕы№8Tы№ пќYY9    BЊы№ы№ы№›ујFо    U@шѓј?ЊЗ
№ШПЗрПрлПP6
isRisingEdgeSensitive   False
‰u
DrawAnalog      0
я`u#`фџb€AЛ@ўќu
J ‰.Q#DB˜ц     ˜#ж‰uŒ`hр?U\hr|Suі№†‰эZ‰aкчŽ‰Жа{@-№?bH—l;'bE-h’o'—y(œ‰ъёќБ
BooleanEquation
т2rЧqЧс?@ŸєIЭ kЯ?У$бЫ%П?э
NegTolerance    0
Ї@§ƒўі"VЗў*5L Н-brъё/РŒ     ^vдœvі"(2u&€.і"q28i˜vі"uh9 BdД&<O/MЃъё{
PosTolerance    0
#‰§ђ№і1ўћ45ќ`џVis_SBlџ.chm!#22Ÿ474ў`џ7Copyrigџht 1999 ў@io Corpџoration.П  All $AUd3CE„ ‰\^ДŠў4
UserSpecifiedSizeRatio  1
*Lд’1њ$b–‘24„R‹Ÿ(^[аw[D ˆZЬQi‰       ќaЈч59       Ь9”уј3ЬOп'2Х"qМ?/g;2щGеРы№Hы№lы№sї'щђ$њѕы№џН!џРOyŽaїўѓGEгЇДфїчєFўы№РїyЛЮы№ж#ы№ЄџТїG7ПB
VerilogCode
ы№LФї~$ы№drъёХoъё@+ы№I”k€"sђёќk5чoЯў№ж•Кы№(ы№†мџсњъы№чєы№ќБїПД–ы№SћЩы№ŒЎїJї+B?Њы№Д9љ=3ы№RћDы№œАїFсPi{"ОїŸЖ˜/ъё| ы№мџUы№џђ№ы№Pшѓxњєёђмџ№ПP4фїіёъёFчєы№Dы№Teъё€ёђyŠ
рћaъёhjчєы№ НTы№ЁпќРРцѕы№’њујƒqUIў_џ€ђj @IЊЂъДфМ%@?шѓ[Р?ПI?*ря?QcтљџR`›ьъё‘@цѕ†œ№?ЎЃыЯуqуя–НuР`Фщђеўсчёu$ ћoшы№ХАTч <ЈујQ§ђ№4w!яw!ыѕќ Н`        Coџnnectorћў
VHDLCode
Н`ў*˜"
PROPS!
ž*eН3a$Шпќ$Э$ч      Р!aUы№ы№Ь        ы№ЊЋ!ы№ы№
ы№*ы№ы№ы№ы№ЫUы№ы№6$СU!ы№"ы№#ы№'ы№U(ы№)ы№*ы№+ы№,ы№-ы№2ќцѕЋ!+1Hњ<—4РЂ7у—4яЂ7"”7!Ђ7А—4aЂ71“81Ђ71“81Ђ71“81Ђ7Я—4ЯЂ71“81Ђ7Ћ!“8Ћ!Ђ7'1“8'1Ђ7+1“8/1Ђ7/1“831Ђ731“8Ÿ:71“8?1Ђ7;1“8G1Ђ7?1“89!Ђ7Ы“8Ÿ:G1“8W1Ђ7K1“8_1Ђ7O1“8c1Ђ7@9!“8ФЂ7W1“8%Ÿ:ќ—4&Ÿ:_1“8k1Ђ7c1“8o1Ђ7g1“8s1Ђ7k1“8/ы№Gњo1“80Ÿ:s1“81Ÿ:w1“8‡1Ђ7{1“8а!Ђ71“84Ÿ:ƒ1“85Ÿ:‡1“8UŸ6Щу8КНP31ˆ•q•qя‡1‡1РˆW1W1!g1g1aˆя!я!19a9a1ˆа!а!1VaVaЋ!ˆ[q[q/1w1w1?1ƒ1ƒ19a.ы№Eo1чaчa‡1qq[qЂ1яiEiaZC<ђё1|ˆщZEРИ!я!ШыEцѕ!ц5ћ)є‰цѕE–:m џг@@|џ_—=щ$@Р2•™аП2•Р?p!чƒ„Š{1H-J2Щ1a2”’ЄPр?1v–<ў›УDo1<<Х<цѕј[№?ЃџџяlН1чaUЫ™Uцѕ1=Eћ/
3‰ыŽx‘ŠŠ;1™щђ‹рŠЋ:–ЁЅц5БЏ>”ЃЃАŠЏъЊ EџЏхіq411Шp_U§HPЏ™ујчa*И;Ÿ™ЉУ“ъёˆБс•d•ПŸЙПŠ’™—™˜Š’
ЯˆБу”МЄРЌПООц5”П`ЯrЯ‡ВА‘Ы:–ЈЯКЫ31АK1ќШ–FFECTIџVE ADDRESSj45/G/уј•уј*v”„пT€3†ЂвѓПчaЯЦъСЕBэСi4@пRпуј”ујјg1v›я'2+Чq'рМEР†E|ˆЯу•ЇщЯРЫняŸŸ%“ј"_ў/{в2•шЖ
E0      0        11250   11250           1       0        DR      0
2•иЖњVŸhŸzŸ0   !4Q”“\і‡рЮaq'уЌ?ƒџ•іс“kр?Фрђ№яA|0ЮŸTу эŸџŸРЏ/ЏAЏSЏeЏwЏ%П›Џ‚іШЏЏђёЏŠъП0ПBПTПfПxПŠПќієЯЦП‘ъПЕУ\џ&Х/@Я& №ьyЯD/њc/МЯ‡/јЄ/§ЯШ%§8лTAG 0
E1      1       13125   13125           1       0        DR      0
v"11
E2      0        15625   15625           1       0        DR      0
-6...-7ў"0
!
IC_SETS-1ЪвeсЃяЕя5˜ЫqЁяU3
#юџ2с•ф|UЌ?О:Yхф}8 яС38бЯпсп `п7зД‹п†J!ЂпƒчЅ§ПеїПqШqœE?Лўqq`Сkq„;OMO5ˆ5‡BѕUQZ1@яRфЃuaяsя…я—я`?r?Эяпя%ѕюєўфџ+џ=џ(ƒšqž’Vfpџ‚џ…oІџИџЪџT}9щџћџ§eQ+=Oas!—|fФЉшё0BTfxЪ/€hЇЖ/ЫjъќЭVo(У
SIGNAL  dwb_CYC_O
Ÿ>/P/мt/=Ÿk]ŸИ/ ŸўXžŸљ/Т•J;Word%0Ђ,?)ЃЂH52?ЋP?Ѕ_З_†?Ю?р?М?  щ'БЏУЏџ?O#O5OѕOYOkO†OOЁOГOХOзOGПYП
__1RIQ0С>\0СР—[_m_WРYУ_jЏ|ЏХ_з^џ6аiƒ@@|?џ—=щ$Ђ…єр*ƒаeђeРo.o`@oXёуБ.#bжЄVш0АЁHжХƒЗƒА`ФoTЭчoљogСIQ%7I[m‘XяжО…явч`яРц&8J\n€мжъŸМgџр‹џ“bп"%цџ
DIRECTION       output
иzѓŸž ;@>ВkСѕПЯkПѓтIƒП&F0ЉПЩП^ЁРCП!ЏJй'ПIQ>Q:ѕ>\>ѓ>ѕgЯyЯ€W>ѕЯЏЯСЯгЯхЯаWiCћЮиuўШп1пCпUк46uп‡п™пЯe>љПпбп”5&!япяя%я7яIяїяmяOЧ&šя@OОяOтяˆOџџ*џ<џNџ з(}џŒЁџе*Рџвџ&7&8њѓЁ_ЗOМI_Zд-є_ŽoХ(5oЯс­CJС€б1d!JЬгSб5"/ыkˆЪeX)ЇрЛQœ˜Х90СqЩ5fгЌ30СИeњ›)“эФtк@Їз
і?ќФ Ђ…ќПжzdРzdь“uўПЙPњKАЁus `НuуА`€ARў.Оru
ЦqЫw§aГб1s!ьrжђvYXИэФ:Om га§ТЉаџ шДNр?џ@ј"ў/{R/@)Ћ2p 0РюK‡€сp@z3„бqE‚K]Žьw  ьrЅ„‚ ьrТН‡œаXЮCЙE’v№Пћ2rјЂс?@Ÿє­IЯ?ќ„б•ПU?Џ|Ћ2uЎ0`X0ЖŒ3ў/’ud `Ћ Q’бBП†Ј&8‰ЉЅ§b…VhД0Й…ыQИžP4‡ЎаpЇв8вБЬ№РХБсp­0`0ўѓ!•Хџ/кј‚”fгІ[?Tе9У;№‰5Пыoџџб1Њ9кCрМ2хOг?щ?ћ:`Izaп_gв/Ÿ€C›ЗYIфЏТ#П§ЏПš™uБЙB€I7Л’vNП=ŸrНљEŠП–tЃПЕПЧJСYСЎ1РoтorІUЭћO@H%\%”ІЦ8›)‘s}V;‚в
о
RADIX   hex
Ењ›ЋЯјВўЙрB• Й(бьsђ‘ ќsHжЊ1L%‡ЏьOўOЙЂТЏдЏ9ЙъШіПЯђз2I7Пнп[Зњпч/ПюЏ:яLя›ф~Пбоˆяєп–щ!q,Я>ЯPЯbЯtЯ[&КЁ,Ё—Ф§gHwžЩЎ1u›)QРЋ!2ŒтХеіњ›E№ygP-DTїћ!љ[‘ˆ->П}фbлxЛ€ж@ў"Ћ1”лxФyбvЩrФr
GRID    0        1       0        1       0        16711680        0        0
дsрrлrhп (п:лqLйИ‰xОџ=ƒх
@E‚CpЄa:ta„#h!rГИЗ]Зl~ИЊv€ЧД~”‘гU ŸВš
­0Х’ѓ!eњŸЉqЩRЗЩRbевA]€К4іqХ9CTџЉпЛн*rяъ$пяДхгUТ,оїл/ЧЄaб1ќе3;нog;ЈЋе5КЁnџ€џ’џЄџЌDEоД2ŒтХяіяі8€’Q‚™""\UЏ‘3,\R.H/Z$ОqQ#lFНэU0O3kRЏ“(}ЁКЁЄp˜0Оq3&\SNSZр,ЏЉT;њOјZЅ?g?џСџЄa˜aгUмpЇiDMMUт„hйЅ2yп‹пйЯQЎхdоКFяјƒoЅrQ-ЂЊQ-–QУеakFа(Ф_“Tї%k,ц'oBo'%ono€o•R˜•Ђ[OПoдXlOёU_#G5ŸarдšС–Љ"ЁІ­йОЏ1%ПйfQ`oб’щК{яјгs'%сTІИщКŠzU„/™Іi‘tЯЁЯ—Ј”ј—Јљy{'2U
ENDGRID -1
Э‚ХЏ’ю‘ёM‡"џп„@ѕ]?—Њ7Ю5Ц5‡Хa4~‡}–Љђ‘a В9^ѕђ‘"Ёв=“оДџ:m г†@@|џ—=щ тФЇ€РэЖЕ”Н•ў‘ПкРC
Clock   Unclocked
€ V <љ“Втx!Љ2еІв     ИоДп6аiƒЋ”Љ$кішэpx•CvІ'uЏ‡ЎЇ@нТс‚ЫЈ+ЂЎТТEчЇœє(OSЕ
EdgeLevel       neg
Н•џюП2rЧqЧс?@ŸєI0АЋЯ?&Дб.ЕПлўоъЩgн`Š|цLђячТў'%&;HŒ)ŠЊ2€A'…љ*ЎУЂ"Їux1§љB‰P`0ў€#!Xб+/=-тx“BЦBрOTтlЯ…ыђПŸџџтbбŠQjпi_y|@Ёеœ/Ў/oядяф)€mП9гя„Л™'пяя[я
Set     Not Used
п,цюПzп9п{ЗИяgоЫпŠпyЙъ
Уш'џ9џ€Kџ]џ”?І?И?Ъ?Зћtк@Ї
я№яѓo{ЕёїЛ‰+=Oas…—Љ
СМ    ћіЂб
Clear   Not Used
Жу:bЈєєcЈ€]ћіSњї€Tfћі›g
ClockEnable     Not Used
ЅъЭП/ ,Ф+Юa/s/…/—/ѕЯј/Э/п/ё/ЃoЏ':O8?yTqя      С“<%“яL%@­яПябя,šŠQєщ‘ „Њѓљё4віф3ѕ
ActiveLowSetClear       True
Њ5д3ѕњIЖ€т‘ЯЩџлџэћ Ѓ76(оеъe2‘TФЮ!вOЋ€L—ё‡†ИG      ƒ2(ВqЌ?Ъ?м6гT+р?арят‘џР8Ugd‹|п$пС8яЦ~Kй&•O0яЙMЌпе,ъOќOžлџпЃ;_ЇOœнN…w_уO”›_^Ы9~ƒЛESпET 0
AsyncSetClear   True
,a1
ActiveLowClockEnable    True
Ю7f...7g1bIC_,`S-1p‚PA‘Рv/ˆ*аЩшхTAЈUшПЪЩд3МдƒџŸbU<aЗoЩnтcЦ„PћoППiЫЩ‡ЕЬgju˜(}љф•СШd”7є4оФ!3тrѓП˜AћтъvСыїv§Дсu?ўт`еkr‹ˆ]œ$Zс€№WB/x„$%ŸЎ‡>Kˆe=™LAб6„l™фхЮ-•єщ§EК*џ?@№EќЏ_і$б%ђ3ѕиК3ѕт3ѕШ?QO)pvEє1—?.'ЂICЦ—–aPТЋ–ЅVЯT˜…йŸј„Х?Ўџџ{ЅХO+O=OOOaLrIМСЮ_ћтХI{ЋA–’Ѕ‰ЕЂЏE””Ѓ@мх{ЏлЊˆe№ЏУЦq^h БУobМЯЮЯIЉ™АLЄJ–‰ЊўН†<ТЋŸ<ТЊŸМyБvE…ПЂ˜ЇПЙЖ—ŸжГ9ЯyБЮЁП[Я'ЩyБСЅsЫS˜ŒЯžЭмхsЫРA–ЭЯ%ЫмЕ”…!hCOMPYтeZяЅ~яI/€Ђяm/roияъяќя/–јб%œПиP-DTћ!љПFџXџjџ|џŽџ џВџФџ?$?Д’џљ$§ц
VhdlType        std_logic
э29/•Є
@N§цUїќчqVџhўлВФ„џИžџhљ)Oтp˜…@цїw€‡р@z3™срђцџјўо№u?+zŸЗЗђЏ8J\n€ЯЄч_Ш(W"ш 'Uпgпyп‹ппрЏпСпгпхпїп@:Пm г@3ѓ’9•і#юц5яGяYяkя}яяЁяГяХязящяƒy;9"6џ,.Rг@.'Fірђp%|6ќџ{?>Pѓ"6Ь7!7sєЭ?п>jФѕћ?КѕOп92DVh zŒy|sЗFІИЪмю=$6КЧG(E_oй!iƒ›TЊ@ЄбWяЉ4бŽё83‡RVўXё‰|uЧQIЁi9Ёњ-‘"™ї?@|Ÿџ—=I:№ќгюеПpTа#хо}eР?бPїKй"x)€‰@@ў‚~fЙcїуй!тAVюкf<9˜"ДM#:і№2їрє NЄ4v‘?3E~дgаѓфbRаѓœ^X2ГUџ@@ш€&lнџП@€/тџВ'џС?2rЧqЧс?@ŸєIЮp•ЯУuбЬuϘm„YоПC3Kbп5D3Мsс0l!СЅ&šOAсdWA%cOuJ~ѓЊˆB‡ZИGЗУ2Цrq“Ќ?ЅЗ†aRэ”р•?ћ рУPя‰A‘џЂёPЇ6Ј› ЙС§УPљЌ H `0ўm‘ёU™O†      й!Џ“:–ОŸCTй!dŸ’STПб_џџй!Ѕ:ЗнBIП[П€IЁQЁMЁ
VerilogType     wire
_]pQ0[Ё;šАН?іzћд€‹Ѓн0]YЅШkё)Ш}`ќЏ›иVЦ™Щ
SystemCType     sc_logic
ŒCЋСЅЋ|`МuЏ”S
]Q%YЎНЏ|ЏсЏАцБіE]q@иi1hх)ƒ‡К—”Й˜h„Ж›з'З„МrBџjЂ”jП|ПЙ˜Х•Й˜dІЗЯ„Я!39ТѓПsСєЦ§DДџ~Rїѕ„8Х?{ўЗ `$а!kEdзПщПɘˆЙ˜ёQ •яDШ_ЅЗѓHдЅ—ъДŸЦ›ји•/я@VЌbЦџ\‹ќ?@Šп•љОte:PžгјZ/l/~//Ђ/Д/Ц/и/ъ/ќ/?вСљцh;?‰йFѓ
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
;ј`fЩсƒЮ?s6Љ5йцIияЖ?Eц)ї~чsє*џ<ўцqї=§Žч{џTOkxOŠOЈПЎFвСЛC’%ž=FaSЯ|TяЫOнOяO_эŸb_7_I_[_Hžоќ”SFБјaUQXЖHIT 0йТ‰СжЯшЯ•ёЃп%пˆ	Т™ЋБ1PoБpПаi6иke%Tte…fРA.А˜f€‚СЯMя_я;‰С&9ž&QДёR•РѕЬ"‘eˆжџшѓaUїџR’ь€Lс‚ЗAС’DбLйЗЗЙЭБUСUјŸч‚Т;ŠЊˆ>…fЂ?еЏЦ=ЄЏ<,ї?	OWѓЏ‘>HOД?lMШ•„O№?ЈONQ“XЖ31}њ!ЗІ_ЂДэˆ-йм‘N‘ФуW.g№”Щpе/Ѓ6аЏiУ@0-ьA.мS/e/w/‰/|рњ!ƒщlfЗ/Щ/л/э/џ/:’%4Т…`м?0?B?T?f?x?жOшOњO_в?ЅfЪZOOj1nOU’Oг‹ШOЏРг_ИѕDбVИloџg2(IC_SETS)+3aВќсѓaиё™ПU)ИГUе’ЕХЗА‘Šl*QЧŸйžИќЙЏЬДfП“ЯїП      Я$Я-Я?ЯQЯcЯuЩ гПhЏЅЯЗЯЩЦA_S_e_w_‰_›_­_П_б_у_џ@:m г†§_o!o3oEoWo|рUБƒщЦ…o—oЉoЛoЭoпoёo'9K]o“ЅŸŸ'ŸэСпvїпGяО?ятЁГ‡яѓпщНяжпсяMяCŸUŸg•4pŸ‚Ÿ”ŸІŸИŸЏмŸюŸпџЏ$Џ6ЏHЏПП~ЏЏЂЏДЏЦЏиЏъЏќЏu‡2ПDОЊє]МуtП„П–П%@АЙŽџ џ‡піПѓVЮI/А6ЯHЯZЯlЯi`jpi’&šЯЌЯОЯаЯтЯєЪ[пmпп‘пЃпЕпџ%џ7џIџяЧх4&–?—яVяЬ?2*ы?§?Ћя!OЯяŸ?WOџ{Oч?ŸOMџЪ5lї4\Вk!k]Миѓ‰™Ћ,ХзщћќПo гФ)!Хфс5ас5д5'Q/c/u/vШ4a…Щ[fЋ/Н/Я/с/ѓ/??)?;?M?_?q?ЯOсOѓOЙ?AњY_NO
O•ћZДЦbOъVvqГO;T_qјVў[ѓmіWAY 0…і/аИХџНilPRErвС]Ћa]Б!k}X_j_ГŽ_ _В_Ф_
/аiC#/5/G/"o4oFo~Рm‘…Щ•Іto†o˜oЊoМoЮoрoђo(:˜ЊМ‚{Пн?БПмеПŠOљПw6OAЯ­П~wЯП›Я(Я_jљ3:R"nŸ€Ÿ’ŸЄŸЖŸШŸкŸьŸўŸЏ &Џ8ЏJЏ\ЏnЏ€Џ 6б–)^цЎЏРЏвЏфЏіЏПП,П>ПPПbПtПвЯфЯіЯМПDџрПEЯzџЯžџЯТџБЯpЯ‚Я
StateEquation   Hex(Inc(0,2,5))
vџИЯ@Yџdаџп!Y0:R%;\џOе%ёUп2ћ–ё•пЇпШЙпЫпф€E*%Ѕщ$ЊѕUиў^ШчQŠЄ­т|х+Ля|т"(Ж9&Є“ј)|уўA2Q!|хб
HighVoltageThreshold    5
цёъŒ П
LowVoltageThreshold     0
ЈКS
Г
ЉФћ›ŽуХЁ‰ХбЅЙ_…ыQИžрЃєШT-БіЂЇSИхУ§Й’|uртА`0ўћЁ@вб§xЗ/+%]/TЌhжаУЮФПпџџЌ€Ќ)м3=Вч?TПjП|КŠПшЯњЯlЄпЃ2Я—ЮєП‘Ѓхї…Я}ѕ&цтgЯ-мЯ"ь7/I/ЮЧј+б_9ЊXWORD ?SELECTSвйуRп›Ÿ4mе9XПк!Ќђ”‘змз%Ѓев•!ЉБМЯЦы)!EЅрќ{^:HP-DTћ{!љяёˆ-SэŸфboшю2]€j@ў"рБoшJXщeц]тXтю1hуtтoт
SignalActionType        0
№ЌУjл+Еъ—=ВљŸЏуБVh       *Ь‹Œ/лН*kБ8рCoœ#ы!н2ш//§/?!?3?}ЖeAђ”жйШЃеєY­љ+dІят?@ќMВШ?@UўЛbёњЕиZuсњЕ…ШГћРxЏkO›vІГt•qЕa шЛbяІЗutЩСХr[Ы{РwрSЖvкw
ГЁЇн1ЏЉ(†ФЂs]йЊ_ЦX3П EПрoI{ПЦЈ`+o‹      п"Э;ѓн1П
MSB     0
у*2–пПU[tбcwўрС1ŸвЧУqџџъgŸ”yш†Ÿ~ЯWœbvќHš/Omi%2цЅM’Љr>17аўlЂrЃ—b.oЏoСoгoхo€їo   -?xжгPp|(Tfxu(а2  М1‹@ЏСгхЕДј­Ђп{NŽЁ,‰ЦASew‰›­ПбуЏŸ2Џ+”ŽЁ6™$жKŸ]ŸТŸŸ“ŸЅŸЗŸЩŸzпэŸџŸъЯ#Џ5ЏGЏпЯkЏ}ЊG—рЇЁ_aђ!я$Е@ЉЏЛЏЭ­“чыЇ>1њЇаm9OЗЧ…9сDфџ6аiƒ@@аџ‹јПьIў?@‚рSђCЕ]АрSBИzЯП‘Пwі8‡BЇЁ,ƒ(†@›b_SЦЂ_S–ђœі(†A’,‚)Ч3вьѓe §XљЏp:_eХƒЖШ!@Fсн1ы!?pMŽЁXы!vУ”Џ˜яЊяМямЏC?рU?g?y?‹;&іЦяЪџќGŸ
LSB     0
@@ЈS9ЃєЉ5@GѓФ?ж?ш?њ?OO0O0BOTOvџxOvС,‰и(&ЅO#љЭЬ` L§@%їђEќ_іЄмF(&€'''T/“.(&Ш'”-7'в/l_~_UЮaЂ_Д_Ц_и_ъ_ќ_o oKяoVoЧ4Gп?’g1€’ЄЖШк№ьў"@:mџ г@@ј"ў/{RNuhhДа`&1vˆšЌОатє/
isFallingEdgeSensitive  False
Э8A,‰сVТA*чOљAe юL@—)3RpСС“AЛ:g€kP@z3[Q4b:oLn{#@сV‹gрWž$ŒožnсVгgŸm№Wнo??UЯ><+N?ŒТЌБяSТAžczre?w?‰?›?­?П?б?у?ѕ?яwX.GCу>O>цiEБСWOƒЎGвEЕэЅ<Б4чсЅyl`
isRisingEdgeSensitive   False
 zr?дуyAжM‘њlh‹УР]ќПhДMРZћ˜R7Y€fР@ўЧВVt“УCсЊЁq-г•–B)F§oЬ•—ДѓгЪю—œ?иqьzI˜2rпЧqЧfАŸєEI7 Я,ЅXа7ЃПS@CСVгкСQrE5&Yx€ЕyєэЎBqТE"4zŠvP;3Ї’ШM4Ѕб)kPp`Ш ўA1уI?ЗЧЃAуu<CсYП4мгкдПџџCсjСqБС,wЧЂ|БС;х@Ј‰KEЩл}№еѓ|РЕпС€tЏПS>пёu7–Яя6Э•н$У]ЯfЃЗ?mлЖmлт|Я;ШшнЉЯЛЯЭЯМVeX``MO_OqOЈ“OЅOЗOЩOќлOТ—бёй“/ю?@я^вїXуч_r=_O_a_s_…_0—_Љ_Л_Э_?б,)јшцA/Р™р‹јПьїIћ?Т—ˆ_ФџeOЪ?y%шц@їччž$AџSўшцˆїT§їч’џдЏ,8
8?(П\?“ЅЗйПл§П<P
DrawAnalog      0
юŸyУCШ'Ћгў­TO/FROMП CPU
BooleanEquation
NegTolerance    0
EџXTEN I/FFвШCпЮєШ~dЂ@ДЦиъќC“М™џу@@|џ—W=i$Eд хаJ•Ф хРПTŸfŸ†ф@lш‰™™™l&ЎšИМ™ЅCњЉ (ѓћ)o$@4bpšБheЦ&PoХ/з.f'ђ™(<{"Ђј’77Џ‚Œ 
'-Џ?ЏQЏсš™Ж1Й"пxФŒЏАЏТЏкџцЈжвGrћЏ
ПЙ XjyШ’FCПTМOlПпM’ЙЊгЄВЕпЛПЭЕdыПˆDо`ГП?(С•Я`^аПs_…_O‡шЯ`U(Ц_yЯO‹53Rпdпvп{šпЌп0ОпаптпТ“УГ'K”фш,(рQ  7яIя[яmяя‘яЃяЕяЧяйьKaрьщєvџР–В(@‚NшД Г(:єєv L‡ѓw^єM_Žєv”‡@`‡žШџOьјјђ@AzO%7I[A_‘Ъ_Е–—xЋŸюќъ“BYTE
PosTolerance    0
UserSpecifiedSizeRatio  1
џSELECTSU>щђы№ы№ы№U#ы№$ы№%ы№&ы№U*ы№-ы№.ы№0ы№U1ы№2ы№3ы№4м№Ulы№4ы№,чєы№§џёў_€ђjџ @ЊЂъДфМK%@ујъёы№Пљ D№ѓCО-єљT7ы№AщђU2ы№ы№пќчє§@ы№$љZD7Jы№RHы№<мџ(
VerilogCode
U2ы№ы№пќчє§Eы№lљУD7
ы№RUlы№ы№Lујы№ѕчєы№дЮїџРO(їгЩяёЭїяDы№@?Њы№,%Є)ы№R-)<а;U$ы№мџ
VHDLCode
ѕ4ы№(чєєюмџU1ы№џђ№ы№(шѓы№мџіёіёцѕUы№ы№O"D&aU=шѓђёQџџJf        рћ)ъёh"Tы№y‡ъёМуј+Uvы'_Щ…&aQ-З
PROPS!
-H*9(TYіёgЉŒЈžАщђ›ујEQю№/,GuideTheDocPage-1ѕы№ы№Gestџure FormatBlock NormalVisio 10Block ShadowVisio 12ѕы№ы№Block Highl§№tVisio 11ConnectorVisio 90ѕы№ы№Dot џConnectorѕы№ы№Connџector ArrowVisio 00Visio 01Visio 02Visio 03Visio 13Visio 20Visio 21Visio 22Visio 23Visio 50Visio 51Visio 52Visio 53Visio 70Visio 80BoxBox.3Box.4Box.5ѕы№ы№Dynaџmic conn?ectorѕы№ы№Dynaџmic connџector.10ѕы№ы№Dynaџmic connџector.23Box.37ѕы№ы№Dynaџmic connџector.40ѕы№ы№Dynaџmic connџector.50ѕы№ы№Dynaџmic connџector.52Box.2Box.9Box.13_Вы№Žя№Ѕуј5ъё3ы№œџФјјE
E0      0        3125    3125            1       0        DR      0
ъы№EЌFЋМ
-
E1      1       13125   13125           1       0        DR      0
ЬR-ђёGфU0-ќA-}
ХјNc
E2      0        15625   15625           1       0        DR      0
U,ƒ_u
!
DƒlQ
U\ƒ„u
SIGNAL  dwb_ERR_I
tƒ‘-UŒƒŸu
DIRECTION       input
ЄƒUЌ-UМƒУ-UUдƒмu
RADIX   hex
ьƒ}щu
GRID    0        1       0        1       0        16711680        0        0
Цјіu
ENDGRID -1
­7Gv 47ЊML7Md7*ЊM|77M”7DЊMЌ7QMФ7^ЊMм7kMє7xОMЧј…M$Њ§’M<§ŸMdc§ЇMя№AЅT§ЋMd§ЕЊ7*l§Й7*t§НЊ7*|§СI*Œ§Ы*I*œ§еMї§е№MUм§HЊ8)ф§й*ь§Ъй*є§й Ъ'ШWј:й*0>й*Ѕ$0Bй 040MЊ:T0lй*\0pЊ:|0:œ0ЎЈй 0ИŸ:М0ТTE6ъёы№ы№3*ы№ы№ы№ы№(!   ы№0ы№xвЅы№ы№fы№ы№ы№ы№іђёRы№И!ы№ы№TњёЪ! ы№!ы№"ы№Љ#!ы№%ы№&ы№'Њы№(ы№)ы№*ы№+T‘ы№-ы№.ы№/ы№U0ы№1ы№24м№щђујм№Ujхіы№ы№ы№Uы№ы№        ы№
Clock   Unclocked
ы№Uы№ы№
ы№ы№Uы№ы№ы№ы№Uы№ы№ы№ы№Uы№ы№ы№ы№ы№м№Ulы№4ы№,чєы№§џёў_€ђjџ @ЊЂъДфМK%@ујъёы№џLљKUUы№C-<3q7ы№AщђUlы№4ы№,чємџшнўўёўѕы№љПУK
EdgeLevel       neg
ы№AJ-3Э7ўёAщђ_ы№ќпќмџ*<Nчє@ўы№ЄљwKLы№RVŠœЎ№РвфgœЏїЯq6uHы№<мџ(
Set     Not Used
Hы№<мџ(
Clear   Not Used
_ы№ќпќмџ*<NчєEўы№ьљKL
ы№RVŠœЎ№РвфgАїXq ы№мџ>=–{†ы№zѓ№œцѕїѓы№
ClockEnable     Not Used
*ы№   ы№gѓ№"мџ4pFXпќїј„ќшѓ(‰rИџт@(jјлдЯaт@ЏА2ЙЬy
ActiveLowSetClear       True
ы№№Jїхіњчєы№lOї:Кы№]ы№Rы№мђџ—
AsyncSetClear   True
TQїU ы№„#Љы№нuы№в&ы№ьTзїѓ№!ы№B}ы№ЬUї?ѓ№ыQ
>ы№4YCПнOўы№Ф9Bmы`Oy­їеNfi$ћЬїSЗf'ы№œЁŸяDON4_Йј>E)ы№UdХGЩ1ы№UЄХWЩЁ=џгЛПјхі`2ы№LџМјЭHEюя№V
ActiveLowClockEnable    True
O?
џјLFќЗќОјeъ5 C=ы№|ЪјуЈ5 J!є_їkБ5 ы№@ўџр…ŸђљOhЋ‘+'Гй0Є@Hht€Œ˜фValued Sony CustomerG(Eџџџџxw
VhdlType        std_logic
w
VerilogType     wire
 EMF EXиЂVISIODrawing‰M”D€€ Ь€?€?џџџl(”@€€(€€€€€€€€€€€РРРРмР№ЪІ№ћџЄ  €€€џџџџџџџџџџџџ§џџџ  
SystemCType     sc_logic

ўџџџўџџџƒ !"#$%&'()*+,-./ўџџџ123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~‚ўџџџўџџџ…ўџџџўџџџўџџџ‰ўџџџўџџџўџџџŽ‘’“ўџџџўџџџ–ўџџџўџџџўџџџš›œžŸ ўџџџўџџџЃўџџџўџџџўџџџЇЈЉЊЋЌ­ЎўџџџўџџџБўџџџўџџџўџџџЕўџџџўџџџўџџџЙКЛМўџџџОПРСТУўџџџўџџџЦўџџџўџџџўџџџЪЫЬЭўџџџЯабвгдўџџџжўџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџœЈД_VPID_PREVIEWSП_VPID_ALTERNATENAMESЈ @_PID_LINKBASEУПф        Aўџ
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
џџџџQН…<ѓбЅ=Kuy›Timing DiagramTiming.Document.1є9ВqTimingDiagramTiming Diagram Editor v7.1g - Output File
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
PROJECT
LowVoltageThreshold     0
BaseTimeUnit    1
SignalActionType        0
DisplayTimeUnit 2
MSB     0
TextGridX       250.000000
LSB     0
TextGridY       6
isFallingEdgeSensitive  False
EdgeGridX       250.000000
isRisingEdgeSensitive   False
ImportStartTime 0.000000
DrawAnalog      0
ImportEndTime   281474976710656.000000
BooleanEquation
TimePerPixel    5.428571
NegTolerance    0
Visible DELAYS  SETUPS  HOLDS   SAMPLES TEXT    HIDDENATTACHMENTS       CRITICALPATHS   GRIDLINES       UNCERTAINTY
PosTolerance    0
ColWidths       144,216,288,423,488
UserSpecifiedSizeRatio  1
ScrollPos       0.000000,0.000000,0.000000
VerilogCode
DefDelayRule    1
VHDLCode
NoEventOverlap  NO
PROPS!
SigLabelFontHeight      10
E0      0        15625   15625           1       0        DR      0
LabelHeight     12
!
LoadLibsToMem   1
UseFullPathNames        1
SIGNAL  dwb_RTY_I
LibPath
DIRECTION       input
EntireTime      YES
RADIX   hex
PrintTimeSpecified      NO
GRID    0        1       0        1       0        16711680        0        0
FromTime        0
ENDGRID -1
ToTime  4.75
Clock   Unclocked
AllSignals      YES
EdgeLevel       neg
CurrSelSigs     NO
Set     Not Used
PrintTo 2
Clear   Not Used
PrintFileName   C:\DOCS\untitled1.wmf
ClockEnable     Not Used
PreviewInterchange      YES
ActiveLowSetClear       True
PreviewTIFF5    NO
AsyncSetClear   True
UseMargins      NO
ActiveLowClockEnable    True
PrintTimeLine   NO
VhdlType        std_logic
PrintBorderBox  YES
VerilogType     wire
PrintSigNames   YES
SystemCType     sc_logic
PrintSigNamesOnEachPage YES
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
AddPreviewToEPS NO
StateEquation   Hex(Inc(0,2,5))
PreviewRes      150
HighVoltageThreshold    5
MarginLR        1.25
LowVoltageThreshold     0
MifImageWidth   6.00
SignalActionType        0
MarginTB        Auto
MSB     0
Header  %d %t;%f;%p
LSB     0
Footer
isFallingEdgeSensitive  False
ScaleHorz       100
isRisingEdgeSensitive   False
ScaleVert       100
DrawAnalog      0
ScaleHPage      1
BooleanEquation
PrintImage      DIAGRAM
NegTolerance    0
DefaultTimingModel      minmax
PosTolerance    0
DefaultClock    Unclocked
UserSpecifiedSizeRatio  1
DefaultEdgeLevel        neg
VerilogCode
DefaultSet      Not Used
VHDLCode
DefaultClear    Not Used
PROPS!
DefaultClockEnable      Not Used
E0      0        15625   15625           1       0        DR      0
DefaultClockToOutLH     0
!
DefaultClockToOutHL     0
DefaultSetup    0
MARKER  MARK0
DefaultHold     0
ATTACH  dwb_DAT_O       NULL    S4
DefaultRegStartupState  unknown
TIME    7500.000000
DefaultPodSize  8
RELATIVETIME    0.000000
DefaultActiveLowSetClear        True
DISPLAYAS       5
DefaultAsyncSetClear    True
MARKERTYPE      Timebreak(Curved)
DefaultActiveLowClockEnable     True
WHILERETURN
SigLabelFontHeight      10
REPEATNUMBER
PROPS!
SNAPTO  0
!
COMPRESSTIME    0.000000
COMMENT
STYLE
!
DefaultFont     USER    {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
DrawWndFont     DEFAULT
Timing Diagram Editor v7.1g - Output File
DrawWndColor    DEFAULT
GridWndFont     DEFAULT
PROJECT
GridWndColor    DEFAULT
BaseTimeUnit    1
LabelWndFont    USER    {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
DisplayTimeUnit 2
LabelWndColor   DEFAULT
TextGridX       250.000000
ParamDispPref   0
TextGridY       6
ParamWndCellDisplay     0
EdgeGridX       250.000000
CustDispString  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
ImportStartTime 0.000000
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
ImportEndTime   281474976710656.000000
MarkerDispPref  4
TimePerPixel    6.497175
MarkerCustDispString    %n v=%mv,%Mv d=%md %t
Visible DELAYS  SETUPS  HOLDS   SAMPLES TEXT    HIDDENATTACHMENTS       CRITICALPATHS   GRIDLINES       UNCERTAINTY
MarkerCustomDisplayStringRTF    {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
ColWidths       144,216,288,423,488
SignalColor     2
ScrollPos       0.000000,0.000000,0.000000
LabelOffset     2
DefDelayRule    1
BusDisplay      0
NoEventOverlap  NO
WaveFormWidth   1.000000
SigLabelFontHeight      10
WaveFormColor   0
LabelHeight     12
InputWaveFormColor      16711680
LoadLibsToMem   1
SlantedEdges    1
UseFullPathNames        1
SlantAngle      75
LibPath
RightJustifySigNames    1
EntireTime      YES
AutosplitEnabled        1
PrintTimeSpecified      NO
AutosplitChar   _
FromTime        0
DynamSizedSignals       1
ToTime  5.75
!
AllSignals      YES
CurrSelSigs     NO
DIAGRAMTESTBENCHSETTINGS
PrintTo 2
FilesBeforeDiagramModel
PrintFileName   C:\DOCS\reset_gated.wmf
FilesInsideDiagramModelDeclarationSection
PreviewInterchange      YES
AbortHdlCodeEnabled     1
PreviewTIFF5    NO
DelayHdlCodeEnabled     1
UseMargins      NO
SampleHdlCodeEnabled    1
PrintTimeLine   NO
MarkerHdlCodeEnabled    1
PrintBorderBox  YES
VerboseSamples  0
PrintSigNames   YES
VerboseDelays   0
PrintSigNamesOnEachPage YES
VerboseFileInput        0
AddPreviewToEPS NO
VerboseSequenceVerification     0
PreviewRes      150
IncludeDelayTime        1
MarginLR        1.25
ExecuteFromTopLevel     1
MifImageWidth   6.00
TimeOutInDiagramLengths 0
MarginTB        Auto
DefaultCycleClock       Unclocked
Header  %d %t;%f;%p
DefaultCycleEdge        neg
Footer
!
ScaleHorz       100
ScaleVert       100
MACROS
ScaleHPage      1
!
PrintImage      DIAGRAM
DefaultTimingModel      minmax
CORGROUP        $$CLK_I_BufferRising
DefaultClock    Unclocked
Percent 100
DefaultEdgeLevel        neg
!
DefaultSet      Not Used
DefaultClear    Not Used
CORGROUP        $$CLK_I_BufferFalling
DefaultClockEnable      Not Used
Percent 100
DefaultClockToOutLH     0
!
DefaultClockToOutHL     0
DefaultSetup    0
CORGROUP        $$CLK_I_BufferRisingFalling
DefaultHold     0
Percent 100
DefaultRegStartupState  unknown
!
DefaultPodSize  8
DefaultActiveLowSetClear        True
CORGROUP        $$CLK_I_BufferRising
DefaultAsyncSetClear    True
Percent 100
DefaultActiveLowClockEnable     True
!
SigLabelFontHeight      10
PROPS!
CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
!
STYLE
DefaultFont     USER    {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
CORGROUP        $$CLK_I_BufferRisingFalling
DrawWndFont     DEFAULT
Percent 100
DrawWndColor    DEFAULT
!
GridWndFont     DEFAULT
GridWndColor    DEFAULT
CORGROUP        $$CLK_I_BufferRising
LabelWndFont    USER    {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
Percent 100
LabelWndColor   DEFAULT
!
ParamDispPref   0
ParamWndCellDisplay     0
CORGROUP        $$CLK_I_BufferFalling
CustDispString  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
Percent 100
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
!
MarkerDispPref  4
MarkerCustDispString    %n v=%mv,%Mv d=%md %t
CORGROUP        $$CLK_I_BufferRisingFalling
MarkerCustomDisplayStringRTF    {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
Percent 100
SignalColor     2
!
LabelOffset     4
BusDisplay      0
CORGROUP        $$CLK_I_BufferRising
WaveFormWidth   0.500000
Percent 100
WaveFormColor   0
!
InputWaveFormColor      16711680
SlantedEdges    1
CORGROUP        $$CLK_I_BufferFalling
SlantAngle      75
Percent 100
RightJustifySigNames    1
!
AutosplitEnabled        1
AutosplitChar   _
CORGROUP        $$CLK_I_BufferRisingFalling
DynamSizedSignals       1
Percent 100
!
!
DIAGRAMTESTBENCHSETTINGS
CORGROUP        $$CLK_I_BufferRising
FilesBeforeDiagramModel
Percent 100
FilesInsideDiagramModelDeclarationSection
!
AbortHdlCodeEnabled     1
DelayHdlCodeEnabled     1
CORGROUP        $$CLK_I_BufferFalling
SampleHdlCodeEnabled    1
Percent 100
MarkerHdlCodeEnabled    1
!
VerboseSamples  0
VerboseDelays   0
CORGROUP        $$CLK_I_BufferRisingFalling
VerboseFileInput        0
Percent 100
VerboseSequenceVerification     0
!
IncludeDelayTime        1
ExecuteFromTopLevel     1
CORGROUP        $$CLK_I_BufferRising
TimeOutInDiagramLengths 0
Percent 100
DefaultCycleClock       Unclocked
!
DefaultCycleEdge        neg
!
CORGROUP        $$CLK_I_BufferFalling
Percent 100
MACROS
!
!
CORGROUP        $$CLK_I_BufferRisingFalling
CORGROUP        $$CLK_I_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_I_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_I_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_I_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_I_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferRising
CORGROUP        $$CLK_I_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferFalling
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferRisingFalling
CORGROUP        $$CLK_I_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_I_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_I_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferRising
CORGROUP        $$CLK_I_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferFalling
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferRisingFalling
CORGROUP        $$CLK_I_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_I_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferRising
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferFalling
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_I_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_I_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_I_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_I_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_I_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_I_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferRising
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferFalling
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferRising
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferFalling
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferRising
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferFalling
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CLOCK   clk_risc
CORGROUP        $$CLK_RISC_BufferFalling
PERIODE 1
Percent 100
DUTY    50
!
OFFSETE 0
INITIAL LOW
CORGROUP        $$CLK_RISC_BufferRisingFalling
MAXUNCERTRISE   0
Percent 100
MAXUNCERTFALL   0
!
MINUNCERTRISE   0
MINUNCERTFALL   0
CORGROUP        $$CLK_RISC_BufferRising
JRISEE  0
Percent 100
JFALLE  0
!
GRID    1       1       1       2       2       16711680        0        0
ENDGRID -1
CORGROUP        $$CLK_RISC_BufferFalling
DIRECTION       input
Percent 100
MASTERCLOCK     None
!
Clock   Unclocked
EdgeLevel       neg
CORGROUP        $$CLK_RISC_BufferRisingFalling
Set     Not Used
Percent 100
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CORGROUP        $$CLK_RISC_BufferRising
AsyncSetClear   True
Percent 100
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
CORGROUP        $$CLK_RISC_BufferFalling
SystemCType     sc_logic
Percent 100
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
CORGROUP        $$CLK_RISC_BufferRisingFalling
LowVoltageThreshold     0
Percent 100
MSB     0
!
LSB     0
isFallingEdgeSensitive  False
CORGROUP        $$CLK_RISC_BufferRising
isRisingEdgeSensitive   True
Percent 100
DrawAnalog      0
!
BooleanEquation
NegTolerance    0
CORGROUP        $$CLK_RISC_BufferFalling
PosTolerance    0
Percent 100
UserSpecifiedSizeRatio  1
!
VerilogCode
VHDLCode
CORGROUP        $$CLK_RISC_BufferRisingFalling
PROPS!
Percent 100
!
!
SIGNAL  dbg_wp_o[11]
CORGROUP        $$CLK_RISC_BufferRising
DIRECTION       output
Percent 100
RADIX   hex
!
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
CORGROUP        $$CLK_RISC_BufferFalling
Clock   Unclocked
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$CLK_RISC_BufferRisingFalling
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$clk_risc_BufferRising
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$clk_risc_BufferFalling
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
SignalActionType        0
CORGROUP        $$clk_risc_BufferRisingFalling
MSB     0
Percent 100
LSB     0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
CORGROUP        $$clk_risc_BufferRising
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$clk_risc_BufferFalling
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
PROPS!
CORGROUP        $$clk_risc_BufferRisingFalling
E0      0        1750    1750            1       0        DR      0
Percent 100
E1      1       3750    3750            1       0        DR      0
!
E2      0        4750    4750            1       0        DR      0
!
CORGROUP        $$clk_risc_BufferRising
Percent 100
SIGNAL  dbg_bp_o
!
DIRECTION       output
RADIX   hex
CORGROUP        $$clk_risc_BufferFalling
GRID    0        1       0        1       0        16711680        0        0
Percent 100
ENDGRID -1
!
Clock   Unclocked
EdgeLevel       neg
CORGROUP        $$clk_risc_BufferRisingFalling
Set     Not Used
Percent 100
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CORGROUP        $$clk_risc_BufferRising
AsyncSetClear   True
Percent 100
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
CORGROUP        $$clk_risc_BufferFalling
SystemCType     sc_logic
Percent 100
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
CORGROUP        $$clk_risc_BufferRisingFalling
LowVoltageThreshold     0
Percent 100
SignalActionType        0
!
MSB     0
LSB     0
CORGROUP        $$clk_risc_BufferRising
isFallingEdgeSensitive  False
Percent 100
isRisingEdgeSensitive   False
!
DrawAnalog      0
BooleanEquation
CORGROUP        $$clk_risc_BufferFalling
NegTolerance    0
Percent 100
PosTolerance    0
!
UserSpecifiedSizeRatio  1
VerilogCode
CORGROUP        $$clk_risc_BufferRisingFalling
VHDLCode
Percent 100
PROPS!
!
E0      0        2750    2750            1       0        DR      0
E1      1       4750    4750    If Enabled      1       0        DR      0
CORGROUP        $$clk_risc_BufferRising
!
Percent 100
!
SIGNAL  dbg_ewt_i
DIRECTION       input
CORGROUP        $$clk_risc_BufferFalling
RADIX   hex
Percent 100
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock   Unclocked
CORGROUP        $$clk_risc_BufferRisingFalling
EdgeLevel       neg
Percent 100
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
CLOCK   clk_risc
ActiveLowSetClear       True
PERIODE 1
AsyncSetClear   True
DUTY    50
ActiveLowClockEnable    True
OFFSETE 4.5
VhdlType        std_logic
INITIAL HIGH
VerilogType     wire
MAXUNCERTRISE   0
SystemCType     sc_logic
MAXUNCERTFALL   0
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
MINUNCERTRISE   0
StateEquation   Hex(Inc(0,2,5))
MINUNCERTFALL   0
HighVoltageThreshold    5
JRISEE  0
LowVoltageThreshold     0
JFALLE  0
SignalActionType        0
GRID    1       1       0        2       2       16711680        0        0
MSB     0
ENDGRID -1
LSB     0
DIRECTION       input
isFallingEdgeSensitive  False
MASTERCLOCK     None
isRisingEdgeSensitive   False
Clock   Unclocked
DrawAnalog      0
EdgeLevel       neg
BooleanEquation
Set     Not Used
NegTolerance    0
Clear   Not Used
PosTolerance    0
ClockEnable     Not Used
UserSpecifiedSizeRatio  1
ActiveLowSetClear       True
VerilogCode
AsyncSetClear   True
VHDLCode
ActiveLowClockEnable    True
PROPS!
VhdlType        std_logic
E0      0        1250    1250            1       0        DR      0
VerilogType     wire
E1      1       3750    3750            1       0        DR      0
SystemCType     sc_logic
E2      0        4750    4750            1       0        DR      0
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
MARKER  MARK10
LowVoltageThreshold     0
ATTACH  dbg_wp_o[11]    NULL    S1
MSB     0
TIME    1610.903040
LSB     0
RELATIVETIME    0.000000
isFallingEdgeSensitive  False
DISPLAYAS       5
isRisingEdgeSensitive   True
MARKERTYPE      Timebreak(Curved)
DrawAnalog      0
WHILERETURN
BooleanEquation
REPEATNUMBER
NegTolerance    0
SNAPTO  0
PosTolerance    0
COMPRESSTIME    0.000000
UserSpecifiedSizeRatio  1
COMMENT aaa
VerilogCode
!
VHDLCode
PROPS!
MARKER  MARK20
E5      1       7000    7000            1       0        DR      0
ATTACH  dbg_bp_o        NULL    S2
E6      0        7500    7500            1       0        DR      0
TIME    2644.928640
E7      1       8000    8000            1       0        DR      0
RELATIVETIME    0.000000
E9      1       9000    9000            1       0        DR      0
DISPLAYAS       5
!
MARKERTYPE      Timebreak(Curved)
WHILERETURN
SIGNAL  rst
REPEATNUMBER
DIRECTION       input
SNAPTO  0
RADIX   hex
COMPRESSTIME    0.000000
GRID    0        1       0        1       0        16711680        0        0
COMMENT
ENDGRID -1
!
Clock   Unclocked
EdgeLevel       neg
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Clear   Not Used
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ClockEnable     Not Used
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ActiveLowSetClear       True
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AsyncSetClear   True
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ActiveLowClockEnable    True

VhdlType        std_logic
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SystemCType     sc_logic
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TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
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StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
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LowVoltageThreshold     0
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SignalActionType        0
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MSB     0
LSB     0
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isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
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DrawAnalog      0
BooleanEquation
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NegTolerance    0
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PosTolerance    0
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UserSpecifiedSizeRatio  1
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VerilogCode
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%€(RLНџџџ Arial2. All Rights ReservedAriRegularMonotype:Arial Regular:Version 2.76 (Microsoft)ArialVerson 2.76ArialMTArialЎ Trademark o%(RLНџџџ Arial & TM Off. and elsewhere.notype TypographyMonotype Type Drawing Office - Robin Nicholas,Patricia Saunders 1982Contempors%(RLНџџџ Arialacteristics than many of s predecessors and as such is more in tune with the mood of thelast decades of the twentieth ca%(RLНџџџ Arialuller than in most industal style sans serif faces.  Terminal strokes are cut on the diaonal which helps to give the fac%(RLНџџџ Arialversatile family of typefes which can be used with equal success for text setting in reprts, presentations, magazines ea%(RLЮџџџ Arialromotions.http://www.monop˜Ъњ*œа ž! #0%`'Њ)<) ***:*Ш,r-P...Ъ/к1ž33т3ђ44і555&5666(686Ќ6М707@8*8:8J8Z9f:Ђ:д;
PROPS!
%(RLЮџџџ ArialL0MMLNpN€NNТNвOњPцQвQњR*RцSОSЮTTмTьWXlXђY"Z@ZоZюZў[[€[[ [А\’]М]Ь^B^№_”`VaaєbВbжcаde&fRfgXghizjфkІkжm mцooИoШ%(RLЮџџџ Arial€€H€№:ˆЖƒƒx„…2…ц†Р‡
E0      0        1750    1750            1       0        DR      0
ˆNˆvˆР‰‰јŠBŠvŠžŠЦŠњ‹>‹‚‹РŒц~Ž†Žкhž(˜‘^‘–’’Ж“<“Ў”Є”к•`•ў—p˜B™™жšpšш›жœ–œф2~ДžžиŸH%(%
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E1      1       3750    3750            1       0        DR      0
ОјПЂР’СHТТіУІФ(Ц†ЦАЦкЧ’ЧМШўЪЪюЫЫBЫlЫ–ЫРЭ@ЭjЭ”ЭОЭшЮ<ЮfЮЮФЮюЯЯBаМаЬбюбўв(вRв|вІ%TlК[{Ѕ
E2      0        5750    5750            1       0        DR      0
О‡@
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О‡@К[LXVPN 0--0%TlКЋ{ѕ
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SIGNAL  dbg_dat_o
О‡@КЋLXVPN 1--0%RLНџџџМ ArialЪ J
DIRECTION       output
№B
’‚Vn~Žž>NdЖціФдJZn~ВH  !"l"ј#$2%О&z&Š'"'2'ў((ц(і*+д+ф-<-L/Ж/Ц1Р1а3:3J4:4J5т5ђ%T`џЫ    7
RADIX   hex

GRID    0        1       0        1       0        16711680        0        0
О‡@
ENDGRID -1
О‡@џЫ        LT...RLНџџџ Arial[Р[а^0`zcehgьjbl2mьnn@nPnŠnДnоnюnўo(oRoboroœoЦo№ppp p0p@pPpzpŠpšpФpюqqBqlq–qРqъrr>r’rМrцss:sdsŽsИsтtt6t`tŠtДtо%(%T`ш,
Md

Clock
О‡@
EdgeLevel       neg
О‡@ш,
LTVPN!!$Th
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Set     Not Used
О‡@
Clear   Not Used
О‡@h
LdITLB_SETS-1!!!!&%%€V0jЕЬ        MkLЫ LЫ     ЖkЖkL%€(%€RLНџџџМ ArialІІ€ІжЇBЇ–Ј
ClockEnable     Not Used
ЈPЈИЈўЉZЉ€ЉЊЉаЊ&ЊLЊ~ЊЎЋЋfЋМЌ"ЌvЌф­&­†­ШЎЎNЎŠЎФЏЏ4ЏfЏ–ЏЦЏ№АА@АnА˜АфБ(Б^БšБќВ0В`ВšВФВђГГ>ГjГЈГиДД8ДpДЄ%TДЗ~b
ActiveLowSetClear       True
О‡@
AsyncSetClear   True
О‡@ЗLpEFFECTIVE ADDRESS a-))-0(---000---&%&" WMFC д9дy%€V0Fћ6        ›
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%€(RLНџџџ Arialpearance.  Arial is an extremely versatile family ypefaces which can be used with equal success for text setting in reports, presentations, magazines etc, and for display use inewspapers, advertising and promotions.http://www.monotype.comww%(RLНџџџ Arial
ActiveLowClockEnable    True
This typeface is the property of Monotype Typogr and its use by you is covered under the terms of a liцВцшч6ч€чЪчцшш"шBшbш‚шЈшЮшєщщJщrщšщђъ&ъPъ|ъВъмыы>ыhы’ыЦыіь*ьnьž%(RLНџџџ Arialјђљ’њhњшћpћрќvќд§§x§кўўpўјџ4 ”Ок>ŠЪў.^ŽТђ"R‚ВтBrЂаT„ДА      в
VhdlType        std_logic
0
VerilogType     wire
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SystemCType     sc_logic
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TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
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StateEquation   Hex(Inc(0,2,5))
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HighVoltageThreshold    5
;@;p; ;ф<%(RLНџџџ ArialNNТNвOњPцQвQњR*RжRцSОSЮTTьWXlXђY"Z@ZоZюZў[[€[[ [А\’]М]Ь^B^№_”`VaaєbВbжcаcўde&fRfghizjфkІkжm mцooИoШpRpbprpцpі%(RLНџџџ ArialЖƒƒx„…2…ц†Р‡
LowVoltageThreshold     0
‡ˆˆNˆvˆР‰ŠBŠvŠžŠЦŠњ‹>‹‚‹РŒц~Ž†Žкhž(˜‘^‘–’’Ж“<“Ў”Є”к•`•ў–Ф—p˜B™™жšш›жœ–œф2~ДžžиŸHŸ€ŸЦŸі LЁ%(RLНџџџ Arial­О­ќЎ*ЎhЏ†ЏЎАъБzВ$ВІГbДzЕˆЖBЗžИ ИjЙtЙМКРЛ<Л”ММєО
LSB     0
ОјПЂР’СHТТіУІФ(Ц†ЦАЦкЧ’ЧМШўЪЪюЫЫBЫlЫРЭ@ЭjЭ”ЭОЭшЮЮ<ЮfЮЮФЮюЯЯBаМ%(%
€(%€RLНџџџ ArialюˆяЬёДђќѓ&ѓPѓ€ѓАєєPєѕѕVі
MSB     31
і@і‚іШїїBїzїЊјтќ(ќRќ|ќІќаќњ§$§N§x§Ђ§Ь§іў ўJўtўžўШўђџџFџpџšџюBl–Р^tž~ŽЈЪ  J%Tl]oЙ
SignalActionType        0
О‡@
isFallingEdgeSensitive  False
О‡@]oLXPPN 0--0%Tl]П 
isRisingEdgeSensitive   True
О‡@
DrawAnalog      0
О‡@]ПLXPPN 1--0%%T`Ђп    к,
BooleanEquation

NegTolerance    0
О‡@
PosTolerance    0
О‡@Ђп        LT...RLНџџџ ArialnŠnДnоnюnўo(oRoboroœoЦo№pp p0p@pPpzpŠpšpФpюqqBqlq–qРqъrr>rhr’rМrцss:sdsŽsИsтtt6t`tŠtоuu2u\u†uАuкvv.vXv‚vЌvжww*%TЈЁџлI

UserSpecifiedSizeRatio  1
О‡@
VerilogCode
О‡@ЁџLlPPN ITLB_SETS-2--0)%-%--)-%TЈЁO
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VHDLCode
О‡@
VhdlMapping     DefaultVhdlMapping
О‡@ЁO
LlPPN ITLB_SETS-1--0)%-%--)-%%
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YќУќУš
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PROPS!
BLB——
E0      X       1750    1750            1       0        DR      0
%€(%€%€V0Љ%ЫдЉдЫдЫ%Љ%Љд%€RLНџџџ Arial%TxБkСЕ
E1      V       4750    4750    0x0     1       0        DR      0
О‡@
E2      V       5750    5750    0x4     1       0        DR      0
О‡@БkL\TLB SET)%---)TlдЛž
!
О‡@
О‡@дЛLXINDEX00-+&%W$Ž
SIGNAL  dbg_op_i
a
DIRECTION       input
—
RADIX   hex
X
GRID    0        1       0        1       0        16711680        0        0
%€(%€%€V,Nя       У=
ENDGRID -1
Nя       У
Clock   Unclocked
N=
EdgeLevel       neg
Nя     &%%€V0
вВЖЕБЕБггЕ%€(%€%TdћXТЂ
Set     Not Used
О‡@
Clear   Not Used
О‡@ћXLTCOMP047-&%W$›щ­qЄђЄh%€(%€%€V,}^ЫгЫ^Єг}^Ы^&%%€W$‘
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h%€(%€%€V,є^BгB^гє^B^&%%€V0юЂВ…я„Б„БЃяЃя„%€(%
€(%€%T`˜'q
ClockEnable     Not Used
О‡@
ActiveLowSetClear       True
О‡@˜'LTINV0-&%W$WЌi@`Е`7%€(%€%€V,9.‡Ѓ‡.`Ѓ9.‡.RLНџџџŒ
AsyncSetClear   True
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ActiveLowClockEnable    True
 Arial%(%
€(%€%Tl•й8#
VhdlType        std_logic
О‡@
VerilogType     wire
О‡@•йLXHIT 00)%%
€(RLНџџџ Arial%TX‘Єкю
SystemCType     sc_logic
О‡@
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
О‡@‘ЄLP31%%RLЮџџџ Arial&" WMFC ддypˆ
StateEquation   Hex(Inc(0,2,5))
      шќ
HighVoltageThreshold    5
%T`ЕŸјз
LowVoltageThreshold     0
О‡@
SignalActionType        0
О‡@ЕŸLTlogRLпџџџ Arial()*+,-/0123456789:;<=?@ABCDE%TTљА
MSB     3
е
LSB     0
О‡@
isFallingEdgeSensitive  False
О‡@љАLP2, RLЮџџџ Arialessors and as such is more in tune with the mood oe last decades of the twentieth century.  The overall treatment of curves is softer and fuller than in most industrial style ss serif faces.  Terminal strokes are cut on the diagonal whichha%(%T Ÿ‰    з
isRisingEdgeSensitive   False
О‡@
DrawAnalog      0
О‡@ŸLh(ITLB_SETS)+13!!!!%
€(RLНџџџ Arialtname/ms_welcome.htmlNOTIFICATION OF LICENSE AGREE
BooleanEquation
NegTolerance    0
This typeface is the property of Monotype Typography and its use by you is covered under the terms of a license agreement.ou have obtained this typeface software either directly from Mdi%TXIЄ’ю
PosTolerance    0
О‡@
UserSpecifiedSizeRatio  1
О‡@IЄLP13%%%TTЉЄЭю
VerilogCode
О‡@
VHDLCode
О‡@ЉЄLP0it%RL­џџџМ Arialte this software.
PROPS!
E0      V       5750    5750    READ PC 0x0     1       0        DR      0
If you have any question concng your rights you should review the license agreement you received with the software or contact Monotype for a copy of the linse agreement.
!
Monotype can be contacted at:
MARKER  MARK0
ATTACH  rst     NULL    S1
USA - (847)
TIME    2750.000000
%Tl™о
RELATIVETIME    0.000000
О‡@
DISPLAYAS       5
О‡@™LXWAY 0nO98.&%W$Ч{йІа„а%€(%€%€V,Љ“її“аЉ“ї“%€RLНџџџŒ
MARKERTYPE      Timebreak(Curved)
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WHILERETURN
 ArialialRegularMonotype:Arial gular:Version 2.76 (Microsoft)ArialVersion 2.76ArialMTArialЎ Trdemark of The Monotype Corporatd%T„ЃPэ
REPEATNUMBER
О‡@
SNAPTO  0
О‡@Ѓ     L`ITLB MISSr)%-7--T„l…эЯ
COMPRESSTIME    0.000000
О‡@
COMMENT
О‡@l…     L`EXCEPTIONe-+0--)40%
€(%
€(RLНџџџ Arialy of its predecessors ands such is more in tune with the mood of the last decades of thetwentieth century.  The overallv%TXЭЄ
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!
О‡@
О‡@ЭЄLP12%%&%W$дЧцšнан‘%€(%€%€V,Ж‡ќ‡нќЖ‡‡&%%€W$ъШќѓбѓ„%€(&%%€W$Е‘
ЧЯОЦОš
%€(&%%€W$ЕНќЯѓЦОЦ%€(%€%€VкЎп9кЦкЩкЬлЯмбодпжсиукхлшнъоэп№пѓпѕпјпћо§нлкижд б
ўџ
ЯЬЩЦФС
џџџџQН…<ѓбЅ=Kuy›Timing DiagramTiming.Document.1є9ВqTiming Diagramўџ
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€(%
€(%€RLНџџџŒ
џџџџРFMicrosoft Visio DrawingVISIO 6.0 ShapesVisio.Drawing.6є9ВqўџTiming Diagram Editor v7.1g - Output File
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PROJECT
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BaseTimeUnit    1
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DisplayTimeUnit 2
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TextGridX       250.000000
ьтР№DtœЪюD.@xЈфB^ŽОŠ’Тќ,\ŒОт&V†Иш Єд4 в4d˜Ъњ*œа ž! #0%`%T”jНД
TextGridY       6
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EdgeGridX       250.000000
О‡@jLdPADDR[31:13]--000%%%%&%W(ОCGыЧLЧт>т%€(&%%€W$5й3ы>т*т%€(%€%€V,!Л–     !Л–т!       !ЛRLНџџџ ArialzzT{Š{Ў|В|Т|в}}~~ьє€€№:ˆЖƒƒx„…2…ц†Р‡
ImportStartTime 0.000000
‡ˆˆNˆvˆР‰‰јŠBŠvŠžŠЦŠњ‹>‹‚‹РŒц~Ž†Žкhž˜‘^‘–’’Ж“<“Ў”Є”к•`•ў–Ф—p˜B™%(%€%T~ІT№
ImportEndTime   281474976710656.000000
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TimePerPixel    6.497175
О‡@~ІLdPAGE OFFSET--4-4))--)T F1
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О‡@
ColWidths       144,216,288,423,488
О‡@ FLdPADDR[12:0]--000%%%%
€(RLЮџџџ Arialт‚умхОчш0шZш„шЎшищщ,щVщ€щдщўъ(ъRъ|ъІъаэюˆяЬёДђќѓ&ѓPѓ€ѓАєєPєѕѕVѕДі
ScrollPos       0.000000,0.000009,0.000000
і@і‚іШїїBїzїЊјтќRќ|ќІќаќњ§$§N§x§Ђ§Ь§іў ўJўtўž%(RLпџџџ Arialn~ŽŽž>NdЖціФJZn~ВH  !"l"ј#$2%О&z&Š'"'2'ў((ц(і)ў*+д+ф-<-L/Ж/Ц1Р3:3J4:4J5т5ђ77 8`8p8€8:::(%(%
€(RLЮџџџ ArialWdWtW„W”Y2Zђ[Р[а^0`zcehgьl2mьnn@nPn`nŠnДnоnюnўo(oRoboroœoЦo№ppp p0p@pPpzpŠpšpФpюqqBq–qРqъrr>rhr’rМrцss:sdsŽsИsт%T`
DefDelayRule    1
ŸP
NoEventOverlap  NO
з
SigLabelFontHeight      10
О‡@
LabelHeight     12
О‡@
LoadLibsToMem   1
ŸLTlogRLпџџџ Arial}ю~~B~l~–~Р~є(\€xz‚Jƒ.ƒК„(„„„ж…F††к‡Вˆn‰Š(Šм‹^‹И‹јŽ`јTВ‘‘j’’Ж“b””К•r–*–т–є——*—<—Њ˜˜а˜т˜є™™™(™:™L™^™p%TTQ
UseFullPathNames        1
Аb
LibPath
е
EntireTime      YES
О‡@
PrintTimeSpecified      NO
О‡@Q
FromTime        0
АLP2RLЮџџџ ArialЊ~ЊЎЋЋfЋМЌ"ЌvЌф­&­†­ШЎЎNЎФЏЏ4ЏfЏ–ЏЦЏ№АА@АnА˜АфБ(Б^БšБЮБќ
&іWMFCддyВ0В`ВšВФВђГГ>ГjГЈГиДД8ДpДЄЕЕ2ЕbЕ’ЕЦЖЖPЖАЖфЗ<ЗpЗЬИjЙ8КX m%T c
ToTime  5.75
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AllSignals      YES
О‡@
CurrSelSigs     NO
О‡@c
PrintTo 2
ŸLh(ITLB_SETS)+12!!!!&%W$дЧ      йана%€(%€%€V0zžb
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žzžz§%€RLНџџџ Arialњшћpћрќvќд§§x§кўўpўœўјџ4”Ок>ŠЪў.^ŽТђ"R‚ВтBrЂаT„ДА в
PrintFileName   C:\DOCS\reset.wmf

PreviewInterchange      YES
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PreviewTIFF5    NO
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UseMargins      NO
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PrintTimeLine   NO
ьтР№DtœЪюD.@%TЌƒфY
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PrintBorderBox  YES
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О‡@ƒфLlD & A attributes0--%%%%"&%%€V0`
PrintSigNamesOnEachPage YES
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AddPreviewToEPS NO
eЙeЙЃa
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Ѓa
MarginLR        1.25
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€(%€RLНџџџ ArialQњR*RжRцSОSЮTTмTьWXlXђY"ZоZюZў[[€[[ [А\’]М]Ь^B^№_”`VaaєbВbжcаcўde&fRfgXghizjфkІkжmцooИoШpRpbprpцpіrrr‚ssžtpu^%TˆМ
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€(%€%€V0mžЅMmMЅMЅžmžmM%€RLНџџџЬ Arialбўв(вRв|вІдPж\зŠзšйй&кlм8оОр^т‚умхОчш0шZш„шЎшищщ,щVщ€щЊщдщўъ(ъRъ|ъІъаэюˆяЬёДђќѓ&ѓPѓ€єєPєѕѕVѕДі
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О‡@
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О‡@vфL\SR[SUPV-0-0--TT4~
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О‡@
DefaultSet      Not Used
О‡@4LP]&%W$    ыџ §     єі     є%€(%€%€V,ь Эa
DefaultClear    Not Used
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DefaultClockEnable      Not Used
єь     ь     Э&%%€W$     ы      є     %€(%
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CORGROUP        $$CLK_RISC_BufferRisingFalling
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CORGROUP        $$CLK_I_BufferRising
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CORGROUP        $$CLK_I_BufferFalling
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CORGROUP        $$CLK_RISC_BufferRisingFalling
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CORGROUP        $$CLK_RISC_BufferRisingFalling
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!
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CORGROUP        $$clk_risc_BufferRising
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!
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CORGROUP        $$clk_risc_BufferFalling
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Percent 100
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CORGROUP        $$clk_risc_BufferFalling
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CORGROUP        $$clk_risc_BufferRisingFalling
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Percent 100
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ЁWSET 1--)%ћCМ Arial?A?A?A?A?A?A?A?A?A?A?A?A?-2
Percent 100
С       ˜...ћC Arial?A?A?A?A?A?A?A?A?AhA?A?A?-2
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2ќpќpš
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CORGROUP        $$clk_risc_BufferFalling
o№TAG 0)-4%2
Percent 100
П№TAG 1)-4%ћCМ Arial?????????????????????????-2
!
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CORGROUP        $$clk_risc_BufferRisingFalling
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Percent 100
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№-
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эEFFECTIVE ADDRESS(-))-0(---000---њ--$}š
k       š
k     ќ}ќ}š
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Percent 100
o‡Word 0B%%%2
!
П‡Word 1B%%%-2
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CORGROUP        $$clk_risc_BufferRisingFalling
џтWord DC_SETS-2B%%00%--)-%2
Percent 100
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LHLHЖ
CORGROUP        $$clk_risc_BufferRising
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Percent 100
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CORGROUP        $$clk_risc_BufferFalling
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Percent 100
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-№-ћdМ Arial?A?????-
2
CORGROUP        $$clk_risc_BufferRisingFalling
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Percent 100
-№њ--%Э
!
Ž
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CLOCK   clk_risc
„=
PERIODE 1
„я     њ--$DЕчЕчгDгDЕ-№-ћC Arial??-
2
DUTY    50
X1COMP047-њ-      %–ђ–h-№ --$Н^–гo^Н^њ- -%Qš
Qh-№ --$x^Qг*^x^њ- -%”§#§#ђcђ-№ њ- -%–Е–‰-№ --$Н€–ѕo€Н€-ћCŒ
OFFSETE 0
Œ
INITIAL LOW
 Arial?A?A?A?A?A?A?A?A?A?A?A?A?-        2
MAXUNCERTRISE   0
ЫHIT 00)%-
MAXUNCERTFALL   0
№-
MINUNCERTRISE   0
№ћC Arial?A?A?A?A?A?A?A?A?A?A?A?A?-
MINUNCERTFALL   0
2
JRISEE  0
ЄЧ31%%-
JFALLE  0
№ћ! Arial?A?A?A?A?A?A?A?A?A?A?A?A?-№ћ2 Arial?A?A?A?A?A?A?A?A?A?A?A?A?-№ћ2 Arial?????????????????????????-2
GRID    1       1       1       2       2       16711680        0        0
Ÿ/logћ! Arial????????????????????p???А-      2
ENDGRID -1
Аs2,ћ2 Arial?????????????????????????-2
DIRECTION       input
Ÿ…(DC_SETS)+4$$!!!-
MASTERCLOCK     None
№ -       2
Clock   Unclocked
Є4,%ћC Arial?????????????????????????-             2
EdgeLevel       neg
Єh3,%ћC Arial?????????????????????????-    2
Set     Not Used
Єп0,%ћSМ Arial?????????????????????????-
2
Clear   Not Used
ЮWAY 0O98.њ--$HL)L)ЖHЖHL-№-
ClockEnable     Not Used
№-
ActiveLowSetClear       True
№-
AsyncSetClear   True
№-ћC Arial?????????????5???4???????-       2
ActiveLowClockEnable    True
Єў2,%-
VhdlType        std_logic
№-
VerilogType     wire
№ћC Ariale Monotype Corporation pl-       2
SystemCType     sc_logic
ЄI1,%њ-%ИLИ::а-№-
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
№--$’g‘
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StateEquation   Hex(Inc(0,2,5))
NšWORD SELECTB400--%-0)њ-%а‘-№--$:‡ќь‡:‡њ
HighVoltageThreshold    5
--$з„€ЃбЃz„з„-№њ
LowVoltageThreshold     0
--$zЃб„€„зЃzЃ-№њ--%)Ъ)7-№--$P.)Ѓ.P.њ--%єЦє-№--$Эєš
Эњ--%)ЦєЦ-№--v$9ЦЩЬЯбджиклн о#п&п)п+п.п1о3н6л8к:и<ж>д?б@ЯAЬAЩAЦAФAС@О?М>Й<З:Е8Г6Б3А1Џ.Ў+Ў)Ў&Ў#Ў ЏАБГЕЗЙМОСФЦњ--%)я)-№--$љ)„Pљљ--$P“)“P“-
MSB     0
№ ћCŒ
LSB     0
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isFallingEdgeSensitive  False
 Arial??гu???????t-№-
isRisingEdgeSensitive   True
№
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DrawAnalog      0
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BooleanEquation
 Arial???>?N???Џ??-2
NegTolerance    0
\eTO/FROM CPU)4)0470-0!2
PosTolerance    0
ХTO/FROM EXTEN I/F()4)047-+)-0)њ-
UserSpecifiedSizeRatio  1
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2
VerilogCode
ІИBYTE--)-2
VHDLCode
FwSELECTS--%-0)--
PROPS!
№-
E5      1       2500    2500            1       0        DR      0
№ћ! Arial????????????-№ћ2 Arial???-№ћ2 Arial??C+???AC?A??-2
E6      0        3000    3000            1       0        DR      0
Ÿ<
E7      0        3500    3500            1       0        DR      0
logћ! ArialA??A?????-  2
E9      1       4500    4500            1       0        DR      0
А€
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2,ћ2 Arial?A?A?A?A?A?A?A?A?A?A?A?A?-№-2
Ÿ’
SIGNAL  rst
(DC_SETS)+3$$!!!Visio (TM) Drawing
DIRECTION       input
MN„THїЩL„Rэlъёщђџџџƒџіђџѓћ№јё‰€ъё€ €џРРРцццџЭЭЭГГГяššš!€fџffMMM3џ33яяяњњњ$ы№мџ
RADIX   hex
$ы№мџ
GRID    0        1       0        1       0        16711680        0        0
Uы№џђ№3ы№8шѓ@њєсњіёъёуј§ы№Tdџ Arialъ@чєNПWingdzsЊ@чєN@tMџonotype ЏSort+чє
њNtSymbol5Tы№?шѓа?ђџкъё шѓY@-1Uы№џђ№ы№шѓ њєы№іёъёJчє:ы№Dы№T1шѓ€ђёEWђёрћ-ъёhъчєы№Tы№T…ы№<пќŒŒцѕЎ‘*ы№Њы№ы№ы№  ы№
ENDGRID -1
Њы№ы№ы№
ы№ъы№“уј/РUљКпbеў
bOў…Иъё‰џ0zЎGсz„Ѕ?Ж@цѕП8@‘H2!kWЎb*Ѕ†МъёUВ
Clock   Unclocked
ь
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EdgeLevel       neg
1 yрЙ
‚€‚ )‚ЎPР? 2
U
U1ЄШŠъёэ2?§k9лЏaўBBHEЊHEHEHEHE‚HEH@ ?В>з?щ:`T2BBHEHEHEUHEHEHEHE%H@„Ьъё%O9      ЃаъёF7AOY@;P
ЬAsVsVЬA!ЇдgLTkYЗиъёї  WЭ_Wп_ќ_њ !`Г#Ј•k4l•ƒb”6u`kђWŽ     *4l
Set     Not Used
4l•Нмъё§Б%Y№?ˆˆP:?-\
Ѓ#!ю+|QtKf2|2|2|I2wŠGОръёQAUѓoІTMeE$жttAПфъёв%_8BOTOfOxOŠOВ?Ф?HЌOш?њ7РшъёмЛXњuЛWР?ыаќŽYиžђˆsU4‘х2–
Clear   Not Used
TŸ*<N`r@„–ЂД„k!–JŽЌ§†Ž0ЌЉ–ŽPЌЌ&Ќ 3•ŽЇ
•1’ьъёїмЏюЏПП$П6Пуќw
Р[ЕiИЛњё”|Г .ф”ујМЫЏi7'04’UХP§iW?i?{4Lz№y‘2ї#TЩЖz“x•       x•
ClockEnable     Not Used
x•Ѕx•x
ActiveLowSetClear       True
Ѓ0–jPМvПˆПуј•ујШВЗl^/ЫЦ!3оТѓПjЦBjЦ6DŒ/ž/А/ў$Q0pоФ?MdjЧ^cjЧŒ4ТЬAk[Ж~ЯЯхіˆуј$YkU1%Л1ўптУэFЛе„-(‘kp
йЛ   ѓ       A.$–5-Bi`яЗб#ошяЗ9)›F/Pџтљv/ˆ/п пО/u?‡2tСrПœпœЯKЖSИЯ5мЯюЧ2ћЩŒ7сбxХэпЂя#я6@хhБ$MчюuLЕhБЪ        хеƒя•яЇяЙяЫяняяяџџ%џодŠе‘ї§ѓ)Й<щ€№Oх™U‡#5G‹˜:ёмО:ѓU2ЧqЩ Ќ?Ш/к&мwџ‰ўк&Ѓє
AsyncSetClear   True
<<7сбHсщпєБУ1яOВQjСPфSсHЙQ›ywщHсAt/†/˜/YOВGТ$_щpЅ4Ыћb%F!ЂДЦ8ћqТ/д#P?˜Cђ/‰§Nм^мТqЄhшE!	@d)nм{”щrѕ1PБ1	@/ЋOq•жt}Q„”!ўnПњџЄК=ВЙkх@ЦБь…Љ{…B'ФІЩ‚XVйP_0TБNJgхй2ѕ1ѕ1”Rе5P"”Q”Q[СO"P!ДЁq’[СŠrДЁДЁюrŠqŠqг‚юqюqТЂггPБТЁТЁWт§a§a7б$VтWсХе7бPБ$q"$qPБ1q1qPБ>q">qPБKqKqPБXqXqХ2eqeqZБФ2SсobZБZБdБSВTБсQcВdБPБсQсQPБсбй1Hс[<k?шtЋaі}Yя рђMД/OOш*DљЗd3qOш/ДNkS\O’ѕИ†9ђ˜EС/Ÿх/_      ??-??=е_ч_љ_ЄКБ„ИО”МбЗ'Ур–sЯ–ŸdЈŸЉЫI,OЏ0Rн7nOВ†пЏ&ЏМкЋaЬ—сбЋaW?Oрш  //Ђ?*<N`r„w€|rŽЄБdU0{yЦ?gЁ7ЁMЗFКHЃЙ}E ‚…ŸЇЏЙЏjpЯž0UЌТХ8nодP!ЭпъЦЌ!јЭ5/G/Y/k/lŸПБПЂДчПиOЯaЯsЯКŸ—ЯоŸ№ŸЏћп
я8ЏJЏ\ЏnЏ€Џ’Џuя‡яШЏк­КS№ЏуЯП&П8ПJП\ПnП€П’ПпЖПШПкПьПўПЦ$rм#Я
ActiveLowClockEnable    True
KЯџџя“ЯЅЯЗЯОCЯЯсЯNЩa\п"п4пFпXпjп пВпKжпГХзяћBяTяfя_/q/œяЎяРявяфяіяй/ы/,џк­ЩaRџdџvџˆџšџЌџОџаџтџєџу*<€+/`Ш§b§b‡iAnFUЏj?|?~/ї "CЖ?Ш?ВVуaР]ї?     I„a(G
VhdlType        std_logic
rpl/YDE@a1LOзpOћŸ#Q/ˆ­ISПGQл„BQfQaЮIq_U‚ѕ…yjŸЕ(ŸШ„Bb_(_:_/^_Ѕ/З/ЦТдQ—_Љ_†a1и_      OO-OДFСZOQo~MЮA%ФъoCХЅŽAЕšOЌOОMgy ‹N_Џr_МЬO”7ш”ZіgŸ†˜@ЊМ:oЏ,K€o-ŸXyCХЎbУddpЭddpЧСсAЭŸпŸёŸЏЏ'Џ@9ЏKЏ]ЏФvЏAЧBЫ(ŽOГЏn–ЁlХУ=#юПм?ю?6HZl•ПЏДЦŽѕ'сЖПŸŸМЏ;ŸMŸ_ŸqŸƒŸ•ŸЇŸ Я2ЯDЯVЯhЯzЯŒЯžЯАЯТЯдЯцЯјЯ
VerilogType     wire
пп.п@пRпdпvпˆпšпЌпОпаптп#}яя(я:яLя^яpя‚я ”яІяИяЪямяUЩ‘л’ј"џ4џFџXџjџ@|џŽџ џВџФџˆXтџєџ*<N`r„–ЈКыяоџ&8J\n€’Є‡YУечљ////A/S/e/w/‰/›/нFсёК/ќLм/ю/??$?6?H?Z?l?~??Є?Ж?Ш?к?ь?ў?O"O4OFOXOjO|OЬ O№ФOжOшOњO__ 0_B_T_f_Н™…_—_Љ_Л_Э_п_ё_oo'o9oKo]oŽFxoЉOœoЎoРoвoфoіo,>PPfxŠœЎРвфі,> nЁ—BsgcŽМE’f†˜ЊМЮрђŸŸ(ŸєйД‘JŸ\ŸnŸ€Ÿ’ŸЄŸЖŸШŸкŸьŸўŸЏ"Џ‘OeЕOjЏ|ЏŽЏ ЏВЏ@ФЏжЏшЏњЏПїж(П:ПLП^ПpП‚П”ПІПИПЪПмПюПЬBЋ#vбX„ИT‡+С„Sb ‰Рbсz„@v6РMЯ_ЧTƒoЯЦ6РЯŸЯБЯУЯеХТтЯiэнё      пп-п?пQпcпuп‡п™пЋпНпЯпЯ­,ыЪ/-я?яeСYƒ[яЦЏ№€yя‹яяЏяСягяхьѕяџџ+џ=џOџaџsџ…џ—џЉџЛџспЦбьџ1Х„RфыщZЬsc<Ц“`Zl~еХsbЏ6-Ÿ1R#лэџ#5GYk}ЁвџІЮx;6Х/Fя%/jяI/[/m//‘/Ѓ/Е)Т/д/ц/ј/
SystemCType     sc_logic
??.?@?R?d?v?ˆ?š? YTV
|ъ?bЯO†Я2ODOVOЮЯzOђЯaqЃOЕOЧOйOыO§O_!_3_E_W_i_{__Ÿ_Б_У_е_ч_љ_oo/oAo}x^oKџ€Acroџbat Distпillerо§џ”ъo€Џщђd7XXя№6њнўы№РШсфї  рћ$ь…џѓ)ѓ/ž@oр  .0ТВr
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
dtујџџв        гТ'9K]o“ЅЗЩлэўрћCustom ?page 0ќ,/FнўBN#/#1>/‚/?/Q/
*2”/и/•/Ї/
*3ъ/.?ы/§/d:§hы№#џwinspoџolAcrobџat Distiџllerc:\џProgram џFiles\Adяobe\4.0џ\PDF Outџput\*.pdfмџUFы№џђ№ы№DшѓfњєёђџџъёP
рћіёъёh> ы№/Tы№6DЊъёы№’ујƒUmAшѓ@›
Р?­лПIшѓ№?ПСYзщћ{џвъёЗъёO•1@цѕ3EEbOУe„ZЁцѕ
StateEquation   Hex(Inc(0,2,5))
•ы№Hu§щђ ѓ№ящђџ˜џP№р№(:њџџŒˆџџ№{ŒW‹џ№_€qƒ•ЇЙЫеŒтџ§Qы№Generiџc box wiџth text џand connџection pџoints. Cџan be stџretched ћtoy dimwenss.mbујшПшѓр?єєўрПшДNoшПр?kш?рћєР4
№ћє№П•Hы№џђ№ыєы№DDы№іёщђђё
яє$#       фї=hчєіё-(>Tы№пќіёTE=›ујѕ‰›UAшѓј?ЇА№КЏшЏр?Q6   Ял‰uŒ` 6еўьu   і      mB>ъё0Œ0       Ќ0іё(2s@sJs&T„>ъёЁ5
ћ‰€LЇ@ўЃ‰ъё{Ё§Фђ№пўф5Аџ`7Copyriџght 1999џ Visio Cџorporatiџon.  All§  "s reseџrved.ўі‰` _SBlџ.chm!#22П448ў ‘dЌ9   l>#0>Uddтљ#3     ˆ       Фіё‰уј        ЌŠTЁ
HighVoltageThreshold    5
ќ<hЋђbЪ ў
2Є61
LowVoltageThreshold     0
g,s72‹Э4Ё?`b?ўM1^%Y?Фr?9€1M1E ;6З==з5(2ш?;z‰rA
SignalActionType        0
РўIB=OCРўq‰…,^пќ35Д/™rујVЁ:в№?@цѕгFќьAьCїMЎA КOеMмOюO@_2ЎAа#[6рвO€MZMь"3їЎA^%\$_Ÿ_Б_Z_ўи_B#[@ЗoЕ_П9Boў[(љ
^цѕtextеРы№Hы№lы№&ї'щђдяњъёџН!џРOyŽaў§єGEгџЉГфїчєFы№єџБїЭЂюы№ж#ы№,ДїПoJы№Bћ
MSB     0
ы№4ЕїЙj]\aŒk_@+ы№”kЅ3aђёќkIkў№ж•ы№ы№ѓєщђ%мёUlы№4ы№,чєїѕџў_€ђj @џЊЂъДфМ%@вујъёы№ќQј]ы№=A-Pјc7"Aљі%Ulы№4ы№,чєћѕџў_€ђj @џЊЂъДфМ%@вујъёы№ЌRјЋы№A-М3Б7њѕUžы№ы№~пќчє}@ы№dQјeђ№Fы№Rмџ0BTfО
RјЗђ№BHы№<мџ(
LSB     0
Hы№<мџ(
isFallingEdgeSensitive  False
Užы№ы№~пќчє§Eы№ЌQј.
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TRј;UFы№џђ№ы№Dшѓfњєёђџџъёа
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мюїbu‘ЉўoqЈYkчєЈујQ‘§hђ№u23uъќі№‘`   Cџonnectorїў
isRisingEdgeSensitive   False
‘`ў–
DrawAnalog      0
œe‘1Crw
BooleanEquation
ƒујЉUы№HыЄъё ѓ№–ўяђџ^€џџџПџўџќњј№єџїєїїЕŸ  €-џ}|5pїџ`Iоџџ`V?џпџ}ƒџ`Сџџјƒx‹їџїaŠџџѓ833џŠџџƒџ‰џџѓџџџя‰џ‡Ž‡‡џƒџљо…џ Ÿ™џЊŸџ™љ]ЉџŽЗ№ўТџ№ƒ3Яƒƒ3‚Й†“Уu…Ыџ‚ŸЉОпџ3“3?,№      ї™?№џŸ№ўG‡xpџџ№хx“^мŠџ№ƒ‹џ&яŒџŒџ
ƒДџ§Cы№This cџonnectorџ automatџically rџoutes beџtween thПe shapi
tіѕs.­bујрПєє?ќќПџшДNрП?єџ•Hы№џђ№ыєы№DŠы№ы№щђђё
@яє#      фї      іё=hчєЕы№8Tы№ пќYY9    BЊы№ы№ы№›ујFо    U@шѓј?ЊЗ
№ШПЗрПрлПP6
NegTolerance    0
‰u
PosTolerance    0
я`u#`фџb€AЛ@ўќu
J ‰.Q#DB˜ц     ˜#ж‰uŒ`hр?U\hr|Suі№†‰эZ‰aкчŽ‰Жа{@-№?bH—l;'bE-h’o'—y(œ‰ъёќБ
UserSpecifiedSizeRatio  1
т2rЧqЧс?@ŸєIЭ kЯ?У$бЫ%П?э
VerilogCode
Ї@§ƒўі"VЗў*5L Н-brъё/РŒ     ^vдœvі"(2u&€.і"q28i˜vі"uh9 BdД&<O/MЃъё{
VHDLCode
#‰§ђ№і1ўћ45ќ`џVis_SBlџ.chm!#22Ÿ474ў`џ7Copyrigџht 1999 ў@io Corpџoration.П  All $AUd3CE„ ‰\^ДŠў4
PROPS!
*Lд’1њ$b–‘24„R‹Ÿ(^[аw[D ˆZЬQi‰       ќaЈч59       Ь9”уј3ЬOп'2Х"qМ?/g;2щGеРы№Hы№lы№sї'щђ$њѕы№џН!џРOyŽaїўѓGEгЇДфїчєFўы№єОї{ЛЮы№ж#ы№ФџСїI7ПB
E0      0        1750    1750            1       0        DR      0
ѓёУї€$ы№dъёЙЧoъё@+ы№Дфk€"sђёФїkщoЯў№ж•Кы№(ы№†мџсњъы№чєы№,БїПД–ы№SћЩы№Ь­їJї+B?Њы№є9љ=5ы№RћD5ЏїH‡3Si{"ОїИ˜/ъё| ы№мџUы№џђ№ы№Pшѓxњєёђмџ№ПP4фїіёъёFчєы№Dы№Teъё€ёђyŠ
рћaъёhjчєы№ НTы№ЁпќРРцѕы№’њујƒqUIў_џ€ђj @IЊЂъДфМ%@?шѓ[Р?ПI?*ря?QcтљџR`›ьъё‘@цѕ†œ№?ЎЃыЯуqуя–НuР`Фщђеўсчёu$ ћoшы№ХАTч       <ЈујQ§ђ№4w!яw!ыѕќ Н`        Coџnnectorћў
E1      1       3750    3750            1       0        DR      0
Н`ў*˜"
E2      0        5750    5750            1       0        DR      0
ž*eН3a$Шпќ$Э$ч      Р!aUы№ы№Ь        ы№ЊЋ!ы№ы№
ы№*ы№ы№ы№ы№ЫUы№ы№6$СU!ы№"ы№#ы№'ы№U(ы№)ы№*ы№+ы№,ы№-ы№2ќцѕЋ!+1Hњ<—4РЂ7у—4яЂ7"”7!Ђ7А—4aЂ71“81Ђ71“81Ђ71“81Ђ7Я—4ЯЂ71“81Ђ7Ћ!“8Ћ!Ђ7'1“8'1Ђ7+1“8/1Ђ7/1“831Ђ731“8Ÿ:71“8?1Ђ7;1“8G1Ђ7?1“89!Ђ7Ы“8Ÿ:G1“8W1Ђ7K1“8_1Ђ7O1“8c1Ђ7@9!“8ФЂ7W1“8%Ÿ:ќ—4&Ÿ:_1“8k1Ђ7c1“8o1Ђ7g1“8s1Ђ7k1“8/ы№Gњo1“80Ÿ:s1“81Ÿ:w1“8‡1Ђ7{1“8а!Ђ71“84Ÿ:ƒ1“85Ÿ:‡1“8UŸ6Щу8КНP31ˆ•q•qя‡1‡1РˆW1W1!g1g1aˆя!я!19a9a1ˆа!а!1VaVaЋ!ˆ[q[q/1w1w1?1ƒ1ƒ19a.ы№Eo1чaчa‡1qq[qЂ1яiEiaZC<ђё1|ˆщZEРИ!я!ШыEцѕ!ц5ћ)є‰цѕE–:m џг@@|џ_—=щ$@Р2•™аП2•Р?p!чƒ„Š{1H-J2Щ1a2”’ЄPр?1v–<ў›УDo1<<Х<цѕј[№?ЃџџяlН1чaUЫ™Uцѕ1=Eћ/
3‰ыŽx‘ŠŠ;1™щђ‹рŠЋ:–ЁЅц5БЏ>”ЃЃАŠЏъЊ EџЏхіq411Шp_U§HPЏ™ујчa*И;Ÿ™ЉУ“ъёˆБс•d•ПŸЙПŠ’™—™˜Š’
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2•иЖњVŸhŸzŸ0   !4Q”“\і‡рЮaq'уЌ?ƒџ•іс“kр?Фрђ№яA|0ЮŸTу эŸџŸРЏ/ЏAЏSЏeЏwЏ%П›Џ‚іШЏЏђёЏŠъП0ПBПTПfПxПŠПќієЯЦП‘ъПЕУ\џ&Х/@Я& №ьyЯD/њc/МЯ‡/јЄ/§ЯШ%§8лTAG 0
v"11
SIGNAL  dbg_dat_o
-6...-7ў"0
DIRECTION       output
DC_SETS-1ЪвeсЃяЕя5˜ЫqЁяU3
RADIX   hex
#юџ2с•ф|UЌ?О:Yхф}8 яС38бЯпсп `п7зД‹п†J!ЂпƒчЅ§ПеїПqШqœE?Лўqq`Сkq„;OMO5ˆ5‡BѕUQZ1@яRфЃuaяsя…я—я`?r?Эяпя%ѕюєўфџ+џ=џ(ƒšqž’Vfpџ‚џ…oІџИџЪџT}9щџћџ§eQ+=Oas!—|fФЉшё0BTfxЪ/€hЇЖ/ЫjъќЭVo(У
GRID    0        1       0        1       0        16711680        0        0
Ÿ>/P/мt/=Ÿk]ŸИ/ ŸўXžŸљ/Т•J;Word%0Ђ,?)ЃЂH52?ЋP?Ѕ_З_†?Ю?р?М?  щ'БЏУЏџ?O#O5OѕOYOkO†OOЁOГOХOзOGПYП
__1RIQ0С>\0СР—[_m_WРYУ_jЏ|ЏХ_з^џ6аiƒ@@|?џ—=щ$Ђ…єр*ƒаeђeРo.o`@oXёуБ.#bжЄVш0АЁHжХƒЗƒА`ФoTЭчoљogСIQ%7I[m‘XяжО…явч`яРц&8J\n€мжъŸМgџр‹џ“bп"%цџ
ENDGRID -1
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і?ќФ Ђ…ќПжzdРzdь“uўПЙPњKАЁus `НuуА`€ARў.Оru
ЦqЫw§aГб1s!ьrжђvYXИэФ:Om га§ТЉаџ шДNр?џ@ј"ў/{R/@)Ћ2p 0РюK‡€сp@z3„бqE‚K]Žьw  ьrЅ„‚ ьrТН‡œаXЮCЙE’v№Пћ2rјЂс?@Ÿє­IЯ?ќ„б•ПU?Џ|Ћ2uЎ0`X0ЖŒ3ў/’ud `Ћ Q’бBП†Ј&8‰ЉЅ§b…VhД0Й…ыQИžP4‡ЎаpЇв8вБЬ№РХБсp­0`0ўѓ!•Хџ/кј‚”fгІ[?Tе9У;№‰5Пыoџџб1Њ9кCрМ2хOг?щ?ћ:`Izaп_gв/Ÿ€C›ЗYIфЏТ#П§ЏПš™uБЙB€I7Л’vNП=ŸrНљEŠП–tЃПЕПЧJСYСЎ1РoтorІUЭћO@H%\%”ІЦ8›)‘s}V;‚в
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Clock
Ењ›ЋЯјВўЙрB• Й(бьsђ‘ ќsHжЊ1L%‡ЏьOўOЙЂТЏдЏ9ЙъШіПЯђз2I7Пнп[Зњпч/ПюЏ:яLя›ф~Пбоˆяєп–щ!q,Я>ЯPЯbЯtЯ[&КЁ,Ё—Ф§gHwžЩЎ1u›)QРЋ!2ŒтХеіњ›E№ygP-DTїћ!љ[‘ˆ->П}фbлxЛ€ж@ў"Ћ1”лxФyбvЩrФr
EdgeLevel       neg
дsрrлrhп (п:лqLйИ‰xОџ=ƒх
@E‚CpЄa:ta„#h!rГИЗ]Зl~ИЊv€ЧД~”‘гU ŸВš
­0Х’ѓ!eњŸЉqЩRЗЩRbевA]€К4іqХ9CTџЉпЛн*rяъ$пяДхгUТ,оїл/ЧЄaб1ќе3;нog;ЈЋе5КЁnџ€џ’џЄџЌDEоД2ŒтХяіяі8€’Q‚™""\UЏ‘3,\R.H/Z$ОqQ#lFНэU0O3kRЏ“(}ЁКЁЄp˜0Оq3&\SNSZр,ЏЉT;њOјZЅ?g?џСџЄa˜aгUмpЇiDMMUт„hйЅ2yп‹пйЯQЎхdоКFяјƒoЅrQ-ЂЊQ-–QУеakFа(Ф_“Tї%k,ц'oBo'%ono€o•R˜•Ђ[OПoдXlOёU_#G5ŸarдšС–Љ"ЁІ­йОЏ1%ПйfQ`oб’щК{яјгs'%сTІИщКŠzU„/™Іi‘tЯЁЯ—Ј”ј—Јљy{'2U
Set     Not Used
Э‚ХЏ’ю‘ёM‡"џп„@ѕ]?—Њ7Ю5Ц5‡Хa4~‡}–Љђ‘a В9^ѕђ‘"Ёв=“оДџ:m г†@@|џ—=щ тФЇ€РэЖЕ”Н•ў‘ПкРC
Clear   Not Used
€ V <љ“Втx!Љ2еІв     ИоДп6аiƒЋ”Љ$кішэpx•CvІ'uЏ‡ЎЇ@нТс‚ЫЈ+ЂЎТТEчЇœє(OSЕ
ClockEnable     Not Used
Н•џюП2rЧqЧс?@ŸєI0АЋЯ?&Дб.ЕПлўоъЩgн`Š|цLђячТў'%&;HŒ)ŠЊ2€A'…љ*ЎУЂ"Їux1§љB‰P`0ў€#!Xб+/=-тx“BЦBрOTтlЯ…ыђПŸџџтbбŠQjпi_y|@Ёеœ/Ў/oядяф)€mП9гя„Л™'пяя[я
ActiveLowSetClear       True
п,цюПzп9п{ЗИяgоЫпŠпyЙъ
Уш'џ9џ€Kџ]џ”?І?И?Ъ?Зћtк@Ї
я№яѓo{ЕёїЛ‰+=Oas…—Љ
СМ    ћіЂб
AsyncSetClear   True
Жу:bЈєєcЈ€]ћіSњї€Tfћі›g
ActiveLowClockEnable    True
ЅъЭП/ ,Ф+Юa/s/…/—/ѕЯј/Э/п/ё/ЃoЏ':O8?yTqя      С“<%“яL%@­яПябя,šŠQєщ‘ „Њѓљё4віф3ѕ
VhdlType        std_logic
Њ5д3ѕњIЖ€т‘ЯЩџлџэћ Ѓ76(оеъe2‘TФЮ!вOЋ€L—ё‡†ИG      ƒ2(ВqЌ?Ъ?м6гT+р?арят‘џР8Ugd‹|п$пС8яЦ~Kй&•O0яЙMЌпе,ъOќOžлџпЃ;_ЇOœнN…w_уO”›_^Ы9~ƒЛESпET 0
VerilogType     wire
,a1
SystemCType     sc_logic
Ю7f...7g1bDC_,`S-1p‚PA‘Рv/ˆ*аЩшхTAЈUшПЪЩд3МдƒџŸbU<aЗoЩnтcЦ„PћoППiЫЩ‡ЕЬgju˜(}љф•СШd”7є4оФ!3тrѓП˜AћтъvСыїv§Дсu?ўт`еkr‹ˆ]œ$Zс€№WB/x„$%ŸЎ‡>Kˆe=™LAб6„l™фхЮ-•єщ§EК*џ?@№EќЏ_і$б%ђ3ѕиК3ѕт3ѕШ?QO)pvEє1—?.'ЂICЦ—–aPТЋ–ЅVЯT˜…йŸј„Х?Ўџџ{ЅХO+O=OOOaLrIМСЮ_ћтХI{ЋA–’Ѕ‰ЕЂЏE””Ѓ@мх{ЏлЊˆe№ЏУЦq^h БУobМЯЮЯIЉ™АLЄJ–‰ЊўН†<ТЋŸ<ТЊŸМyБvE…ПЂ˜ЇПЙЖ—ŸжГ9ЯyБЮЁП[Я'ЩyБСЅsЫS˜ŒЯžЭмхsЫРA–ЭЯ%ЫмЕ”…!hCOMPYтeZяЅ~яI/€Ђяm/roияъяќя/–јб%œПиP-DTћ!љПFџXџjџ|џŽџ џВџФџ?$?Д’џљ$§ц
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
э29/•Є
@N§цUїќчqVџhўлВФ„џИžџhљ)Oтp˜…@цїw€‡р@z3™срђцџјўо№u?+zŸЗЗђЏ8J\n€ЯЄч_Ш(W"ш 'Uпgпyп‹ппрЏпСпгпхпїп@:Пm г@3ѓ’9•і#юц5яGяYяkя}яяЁяГяХязящяƒy;9"6џ,.Rг@.'Fірђp%|6ќџ{?>Pѓ"6Ь7!7sєЭ?п>jФѕћ?КѕOп92DVh zŒy|sЗFІИЪмю=$6КЧG(E_oй!iƒ›TЊ@ЄбWяЉ4бŽё83‡RVўXё‰|uЧQIЁi9Ёђ-‘ЗФ/"†ї?@П|џ—=I:№рK~БфэПpTыа?udн}eР?PшїKй"x)€‰@@ў@‚~fЙcїуй!тAю+кf<9˜ЗЪ1№ДM#:і№2їрє	NЄ4v‘?3E~дgаѓфbRаѓœ^X2ГU@ ZўзPŽ`џ€/тџВ'С?џ2rЧqЧс_?@ŸєIЮpЯУuхбЬuϘm„Yiъ/#Лaп53Мsс0l!СЅ&šOAсdWA%cOuJ~ѓˆB‡ъZИGЗУ2ЦrqЌ?dЅЗ†aRэ”р?ћ ЅрУPя‰A‘џёPЇh6Ј› ЙС§УPЌ >H `0ўm‘ёUР™O†   й!Џ“:–ОŸTай!dŸ’STПб_џџй!Ѕ:ЗнBIП[ПIЁQЁрMЁ
StateEquation   Hex(Inc(0,2,5))
_]pQ0[Ё;ŸšАН?іzћд€Ф‹Ѓн0]YЅРkё)Ш}`Џљ r3B)БЩ
HighVoltageThreshold    5
ŒCЋСЅЅvfМuЏ”S
]Q%YЎНЏ|ЏсЏцБXіE]q@иi1hхˆ)ƒ‡К—”Й˜h„Ж›ы'З„МrBџ‡jЂ”jП|Пɘ•тɘdІЗЯ„Я!
39ТѓПsСєЦ§Dџк~Rїѕ„8Х?НўЗ `$аkEdзПщПɘˆЙ˜ёQ •яDШ_ЅЗѓHдЅ—ъДŸЦ›и•ќ/я@VЌbЦ\џ‹ќ?@Šп•љGОх:PžгјZ/l/~//Ђ/Д/Ц/и/ъ/ќ/?вСљц;?Д‰йFѓ
LowVoltageThreshold     0
;ј`fЩсЮA?s6Љ5йцIияЖ?Eц)ї~чsє*џ<ўцqї=§Žч{џTOk€xOŠOЈПЎFвСЛC’%ž=FaSЯ|TяЫOнOяO_эŸb_7_I_[_Hžоќ”SFБaU|QXЖHIT 0йТ‰СжЯшЯ•ёЃп%пРˆ	Т™ЋБ1PoU@@аi6иkeЁ%Ѕе…`‘eB-А˜f€‚СЯMя_я;‰С&9Ђž&ДёR•РѕЬ"‘eжџшѓaUїџR’ь€Lс‚ЗAС’DбLйЗЗЙЭБUСUјŸч‚Т;ŠЊˆ>@&Ђ?еЏЦ=Є­:.ї?	OWѓЏ‘>HOД?lMШ•„O№?ЈONQ“XЖ31}њ!ЗІ_ЂДэˆ-йм‘N‘ФуWр.g”Щpе/Ѓ6_аiУ@0-ьA.мS/e/w/‰/|рњ!ƒщlfЗ/Щ/л/э/џ/:’%4Т…`м?0?B?T?f?x?жOшOњO_в?ЅfЪZOOj1nOU’Oг‹ШO€Џг_ИѕDбVИlџog2(DC_S?ETS)+3aВќ сѓaиё™ПU)ИГUе’ЕХЗА‘Šl*QЧŸйžИќЙЏЬДfП“ЯїП	Я$Я-Я?ЯQЯcЯ@uЩгПhЏЅЯЗЯЩЦA_S_e_w_‰_›_­_П_б_ўу_@:m г†§_o!o3oEoWo|рUБƒщЦ…o—oЉoЛoЭoпoёo'9K]o“ЅŸŸ'ŸэСпvїпGяО?ятЁГ‡яѓпщНяжп сяMяCŸUŸg•4pŸ‚Ÿ”ŸІŸИŸЏмŸюŸпџЏ$Џ6ЏHЏПП~ЏЏЂЏДЏЦЏиЏъЏќЏu‡2ПDОЊє]МуtП„П–П€%АЙŽџ џ‡піПѓVЮI/А6ЯHЯZЯlЯi`jpi’&šЯЌЯОЯаЯтЯєЪ[пmпп‘пЃпЕпџ%џ7џIџяЧх4&–?—яVяЬ?2*ы?§?Ћя!OЯяŸ?WOџ{Oч?ŸOMџЪ5lї4\Вk!k]Миѓ‰™Ћ,ХзщћоќП гФ)!*Хфс5ас5д5'Q/c/u/vШ4a…Щ[fЋ/Н/Я/с/ѓ/??)?;?M?_?q?ЯOсOѓOЙ?AњY_NO
O•ћZДЦbOъVvqГO;T_№qVў[ѓmіWAY 0…і/аИХџНilPŠRrвС]Ћa]Б!k}X_j_ГŽ_ _В_<Ф_
/аiC#/5/G/"o4oFo~Рm‘…Щ•Іto†o˜oЊoМoЮoрoђo(:˜ЊМ‚{Пн?БПмеПŠOљПw6OAЯ­П~wЯПP›ЯЯ_jљ3:R"nŸ€Ÿ’ŸЄŸЖŸШŸкŸьŸўŸЏ &Џ8ЏJЏ\ЏnЏ€Џ 6б–)^цЎЏРЏвЏфЏіЏПП,П>ПPПbПtПвЯфЯіЯМПDџрПEЯzџЯžџЯТџБЯpЯ‚Я
LSB     0
vџИЯ@Yџdаџп
MSB     31
!Y0:R%;\џOе%ёUп2ћ–ё•пЇпЙпЫпф€E*%ЅщU$ѕUиў^ШчQŠI­т|х+Ля|т"m(9&Є“ј))|уўA2Q!Ђ|х
SignalActionType        0
ЈКS
Гˆ
Љћ›ŽуХЁ‰ХбЅЙП…ыQИžрЃЈєШ-БіЂЇSИхУ§јЙ’uртА`0ў€ћЁвб§xЗ/+%]/TаЌжаУЮФПпџџЌЌ)м3=Вч?TПjП|КŠПшЯњЯlЄпЃ2Я—ЮєП‘Ѓхї…Я}ѕ&цтgЯ-мЯ"ь7/I/№ЮЧ+б_9ЊXWORD SELECTSвйуRп›Ÿ4mе9XПк!Ќђ”‘змз%Ѓев•b!ЉМЯЦы)!EЅљр{^:HP-DTїћ!љяёˆ->Sэфboшю2Л€j@ў"рБ”oшXщeц]тXт
isFallingEdgeSensitive  False
ю1hуtтoт
isRisingEdgeSensitive   True
№ЌУjл+Еъ—=ВљŸЏуБVh*Ь‹Œ/лН*kРБ8Coœ#ы!н2ш//§/?!?3?}ЖeAђ”жйЃеєY­љ+dІпт?@ќMВШ?Ћ@ўЛbёњЕиZuс
DrawAnalog      0
њЕШГћРxЏkO›vІgt•qЕa шЛbMяЗutЩСХr[Ы{РwрSЖvкw
ГЁЇн1ЏЉ(†ФЂs]йЊ_ЦX@3ПEПрoI{ПЦЈ`+o@‹      п"Э;ѓн1П
BooleanEquation
уU2–пПU[tбcwРўС1ŸвЧУqџџ  ъgŸ”yш†Ÿ~ЯWœbvќš/Omi%2цЅRM’r>17аўlЂrЃ—b.oЏoСoгoхoїo  -?xжгPpQ|Tfxu(а2  EС€‹ЏСгхЕДј­Ђп{NŽЁ,‰ЦASew‰›­ПбуЏŸ2Џ+”ŽЁ6™$жKŸ]ŸТŸŸ“ŸЅŸЗŸЩŸzпэŸџŸъЯ#Џ5ЏGЏпЯkЏ}ЊG—рЇЁ_aђ!я$€ЕЉЏЛЏЭ­“чыЇ>1 њЇm9OЗЧ…9сDфџ6аiƒ@@џа‹јПьIў?@рSђCЕ]АрSBИzЯП‘Пwі8‡BЇЁ,ƒ€(†›b_SЦЂ_S–ђœі(†A’,‚)Ч3вьѓAe§XљЏp:_eХƒЖШ!@Fсн1ы!?pMŽЁXы!vУ”Џ˜яЊяМямЏРC?U?g?y?‹;&іЦяџЪќGŸ
NegTolerance    0
@@Ј?S9ЃєЉ5@GѓФ?ж?ш?њ?OO`0OBOTOvџxOvСА,‰(&ЅO#љЭЬ` Lћ@%їђEќ_іЄмF(&€'''T/“.(&Ш'”-7'в/l_~_UЮaЂ_Д_Ц_и_ъ_ќ_o oKяoVoЧ4Gп?’g1€’ЄЖШркьў"@:џm г@@ј?"ў/{RNuhaа`&1vˆšЌОатє/
PosTolerance    0
Э8A,‰„сVA*чOљAe юL/@)3RpСС“Aw:g€kP'@z3[Q4b:oLn€{#сV‹gрWž$ŒožnсVгgŸm№Wнo??UЯ><+N?ŒТЌБяSТAžczre?w?‰?›?­?П?б?у?ѕ?яwX.GCу>O>цiEБСWOƒЎGвEЕэЅ<Б4чсЅyl`@
UserSpecifiedSizeRatio  1
zr?дуyAжM‘њйh‹УР]ќПšaРZћ˜R7Y€fР@ўЧВVt“УTCсЁq-г•–B)1F§oЬ•—Дѓ”гю—œ?иqьzI˜2ПrЧqЧfАŸ‹єI7 Я,ЅXа7ЃП€SCСVгкСQrE5&YxЕyєэЎBqТE"4zvP;3Ї’ШM4ЅбSkPp`Ш ўA1 уI?ЗЧЃAуu<CсhYПмгкдПџџCс(jСqБС,wЧЂ|БС€;хЈ‰KEЩл}№еѓ|РЕпС€tЏПS>пёu7– Яя6Э•н$У]ЯfЃЗmлЖmлт|Я;ШшнЉЯЛЯЭЯМVeX``MO_OqOЈ“OЅOЗOјЩOлOТ—бёй_“ю?@я^вїXуч_r=_O_a_s_`…_—_Љ_Л_Э_?б№,)шцA/Р™р‹јПяьIћ?Т—ˆ_ФџeOЪ?y%шц@їччž$AџSўшцˆїT§ їч’џдЏ,8
8?(П\?“ЅЗйПл§П< 
VerilogCode
юŸyУCШ'ќЋг­TO/FROM CPU
VHDLCode
VhdlMapping     DefaultVhdlMapping
џEXTEN I/FFвШCпЮєШ~d€ЂДЦиъќC“ўМ™у@@|џЏ—=i$Eд хаJ•Ф хРПTŸfŸ†фlш‰™™™l&ЎšИJМ™CњЉ (ѓћп)$@4bpšБheЦ&PoХ/з.f'Pђ™<{"Ђј’77ЏŒ 
'-Џ?ЏQЏсš™Ж1Й"пxФŒЏАЏТЏкџцЈжвGrћЏ
П@ЙXjyШ’FCПTМOlПпM’ЙЊгЄВЕпЛПЭЕdыПˆDРоГП?(С•Я`^аПs_…_O‡шЯ`U(Ц_yЯO‹53Rпdпvп{šп`ЌпОпаптпТ“УГ'!ффш,(рQ  7яIя[яmяя‘яЃяЕяЧяйьРKaьщєvџР–В(@‚?NшД Г(:є@єvL‡ѓw^єM_Žєv€”‡`‡žШџOьјјђ@AzO%7I[A_‘Ъ_Е–—xЋŸјюъ“BYTE
PROPS!
џ
E0      X       1750    1750            1       0        DR      0
SELECTSU>щђы№ы№ы№U#ы№$ы№%ы№&ы№U*ы№-ы№.ы№0ы№U1ы№2ы№3ы№4м№Ulы№4ы№,чєы№§џёў_€ђjџ @ЊЂъДфМK%@ујъёы№ПQј1D№ѓCЊ-3e7ы№AщђU2ы№ы№пќчє§@ы№TPјkD7Iы№RHы№<мџ(
E1      V       4750    4750    0x0     1       0        DR      0
U2ы№ы№пќчє§Eы№œPјгD7
ы№RUlы№ы№Lујы№ѕчєы№ЮїџФ\(їгЩы№4Ьїп Dы№@Љ?ѓё%Д)ы№R§)tЭїр;U$ы№мџ
E2      V       5750    5750    0x4     1       0        DR      0
ѕ4ы№(чєєюмџU1ы№џђ№ы№(шѓы№мџіёіёцѕUы№ы№O"D&aU=шѓђёQџџJf        рћ)ъёh"Tы№y‡ъёМуј+Uvы'_Щ…&aQ-З
!
-H*9(TYіёgЉŒЈžАщђ›ујEQю№/,GuideTheDocPage-1ѕы№ы№Gestџure FormatBlock NormalVisio 10Block ShadowVisio 12ѕы№ы№Block Highl§№tVisio 11ConnectorVisio 90ѕы№ы№Dot џConnectorѕы№ы№Connџector ArrowVisio 00Visio 01Visio 02Visio 03Visio 13Visio 20Visio 21Visio 22Visio 23Visio 50Visio 51Visio 52Visio 53Visio 70Visio 80BoxBox.3Box.4Box.5ѕы№ы№Dynaџmic conn?ectorѕы№ы№Dynaџmic connџector.10ѕы№ы№Dynaџmic connџector.23Box.37ѕы№ы№Dynaџmic connџector.40ѕы№ы№Dynaџmic connџector.50ѕы№ы№Dynaџmic connџector.52Box.2Box.9Box.13_Вы№Žя№Ѕуј5ъё3ы№Dџљ
F
SIGNAL  dbg_op_i
Њы№ETО,љ-
DIRECTION       input
<’;*ђёG#;BЊl;S
Њ„;`c
RADIX   hex
œ;qЊu
GRID    0        1       0        1       0        16711680        0        0
Д;~Q
ENDGRID -1
Ь;–Њu
Clock   Unclocked
ф;Ѓќњ;Бu
EdgeLevel       neg
љОЊU,яеЊUDяюu
Set     Not Used
\яћZu
Clear   Not Used
tяGv  ŒяU;Єя";МяU/;дя<;ья}I;љV;UЃc;4Ѓp;ULЃ};dЃŠ;U|Ѓ—;”ЃЄ;•ЌЃБ;cЃЙЌ;я№AФЃНT;дЃЧ7*мЃUЫ7*фЃЯ7*ьЃ}гI* љнI*UŸ ч;U4Ÿ ŸHUŸ !TЧ :'dŸ %й*tŸ U)й*„Ÿ -Ч*ЄŸ ULй*ДŸ Pй*дŸ ЉTЧ 0фŸ _Ч*Љ!Јй*$e0‚Ч*D*e0ЁЧ*de0РЧ Ute0ЪŸ:„e0дE6*ъёы№ы№Ÿы№•ы№ы№ы№(!  ˆы№0ы№xвRы№ы№fы№ы
ClockEnable     Not Used
ы№ы№ы№іђё)ы№И!ы№ы№њёЊЪ! ы№!ы№"ы№#Ts1ы№%ы№&ы№'ы№U(ы№)ы№*ы№+7Њы№-ы№.ы№/ы№0*ы№1ы№24м№щђујм№Ujхіы№ы№ы№Uы№ы№     ы№
ActiveLowSetClear       True
ы№Uы№ы№
ы№ы№Uы№ы№ы№ы№Uы№ы№ы№ы№Uы№ы№ы№ы№ы№м№Ulы№4ы№,чєы№§џёў_€ђjџ @ЊЂъДфМK%@ујъёы№џdSј-KѕUы№C-Pј‚7ы№AщђUlы№4ы№,чємџшнўўёўѕы№DPјПеK
AsyncSetClear   True
ы№AJ-<3п7ўёAщђ_ы№ќпќмџ*<Nчє@ўы№ЬRјˆKMы№RVŠœЎ№РвфgЄЎїсq6uHы№<мџ(
ActiveLowClockEnable    True
Hы№<мџ(
VhdlType        std_logic
_ы№ќпќмџ*<NчєEўы№Sј]L
ы№RVŠœЎ№РвфgєЎїjq ы№мџ>=–{†ы№zѓ№œцѕїѓы№
VerilogType     wire
*ы№   ы№gѓ№"мџ4pFXпќїј„ќшѓ(‰rИџт@(ѕ3БЯaт@ЏА2ЙЬy
SystemCType     sc_logic
ы№№Jїхіњчєы№„Oї:Кы№]ы№RPЇї—
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
4 Њы№dЉы№uюы№в&ы№ЬSїыѓ№!ы№BоћTї?ѓ№Q
њ>ы№ Cяны№Fўы№ ŸCmы`sы№ФЌїЋPfk$ы№ŒOЫїЛf'ы№МЁџD^N4_љPE)1ЊХYЩ1ы№ЄЊХiЩЁ=џы№дЛџјхі`2ы№џљпHDюя№V<ы№ьoїП#K
StateEquation   Hex(Inc(0,2,5))
O?~ы№мїLtќЗ$љwъ5 C=ы№є%љЃК5 J!єџУ5 ы№@ўџўџеЭеœ.“—+,љЎDеЭеœ.“—+,љЎ"о@€HP\ht
Ќф   PagesMastersPage-1BoxDynamic connectorМ8Œ€”œЈД_VPID_ALTERNATENAMES`_VPID_PREVIEWS_PID_LINKBASEшф       Aўџр…ŸђљOhЋ‘+'Гй0Є@Hht€Œ˜фValued Sony CustomerG(Eџџџџxw
HighVoltageThreshold    5
w
LowVoltageThreshold     0
 EMF EXиЂVISIODrawing‰M”D€€ Ь€?€?џџџl(”@€€(€€€€€€€€€€€РРРРмР№ЪІ№ћџЄ  €€€џџџџџџџџџџџџўџ
SignalActionType        0
џџџџРFMicrosoft Visio DrawingVISIO 6.0 ShapesVisio.Drawing.6є9ВqўџўџеЭеœ.“—+,љЎDеЭеœ.“—+,љЎN
MSB     3
@€HP\ht
вFQ/   %8&" WMFCcR P3PSxU>вFQ/ EMFPSЦXРьЫVISIODrawing
LSB     0
 Y=&%%€V0JJJJ%€(%€RLѓџџџ Arial§џџџ‚ƒ„…†‡ˆ‰Š‹ŒŽ‘’“”•–—˜™š›œžŸ ЁЂЃЄЅІЇЈЉЊЋЌ­ЎЏАБВГДЕЖЗИўџџџКЛМНОПРСТУФХЦЧШЩЪЫЬЭЮЯабвгдежзийклмнопрстуфхцчшщъыьўџџџюя№ёђѓєѕіїјљњћќ§ўџ	dxі	фі	ф№П№П№П_VarMemberFlagsџџџџоОџVB_Var@?>=<;:98%Tˆ+.g=Ћ*ЉAЋ*ЉA+.
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CORGROUP        $$dwb_CLK_I_BufferRising
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CORGROUP        $$dwb_CLK_RISC_BufferRising
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CORGROUP        $$dwb_CLK_RISC_BufferFalling
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CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
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L`Exceptions
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”Z‘‘W%€(%€%€V,†TœjœT‘j†TœT&%%€W$о фmсjс#%€(%€%€V,жь&ж&сь&ж&%€RLѓџџџ Arialџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџ%T|šUзdЋ*ЉAЋ*ЉAšUL\Data MMU          Tx eбtЋ*ЉAЋ*ЉA eL\& Cacheџџ  RLѓџџџЬ Arialџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџ%(RLѓџџџ Arialџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџ%T|A<PЋ*ЉAЋ*ЉAAL\Insn MMU TxQ8`Ћ*ЉAЋ*ЉAQL\& Cache,  &%W$џџџџY[_\X\%€(%€%€V,UQkgUQk\UgUQ&%%V0kпъ.k.ъ.ъпkпk.%€(%€RLьџџџМ Arial
!
     
                         
          
CORGROUP        $$iwb_CLK_I_BufferRising
Percent 100
                
%Tp‡
Ь$Ћ*ЉAЋ*ЉA‡
LXSystem
RLѓџџџ Arial


!
     
CORGROUP        $$iwb_CLK_I_BufferFalling

Percent 100
                          
                               %Tp
!
6Ћ*ЉAЋ*ЉA
LXSystem     & %     W$[X%€(     %€%€V,!!!%€%€V,Uk"UkU"U&     %     %€W$AЪiаfЭDЭ%€( &     %     %€W$AW“TD%€( &     %     %€W$QQWTTT%€( &     %     %€W$ghmцjуjk%€( &     %     %€W$ghnŒkjk%€( &     %     %€W$gГЙŒЖjЖ%€( &     %     %€W$gрцŒуjу%€( &     %     %€W$Q•y›v˜T˜%€( & %     %V0uBѕ~u~ѕ~ѕBuBu~%€(     %€RL     ьџџџМ ArialџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџF&‚
CORGROUP        $$iwb_CLK_I_BufferRisingFalling
WMFC`
Percent 100
`*џџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџ%      Tˆ„ZхqЋ*ЉAЋ*ЉA„Z
!
L`Integer EX

T|rй‰Ћ*ЉAЋ*ЉArL\Pipeline
&
%
CLOCK   CLK_RISC
%V0њVDњDDVњVњ%€(
PERIODE 2.5
%€%TdД9ЫЋ*ЉAЋ*ЉAДLTGPRs
&
DUTY    50
%
OFFSETE 0
%V0uдѕuѕѕдuдu%€(
INITIAL HIGH
%
€(%€RLьџџџМ Arialџџџџџџџџџџџџџџџџ@?>=<;:98543210/.-,+*)('&%џџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџ%TˆьшЋ*ЉAЋ*ЉAь
MAXUNCERTRISE   0
L`Load/Store
TdЃШЋ*ЉAЋ*ЉAЃLTUnit&
MAXUNCERTFALL   0
%
MINUNCERTRISE   0
%V0u‰ѕХuХѕХѕ‰u‰uХ%€(
MINUNCERTFALL   0
%
€(%€RLьџџџМ Arialџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџ%T|Š­сФЋ*ЉAЋ*ЉAŠ­L\MAC Unit
&
JRISEE  0
%
JFALLE  0
W$FЕLIIИ%€(
GRID    0        1       0        2       0        16711680        0        0
&
ENDGRID -1
%
DIRECTION       internal
%€W$FГ[ЙIЖXЖ%€(
MASTERCLOCK     None
%€%€V,UЋkСUЋkЖUСUЋk\њ-ќќB0-$>=K=K>>=њџџџ-№ќ-№.-ћМ Ariald??????П-2
Clock   Unclocked
/CPU/DSPњ-ќџџ-$koъoъ k ko-№-ћМ Arial%%?W$?--2
EdgeLevel       neg
A|
Set     Not Used
Instuction
2
Clear   Not Used
Y˜Unitњ-%`н`-№њ--$kЮъЮъ€k€kЮ-№-ћМ Arial
ClockEnable     Not Used
ActiveLowSetClear       True
-2
AsyncSetClear   True
­v
ActiveLowClockEnable    True
Exceptions
њ-%ђѕђ-№њ--%`ђ-№њ--%<ЇѕЇ-№њ--%<//-№њ--%<Ї<0-№њ--%C/-№-ќ-$*@V@*@њ--%TTuT-№њ--%ˆT-№њ--%‘‘W-№--$œT‘j†TœTњ--%сjс#-№--$ж&сь&ж&-ћ
 Arial?????????????????????????-2
VhdlType        std_logic
UšData MMU           2
VerilogType     wire
e & Cache             ћ
Ь Arial?????????????????????????-№ћ
 Arial????????????????џ-2
SystemCType     sc_logic
AInsn MMU  2
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Q& Cache             њ- %\X\-№ --$UQk\UgUQњ- -$k.ъ.ъпkпk.-№     -ћМ Arial
StateEquation   Hex(Inc(0,2,5))
   -      2
HighVoltageThreshold    5

‡System
ћ
 Arial


LowVoltageThreshold     0
MSB     0
       -
LSB     0
2
isFallingEdgeSensitive  False

isRisingEdgeSensitive   False
System     њ-%X-№--$!!--$UkU"Uњ--%fЭDЭ-№њ--%TD-№њ--%TTT-№њ--%jуjk-№њ--%Œkjk-№њ--%ŒЖjЖ-№њ--%Œуjу-№њ--%v˜T˜-№њ--$u~ѕ~ѕBuBu~-№-ћМ Arial?????????????????????????-2
DrawAnalog      0
Z„
BooleanEquation
Integer EX

2
NegTolerance    0
rPipeline
њ--$њDDVњVњ-№--      
2
PosTolerance    0
ДGPRs
њ--$uѕѕдuдu-№ћ        М"SystemЮќєcФјПЯ -№-ћМ Arial????????@?>=<;:98-2
UserSpecifiedSizeRatio  1
ь
VerilogCode
Load/Store

2
VHDLCode
ЃUnitњ-
-$uХѕХѕ‰u‰uХ-№
-№-ћМ Arial?????????????????????????-2
PROPS!
­ŠMAC Unit
њ-
%IIИ-№
њ-
-%IЖXЖ-№
--$UЋkЖUСUЋVisio (TM) Drawing
!
ЊA„THї2@xRэ|ъёщђџџџƒџіђџѓћ№јё‰€ъё€ €џРРРцццџЭЭЭГГГяššš!€fџffMMM3џ33яџяяњњњ?мчќBa$ы№мџ
$ы№мџ
CLOCK   iwb_CLK_I
Uы№џђ№,ы№8шѓ@њєсњіёъёуј§ы№Tdџ Arialъ@чєNПWingdzsЊ@чєN@tMџonotype ЏSort+чє
њNtSymbol5Tы№?шѓа?ђџкъё шѓY@-1ы№џђ№ы№іёїїTўјJчєы№Dы№T1шѓђёEWPђёрћ-ъёhчєы№НTы№Tы№<апќŒŒцѕ‘U*ы№ы№ы№Uы№       ы№
PERIODE 5
ы№ы№Uы№
ы№ы№“уј=/РUКпПbў
њbўщ…Иъё‰0zПЎGсz„?Ж@цѕП8‘HШ2!kWbU%Ѕ†МъёUВ
DUTY    50
€ь
‚+ŸЎ‡РъёйPы№L/^&œ9^$р? { ђ№яЁAшk^&Ž™,"™,™'%/v&ŽQ&Ц‚      
OFFSETE 0
1 yрЙ
‚€‚ )‚ЎР? 2Њ

ЊJ1ЄШъёэ2?ё§k9лaUўBBHEHEHEUHEHEHEH@ ?В>з?щ:`2BBЊHEHEHEHEЊHEHEHEH@„$Ьъё%O9ЃаъёF7AOY@;
ЬA*sVsVЬAЇдgЄLTkYЗиъёї 1 WЭ_Wп_ќ_њ !`Г#•ku4l•b”6Pu`kђWŽ 4l
INITIAL LOW
4lЅ•НмъёБ%Y№?ˆˆ:?-\
*Ѓ#!ю+|tKf*2|2|2|2wŠG)ОръёQUѓoˆІTMeEжttAПфъёв%_8BOTOfOxOŠOВ?Ф?ЌOш?њ7   РшъёмЛњuЛW+Р?ыаќŽиžђˆsU4‘х2–
MAXUNCERTRISE   0
TŸ*<N`r„–HЂД„k!–ŽЌ)§†Ž0Ќ–ŽеPЌЌЌ Є3•ŽЇ
1’ьъёїмЏюЏрПП$П6Пуќ
nР[ЕiИРЛіё”|Г        фх”ујМЫЏi'04’UХP§iW?i?{4‚Lz№y‘2ї#ЩЖz“Њx•       x•
MAXUNCERTFALL   0
x•x•x
MINUNCERTRISE   0
Ѓ0–jМvПˆПŠуј•ујШВЗ^/ЫЦ!M3оТѓПjЦjЦ6DˆŒ/ž/А/ў$Q0pоФ?MdjЧ^cjЧŒ4ТBЬAk[Ж~ЯЯхіˆуј$YkU1%Л1ўпт@УэFЛе„-(‘ kp
йЛ   ѓ       .$–5-Bi`яЗBб#ошяЗ9)›F/Pџтљv/ˆ/п пО/u?@‡2tСrПœпœЯKЖSИЯ5мЯюЧ2ћЩŒ7сбxХ€эпЂя#я6@хhБ$MчюuLЕhБЪ        хеƒя•яЇяЙяЫяняяяџџ%џодŠе‘ї§ѓ)Й<щ€№Oх™U‡#Р5G‹˜:ём:ѓU27ЧqЩ Ќ?Ш/к&@мwџ‰ўк&Ѓє<<7сбHсщпєБУ1яOВQjСPфSсHЙQ›ywщHсAt/†/˜/YOВGТ$_щЅ4.Ыћb%FЂДЦ8ћqТ/д#?˜Cђ/Њ‰§Nм^мТqЄ€hшE!	@d)nм{” щrѕ1PБ1	@/ЋO0q•жt}Q„”ўnПњџЄК=ВЙkхЦБь…Љ{Ј…B'ФІЩ‚X/йPP\ьfцй2ѕ1ѕ1”Rе5P"”Q”Q[СO"P!ДЁq’[СŠrДЁДЁюrŠq€Šqг‚юqюqТЂггPБТЁТЁWт§a§a7бVтWсХе7бPБ$q$qZБ0r1qPБZБZБdБJrKqobdБdБХ2oaoaAPБС5TБ~rqPБсбй1W?Oрr?~??Ђ? ъќxХљ9/F
@@O$JљД]€”Aм7ЪкДIКHрЙq‡ƒаd˜Ep{y\O@fƒае_ч_љ_ЄКpИПЪПцЖсбЋaІИЂ–й1Ач<яNя`я†4F‰OdћЕ~‰аqŽЖGШ‰3qOшДNkуgLЂІ9њQзOыЏц$˜B_­XоєKPŸŸ,ŸЄК›ЄRžњЄМбЗ'У”ЖрвP!‡Ÿ™Ÿ//ЯŸ$ЏH?Џl~ІH›qЫ}EУеЎЏљ<ПNП`ПAŸSŸeŸw™КSРПвПфПіПЯЯ,Я>ЯPЯbЯtЯ†Я˜ЯЊЯМЯЮЯрЯђЯпп(п:пLп^пpп‚п‚OуЁпГпХпзпщпћп
яя1яCяUяgя€Ž№b{Џ.ВНяЯясяѓяџџ)џ;џMџ_џx˜Щa€џ’џЄџЖџШџкџьџўџ"4FX‰я›я­я ВФжшњ0Bz–Яas…—ЉЛЭпё//'/9/K/]/o//“/Ѕ/З/Щ/л/э/џ/?#?z–уaB?T?f?x?Š?œ?Ў?Р?в?ф?і?OOU§b§b7OжQлV.e_OqOƒO•OЇOЙOЫOнOяO_w™k#_5_G_Y_k_}__Ё_Г_0Х_з_щ_ћ_UlЄŠŒAoSoeowo‰o›o­oПoбoуox˜a(:L^p‚”ІИЪм
cяwo–…!3EWi{ŸБУйІВцј
MINUNCERTFALL   0
ŸŸ.Ÿ@ŸRŸdŸvŸˆŸšŸЌŸОŸk}ЏЏ*Џ<Џ€NЏ`ЏrЏ„Џ–ЏЈЏ“еУЏеЏчЏљЏПП/ПAПSПeПwП‰П›П
JRISEE  0
fЖПчŸкПьПўПЯ"Я4ЯFЯXЯjЯ|ЯŽЯв”ЇЯЙЯЫЯнЯяЯпп%п7пIп[пmппюsБЗў@ібЕФпжпшпњпяя0яBяTяfяQ…я—яЉяЛяЭяпяёяџџ'џ9џKџ]џЬŸџ№ŸЅџЗџЩџлџэџџџ #5G29fxŠœЎРвфі,>B'Cо–дkэћ# Чbсz„@Дп.`‹c­П.`Ыня/%b /Ї=QN3L/^/p/‚/”/І/И/Ъ/м/ю/?? От7?<цNШm??„?—г™?Пэ@€З?Щ?л?э?џ?O#L3OEOWOiO{OOŸOБO@УOеOчOљO?Žж'_lN2T4ы\9S_˜БГz_ПбА˜_Њ_М_Ю_ рUБВэ_t}нo&o8oJo\ono€o’oЄoЖoШoкo_V“3
ЗŠВе?„?cЈ?‡™ЋНЯсѓyx‘'9K]o“ЅЗЩлсS—п’ІKUКп(Ÿ LŸФpŸ‚Ÿ”Ÿ/ИŸ0/ŸСqфŸіŸЏЏ,Џ>ЏPЏbЏtЏ†Џ˜ЏЊЏМЏЮЏрЏђЏПП(П:ПLП^П@pП‚Пн‡žП‹Z€с;дЩМйПСдѓДгйЛ>еЯ.Я@Я*вб[ЯmСаŸƒЯпЩп…3єФOŸшДNkпжŒ
JFALLE  0
т‘цў‡ШФспP27ЧqирЌ?зящцўпƒ?Й\.—ЫхПт? рюАяQAqиДущцўДт$ќ$ќ$ї'п9пKп]кHŠфОщфМЉЗДтЙіCўjPШjџ|џxд•“ИaIмW™у&V03EЇѓП0<њїўџЙkPDФуџѕџ“Иˆ“ИЂњB!ЃпЕпт        Vс№
чпљпяя/яAяSяeяwя‰я›я­яПябяћѕяџџ+џ=џOџaџƒ…џ—џЉџЛџЭџпџ•/09K]o?!?ЅШ%§”ы№Acrobaџt PDFWriwterо§юёп$ъ
GRID    1       1       1       2       2       16711680        0        0
wodx)3EWi{§<ы№#џwinspoџolAcrobџat PDFWrџiterLPT1:мџUFы№џђ№ы№DшѓfњєёђџџъёP
рћіёъёh> ы№/Tы№6DЊъёы№’ујƒUmAшѓ@›
Р?­лПIшѓ№?ПСYзщћ{џвъёЗъёO•1@цѕ3EEbOУe„ZЁцѕ
ENDGRID -1
•ы№Hu§щђ ѓ№ящђџ˜џP№р№(:њџџŒˆџџ№{ŒW‹џ№_€qƒ•ЇЙЫеŒтџ§Qы№Rectanџgle. wiџth text џand connўѓ№ion poiџnts. Canџ be streџtched toўy dimenss.mbујшПшѓр?єєўрПшДNoшПр?kш?рћєР4
№ћє№П•Hы№џђ№ыєы№DBы№ы№іё№ѓ
яє$#        фї?hчє-(>Tы№пќT9   ›ујѕ‰›UAшѓј?ЇА№КЏшЏр?Q6 Ял‰uŒ` 6еўьuі№і        mB>іё0Œ0XA0ъё(2s@sJLsT„>ъёЁі5
‰€LO@ўЃ‰ъё{Ё‰§ђ№пўф5Аџ`7Copyrџight 199џ9 Visio џCorporatџion.  Alћl      "s resџerved.ўэ‰` _Sbџa.chm!#22430ў BЈdЌ9     l>ы№0>Uddтљ!!€Ф‰ујіёЌŠTЁ
DIRECTION       input
ќ<hЋђbЪ ў
2Є61
MASTERCLOCK     None
g,s72‹Э4Ё?`b?ўM1EY?Фr?9€1M1| ;6З==з5P2ш?;z‰rA
Clock   Unclocked
РўIB=OCРўq‰…,^пќ35Д/™ТујVЁ:вШЫNќьAьCї=ЎA КKЗр?гOхIЛ=ь"3їЎAаКOФ<_хOїOKЎAEŒ[6:_ L_Ij_|U|\_ooУ_ўAnеРы№Hы№lы№&ї'щђћnѕы№џН!џРOyŽa§§єGEгЏ-szьтљчєFўы№фЌїƒЛЂы№ж#ы№ЏАї%Jы№Bћ
EdgeLevel       neg
ы№ЏїoЊ[atkЪЎы№@+ы№|kЫђ3aђёБї5ў\ў№ж•ы№ы№ѓєщђ&мёUlы№4ы№,чєчє-шѓ@шѓщђщъёы№ф€Пы№AJ-м3
Set     Not Used
7"Aљі&Ulы№4ы№,чєћє-шѓ@шѓщђщъёы№d‚ПJы№A
Clear   Not Used
-|3P7њѕUzы№ы№Zпќчє§@ы№,>ы№Rмџ0B*
ФV;Hы№<мџ(
ClockEnable     Not Used
Hы№<мџ(
ActiveLowSetClear       True
Uzы№ы№Zпќчє§Eы№tС
ы№Rмџ0B>
‚ЮUFы№џђ№ы№Dшѓfњєёђџџъёа
рћіёъёh-Tы№пќUдUцѕ’уј”ы№[U@шѓ@—?шѓлР?ЉПIшѓ№?`Лd
мюїbu‘ЉўoqЈYkчєЈујQ‘§hђ№u23uъќі№‘`        Cџonnectorїў
AsyncSetClear   True
‘`ў–
ActiveLowClockEnable    True
œe‘1Crw
VhdlType        std_logic
ƒујЉUы№HыЄъё ѓ№–ўяђџ^€џџџПџўџќњј№єџїєїїЕŸ  €-џ}|5pїџ`Iоџџ`V?џпџ}ƒџ`Сџџјƒx‹їџїaŠџџѓ833џŠџџƒџ‰џџѓџџџя‰џ‡Ž‡‡џƒџљо…џ Ÿ™џЊŸџ™љ]ЉџŽЗ№ўТџ№ƒ3Яƒƒ3‚Й†“Уu…Ыџ‚ŸЉОпџ3“3?,№      ї™?№џŸ№ўG‡xpџџ№хx“^мŠџ№ƒ‹џ&яŒџŒџ
ƒДџ§Cы№This cџonnectorџ automatџically rџoutes beџtween thПe shapi
tіѕs.•Hы№џђ№ыєы№DŠы№ы№щђђё
@яє#        фї      іё=hчєЕы№8Tы№ пќYY9    BTы№#ы№›ујF      oU@шѓј?З
е№ШПЗрПрПэP6
VerilogType     wire
‰u
SystemCType     sc_logic
я`uфbџ€A@]ўќu
  Ѕ‰.(#DB˜     Ѓ˜‰uuŒ`hр?\еhr|u”і№†‰эV‰aкчЧŽ‰Жа@-№?b—l’;'bE-ho'$—y(œ‰ъёБ
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
тџ2rЧqЧсп?@ŸєIЭ Я?кУ$бЫ%П?э
StateEquation   Hex(Inc(0,2,5))
@Љ§ƒўі"ЗўU*5L -яbrъёРŒ     ^vœvЕі"(2u€I.і"q28˜švі"uh9 РBdД&</MSЃъёz
HighVoltageThreshold    5
#§ђ№ті1ўћ45|`џVis_SE.cПhm!#20)@љў`7Copџyright 1я999 @io џCorporatџion.  Alћl ;Bs resџerved.ўёЄ•ъё4UјŒЂ#ў1#ЇЇъё№7)A,@„™ъёA+Х4о§j'vQ8l>$UdvтљіёEђ„       ‰\ДŠbў4
LowVoltageThreshold     0
*д’1Bњ$b–‘24ƒR‹Ÿ(@][аv[D ‡ZЫQi‰@       ќaч59        Ь9”уј§3ЫO'2Х"qМ?.g;2шGеРы№Hы№lы№sw'щђ‘*щђ§џЎO`ЩѕЉы№ў­увEW
MSB     0
)їтљчєFы№џмЙї нЮы№ж#ы№|МзїзK7B§
LSB     0
ы№$ОїGGы№dъёUoBъё@мџёѓk€Эў№ж•–ы№(ы№bмџсњъы№чєы№ЌїПZ—ы№SћЩы№ЉїёК+ы№B?ы№4ъ9‘@0ы№RDОы№фЊїл@.ќS"Йї"'‰/ъё ы№мџUы№џђ№Ђы№Pшѓxњєёђмџ№Пђёoџџ@#ї?ЈтљіёъёFчєы№DNы№Teъёёђ@yŠ
рћaъёhчєѕы№$ы№TBы№пќРРцѕХз’ујєНUIЖшѓ@
isFallingEdgeSensitive  False
@2Р5?П
isRisingEdgeSensitive   True
№?.у  №K]oыїзХў%`Н
яРuОHать›ьъё‘@цѕ-№?#-(ŽыЯНѓюлХuѓ` FцѕўV"у`"f"“uРp)Р№ъёэя5$Р+%Х&аВЯ.ис.Х(sU1х 6t'?ы["gьЫШШ[?Є'ЩујЅPяŒ4"Дџ&ЎНTш§›ќђ№ћХ`
Blaџck & WhiŸteўn№я ХŠ1<'ъёЉујрА1Eq&ы0ўП3Color џSchemes.п..ў1Х`џ'Set thek cDBsJB fF@џthis doc_umentR@
DrawAnalog      0
Хužўс2`
CJЗ€Q ўeН"
BooleanEquation
ы№ ХˆпќДAДAцѕIы№;AНaы№Љ   ы№†AЬ
ы№Ђы№ы№V!ы№ыєО1ЫŒ4с1
NegTolerance    0
ы№ы№ьь1ѓf!
PosTolerance    0
q!!ы№ƒуј†AяHщђgQ%sTѓ~WІ%sTь1~WуsTыA~Wь5sTР~WыAoXa~WАsTїA~WїAoXуA~WуAoXћA~WћAoX†A~W†AoXQ~WQoXЯ~WЯsTQ~WQoXQ~WQoXQ~WQoXV!~WV!oX~WoXQ~WQoX#Q~W#QoX'Q~W'QoXюё~WюёoXf!~Wf!oXО1~WО1oXЫ~WX5sT7Q~W7QoX;A~W;AoX1~W1oXс1~Wс1oXCQ~WCQoXGQ~WGQoXKQ~WKQoXq!~Wq%sTcQ~WcQoXДA~Sx1Šь5“ХPуE;Aя1%ы№e‘ѓ,ы№r‘"РCQCQь1KQKQaгEћAс1с1'QGQGQО1XuЦŸрћoшDн?я?ујЈујЇ@IjЗ!А5ќРќ#QТ0       Conne/ctor„DŒARЂ
UserSpecifiedSizeRatio  1
XЊ~Qя(eiў‘6c%ђёыAьˆщ6eѓИў‘(Х;uцѕў‘ў™аЄѓўцѕE)€Е@5$њ+$€CЕ6CД€CЕє?*Ёч‡„џ„3Д х…†Ѓ(. ‡™ИРЗюёџbќbBbwzgP@ў‡рНG2ЧqљАЌё?јП
VerilogCode
ЦІ#?Й\._—Ыхт?q рђ№CяAщV!ёЁ%<Х4Iрћј4№?ЙЏК1'l№a0Х‚€X=aАы     Рў‘ыA‰„д’БŠџ'Q/щђ‹Ѓ(ћЪSЗеу"пXДг@ў•ћЯ[кќUpпхіqН€ыAr‘ШЏur&љXСЯ™ујšС8ЗfЖ/ъёAў›љб%ыTЖє4//юІ%яXКgя6чу‹ъч_яДяў•‹яряђяR№ў•V!ШцѕCPU/DSPiшŸњŸЏх”уј#Оя'Џ28ŽуЧ№Ш2B€Бj^sџ…џy8•y8А
VHDLCode
Д6&03Bѓ!ПšСіъ2х*ё~Q’ХŽЌАІ%ЋЏНЏщe€яёхЏїЏ     ПФЪ(Пе
Њ^ДРfЖё+%р+%сЯ'qПƒП•ПЅ&7QЮTЛП‚? ЄПXО1y#2у^Q?ЯTІ%§lЯ)сЁ№QІ%фєntegџer EX
PROPS!
Pi?pelinejђАAРрџђџ—џЉџЛљ2UХЮїŽС‚šЯЌЯўаЯтЯппп79пd?Cbп??Ÿ6пЁпжиОпапў/€єпи:Oяїя@я9аTOrяOLFЈOНяи?›O№OџKN%_7[›Qz‘sdщЕ”ІИЪмpюjT@@rAїџџјLДРу?@шyžчyžїRe%г[eчYх+vчf\‘Чa5AАfŸБУечщЕ 4/Syz‘2)
UћGPRs`/r/„/–/Ј/К/Ь/о/№/&O?&?д?J?]Xbs?†ZhЂ?gŠТ‹Я?с?ѓ?OO)O;OffVOt_zOЕt`†ŸГOљƒdn]kЯŸљƒЊbЙg4ЙhЊb0Џ_оŽЧŸйŸI_hlƒЏ|]‚”_xБ_У_е_ч_љ_oo/o$Np?X_wo‰o›o(­`БДbЦФoжoшoњoч }=O
Б№]‘2)œqB(Loadџ/Store
!
UnitˆšЌОатєNŸ<NќrФпn?Ј’?ЬЖ?№BяŸ&Ÿ8Ÿп\ŸR_€Ÿ€вЏЄ™ѓš•Oѓя$ЉЯDЃTџПOбO/џѕO‡џ_Ћџ™ЏŒџсџѓџРсЄБ.!№ЌŒЏЯџџЊa|
ЎяДхGПYПkПВd~Б†НEаД–PЅОѕж,Ц,P-DяTћ!  Иˆэ-§СuJ `u
ўQфbuюup`uV€–ырў"§С_O€™rXСTOŠZ—d_Ј–§Сu. `sРЛГFХuepаХТbвђТвwШmў       ЅН ЅЗ‡$OігјїK"їZ/l%mђв˜'d-Ј'Ђ/l )JpДcяс'€Ne@z3rл"с/ђѓ.…ƒј3д06/аi­ЄУ-‚БРЎ€тБЩѕюП$ЈЯР]бщK!mдJЁxйДгМ”ЈпUОй*”вџВфЦЬЂаў`хйKOЉСў№Ё„е№Џ8И
ПП1ПCПМАЮyП‹ПИƒ€іРЕњ.ЎИУ0EPхРИESевПІ—qёПЎ€ Я2ЯDЯVЯhЯ|ˆй•ЯЇЯ!eєeбХЩv{Exception‡пп$п6пHпZпlп~пДяЂпДпbяип0ќпя<^1я;z–{^яpя‚я”яІяИя@Ъямялџ<AWеPкŸ}QYKVЄРџ­—ьЭŽ!Ÿ=0RdvˆšбOуOѕOтєЖ'*РљРД€ѓe€
у0љПCUgy@‹ЏСгхˆ‘Hќ1Ж*Ж_zDІЅЕ,(K#1Ж‰З0Зn$ŠПœО1ЖбЗН@ЗлПl -???Q?c9z_ЭsЁ?Г?Х?з?щ?8O
OO1O&WVЈшЯjG‰Ÿ›Ÿ­ŸПŸбŸуŸѕŸЏЏ+Џ7#!а9VhЈжФг0BЏŸЏБЏУЏеЏчЏљЏППAбќъц/cv	ўн='њH&ъцBїщчn$CџUўъцŠїV§љч@”џи'ЪQ5дії/гџ?Я'Я9Яd?v?ѕц‘3 ?Я‘ЯЃЯЕЯЧЯйЯ@ыЯ§ЯaxhЈ
7з	uO‡Gf•O˜ЙOЫOЊпМпј_%[чyžчy^xЕB_T_f_TЯŠ_œ_Ў_Р_в_ф_kbƒє/Рo9f7ipaGhInяstucWa Unit\ono€o’oЄoЖoШoкoьo""аF(Oj|Ž ВФ1Oшњё?0BTrŸx‰d}O`Ÿ]_y’oдК_џџЛЭ“_ёы_Ÿo9Ÿ№_EoWok‘рDпVпhпzпŒпУречдпцпQЂ@@ЅxЕ+&OVVЈ,я>яPяbяtя†я˜яЊяМяЮя'ЗГa5Й\†JПљr“…€‚Е\†Д‡[‡`єЕЧŽ\†ќ‡Шk‡ŸЯ.@GЯdkЯЂДЦиъќK VJxЏ7зЩpЖoШoкoьoўo"4јFXњј@@ќІ‹Пяh4Гп”~љ1ЊМЮрђ(:кэlЁющЦuџц…яЋ‡ЦmЧЧ`єnЯ€ЮЦЕЧЭ$ЧПЯ<ŸNŸ`ŸrŸ„Ÿ–ŸЈŸКŸЬŸоŸ№ŸЏQЏ&ЏVD4ОЬп\iбpЏ‚Џ”ЏІЏИЏРЪЏмЏюЏПП}t<ЯЏѓ<ЯГ+ 89!У	дhэуФMП_ПqПƒП€•ПЇПЙПЫПнПяПЯ!iб`‰Юі.Ъдэ&!їžgy~@€hУЮі&Эї‹Ф'9@Юіn:
нїx­Р)a2йp$Q!Ж€;№@z3HёБ€ЗЩјЯ
SIGNAL  iwb_ADR_O
пДх(P'аc+м+;п­Wнђ(QSgRпdпvпˆпšпЌпОпаптпeqэюёbЇ6№(я:яLя^яpя‚я”яІяИяЌЪяЦAЄš„€Р
бmРС”xž9џ/џAџSџeџwџ‰џ›џ­џMŒ`J!`‰ѓ6.Яfuˆ>7­…ѓ6KGђ7‹ФLO^Nѓ6“G_MGOѕЯп+пHOп†˜ЊМЮр///yi9Њ_@'K/]/o//“/Ѕ/ З/Щ/л/э/hsD9E-ь”tРл>Ы”ІO?a?s?…?—?Љ?Л?Э?п?a`‰ЌvO–V
DIRECTION       output
Рm&FЧ`­…Ќv‡Ћw‹ФŽЌvL‡ЛwVгOхOїO	__-_?_Q_c_u_‡_™_ш_Н_ЯZбhcŸ@'oo(o:o€Lo^opo‚o”oІo3 \рp4Вџз?zЄч;Н€Ё§Пїo    -? Qcu‡™М‘ЩeЖХoЏŠЅwЁ˜–gФeЖ НЗdЗ‹ФОПаОeЖЧ@бНtЗЯŒžА‰1CТдцј
RADIX   hex
ŸŸ.Ÿ@ŸRŸЁŸvŸёй‰ЉпВ—ІrСŸгŸхŸїŸTЇЏ%Џ07ЏIЏ[Џеw№yЏ‹ЏЏџСЏгЏхЏїЏ     ПП-П?ПQПыбвљіX~П(щ„УР
GRID    0        1       0        1       0        16711680        0        0
&6?cлV?щ;x>%‘?Ѓ?Ў—эџе%>м?H?Oэ€џ!O3?>OЊ?ъ*ў7Data MMџU
ENDGRID -1
& CacheQЙрM_qƒ•@ЇЙЫня=афd€@в?/-,L/ўяž{шAАyfˆ/š/Ќ/О/а/т/є/??vOˆOšO`?Х?„?щ?ѓoК?Ь?1O;UOO&Oƒяo\OРЙвoнIЖO:In+snзA мIНŸћOšпЌпЏаптпєпяя*fємDхЌЕьDш<œ^рЪ‰mяя‘яЃяЕяЧяйяыяы_VМ†iЙ/І7џKŸ@ЖЕ/І‡Ї.ЇлДˆЏšЎ/ІЯЇ›­>ЇйЏўџ"4FXj|Ž ВшНzT˜цПkз[dŽŒc?СŸ…aЅrУ™Лeэхаї	ŸŒj(™EНy€іџ?@b†a†§ъDхё?@У0tа$vсее?QЪЩ!GВХЕTПФГ†WŒ’P8…УЕzдЄIИЯ‘XЖХГўТRQЊСХЕ<ЋУ\ХЭпј-Г•prЯгџџ?СV‰7Sy?stemiДДеAЋЧ™б…ХЕAб”КШ|ДЪЫ'2U€тХ-ВHБlБRХbotoЮߘoЊhСЙ?СбП@вўЙўы
аћLЕ%ўе€ѓ•ўю]ћ…ўяМЦqефис,ЋЧЦнЙѕРяЄУ™КШс’WаеОјЈгAбќёХЕ
жРP"4ёмk:LЕі€bЗ•Žуѕ‚щO™
__1_C_U_g_ќy_‹_?@ф8Žу8ŽыИUЎ_Р_в_ЏЏ+ЁO3Љs&%oJпIo–яЈяКяЬяояЕožџ%7ёПb!'ЯY?WiЮЁ?ђБУщ?U?љO8?COЏ?SŒя сWA!SeЎ‰›ЯЏЯаСЯŸ,Ÿ>”	 у8џц?@+R*'чјSšЋSf™Ld‡Њ@ПzŸŒŸžŸАŸТŸдŸцŸјŸN/`/$Т3ЉŒfФHЏж	"ЈPNœц?€€ЅŒfфg‹gЅЄхoїnŒf,wјm›g6П!П3И?Вc5HПZПlП~ППЂПДПЯиП“OќПеЋ^Cћ3НI	ЪKъB,aCЯч$,a`Яъ„Я–ЯL_P^_ы/оЯ&H
mЅњи$fe
а)п ‡+В"‚f$QХ‘м–]пoпп“пЅпЗме…€`ЏрпЉ,aНIБqЭHMAC Unit#я5яGяYяkя}яяЭ/п/ё/?щя—џ
џП1џCџeџ—ПїЖ’џЄџЖџШџ€кџьџўџ7Я4ЌrdтПџЗЯЩШж’Фрж’
п‚ЃЮ–пР0ЯѓЯ|пЃЮБп=*‘еыOт_!_\ˆ>_`%Ÿ7Ÿt_†_œu•mѕѕд@вѕн@ТФX-DTћ!	к_ь_ў_o"o4oFoXo€joc-Šсw)СіЅoжР
еэxечнeСіРїt,Сіa-
@аїkl~x‚ЅЗЩлэџ#5GYЖfхщxћ3 сќ‘я.я@яRяdяvяˆяPšяЌяОяуќ§ѕд€Рѕн€Аљяџџ/џAџSџeџwџ‰џ›џ­џƒќ‘iz6кџЗe€дц–%§мfz6в7y7tг?х>z6Gц=‰7$OЁГХзщћ
1CUgЖ‹Ё:Ÿ(1_Ч!ечљ/€///A/S/e/w/Њ9mљѕд їѕн чВ.љtЁШ/к/ь/ў/?"?4?F?X?Б§ЫQХљ3v“?Ѕ?u…Eg@3v‹w2w№4Œž~3vгwŸ}BwнZOlO~OOЂOДOЦOиOъOќO_ _o_D_в‰WiъЧ‹__Џ_С_г_х_ї_	oo-o^г[ьієРіє@ЋЮ@бВ/Ф/oЁoГoХo`зoщoћo
C‘аХљьІLж†­АЇьІDЗыЇ№4EПWОьІŒЗXНћЇ–П%7I[m‘ЃЕЧй(Ÿ§ЈЃЯЧDŸVŸhŸzŸŒŸžŸАŸPТŸдŸцŸфдіѕњѕе№ѕорko}oHЏZЏlЏР~ЏЏЂЏДЏЦЏиЏ ќСХљЅцПЏпђжХИж€;ЗЅц§чЄч№4ўяўЅцEї§ДчOџЬПоП№ПЯЯ&Я8ЯJЯ\ЯnЯ€Я€’ЯсЯЖЯD
Clock
Ъи\Ч§Яп!п3пEпWпiп{ппŸпГ$        ьчЃ|Т$Џ6Џяя%я7яIя0[яmяя‘яЕ~9˜^&ОяHH
EdgeLevel       neg
rъя€Дћ3^&]'№4З/Щ.^&ў'Ъ-m'?…џ—џЉџЛџЭџпџёџ'9€KšoШЪƒO9—ЖШкьў"4FXjјHD‚”ІИЪмю//$/6/H//qnA7yfw/‰/3UЗзј?„ufoggєpo‚nfЗgƒm&gСo>?P?b?t?†?˜?Њ?М?Ю?р?ђ?OSO(O:OШ3oOO“OЅOЗOЩOлOэOџO_jтх;_M___q_ƒ_•_Ї_Й_Ы_н_я_oЁс'№Ља–0oBoтяђgfа–(ЇЯ—є)Џ;Ўа–pЇ<­п—zЏїo      -?Qcu‡™ЋНсѓПьЭЉ‘+=Oas…—АЉЛЭђ ЄЅќэџŸ#Ÿ5ŸGŸYŸkŸ}ŸŸЁŸГŸšшbбЉщ‰жdщŸsЕШйцЅХ€Ч€іх‰жсзˆзєтпєо‰ж)чѕн˜з3яАЏТЏдЏцЏјЏ
Set     Not Used
ПП.П@ПRПdП@vПХПšПЌП:џЅ
!сПѓПЯЯ)Я;ЯMЯ_ЯqЯўƒЯ@PуAКjјџт?@Txы!џiё?@‚W†Ї€[щЏШaйСШ|?Bзи.љ‡сзЯщЯћЯ
пп1пCпUпgпРN-™ёb)BЂп,№Нџѕœу?@OџсmЌ‡$ц?@?ф8Žу8юUЉтРїgfBšAд$›­BтЎQьiя{яяŸяБяУяеячяљяџџ/џ~џSџс$aљ/їРžџАџТџдџцџјџ№
Clear   Not Used
.‡ЬrЧqЧwч,53PƒŽ#ЎЩCРЩ–9‘ЃЕЧйы§!lyAi ћF[х ‚SgьGhe@ћFSWњGdT_f^ћF€›Wg]
ClockEnable     Not Used
WЅ_"/4/F)S!CX/j/|/Ž/ /В/Ф/ж/ш/7??šdNВoѓU*щђы№ы№ы№Uы№ы№ы№ы№"ы№%ы№,м№Ulы№4ы№,чє
ActiveLowSetClear       True
ы№Еы№шѓ@шѓЄщђъёы№ќџ€и6$Њы№C-Ф3ќ7ы№AщђU2ы№ы№пќчє§@ы№$€77Eы№RHы№<мџ(
AsyncSetClear   True
U2ы№ы№пќчє§Eы№l€f77
ы№RUlы№ы№Lујы№ѕчєы№DШїџ­їгЩы№œЦїпЧ6ы№@ѕ?ы№Д%G7ны№RDы№ЌЧїs;U$ы№мџ
ActiveLowClockEnable    True
#ы№§чєПxЇxsџ[ё№ъёя№"4FрXj|ŽъёКџј“ЙхіC:\Prџogram Fiџles\Visiџo\Solutiџons\Blocпk Diaл\Bџasic Shaџpes.vss(ы№§чєбxЙxsџ[ё№я№        #5GрYk}ы№Кџј“ЙхіC:\Prџogram Fiџles\Visiџo\Solutiћonф Extrџas\Bordeџrs and Tћitт.vssе`ы№(ы№,ы№є“юмџшѓъё*ўы№T7ю7ы~ы№C!p?l8/ъё§ёU1ы№џђ№ы№(шѓы№мџіёіёцѕUы№ы№O"D&aU=шѓђёQџџJf        рћ)ъёh"Tы№y‡ъёМуј+UК
VhdlType        std_logic
ц"_Щ…&aQ-З
VerilogType     wire
-H*9(TYяєkЉPŒžАщђ›ујEQю№/,GuideTheDocPage-1ѕы№ы№Gestџure FormatVisio 90ConnectorVisio 00Visio 01Visio 02Visio 03Visio 10Visio 11Visio 12Visio 13Visio 20Visio 21Visio 22Visio 23Visio 50Visio 51Visio 52Visio 53Visio 70Visio 80BasicBasic ShadowRectangleSchemeNameRectangle.20Rectangle.4Rectangle.23Rectangle.6Rectangle.9Rectangle.2ѕы№ы№Dynaџmic conn?ectorRectangle.3пы№о— уј-ъё3ўы№ьƒјЩ9Ћ
SystemCType     sc_logic
ы№Eќгњ„јоJ-
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
;щђёG}4;:
UL;cd;Uc
StateEquation   Hex(Inc(0,2,5))
|;)c
HighVoltageThreshold    5
”;U6c
LowVoltageThreshold     0
Ќ;Cc
LSB     0
Ф;UPc
MSB     31
м;]c
SignalActionType        0
є;}jc
isFallingEdgeSensitive  False
…јwc
isRisingEdgeSensitive   True
U$„c
DrawAnalog      0
<‘c
BooleanEquation
UTžc
NegTolerance    0
lЋc
PosTolerance    0
U„Иc
UserSpecifiedSizeRatio  1
œХc
VerilogCode
UДвc
VHDLCode
Ьпc
VhdlMapping     DefaultVhdlMapping
Uфьc
PROPS!
ќљc
E0      V       -1      -1              1       0        DR      0
П†ј;        $JЧЫЧ!Ы*xTЧ/Ы?ЧU>н„ЧOЫcЊЧ_нДЧp%*ЬВЧ€Ыя№AдЊЧ„[*мЧˆ%*єЊЧ˜[*ќЧœ[*Џ‡ј %*Б АЊЫU<Б Ы[*DЊБ Я[*LБ г[*TЊБ з[*\Б л[*dБ п%&ъёыёы№ї№Њ]"ы№ы№ы№"ы№ ы№0ы№fPx!(!ры№У*ы№ы№ы№ы№ђёЅы№ы№Ъ!ы№Jы№ы№ы№њё!ы№Ѕ"ы№#ы№%ы№&Њы№'ы№(ы№)ы№*
E1      X       3125    3125            1       0        DR      0
ы№+ы№,м№U^хіы№ы№ы№Uы№ы№    ы№
E2      V       3126    3126    A0      1       0        DR      0
ы№Uы№ы№
ы№ы№Uы№ы№ы№ы№Uы№ы№ы№ы№ы№ы№м№Ulы№4ы№,чєы№Еы№шѓ@шѓЄщђъёяёƒо=Kы№ѕC-$3)>ы№AщђUlы№4ы№,чємџшнўўёўѕы№€Пt>
E3      X       3750    3750            1       0        DR      0
ы№AJ-3~7ўёAщђ_ы№ќпќмџ*<Nчє@ўы№Œ‚/>Eы№RVŠœЎ№Рвфglq€q6uHы№<мџ(
E4      V       13125   13125     A0    1       0        DR      0
Hы№<мџ(
E5      X       13625   13625           1       0        DR      0
_ы№ќпќмџ*<NчєEўы№д‚ќ>
ы№RVŠœЎ№РвфgДq        ?r ы№мџ&AM3'AM3(PPT)PPT1_(ы№я№*ујы№њљ'9K]o“ЅЗЩлэџ#5GYk}ЁГХзщћ
//1/C/U/g/y/ш‹//рћ/ы№\јПc?
ы№AЊН"tУ pЧ*ŒУ }ЊЧ*ЄУ ŠЧ Ы"&ы№'ыёы№)Ќ {†ы№zѓ№œцѕїѓы№
E6      V       23125   23125     A4    1       0        DR      0
*ы№   ы№gѓ№"мџ4pFXпќїј„ќшѓ(S—›0џт@(i^qvЌЏА2Ьђ№^z     №Jїхічє}ы№$Qї:Ўы№Rы№ЄџЁT
E7      X       23625   23625           1       0        DR      0
дџЊЏRїГы№uы№вћ&ы№ЌOї(ъѓ№!ы№B  ЬUї[Iѓ№Ч>ы№џl8Bѕ>Oы№9BЕNo5OgЈїЋf}$ы№єХї
E8      V       33125   33125     A8    1       0        DR      0
њ'ћЦї’7чSNфxјгхЗ)ы№yјы8<§1{ј'9ыЂ=џы№Dјюхі`2ы№|~јПя;яѓ№Vі”?	!‡јЖъrFDћŠјЙ, >!R=ы№ќO‹јZ, .ы№_,Œј˜, šony CustomerAC:\Program Files\Visio\Solutions\Block Diagram\Basic Diagram.vstфўџеЭеœ.“—+,љЎDеЭеœ.“—+,љЎ(ф@LXd
œд€мPagesMastersPage-1
E9      X       33625   33625           1       0        DR      0
RectangleDynamic connectorф ”0lx„€Œ_VPID_ALTERNATENAMES_PID_LINKBASEAф     ўџ
E10     V       43125   43125     A12   1       0        DR      0
џџџџРFMicrosoft Visio DrawingVISIO 6.0 ShapesVisio.Drawing.6є9Вqўџўџр…ŸђљOhЋ‘+'Гй0ф@Visio (TM) Drawing
E11     X       43750   43750           1       0        DR      0
ЕB„THї@AuRэxъёщђџџџƒџіђџѓћ№јё‰€ъё€ €џРРРцццџЭЭЭГГГяššš!€fџffMMM3џ33яџяяњњњ?мчќBa$ы№мџ
!
$ы№мџ
Uы№џђ№,ы№8шѓ@њєсњіёъёуј§ы№Tdџ Arialъ@чєNПWingdzsЊ@чєN@tMџonotype ЏSort+чє
њNtSymbol5Tы№?шѓа?ђџкъё шѓY@-1ы№џђ№ы№іёїїTўјJчєы№Dы№T1шѓђёEWPђёрћ-ъёhчєы№НTы№Tы№<апќŒŒцѕ‘U*ы№ы№ы№Uы№       ы№
SIGNAL  iwb_DAT_I
ы№ы№Uы№
ы№ы№“уј=/РUКпПbў
њbўщ…Иъё‰0zПЎGсz„?Ж@цѕП8‘HШ2!kWbU%Ѕ†МъёUВ
DIRECTION       input
€ь
‚+ŸЎ‡РъёйPы№L/^&œ9^$р? { ђ№яЁAшk^&Ž™,"™,™'%/v&ŽQ&Ц‚      
RADIX   hex
1 yрЙ
‚€‚ )‚ЎР? 2Њ

ЊJ1ЄШъёэ2?ё§k9лaUўBBHEHEHEUHEHEHEH@ ?В>з?щ:`2BBЊHEHEHEHEЊHEHEHEH@„$Ьъё%O9ЃаъёF7AOY@;
ЬA*sVsVЬAЇдgЄLTkYЗиъёї 1 WЭ_Wп_ќ_њ !`Г#•ku4l•b”6Pu`kђWŽ 4l
GRID    0        1       0        1       0        16711680        0        0
4lЅ•НмъёБ%Y№?ˆˆ:?-\
*Ѓ#!ю+|tKf*2|2|2|2wŠG)ОръёQUѓoˆІTMeEжttAПфъёв%_8BOTOfOxOŠOВ?Ф?ЌOш?њ7   РшъёмЛњuЛW+Р?ыаќŽиžђˆsU4‘х2–
ENDGRID -1
TŸ*<N`r„–HЂД„k!–ŽЌ)§†Ž0Ќ–ŽеPЌЌЌ Є3•ŽЇ
1’ьъёїмЏюЏрПП$П6Пуќ
nР[ЕiИРЛіё”|Г        фх”ујМЫЏi'04’UХP§iW?i?{4‚Lz№y‘2ї#ЩЖz“Њx•       x•
Clock
x•x•x
EdgeLevel       neg
Ѓ0–jМvПˆПŠуј•ујШВЗ^/ЫЦ!M3оТѓПjЦjЦ6DˆŒ/ž/А/ў$Q0pоФ?MdjЧ^cjЧŒ4ТBЬAk[Ж~ЯЯхіˆуј$YkU1%Л1ўпт@УэFЛе„-(‘ kp
йЛ   ѓ       .$–5-Bi`яЗBб#ошяЗ9)›F/Pџтљv/ˆ/п пО/u?@‡2tСrПœпœЯKЖSИЯ5мЯюЧ2ћЩŒ7сбxХ€эпЂя#я6@хhБ$MчюuLЕhБЪ        хеƒя•яЇяЙяЫяняяяџџ%џодŠе‘ї§ѓ)Й<щ€№Oх™U‡#Р5G‹˜:ём:ѓU27ЧqЩ Ќ?Ш/к&@мwџ‰ўк&Ѓє<<7сбHсщпєБУ1яOВQjСPфSсHЙQ›ywщHсAt/†/˜/YOВGТ$_щЅ4.Ыћb%FЂДЦ8ћqТ/д#?˜Cђ/Њ‰§Nм^мТqЄ€hшE!	@d)nм{” щrѕ1PБ1	@/ЋO0q•жt}Q„”ўnПњџЄК=ВЙkхЦБь…Љ{Ј…B'ФІЩ‚X/йPP\ьfцй2ѕ1ѕ1”Rе5P"”Q”Q[СO"P!ДЁq’[СŠrДЁДЁюrŠq€Šqг‚юqюqТЂггPБТЁТЁWт§a§a7бVтWсХе7бPБ$q$qZБ0r1qPБZБZБdБJrKqobdБdБХ2oaoaAPБС5TБ~rqPБсбй1W?Oрr?~??Ђ? ъќxХљ9/F
@@O$JљД]€”Aм7ЪкДIКHрЙq‡ƒаd˜Ep{y\O@fƒае_ч_љ_ЄКpИПЪПцЖсбЋaІИЂ–й1Ач<яNя`я†4F‰OdћЕ~‰аqŽЖGШ‰3qOшДNkуgLЂІ9њQзOыЏц$˜B_­XоєKPŸŸ,ŸЄК›ЄRžњЄМбЗ'У”ЖрвP!‡Ÿ™Ÿ//ЯŸ$ЏH?Џl~ІH›qЫ}EУеЎЏљ<ПNП`ПAŸSŸeŸw™КSРПвПфПіПЯЯ,Я>ЯPЯbЯtЯ†Я˜ЯЊЯМЯЮЯрЯђЯпп(п:пLп^пpп‚п‚OуЁпГпХпзпщпћп
яя1яCяUяgя€Ž№b{Џ.ВНяЯясяѓяџџ)џ;џMџ_џx˜Щa€џ’џЄџЖџШџкџьџўџ"4FX‰я›я­я ВФжшњ0Bz–Яas…—ЉЛЭпё//'/9/K/]/o//“/Ѕ/З/Щ/л/э/џ/?#?z–уaB?T?f?x?Š?œ?Ў?Р?в?ф?і?OOU§b§b7OжQлV.e_OqOƒO•OЇOЙOЫOнOяO_w™k#_5_G_Y_k_}__Ё_Г_0Х_з_щ_ћ_UlЄŠŒAoSoeowo‰o›o­oПoбoуox˜a(:L^p‚”ІИЪм
cяwo–…!3EWi{ŸБУйІВцј
Set     Not Used
ŸŸ.Ÿ@ŸRŸdŸvŸˆŸšŸЌŸОŸk}ЏЏ*Џ<Џ€NЏ`ЏrЏ„Џ–ЏЈЏ“еУЏеЏчЏљЏПП/ПAПSПeПwП‰П›П
Clear   Not Used
fЖПчŸкПьПўПЯ"Я4ЯFЯXЯjЯ|ЯŽЯв”ЇЯЙЯЫЯнЯяЯпп%п7пIп[пmппюsБЗў@ібЕФпжпшпњпяя0яBяTяfяQ…я—яЉяЛяЭяпяёяџџ'џ9џKџ]џЬŸџ№ŸЅџЗџЩџлџэџџџ #5G29fxŠœЎРвфі,>B'Cо–дkэћ# Чbсz„@Дп.`‹c­П.`Ыня/%b /Ї=QN3L/^/p/‚/”/І/И/Ъ/м/ю/?? От7?<цNШm??„?—г™?Пэ@€З?Щ?л?э?џ?O#L3OEOWOiO{OOŸOБO@УOеOчOљO?Žж'_lN2T4ы\9S_˜БГz_ПбА˜_Њ_М_Ю_ рUБВэ_t}нo&o8oJo\ono€o’oЄoЖoШoкo_V“3
ЗŠВе?„?cЈ?‡™ЋНЯсѓyx‘'9K]o“ЅЗЩлсS—п’ІKUКп(Ÿ LŸФpŸ‚Ÿ”Ÿ/ИŸ0/ŸСqфŸіŸЏЏ,Џ>ЏPЏbЏtЏ†Џ˜ЏЊЏМЏЮЏрЏђЏПП(П:ПLП^П@pП‚Пн‡žП‹Z€с;дЩМйПСдѓДгйЛ>еЯ.Я@Я*вб[ЯmСаŸƒЯпЩп…3єФOŸшДNkпжŒ
ClockEnable     Not Used
т‘цў‡ШФспP27ЧqирЌ?зящцўпƒ?Й\.—ЫхПт? рюАяQAqиДущцўДт$ќ$ќ$ї'п9пKп]кHŠфОщфМЉЗДтЙіCўjPШjџ|џxд•“ИaIмW™у&V03EЇѓП0<њїўџЙkPDФуџѕџ“Иˆ“ИЂњB!ЃпЕпт        Vс№
чпљпяя/яAяSяeяwя‰я›я­яПябяћѕяџџ+џ=џOџaџƒ…џ—џЉџЛџЭџпџ•/09K]o?!?ЅШ%§”ы№Acrobaџt PDFWriwterо§юёп$ъ
ActiveLowSetClear       True
wodx)3EWi{§<ы№#џwinspoџolAcrobџat PDFWrџiterLPT1:мџUFы№џђ№ы№DшѓfњєёђџџъёP
рћіёъёh> ы№/Tы№6DЊъёы№’ујƒUmAшѓ@›
Р?­лПIшѓ№?ПСYзщћ{џвъёЗъёO•1@цѕ3EEbOУe„ZЁцѕ
AsyncSetClear   True
•ы№Hu§щђ ѓ№ящђџ˜џP№р№(:њџџŒˆџџ№{ŒW‹џ№_€qƒ•ЇЙЫеŒтџ§Qы№Rectanџgle. wiџth text џand connўѓ№ion poiџnts. Canџ be streџtched toўy dimenss.mbујшПшѓр?єєўрПшДNoшПр?kш?рћєР4
№ћє№П•Hы№џђ№ыєы№DBы№ы№іё№ѓ
яє$#        фї?hчє-(>Tы№пќT9   ›ујѕ‰›UAшѓј?ЇА№КЏшЏр?Q6 Ял‰uŒ` 6еўьuі№і        mB>іё0Œ0XA0ъё(2s@sJLsT„>ъёЁі5
‰€LO@ўЃ‰ъё{Ё‰§ђ№пўф5Аџ`7Copyrџight 199џ9 Visio џCorporatџion.  Alћl      "s resџerved.ўэ‰` _Sbџa.chm!#22430ў BЈdЌ9     l>ы№0>Uddтљ!!€Ф‰ујіёЌŠTЁ
ActiveLowClockEnable    True
ќ<hЋђbЪ ў
2Є61
VhdlType        std_logic
g,s72‹Э4Ё?`b?ўM1EY?Фr?9€1M1| ;6З==з5P2ш?;z‰rA
VerilogType     wire
РўIB=OCРўq‰…,^пќ35Д/™ТујVЁ:вШЫNќьAьCї=ЎA КKЗр?гOхIЛ=ь"3їЎAаКOФ<_хOїOKЎAEŒ[6:_ L_Ij_|U|\_ooУ_ўAnеРы№Hы№lы№&ї'щђћnѕы№џН!џРOyŽa§§єGEгЏ-szьтљчєFўы№фЌїƒЛЂы№ж#ы№ЏАї%Jы№Bћ
SystemCType     sc_logic
ы№ЏїoЊ[atkЪЎы№@+ы№|kЫђ3aђёБї5ў\ў№ж•ы№ы№ѓєщђ&мёUlы№4ы№,чєчє-шѓ@шѓщђщъёы№ФўПы№AJ-М3
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
7"Aљі&Ulы№4ы№,чєћє-шѓ@шѓщђщъёы№$QПJы№A
StateEquation   Hex(Inc(0,2,5))
-43P7њѕUzы№ы№Zпќчє§@ы№Ly   >ы№Rмџ0BО
DљV;Hы№<мџ(
HighVoltageThreshold    5
Hы№<мџ(
LowVoltageThreshold     0
Uzы№ы№Zпќчє§Eы№”y     У
ы№Rмџ0B§џџџ‚ƒ„…†‡ˆ‰Š‹ŒŽ‘’“”•–—˜ўџџџšХœžŸ ЁЂЃЄЅІЇЈЉЊЋЌ­ЎЏАБВГДўџџџЖЗИЙКЛМНОПРСТУФўџџџ    ЧШЩЪЫЬЭЮЯабвгдежзийклмнопрстуфхцчшщъыьэюя№ёђѓєѕіїјљњћќ§ўџ 
љаUFы№џђ№ы№Dшѓfњєёђџџъёа
рћіёъёh-Tы№пќUдUцѕ’уј”ы№[U@шѓ@—?шѓлР?ЉПIшѓ№?`Лd
мюїbu‘ЉўoqЈYkчєЈујQ‘§hђ№u23uъќі№‘`  Cџonnectorїў
LSB     0
‘`ў–
MSB     31
œe‘1Crw
SignalActionType        0
ƒујЉUы№HыЄъё ѓ№–ўяђџ^€џџџПџўџќњј№єџїєїїЕŸ  €-џ}|5pїџ`Iоџџ`V?џпџ}ƒџ`Сџџјƒx‹їџїaŠџџѓ833џŠџџƒџ‰џџѓџџџя‰џ‡Ž‡‡џƒџљо…џ Ÿ™џЊŸџ™љ]ЉџŽЗ№ўТџ№ƒ3Яƒƒ3‚Й†“Уu…Ыџ‚ŸЉОпџ3“3?,№      ї™?№џŸ№ўG‡xpџџ№хx“^мŠџ№ƒ‹џ&яŒџŒџ
ƒДџ§Cы№This cџonnectorџ automatџically rџoutes beџtween thПe shapi
tіѕs.•Hы№џђ№ыєы№DŠы№ы№щђђё
@яє#        фї      іё=hчєЕы№8Tы№ пќYY9    BTы№#ы№›ујF      oU@шѓј?З
е№ШПЗрПрПэP6
isFallingEdgeSensitive  False
‰u
isRisingEdgeSensitive   False
я`uфbџ€A@]ўќu
  Ѕ‰.(#DB˜     Ѓ˜‰uuŒ`hр?\еhr|u”і№†‰эV‰aкчЧŽ‰Жа@-№?b—l’;'bE-ho'$—y(œ‰ъёБ
DrawAnalog      0
тџ2rЧqЧсп?@ŸєIЭ Я?кУ$бЫ%П?э
BooleanEquation
@Љ§ƒўі"ЗўU*5L -яbrъёРŒ     ^vœvЕі"(2u€I.і"q28˜švі"uh9 РBdД&</MSЃъёz
NegTolerance    0
#§ђ№ті1ўћ45|`џVis_SE.cПhm!#20)@љў`7Copџyright 1я999 @io џCorporatџion.  Alћl ;Bs resџerved.ўёЄ•ъё4UјŒЂ#ў1#ЇЇъё№7)A,@„™ъёA+Х4о§j'vQ8l>$UdvтљіёEђ„       ‰\ДŠbў4
PosTolerance    0
*д’1Bњ$b–‘24ƒR‹Ÿ(@][аv[D ‡ZЫQi‰@       ќaч59        Ь9”уј§3ЫO'2Х"qМ?.g;2шGеРы№Hы№lы№sw'щђ‘*щђ§џЎO`ЩѕЉы№ў­увEW
UserSpecifiedSizeRatio  1
)їтљчєFы№џмЙї
VerilogCode
нЮы№ж#ы№|МзїиK7B§
VHDLCode
ы№$ОїGGы№dъёVoBъё@мџёѓk€Эў№ж•–ы№(ы№bмџсњъы№чєы№ЌїПZ—ы№SћЩы№ЉїёК+ы№B?ы№4ъ9‘@2ы№RDОы№фЊїн@-ќS"Йї#'‰/ъё ы№мџUы№џђ№™ы№Pшѓxњєёђмџ№Пђёoџџ@#ї?ЈтљіёъёFчєы№DNы№Teъёёђ@yŠ
рћaъёhчєѕы№$ы№TBы№пќРРцѕХз’ујўНUIЖшѓ@
VhdlMapping     DefaultVhdlMapping
@2Р5?П
PROPS!
№?.у  №K]oыїзХў%jН
яРђЈDŠЇЅaЈЅUЅ       Ѕ
E0      X       11250   11250           1       0        DR      0
ЅЅ)›ьъё‘@цѕ-У№?--"(ыЯqНѓюХлuѓ` цѕўh`"уj"p"uРz)Р№ъёэяR?$Р5%Я&ай.иы.Я(sU1х6t1?ыe"gьЫШe?Ў'ЙЩујPяд–4"Д	(&НTшu§›ќђ№Хџ`
Black џ& Whiteўn№яХИ<;
E1      V       13125   13125   D0      1       0        DR      0
'ъёЉујК1)Eм{&ы0Щ3Cџolor Schџemes...ћў1Х`'Set the cNBэsTB fP@thiџs documesnt\@є`юы2`
MJ€QІ" ўeНы1ˆХpпќы1ы1ч РѓТaPжръєы№ ыєp!ИўЯ
ы№‚ы№ы№`!Ш1ЫHы№EA™1ƒујєUяHщђYQ%eTѓpWА%eTТpWуeTИpWі5eTРpWТaXapWАeTжpWжaXрpWрaXъpWъaXєpWєaXўpWўaXЯpWЯeT1QpW1QaX5QpW5QaX9QpW9QaX`!pW`!aXpWaXQpWQaXQpWQaXQpWQaXюёpWюёaXp!pWp!aXШ1pWШ1aXЫpWb5eTMQpWMQaXEApWEAaX™1pW™1aXы1pS‚1
E2      X       21250   21250           1       0        DR      0
і5ЧХP9QEAEAяcы№ЉИы№ŒЖТы№Уa{!{!ж!ы№нрc"ы№ъъ#ы№ФїєФФў'ˆы№‘=R(ы№‘1)ы№+‘Q*ы№8‘FЫ+ы№E‘MQнE†ы1oіDч?љ?ујЈPујБ@%IС!К5уќРQЬ0    ConnectorŽD    –AЪ’
E3      V       23125   23125   D4      1       0        DR      0
аšpQя§UiИА%ђёТ|ˆщАѓИИ‘Ш-u@цѕИv™эI!цѕE*Ћ@?$ј5%ЛЅpЛЅКЈЂ‘ч„      (XŽ3О х†­(.;‡јИ8ЗюёbbмbчzYPз@ў‡рG2ЧqqАЌ?pП‚Жшѓџ?Й\.—Ыхт5?{ рђ№яAщ`!D‘%<Х
E4      X       31250   31250           1       0        DR      0
Iрћј4s№?1ЏФ1l№a0Х‚b=aАы       HРИТ‰дЂ‘Š   (Q/щђ‹­(sЫЬІŠХуšЯŒУv•sЯгЪюU$шЯхіqНТ,ХЁu|&ыX9ЯOъёСАЏ!/ў›іё%}лЬІУІпLА%}паЋрпLуы”жзп,яv•яXяjя4Rьv•p"TцѕOpeџnRISC 1200i`ŸrŸ„Ÿ”№ујїЛя'2W8ŽуE№Ш2јЁpQ
E5      V       33125   33125   D8      1       0        DR      0
ХЏ­(#Џ5ЏGЏИ@]ЏoЏЏ<Ъ Џюђ5%*ў5%т5%юшЏ
E6      X       41250   41250           1       0        DR      0
'H1П&Д1QИ0RR‚Q‚’Пј]‚3ПEЗќbBbVДЄБXШ1d#ЊггЗПTА%+фПРJYЁ5QА%`!ашCPU/DSPштЈѓяџџ)џ;џMіСЅЯ$ЯщџHЯZЯп~ЯЯБЯ†/.кЯa/С&ппNи6пHп /lпСк:”пoяXdЌ/?€?’9EAR–
с2‘ЃїйЊ;`:1Ъ?м8Jџџћ3`Oџџ:щЊ;~6С?JOa‡‡ћ3еO}яm>ЏO;pQ˜ЅbќwѓzOpCw]A?ьѕЙџЫџнџXЂd”Ѕќљ№№Фж€ќ)ем)д'^Ф'WPП-DTћ!    (QЗˆ-uЙ``§uн`фb›uШ``uœ`Sdm€Jp@ўъZhкJh€3@ўјqTObJbUa’c_bXZbЃdЬтuY `аnЛpр?Рcu.аlЫil‡эb­ѓfUљYЕџnњg‘†KwђgFrђgUguѓf“w_}wgp+‘pј№ёи€мww€@z3YБ’жrмю~…јиЦ06аi­“Г       (VYЁЃЫајЁaЕ@E‘dм7r–ˆ†№”Ѕ‘$K`
E7      V       43125   43125   D12     1       0        DR      0
*G#_;/UQ)8‘œO—ЬуЧi5 ўx)§‹hŸDљ’єbџ—џ‘џ€ЃџЕџЗ_Щ_ыџ§џ“ Uѕ)р)х)аDVhzFц7Й–ЇІЅЗЩлэџTš4F”‘W1њ`ЭыDCache
E8      X       43750   43750           1       0        DR      0
8KB‚”ІИЪмю//H?6/     ЖQ/Ÿu/Уи=І›/žЯаbФ/yЯйЦё/??'?€9?K?%ЧЊ;OІ~?СOЇЏљ5МпCmЅ[=ІаŽп‘>wѕ[OІFІя(цO’к
яЈпх8œЈћ<œЈ_…о“я8_˜‘sŸС”	е”ŸІŸИŸЪŸмŸюŸЏЏ$­f=ЏOЏaЏsЏp чЁ‚RезЛзЛЏЭЏпЏёЏПП'ПWйEПWПрWёuЙљA…ЙMMUšПЌПОПаПтПєПЯЯ*Я`пNЯ`Яп„Я(/ЈЯКЯЬЯоЯ№ЯпІ/&п8пJпёV?єя’пџъпќпG? яuяDя˜?Ўпj
амopя‚яж?ш?[[ЭуrOхяТ?KOџч6џ~јSџeџwџ‰џ›џ­џПџбџХDяnќџ h)‚ГЏ„–ЈКЬо1ЕьУeЩuЙГ…ИPICSew‰›­Пбу?//Ч/=/Ьa/s/…/—/Љ/Л/Jп/ё/?•'?­OK?бOo95K‰?ќЎшoЮе\Ÿшг1яШ?;Ÿgяx>€COЖŸ(цЄOЖOѕŸ!њшOAїWЁ_‰Џ,_>_P_pb_З†_˜_ђ­_П_б_у_ѕ_a@кг{Ж€o0oBoTofoxoŠoT@tЅЯЗo3ЩWЁ4цkџTICK TIMERїo  -?Qcu‡НЋНkсCп);M_Спƒ•ЇпЫЏяAЏŸ%ŸbяIŸ?Нp“гяˆŸWяЌŸ{яаŸтŸ(џЏLџ*ЏpџоFXЏњGЮёxЏœЏЎЏРЏвЏ.яіЏП§П/ПAПSПeПa4ГђŽП ПВПФПжПшПњПTыѕ‹'ЯрЊЮёйiйcыfDEBUGnЯ€Я’ЯЄЯЖЯШЯкЯьЯўЯ4я"п4птпXпЕ/|пŽп пВпФпжп3?њпяя~/Bя”џfяИџŠяœяд?Ряиbі
p“EOџяЩ?#џэ?GџYџšO}џОOЁџтONІ       ЯџjЇ@Qяџr_%7I ?mі@?_ЙЫнxАхaГdf);M_qT]U§ožyє@QIЩЭPOWERMрђ//(/:/L/^/p/І?”/І/T?Ъ/(ю/??$?6?H?Іl?~??ёД?_и?*_ќ?OGŸ2OdoххИŸqO<Ÿ•O`ŸЙOЫO
ЏяO1Џ_UЏ7V
!
A_сїГЁa_хЏ…_—_Љ_Л_Ÿп_8Ї e“o)oфhЗqJo‚dUСrbTТrbYAлГыЖxoŠoœoЎoРoвoфoаЅ„ЯЃЩ№ГЁ2yзБаICac?he
8KBSew‰›­ПбуŸЧ=Гпas…—ЉЛ1япёŸ|п'ŸyЏKŸЏo™Уы‰Ÿуяj–ъ•{›Џ&џ­˜ыПщГъПшА)Љ{›CЏiџ­˜зϘѕ§џВѓpЏ‚Џмџ3ZДЏSWrдЏЄјЏ
SIGNAL  iwb_DAT_O
ПП.ПžяRПdПoˆПšПˆЌПОПаД–Ÿї іwoЯ"Я4ЯFЯXЯjЯTC/—Яb)r2y
ЦЬMMUоЯ№Япп&п8пJп\пnпЄя’пЄпRяШпl?ьпўпя"я4яFяъ?jя|яŽя5?ВюIџея[§ГšќГњяџ‹O0џьOTџ_!ЏОџ_X_Џ––˜ѕЖ_):__Р_З’z.Sb/џџЬ‘XmVOбуѕ$ч}WўyЕ7ќM_hP-DTћ{!	Ч1ˆ-Ѕ!лuв`uГ `Пфbu„ `Йur4t€ћ"2Ѕ!;x+x€ћ!S0r+r6qssс@r;r„tаQuв`& EЁsuHh@ЌyЁaл’П"Юr­дv*(кj:/њшg$Г–П#дvгw'‚гw6H…б’@П"t‡@уw~H€)&rЛp	Н‡;€r@z3ћЗ‚ЩНЯŽ…Пл$0П6аi­W#„    fЛН01%+y­—уrж1Хe'4рi‘ 9\3poP?UЅf9*z_cЂrЈyJ0ў9о›љhїŸ\!ўz„#1oCoUogoРyo‹ooЏoСoгo€UќyЕђyЕдnФ0BTfxŠœЎР„!иyљЖэzхZкjџ
О†ђ?ˆ’ƒ"П#љЖјЗJ„RЯdЮљЖ™ЧeЭЧЃЯД…CpяуЦгтЯ@єЯИƒя€ъ†5ж!п4пј
DIRECTION       output
ŸŸ.Ÿ(xФТрж™Тm“рж|ŸŽŸ ŸВŸФŸжŸшŸњŸЏlшИ‚яFЇx%XЏjЏ|ЏŽЏ Џ@ВЏФЏжЏшЏњЏЖ§П(П:ПLП^ПpП‚П”ПІПИПЪПмПЩxx!иy„э$Я і†§?%…„мƒJ„ня„$№
ˆ“.Д‡шˆnJпmoпп“пЅп@ŸRŸm“&яя+я=яOяaя@sя…я—яЉяЃ/Эымяюяџџ$џ6љ5';BD/АV+qѕ}џ@ёeм
RADIX   hex
nЬМўљТбвџфџіџ,>PbФ}1ШиyЅF
GRID    0        1       0        1       0        16711680        0        0
Ж*…€ёeˆ'ƒЅF§GЄGJ„ўO^ЅFEW]ДGO_Д€ЙЫн-/?/ƒ?c/u/Ф/™/Ћ/Н/#gЪ88oбчQё?•aOї,1?Фfы[Јc_ѓ:џLџh^џN6y§E i`Й5ф†Љіѓ
ЕЛіу?Q‚yюЂ@ўЂ†ТQh cŠ7ЂЬtЁЄЗиEAџЂўгb~@ќaЂ<§c}
w1јЃSврФoџџqлхє…ёPЃTFeWB
ENDGRID -1
IidO1§geљK5ФЂ…ё”x”T{'_2Чqа€МЃRяОQЄe0ЫWqy•aфe#}јaКa§_!i oFePiN›Љјg“КеuŸctg“eѕNŸЎšКaПŸ\šq%”Кa,§gъ‘y       ЅŸs™xэю—Лј€hЏјu…ёLЁЂXЋЉіуgЏ‚ЎTeXЏc{ЛЏŠІКеоЋ-fВЏПeѕоЏ3ПEП2—q•oЇd—qВoбПжoРшoњo3Џ0BщЁўhzŒžАТдцј
Clock   Unclocked
‹МЕ-п2LйЅСTf‰Ds…—ЉЛЭпёŸ9Џ'Ÿ9ŸчŸ]ŸVяŸ“ŸЅŸЗŸЩŸлŸдяџŸЏ#ЏяGЏeПkЏ‰ПЏЁЏuџХЏЂџщЏЦџ
ППЙџUПяџD‹П@@ЂПІe­РПпфПіПЯЯAџ>ЯuW§eЮрwЮа‰Я›Я­ЯПЯбЯуЯѕЯпкЪ;/@пZ)­bй3f†
Dp€/Fп“пЅпЗпЩплпэпџпяGџ5яGяѕяkяf?яЁяvУяp?а6№яџџ&џ8џJџ\џ nџO’џqO 7а…OгџВOf„йO        OЬO!_f|NV_›іTЕTcZ/џџзTюYPOЕ%@0РRš!Kš †QЦР WurЂV„HP-DTћ!        Сяˆ-ОQuіJpu
EdgeLevel       neg
Jpфbwunа`uФfЛ€Г@ў"ОQДЭhНh€­@ў!ЉТbНbШas0вbЭbt3aНQЙ"[ОQuСP` Њє33s:vDrЉuV0Nya8liэzm€zg$5{9w:vЙrМRУ еz_wьѓЙr‰e)ОRpУ`U2Nˆw€г`@z3рa’I‚OaŽ…ёHе$06аi­O#9›VСQV1Ї‚7U+ДiвюQ^s$aМRџ‚џ!WeЙq4О`№6jV3oJ?UR`9*@_с$DrJy‚D0ў‡9p›Ё8‰ŸT!ўЕAС_г_х_ї_       o@o-o?oQocoujђƒo•oЇoЙoЫoнoяo %|DVqjVvA>sZs‹Ж€yZЃЉЋwCђ?лu‹ЖуЗŠЗЙsфПіО‹Ж+ЧїНšЗ5Я@єpI„IЁ}…uЦetЯ„†ЯнЂpxЅЧЦГЯЦЯŠœЎР4Xѕ!с.–Жџƒrж+Тџ‚ŠВџ‚Ÿ!Ÿ3ŸEŸWŸ€ІŸ{ŸŸŸŸБŸяеšуŸѕŸЏЏ+Џ=ЏOЏaЏsЏ…ЏrmмЈЏКЏЬЏоЏ№ЏПП&П8ПJП\ПnП€ИmсЙЄКŒ-њЋwмЖulтЙ#ФoЖ‚
%РkЧF1}…мЯџпп%п7пвф!џƒЋŸЋпНпЯпспѓпяя)я;я5/_ыx#sя…я—яЉяРЛяЭяпяёяџџ*yfzeпš^ЯNџ`џrџ„џ–џЈџКџЬџоџ№џw"Й;F/AW5 O7g;F“G:GФ”OІN;FлGЇMJGхO іЈ0|†%V$_:L^p‚”FFџƒаVОатє//*/љ‹Q‰?›?­?П?б?у?ѕ?OO+Mќq?Id\†ЄКЖFi€F€yO@ŽC\†Д‡[‡ФЕЧŽ\†ќ‡Шk‡Ÿіp_‚_”_ф_і_:o,o{oPobotoa'xяŸcч1МoLЁFЃаe5жo{ЃЂ›_Ѓ3ё/??Dv0=EзšMі2џр3ѕ.Mіа?QгЉЅRЉЕ(еpЕ]ЉВ†Јз“ —ЉГƒДЄЇXќqЖVЮ“ўŠЂ*@ГЁЮ•<ДЇвПFјZ“? {ЏџџКЁЈОЁЗ ЦЅџINT
Set     Not Used
I/F    i™”бДЇ9Ј•Ю•тF”УЈK”гЋ'Џ2ЧqŠРМZ’ІQu‘[Ѕ0‚—ЯНLЁ›Ѕк­ЏЁ5ДŸИQЪ™rбкŸEЉл;ј!гЊU/п7„€!г5пhк5yпкqпФ5,ДЇVбТЉУеЪЯЬЃ™УЈЇСњЏу™иБГ FсЮ•ы;іа!я<ю
Clear   Not Used
uяЛuяDцЊU˜ыф–lяСя5˜яэяџяОbrБLЏ^ЄrБiЏ‹џЏŸЏБЏУЏэпчЏ!џU8П(П:ПLП^ПpП‚П”ПІПИПЦђ@vѕчщПƒЩЫPM)Я;ЯMЯ_ЯqЯƒЯ•ЯЇЯЙЯшџнЯяЯпп%п7пIпD/mп/‘пŒ/ЕпЧпйпз§пџ6џ?џEяh/2џH?яŸя~?УяЂ?чяЦ?џЇ?ќ?OНcшaЛoЭoпoёoЗџЩџPлџKwї§a{puyuШ‚~И”ІИЪмРю$6HšA`‰fuŠZ_•Š%U/@€’hBнƒ fgв„ko}nfВgP~m!gМo)jBpЙPvlBњh€P'@z3ŒQѕbћo
‚dRpPЭ-qNv:M_~?ŸQŸcŸSЇДqcЭ.fаA—c§rВb§rb§ruŸ‡Ÿ™ŸЋŸНŸЏсŸѓŸЏi77X›>ЇjO|OŽO OВOФO жOшOњO_Qmщ:7_I_[_m__‘_Ѓ_Е_Ч_й_ы_§_`єiІ+o2ЇŸц:Wgь?ceІ ѕЇœЇˆdіЏОІ=З     НЌЇGПђgЌ!)u‡Жc†П˜ПHsуѕ-qйЖХПиПˆšЌОатЈІ§s„Ц=Вƒ„Ц 2DVhzŒžАТ"пц‹J]џЋєJzџБп€žџАџ]ŸoŸ§/јџЦЏЋ@ёКžс:ИCUgy‹ЏС€г
ClockEnable     Not Used
œе
џњ,љJў)System :L^p‚”ІИЪяю/Ў/$/6/HыV/kП’/FІЌ/О/а/т/є/??Yь9?O]?Iъд˜n™?OРŸЖс?ХŸьO/^щ./wUFщђы№ы№ы№Uы№ы№ы№ы№U ы№!ы№"ы№#ы№U$ы№'ы№(ы№)ы№*ы№+м№Ulы№4ы№,чєы№Еы№шѓ@шѓЄщђъёы№Ьџ~        №6;ъы№C-М3+7ы№AщђU2ы№ы№пќчє§@ы№„x 177Fы№RHы№<мџ(
ActiveLowSetClear       True
U2ы№ы№пќчє§Eы№Ьx     –77
ы№RUlы№ы№Lујы№ѕчєы№\ШїџФїгЩы№œЦїпп6ы№@ѕ?ы№Д%w7ны№RDы№ФЧїЃ;U$ы№мџ
AsyncSetClear   True
!ы№§чєпЧsџ[ё№ъёя№"4FрXj|Žъёоџј“ЙхіC:\Prџogram Fiџles\Visiџo\Solutiћonф Extrџas\Backgџrounds.vss#ы№§чєёйsџ[ё№я№     #5GрYk}ы№Кџј“ЙхіC:\Prџogram Fiџles\Visiџo\Solutiџons\Blocпk Diaл\Bџasic Shaџpes.vss(ы№§чє€ыsџ[ё№ы№я№"4РFXj|ŽъёКџё“ЙхіC:\Pџrogram Fџiles\Visџio\Solutїionф Extџras\Bordџers and їTitт.vssеvы№(ы№Bы№є“юмџшѓъё*ўы№Д€ј8ыyы№C!мјы—+~/    ?9/ъё§ёU1ы№џђ№ы№(шѓы№мџіёіёцѕUы№ы№O"D&aU=шѓђёQџџJf       рћ)ъёh"Tы№y‡ъёМуј+UК
ActiveLowClockEnable    True
ц"_Щ…&aQ-З
VhdlType        std_logic
-H*9(TYяєkЉPŒžАщђ›ујEQю№/,GuideTheDocPage-1ѕы№ы№Gestџure FormatVisio 90ConnectorVisio 00Visio 01Visio 02Visio 03Visio 10Visio 11Visio 12Visio 13Visio 20Visio 21Visio 22Visio 23Visio 50Visio 51Visio 52Visio 53Visio 70Visio 80BasicBasic ShadowRectangleSchemeNameRectangle.28Rectangle.4Rectangle.5Rectangle.6Rectangle.7Rectangle.8Rectangle.9Rectangle.10Rectangle.11ѕы№ы№Dynaџmic conn?ectorRectangle.16Rectangle.17Rectangle.18Rectangle.24Rectangle.25_ьы№Шя№Ѕ%уј,ъё3ы№дџŠј‚:
VerilogType     wire
Њы№EфŒъє—-
SystemCType     sc_logic
‹јSЂђёGMUК
4MЧULMеc
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
dMUтc
StateEquation   Hex(Inc(0,2,5))
|Mяc
HighVoltageThreshold    5
”MЕќc
LowVoltageThreshold     0
ЌM     ;d      ФЊMЯ
LSB     0
мM#Я
MSB     31
єњM0Я
SignalActionType        0
Œј=ЊЯ
isFallingEdgeSensitive  False
$JЯ
isRisingEdgeSensitive   False
<WЊЯ
DrawAnalog      0
TdЯ
BooleanEquation
lqЊЯ
NegTolerance    0
„~Я
PosTolerance    0
œ‹ЊЯ
UserSpecifiedSizeRatio  1
Д˜Я
VerilogCode
ЬЅЊЯ
VHDLCode
фВЯ
PROPS!
ќП|ЯјЩЯIйкЯx<йѕшЯгœјїњн\й<Њtй%*Œй(Њ%*Єй8%*МйHЊ%*дйX%*ьйh|% рŽјy‘*UŸ Š% ы№AЊŸ Ž% UDŸ ЉЊ‘*\Ÿ К‘*tŸ ЫЊ‘*ŒŸ м‘*ЄŸ э‘&ъёы№ы№я№З"Uы№ы№ы№ы№        ы№0ы№fxЈ!(!ры№ы№*ы№ы№ы№ы№ђёЅы№ы№Ъ!ы№Њы№ы№ы№ ы№!Šы№"ы№#!ы№њё&Њы№'ы№(ы№)ы№*ы№+м№U^хіы№ы№ы№Uы№ы№        ы№
E0      X       43750   43750           1       0        DR      0
ы№Uы№ы№
ы№ы№Uы№ы№ы№ы№Uы№ы№ы№ы№ы№ы№м№Ulы№4ы№,чєы№Еы№шѓ@шѓЄщђъёы№ЌџXъ>Kњы№C-ŒQ5/?ы№AщђUlы№4ы№,чємџшнўўёўѕы№Фv   П‚?
!
ы№AJ-М3Œ7ўёAщђ_ы№ќпќмџ*<Nчє@ўы№DQ;?Gы№RVŠœЎ№РвфgTRŽq6uHы№<мџ(
Hы№<мџ(
SIGNAL  iwb_WE_O
_ы№ќпќмџ*<NчєEўы№МR
DIRECTION       output
@
ы№RVŠœЎ№Рвфg\]q ы№мџ&AM3'AM3(PPT)PPT1_(ы№я№*ујы№њљ'9K]o“ЅЗЩлэџ#5GYk}ЁГХзщћ
//1/C/U/g/y/ш‹//рћ/ы№М–јПp@
ы№AЊН"дУ }Ч*ьУ ŠОЧ*—ј—Ч JЫ"&ы№'ыёы№)Ќ {†ы№zѓ№œцѕїѓы№
RADIX   hex
*ы№   ы№gѓ№"мџ4pFXпќїј„ќшѓ(S—›0џт@(ќxKsqRЌЏА2Ьђ№^z     №Jїхічє}ы№$Qї:Ўы№Rы№ЄџЁT
GRID    0        1       0        1       0        16711680        0        0
дџЊЏRїГы№uы№вћ&ы№ЌOї(ъѓ№!ы№B  ЬUї[Iѓ№Ч>ы№џl8Bѕ>Oы№9BЕNo5OgЈїЌf}$ы№єХї
ENDGRID -1
њ'ћЦїТ7чSN€јW8)ы№4Х_–9J1гЏ„јрлЂ=џюы№œ—јхі`2ўы№м†јў<kьѓ№V”?ы№_МŽјФ, F}Dы№„‘ј$ЗѕC=ы№\“јЉgЗ.ы№ŒU ЅЗ›`lx„амValued Sony CustomerAC:\Program Files\Visio\Solutions\Block Diagram\Basic Diagram.vstфўџеЭеœ.“—+,љЎDеЭеœ.“—+,љЎ(ф@LXd
œд€мPagesMastersPage-1
Clock   Unclocked
RectangleDynamic connectorф ”0lx„€Œ_VPID_ALTERNATENAMESўB`_PID_LINKBASEAф     ўџ
EdgeLevel       neg
џџџџРFMicrosoft Visio DrawingVISIO 6.0 ShapesVisio.Drawing.6є9ВqўџVisio (TM) Drawing
Set     Not Used
2„THї›0~Rэlъёщђџџџƒџіђџѓћ№јё‰€ъё€ €џРРРцццџЭЭЭГГГяššš!€fџffMMM3џ33яяяњњњ$ы№мџ
Clear   Not Used
$ы№мџ
ClockEnable     Not Used
Uы№џђ№,ы№8шѓ@њєсњіёъёуј§ы№Tdџ Arialъ@чєNПWingdzsЊ@чєN@tMџonotype ЏSort+чє
њNtSymbol5Tы№?шѓа?ђџкъё шѓY@-1Uы№џђ№ы№шѓ њєы№іёъёJчє:ы№Dы№T1шѓ€ђёEWђёрћ-ъёhъчєы№Tы№T…ы№<пќŒŒцѕЎ‘*ы№Њы№ы№ы№  ы№
ActiveLowSetClear       True
Њы№ы№ы№
ы№ъы№“уј/РUљКпbеў
bOў…Иъё‰џ0zЎGсz„Ѕ?Ж@цѕП8@‘H2!kWЎb*Ѕ†МъёUВ
AsyncSetClear   True
ь
‚+Ÿ$Ў‡РъёйPры№L/^&9^$р? { ђ№яAшk^&Ž™,™,™'%/‰v&Ž&Ц‚       *
ActiveLowClockEnable    True
1 yрЙ
‚€‚ )‚ЎPР? 2
U
U1ЄШŠъёэ2?§k9лЏaўBBHEЊHEHEHEHE‚HEH@ ?В>з?щ:`T2BBHEHEHEUHEHEHEHE%H@„Ьъё%O9      ЃаъёF7AOY@;P
ЬAsVsVЬA!ЇдgLTkYЗиъёї  WЭ_Wп_ќ_њ !`Г#Ј•k4l•ƒb”6u`kђWŽ     *4l
VhdlType        std_logic
4l•Нмъё§Б%Y№?ˆˆP:?-\
Ѓ#!ю+|QtKf2|2|2|I2wŠGОръёQAUѓoІTMeE$жttAПфъёв%_8BOTOfOxOŠOВ?Ф?HЌOш?њ7РшъёмЛXњuЛWР?ыаќŽYиžђˆsU4‘х2–
VerilogType     wire
TŸ*<N`r@„–ЂД„k!–JŽЌ§†Ž0ЌЉ–ŽPЌЌ&Ќ 3•ŽЇ
•1’ьъёїмЏюЏПП$П6Пуќw
Р[ЕiИЛњё”|Г .ф”ујМЫЏi7'04’UХP§iW?i?{4Lz№y‘2ї#TЩЖz“x•       x•
SystemCType     sc_logic
x•Ѕx•x
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Ѓ0–jPМvПˆПуј•ујШВЗl^/ЫЦ!3оТѓПjЦBjЦ6DŒ/ž/А/ў$Q0pоФ?MdjЧ^cjЧŒ4ТЬAk[Ж~ЯЯхіˆуј$YkU1%Л1ўптУэFЛе„-(‘kp
йЛ   ѓ       A.$–5-Bi`яЗб#ошяЗ9)›F/Pџтљv/ˆ/п пО/u?‡2tСrПœпœЯKЖSИЯ5мЯюЧ2ћЩŒ7сбxХэпЂя#я6@хhБ$MчюuLЕhБЪ        хеƒя•яЇяЙяЫяняяяџџ%џодŠе‘ї§ѓ)Й<щ€№Oх™U‡#5G‹˜:ёмО:ѓU2ЧqЩ Ќ?Ш/к&мwџ‰ўк&Ѓє
StateEquation   Hex(Inc(0,2,5))
<<7сбHсщпєБУ1яOВQjСPфSсHЙQ›ywщHсAt/†/˜/YOВGТ$_щpЅ4Ыћb%F!ЂДЦ8ћqТ/д#P?˜Cђ/‰§Nм^мТqЄhшE!	@d)nм{”щrѕ1PБ1	@/ЋOq•жt}Q„”!ўnПњџЄК=ВЙkх@ЦБь…Љ{…B'ФІЩ‚XVйP_0TБNJgхй2ѕ1ѕ1”Rе5P"”Q”Q[СO"P!ДЁq’[СŠrДЁДЁюrŠqŠqг‚юqюqТЂггPБТЁТЁWт§a§a7б$VтWсХе7бPБ$q"$qPБ1q1qPБ>q">qPБKqKqPБXqXqХ2eqeqZБФ2SсobZБZБdБSВTБсQcВdБPБсQсQPБсбй1Hс[<k?шtЋaі}Yя рђMД/OOш*DљЗd3qOш/ДNkS\O’ѕИ†9ђ˜EС/Ÿх/_      ??-??=е_ч_љ_ЄКБ„ИО”МбЗ'Ур–sЯ–ŸdЈŸЉЫI,OЏ0Rн7nOВ†пЏ&ЏМкЋaЬ—сбЋaW?Oрш  //Ђ?*<N`r„w€|rŽЄБdU0{yЦ?gЁ7ЁMЗFКHЃЙ}E ‚…ŸЇЏЙЏjpЯž0UЌТХ8nодP!ЭпъЦЌ!јЭ5/G/Y/k/lŸПБПЂДчПиOЯaЯsЯКŸ—ЯоŸ№ŸЏћп
я8ЏJЏ\ЏnЏ€Џ’Џuя‡яШЏк­КS№ЏуЯП&П8ПJП\ПnП€П’ПпЖПШПкПьПўПЦ$rм#Я
HighVoltageThreshold    5
KЯџџя“ЯЅЯЗЯОCЯЯсЯNЩa\п"п4пFпXпjп пВпKжпГХзяћBяTяfя_/q/œяЎяРявяфяіяй/ы/,џк­ЩaRџdџvџˆџšџЌџОџаџтџєџу*<€+/`Ш§b§b‡iAnFUЏj?|?~/ї "CЖ?Ш?ВVуaР]ї?     I„a(G
LowVoltageThreshold     0
rpl/YDE@a1LOзpOћŸ#Q/ˆ­ISПGQл„BQfQaЮIq_U‚ѕ…yjŸЕ(ŸШ„Bb_(_:_/^_Ѕ/З/ЦТдQ—_Љ_†a1и_      OO-OДFСZOQo~MЮA%ФъoCХЅŽAЕšOЌOОMgy ‹N_Џr_МЬO”7ш”ZіgŸ†˜@ЊМ:oЏ,K€o-ŸXyCХЎbУddpЭddpЧСсAЭŸпŸёŸЏЏ'Џ@9ЏKЏ]ЏФvЏAЧBЫ(ŽOГЏn–ЁlХУ=#юПм?ю?6HZl•ПЏДЦŽѕ'сЖПŸŸМЏ;ŸMŸ_ŸqŸƒŸ•ŸЇŸ Я2ЯDЯVЯhЯzЯŒЯžЯАЯТЯдЯцЯјЯ
SignalActionType        0
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??.?@?R?d?v?ˆ?š? YTV
|ъ?bЯO†Я2ODOVOЮЯzOђЯaqЃOЕOЧOйOыO§O_!_3_E_W_i_{__Ÿ_Б_У_е_ч_љ_oo/oAo}x^oK§”ы№Acrobaџt PDFWriwterо§юёп$ъ
LSB     0
wodx)3EWi{§<ы№#џwinspoџolAcrobџat PDFWrџiterLPT1:мџ4ы№(мџ ы№мџUы№џђ№ы№Pшѓxњєёђмџ№Пщђ7@шѓњ?тљTіёъёFчєы№Dы№Te]ђёyPŠ
рћaъёhZ ^‹Tы№ЁЏъёъы№’ујƒы№UџIQЛšж‹/џ@Itк@Ї
л
isFallingEdgeSensitive  False
@2Р?ПI
isRisingEdgeSensitive   False
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DrawAnalog      0
ы№ы№ы№
ы№Ѕы№%ы№ы№Jы№ы№ыєёы№*Ыы№ы№ќцѕˆ!яHњм$aч'Ам$<ч'<м$p!ч'p!и(t!ч't!и(x!ч'x!и(|!ч'|!и(Яч'Ям$„!ч'„!и(ˆ!ч'ˆ!и(”!GњŒ!и(˜!     G!и(Є!ч'”!и(Ј!ч'˜!и(Ќ!ч'œ!и(А!ч'си(юёч'Є!и(ёч'Ј!и(М!ч'Ќ!и(Ыч'А!и(Ф!ч'юёи(Ш!ч'ёи(Ь!ч'М!и(5!ч'Ыи(ф*Ф!и(ф*Ш!и(ф*Ь!и(Фч#ч!я:5ip!<|џџx!-mхH5яИ1%ШH5ч     ъё‰єцѕ•NЏ@@џ:m г@Њ*јЖрЖшЖаy?вёр?ў/˜qс†e# v      lьx!0^        RŒUцѕ8x!Aid/‰уј<^ŠŠ`–$щюbїюb-сДюt!
BooleanEquation
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уa$yўІ9K]o“Ѕ*тNэtaјyвЖ
rœП–UђПyЯ(ЯЏ†П^ЯЊП‚Я   ŸП-Ÿ?ŸчєЙУў^–Mask Fu?nctionlŸNЏ`ЏЂŸДŸЦŸх#<5ъ˜€А§Ÿ
ЏЏА9Љ<$@Х0EgЛІяtЉяњѕЦРА`6аi@@ОˆуќЉІј№-DTћ!Нљ"ˆ-^эu `uˆ `фпbu” `uьŒ Щф€Є @ў"в^ашРш€Ј @ўPМ!НРЦсРтЫсѓетатєЬЏоЏ{Wе,(uiіŠЖђЩ{стГcКd{сшѓќ?•/сVжСїhїМђhїЫџнѕiі е§Шxїн№…­–д0OПшДNk
PosTolerance    0
јЦ…lЕ+ч    RА:яLыOЕcПUwЛ*ђЯ|ЙЯ;Х№ЕуˆюќvУч!зеЬпоп№пяря@ЏhпdЏvЏЇ]M/ыХW†хќЁЎ.аЁЇНЏ:џLџxт‘mљu&П)П;ПMП_ПqПƒП&ЗЯЩЯлЧюsв%ќuI6ыП?Я%?3Яi?ЇЂЏг‰е?uЯ г5ЯЦ?Uхк?ь?ў4хтЯr?3пйіQж!Yk}РЁГХзщћ@@ bВІ/)/;/M/_/eёж!mљХVŽ/ /В/Ф/ж/ш/њ/?‘?0?эt&aјy™fb?Qo†?uoЊ?ЙoЮ?3OEOO(O7LO^OTo‚O”NaЉOЛOЭOпOёOVтБкСTСї\тБЗeхbяU@NЛšж‹Џ   ЎВІёиЁш…YИяЪямяюяџџ$џ6џЄ_яЌa€mљ––‚џ †Іѕ–ЁЃƒЇКѕ––ю—•—пєяŸЎ––6Ї­Ѕ—@Џн№‚”ІИЪмюмoоЇЛˆѓЏKі€,>Pbt†є†хєh^. ц‚_eŸwŸ\њLБmљpЦLDeXPja}
UserSpecifiedSizeRatio  1
&a,ьWї\ЉeМЉe"aИЏЪЁЌqDeПo^oуo‚nГoрЏзoSпЂи@a
VerilogCode
ЗŠ@пЗƒЋпjз]lZ“пŽЁйTБТБPПbПtП†П˜ПЊПМПЮПрП›…џ..`]жшњŸŸ0ŸBŸTŸ@ЯRЯi)усy)ЏŸLY&џ'ч•f
ЄgyЎz
ИvЏˆЏšЏЌЏОЏаЏ„п1ПП#яe<Н	nя€я’яЄя@ЖяШякяьяўя§з!№X\ЛЭWџiџ{џџŸџБџУџеџчџљџТPФЩYe6'їЖVXNXUч•@e6Н7d7ЄО?а>e6Gб=t7Oю$6HZЉ~апМO<Ноp!bЬЧгуѓ/х)"a(0'њY"aх'%їХ^/•ц+ѕВ†       ЦЗFф/Џ/С/г/х/ї/`      ??-???Q?QPi9Фf~?”Аи^ѕиW€ч•ФfwУgЄ/~Фfdw0}гgnE@ŠСtеT–ЯЈЬИС`˜€‡pHНG2ЧqёpЌa?№†•ƒ„р?=А
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VHDLCode
JВYВTЗPУ‘Чб]ГwВEВKЖrВYВŒВcПuДŒВГ7…€‚WвТ‘_Ѓ[їЩvˆђиЪZ<љhˆ3џУОТ?@ш?3OPы?P8ЄЂ‡љП !гцпЅпЛЎ*ScIТвФЅЎcQХ—ў:ВЂ ЃЃ`Ш 0ЅHцRЎb€4>aEБЃЫЯнЯяЧrЅГƒ€5>aЊИ"СtеЌЭƒEјGЧ`IФfHцmЩќюІƒЯЦžЯЌАШ€еў.ЂяЧ јт“PŒb…qaпhЮЈп      _NЧŸйŸыŸ§Ÿ Џ!Џ3ЏEЏWЋqfЄРѓЏ-ЁPј`РЄПќ™№п?@НЎёџР?@ЉLhє™#№я!ѕј`,ѓпЁЏГЏЈХЏзЏ,!}$ђаєЏ Љ‰-єП€ђР(П  єўL        Ni3"gх
PROPS!
юђЅГљіNwГјђГщђяі›Г:%
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ЧbўЃУжљШжqсж4ШfрвIЭппиџbян“ŸЅŸЗŸЩŸлŸэŸэџ#5GYk}Ща/ХЏUџgџћЏћ#ч      //-/?/Q/c/‡П‡/™/Ћ/ї/jџ|џƒ•?Фі2?D?V?h?Я‹PPф9ЬPЯ`Я@rЯvхŒЯžЯАЯŽ‘чД}Ї6AW@@>bM6„јb‡Q„шѕЕAаho!п3пW#јYFНзy&Jцš0Xч€'qfщšš€ХќIœ‹яћ‘Јх`чДЌIq7ЏIЏ)5јYкк!
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OO.O@OROdOvOˆOзOЌO ОOžтOєOU­п!_3_E_ѕпяя+я=яOюUьяUљяUіОц…я—яo%o7oIo[omoo‘oЃo‘њЙКІаoФŸ@ЦьFЦКІЗЙЇУєП%ОКІZЗ&НЩЇdП-9K]o“тЗџКп˜Яљ“Ё_/ŸAŸSŸZ_l_~__hЂ_ЗŸ)СёЗ@њТrщ8г„щњ_Џ!Џ3ЏEЏWЏiЏ{ЏЏŸЏDіђбQљцгЏРиЃИы-        Зц qччУєrя„юцЙч…э(чУя—ЉЛЭпJџ'ЌПОПаПтПєПЯUЯ*Яює8оѓUlы№4ы№,чєћєџQЛšж‹/џ@tк@Ї
E8      0        43125   43125           1       0        DR      0
Ѕ@ујъёы№|џРљ9**ы№A-Œ3?7њѕU2ы№ы№пќчє§@ы№$РљE*7Cы№RHы№<мџ(
E9      X       43625   43625           1       0        DR      0
U2ы№ы№пќчє§Eы№TФљЇ*7
ы№RUlы№ы№Lујы№ѕчєы№\АїџїгЩы№ЌЎїs(*ы№@?ы№еФ%ˆ)ы№R}Dы№œЏїД;U$ы№мџ
!
ѕ4ы№(чєєймџU1ы№џђ№ы№(шѓы№мџіёіёцѕUы№ы№O"D&aU=шѓђёQџџJf        рћ)ъёh"Tы№y‡ъёМуј+Uvы'_Щ…&aQ-З
-H*9(TYіёgЉŒЈžАщђ›ујEQю№/,GuideTheDocPage-1ѕы№ы№Gestџure FormatBlock NormalVisio 10Block ShadowVisio 12ѕы№ы№Block Highl§№tVisio 11ConnectorVisio 90ѕы№ы№Dot џConnectorѕы№ы№Connџector ArrowVisio 00Visio 01Visio 02Visio 03Visio 13Visio 20Visio 21Visio 22Visio 23Visio 50Visio 51Visio 52Visio 53Visio 70Visio 80_Юы№Њя№Ѕујъё3ы№Фџ5јо+
SIGNAL  iwb_SEL_O
Њы№EдшЊфѓ-
DIRECTION       output
єўєђёG6ј_,$_U'c
<_4c
RADIX   hex
UT_Eu
GRID    0        1       0        1       0        16711680        0        0
l_RcЊT„_ju
ENDGRID -1
œ_wЊcД_…u
Clock   Unclocked
ЬЊ_’cUф_ЉЊcUќ_Тu
EdgeLevel       neg
Џ7јЯu
Set     Not Used
,%мЊu
Clear   Not Used
D%щu
ClockEnable     Not Used
\%іZu
ActiveLowSetClear       True
t%-v  Œ%UqЄ%qМ%U*qд%7qь%}Dq8јQqUй^q4йkqULйxqdй…q%ы№AЁй‰%&ъё™ы№я№еы№Њы№ы№ы№ы№       ˆы№0ы№xвRы№ы№fы№!
AsyncSetClear   True
ы№ы№ы№іђёEы№чы№њём№Ujхіы№ы№ы№Uы№ы№        ы№
ActiveLowClockEnable    True
ы№Uы№ы№
ы№ы№Uы№ы№ы№ы№Uы№ы№ы№ы№Uы№ы№ы№ы№ы№м№Ulы№4ы№,чєы№§ы№QЛšж‹џ/@tк@Ї—
VhdlType        std_logic
@ујъёўы№Ыљѓ.ыUы№C-œРљПH/ы№AщђUlы№4ы№,чємџшнўўёўѕы№РљПž/
VerilogType     wire
ы№AJ-3Ј7ўёAщђ_ы№ќпќмџ*<Nчє@ўы№дФљN/Pы№RVŠœЎ№Рвфg"љЊq6uHы№<мџ(
SystemCType     sc_logic
Hы№<мџ(
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
_ы№ќпќмџ*<NчєEўыёХљ&0
ы№RVŠœЎРјвфg\"љ3q ы№мџщђујм№Єt>{˜ы№Œѓ№œцѕїѓы№
StateEquation   Hex(Inc(0,2,5))
*ы№   ы№gѓ№"мџ4pFXпќїј„ќшѓ(“_,9зџт@(mЋ”шЯФт@ЏА2YЬy
HighVoltageThreshold    5
ъёKїхіы_DOї:ы№]ы№WRы№Дџ—О
LowVoltageThreshold     0
LQї Њы№|#Љы№uы№в{&ћUїѓ№]!ы№Bы№œG­?ѓ№Q
>ы№ џ:B>ЊOы№МkЮo5іOы№Ф­ї_$OЎї“'ы№4Ёг*^NФ_/ј$+)Џ0ј-Щ1Tћз=ЩЁ=џы№wЌ=јхі`2ы№џь2ј-Еfѓ№V”?ы№tџ8јр/FњDы№$;ј@щ0P=ы№ќ<јS‚G <ы№фџе‹G
LSB     0
OC     !_їk•G ы№@ўџр…ŸђљOhЋ‘+'Гй0Є@Hht€Œ˜фValued Sony CustomerG<џџџџx‚Œ/KŸ  EMF4ь        XиЂVISIODrawing
MSB     3
 Ž‹&%%€V0ЂV>Ђ>V>VЂЂ>%€(%€RLьџџџ Arial%Tdт&<РЈAРЈAт&LTICMR&%%€V0ЂдVЂVVдЂдЂ%€(%€RLьџџџ Arial%TœМј:РЈAРЈAМј
LhMask Function
SignalActionType        0
isFallingEdgeSensitive  False

isRisingEdgeSensitive   False
DrawAnalog      0
BooleanEquation

NegTolerance    0
&%W$ќ>ќЬќ>ќЬ%€(%€%€V,јЫдЫќдјЫЫ&%%€V0zGђzђGЪGЂz%€(&%%€V0)ђej)ђ)jeBe)ђ%€(&%%€W$VђАђVђАђ%€(&%%€W,АЖ).ЖАЖА.).%€(&%%€W$GЖПЖGЖПЖ%€(&%%€W$e.П.e.П.%€(&%%€W$ђšђђšђ%€(%€%€V,™эЂї™эЂђ™ї™э%€RLѓџџџ ArialџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџ%TˆJРЈAРЈA
PosTolerance    0
L`INT [31:2] &%WXАьˆАˆН‡Ъ‚е{пrцfъYьLъ?ц2п'еЪНА%€(&%%€WXАПˆАˆГ‡Ж‚Й{ЛrНfОYПLО?Н2М'КИЕВ%€(&%%€WXА\ьдАдНгЪЮеЧпНцВъЅь˜ъ‹ц~пsеiЪbН]А\%€(&%%€WXА\ПдАдГгЖЮЙЧЛННВОЅП˜О‹Н~МsКiИbЕ^В\%€(&%%€V0Яƒ>Я>ƒ>ƒЯЯ>%€(%€RLьџџџ Arialџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџ%Td&?<РЈAРЈA&LTICPR
&%W$)>)†)>)†%€(%€%€V,%….Ž.…)Ž%….…&%%€W$)\G\)\G\%€(&%%€W$G\GўG\Gў%€(%€%€V,B§KK§GB§K§&%%€W$yЕzzЕy%€(%€%€V,ДuН~ДuНyД~Дu%€RLѓџџџ ArialРРРџџџРРРџџџРРРџџџРРРџџџРРРџџџРРРџџџРРРџџџРРРџџџРРРРРџџџРРРџџџРРРџџџРРРџџџРРРџџџРРРџџџРРРџџџРРРџџџРРРџџџРРРџџџРРРџџџРРРџџџРРРџџџРРРџџџРРРџџџРРРџџџРРРџџџРРРџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџ%Tl0œРЈAРЈALXINT 0џџ  &%W$jЕjjЕj%€(%€%€V,ГfНoГfНjГoГf%€RLѓџџџ ArialРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџРџџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџРџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџ%Tl}0ŒРЈAРЈA}LXINT 1џџ &%W$ьLzLьLzL%€(%€%€V,yG‚QyG‚LyQyG%€RLѓџџџ Arialџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџџ%Tѓ_FnРЈAРЈAѓ_LdLOWPRIO INTџџ
UserSpecifiedSizeRatio  1

      
VerilogCode
     Tpѓo$~РЈAРЈAѓoLXEXCEPT            &%W$ь—z—ь—z—%€(%€%€V,y’‚œy’‚—yœy’%
€(%€%T”ѓЊGЙРЈAРЈAѓЊLdHIGHPRIO INT     
VHDLCode
               
PROPS!
     T„ѓК:ЩРЈAРЈAѓК     L`EXCEPTIONџџ                
E0      V       0        0           Valid        1       0        DR      0
     ўџеЭеœ.“—+,љЎDеЭеœ.“—+,љЎьЈ@€HP\ht
”ф     PagesPage-1М8Œ€”œЈД_VPID_ALTERNATENAMES^Р_VPID_PREVIEWS_PID_LINKBASE№?ф     AнP&l   P
&" WMFCœœ XxxjŸ–нP&l EMFxl     XфПиVISIODrawingР
E1      X       3750    3750            1       0        DR      0
 %€RLНџџџ Arialџџџџџџџџџџџџџџ%Tl!yлУ
E2      V       13125   13125       Valid       1       0        DR      0
О‡@
E3      X       13625   13625           1       0        DR      0
О‡@!yLXSET 0--)%Tl!Щл
E4      V       23125   23125     Valid 1       0        DR      0
О‡@
E5      X       23625   23625           1       0        DR      0
О‡@!ЩLXSET 1--)%RLНџџџМ ArialJSTFm*iWpLTSH‚&XмOS/23—јVPCAG?Ќ6VDMXVp]№”cmapямЃ1Иоcvt юи”Ь…88fpgmЂю№Ggasp  Pglyf~НŒ(”оЈhdmxЈзч ЌyшheadfY|6hheaУ­Д$hmtxєТRлŒp:kernAONн*PZlocaЃЕ%T`bщ       š6
E6      V       33125   33125     Valid 1       0        DR      0

E7      X       33625   33625           1       0        DR      0
О‡@
E8      V       43125   43125     Valid 1       0        DR      0
О‡@bщ        LT...RLНџџџ ArialŸвЁFЂИЄЅdІ$ІцЇXЈ*ЈќЉnЊ2Ћ$Ќк­€ЎŒЏАfБЄВГ0ДўЗFЗВИИˆИєЙЂКPКіЛœМBМrМЂМвМфМіННН,НœОО>ОPОrО‚О”ОІОИОЪОмОюПњР СЌТRТЊТаТі%T`=      
ПS

E9      X       43750   43750           1       0        DR      0
О‡@
!
О‡@= 
LTSET--)RLжџџџ ArialбАбъв&вbвžвЬвіг4гdгŠгАгжгќдPддме"еZе„еЎеожж4жZж„жЎжрззBзrзЂзвии0и`ииРи№й$й„йИккPкАлHл№мРнжоЈAll Rights ReservedArialBoldMonotypet)%TєJ
x

О‡@
SIGNAL  iwb_STB_O
О‡@єJ
LdDTLB_SETS-1TM&%%€V09ћ§›
:š
ќš
ќќ:ќ:š
%€(RLНџџџ Arial of the last decades of the twentieth century.  Therall treatment of curves is softer and fuller than in most industrial style sans serif faces.  Terminal strokes are cut on thdiagonal which helps to give the face a less mechanical appearti%(RLНџџџ Arial in reports, presentations, magazines etc, and forplay use in newspapers, advertising and promotions.http://www.monotype.com/html/mtname/ms_arial.htmlhttp://www.monotype.com/ht/mtname/ms_welcome.htmlNOTIFICATION OF LICENSE AGREEMENT
DIRECTION       output
RADIX   hex
Thot%(RLНџџџ Arialreement. You have obtained this typeface software er directly from Monotype or together with software distributed by one of MonotypeЭs licensees.
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
This software is a valuablesset of Monotype. Unless you have entered into a specific licena%(RLНџџџ Arialown publishing use. You may not copy or distributes software.
Clock   Unclocked
EdgeLevel       neg
If you have any question concerning your rights you should review the license agreement you received with the stware or contact Monotype for a copy of the license agreement.
Set     Not Used

%(RLЮџџџ Arial//www.monotype.com/html/type/license.htmlNegraArial Negretatu
nщArial tu
nщfedArial fedFettArial FettˆНФПНБAial ˆНФПНБTypeface Љ The Monotyc%(RLЮџџџ ArialType Solutions Inc. 1990-92. All Rights ReservedArialBoldMonotype:Arial Bold:Version 2.7 (Microsoft)Arial BoldVersion 2i%(RLЮџџџ Arialion plc registered in theS Pat & TM Off. and elsewhere.Monotype TypographyMonotype Type rawing Office - Robin Nicholas,s%(%€RLНџџџ ArialвRв|вІдPж\зŠзšйй&кlм8н>оОт‚умхОчш0шZш„шЎшищщ,щVщ€щЊщдщўъ(ъRъ|ъІъаэюˆяЬёДђќѓ&ѓPѓ€ѓАєєѕѕVѕДі
Clear   Not Used
і@і‚іШїїBїzїЊјтќ(ќR%TlК[{Ѕ
ClockEnable     Not Used
О‡@
ActiveLowSetClear       True
О‡@К[LXVPN 0--0%TlКЋ{ѕ
AsyncSetClear   True
О‡@
ActiveLowClockEnable    True
О‡@КЋLXVPN 1--0%RLНџџџМ Arial4J5т5ђ77 8`8p8€8:::(:8<и=І>Š@
VhdlType        std_logic
AŒBŒC DфDєEтFМHXHhI†JŒL„L”LЄLДMўNNЦNжOфOєPрP№RRRМRЬSЪU>VjWdWtW„W”Y2Zђ[Р[а^0`zceh%T`џЫ     7
VerilogType     wire

SystemCType     sc_logic
О‡@
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
О‡@џЫ        LT...RLНџџџ ArialtŠtДtоuu2u\u†uАuкvv.vXv‚vжww*wTw~wЈwвwќx&xPxzxЄxЮxјy"yLyvzzZzаzњ{${N{x{Ђ{Ь{і| |J|t|ž|ђ}}F}p}š}Ф}ю~~B~l~–~Р~є(\%(%T`ш,
Md

StateEquation   Hex(Inc(0,2,5))
О‡@
HighVoltageThreshold    5
О‡@ш,
LTVPN!!$Tvh
Р 

LowVoltageThreshold     0
О‡@
SignalActionType        0
О‡@vh
LdDTLB_SETS-1$!!!!&%%€V0jЕЬ        MkLЫ LЫ     ЖkЖkL%€(%€RLНџџџМ ArialД8ДpДЄДвЕЕ2ЕbЕ’ЕЦЖЖPЖАЖфЗpЗЬИjЙ8КXЛ s covered under the terms of a license agreement You have obtained this typefac %TДЗ~b
MSB     0
О‡@
LSB     0
О‡@ЗLpEFFECTIVE ADDRESSb-))-0(---000---&%%€V0Fћ6    ›
Gš
5 š
5     ќGќGš
%€(RLНџџџ Arialranting you additional rits, your use of this software is limited to your workstation fo your own publishing use. You ms%(RLНџџџ Arialany question concerning yr rights you should review the license agreement you received wth the software or contact Monof%(RLНџџџ&" WMFC 8x Arialn be contacted at:
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
USA (847) 718-0400              UK - 01144 01737 765959
DrawAnalog      0
http://www.monotype.cmhttp://www.monotype.com/html/to%(RLНџџџ ArialrdNormalNormalnyNormal1KK9NormсlneNormalNormalNavadnothАЁngArruntaNormalNormalNormalNomal. 1990-1992. All Rights Reseo%(RLНџџџ Arialrosoft)ArialVersion 2.76AalMTArialЎ TrademGSUBСПІ'„жJSTFm*i*\LTSHЁ!UdOS/2п2kјVPCLT§{>CЄ6VDMXP’jѕZx”cmapямЃ.@оcvt –pвv|М0fpgmw'ЉѕwАgasp  Pyш%(RLНџџџ ArialDmaxp    Ж“и name6„в`+пpostЦЌ%EЬ0epы­qтl
BooleanEquation
§y"yLyvzzZzаzњ{${N{x{Ђ{Ь{і| |J|t|ž|Ш|ђ}}F}p}š}Ф~~B~l~–~Р~є(\€xz‚Jƒ.ƒtƒК„(%(RLНџџџ Arial–є———*—<—Њ˜˜а˜т˜є™™™(™L™^™p™‚š0šм›Šœ6œ’œЬœі `Вž.žxžєŸHŸЬ  ” ьЁRЁЈЂЂdЂАЃЃrЃРЄЄЎЄиЅЅ,Ѕ`ЅЅРІІ€ІжЇBЇ–Ј
NegTolerance    0
ЈPЈИ%(RLНџџџ ArialЏ№АА@АnА˜АфБ(Б^БšБЮБќВ0В`ВФВђГГ>ГjГЈГиДД8ДpДЄДвЕЕ2ЕbЕ’ЕЦЖЖPЖАЖфЗ<ЗpЗЬИjЙ8КXЛ rif desi, Arial contains more humanist characteristics than many of it i%(%
€(%€RLНџџџ Arialn in most industrial style sans serif faces.  Term strokes are cut on the diagonal which helps to give the face a less mechanical appearance.  Arial is an extremely versatile fily of typefaces which can be used with equal success for text, %Tl]oЙ
PosTolerance    0
О‡@
UserSpecifiedSizeRatio  1
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VerilogCode
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VHDLCode
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PROPS!

E0      0        3750    3750            1       0        DR      0
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E1      1       13125   13125           1       0        DR      0
О‡@Ђп        LT...ofRLНџџџ ArialtypeЭs licensees.
E2      0        13625   13625           1       0        DR      0
E3      1       23125   23125           1       0        DR      0
This software is a valuable a of Monotype. Unless you have entered into a specific license agreement granting you additional rights, your use of this softwe is limited to your workstation for your own publishing use. s %TЈ’џщI

E4      0        23625   23625           1       0        DR      0
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E5      1       33125   33125           1       0        DR      0
О‡@’џLlPPN DTLB_SETS-2 t--00)%-%--)-%TЈ’O
щ™

E6      0        33625   33625           1       0        DR      0
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E7      1       43125   43125           1       0        DR      0
О‡@’O
LlPPN DTLB_SETS-1ty--00)%-%--)-%%
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€(&%%€V0ИЕеMЙLдLдЖЙЖЙL%€(&%%€W,јC$ћL--ђ%€(&%%€W,ТћZ›
YќУќУš
Yš
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E8      X       43750   43750           1       0        DR      0
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SIGNAL  iwb_ACK_I
О‡@БkL\TLB SET )%---)TlдЛž
DIRECTION       input
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RADIX   hex
О‡@дЛLXINDEX00-+&%W$Ž
GRID    0        1       0        1       0        16711680        0        0
a
ENDGRID -1
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Clock   Unclocked
X
EdgeLevel       neg
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Set     Not Used
Nя       У
Clear   Not Used
N=
ClockEnable     Not Used
Nя     &%%€V0
вВЖЕБЕБггЕ%€(%€%TdћXТЂ
ActiveLowSetClear       True
О‡@
AsyncSetClear   True
О‡@ћXLTCOMP047-&%W$›щ­qЄђЄh%€(%€%€V,}^ЫгЫ^Єг}^Ы^&%%€W$‘
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h%€(%€%€V,є^BгB^гє^B^&%%€V0юЂВ…я„Б„БЃяЃя„%€(%
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ActiveLowClockEnable    True
О‡@
VhdlType        std_logic
О‡@˜'LTINV0-&%W$WЌi@`Е`7%€(%€%€V,9.‡Ѓ‡.`Ѓ9.‡.%
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VerilogType     wire
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SystemCType     sc_logic
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TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
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StateEquation   Hex(Inc(0,2,5))
О‡@•йLXHIT 00)%%
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HighVoltageThreshold    5
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LowVoltageThreshold     0
О‡@‘ЄLP31%%RLЮџџџ Arial%T`ЊŸэз
SignalActionType        0
О‡@
MSB     0
О‡@ЊŸLTlogRLпџџџ Arial&" WMFC xg use. You my not copy or distribute this su%TTюАџе
LSB     0
О‡@
isFallingEdgeSensitive  False
О‡@юАLP2 RLЮџџџ Arialt you received with the stware or contact Monotype for a copy of the license agreement.
isRisingEdgeSensitive   False
Monotype can be contacted at:1%(%T Ÿ” з
DrawAnalog      0
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BooleanEquation
О‡@ŸLh(DTLB_SETS)+13$!!!!%
€(RLНџџџ Arial92. All Rights ReservedArialRegularMonotype:Arial lar:Version 2.76 (Microsoft)ArialVersion 2.76ArialMTArialЈ Trademark of The Monotype Corporation plc registered in the US Pat TM Off. and elsewhere.Monotype TypographyMonotype Type Drawing S%TXIЄ’ю
NegTolerance    0
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PosTolerance    0
О‡@IЄLP13%%%TTЉЄЭю
UserSpecifiedSizeRatio  1
О‡@
VerilogCode
О‡@ЉЄLP0er%RL­џџџМ Arialserif faces.  Terminal strokes are cut on the diag which helps to give the face a less mechanical appearance.  Arial is an extremely versatile family of typefaces which can be ed with equal success for text setting in reports, presentatio u%Tl™о
VHDLCode
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PROPS!
О‡@™LXWAY 0:/O98.&%W$Ч{йІа„а%€(%€%€V,Љ“її“аЉ“ї“%€RLНџџџŒ
E0      0        11250   11250           1       0        DR      0
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E1      1       13125   13125           1       0        DR      0
 Ariale distributed by one of MonotypeЭs licensees.
E2      0        21250   21250           1       0        DR      0
E3      1       23125   23125           1       0        DR      0
Tsoftware is a valuable asset of Monotype. Unless you have entered into a specific license agreement granting you additional rits, your use of this software is limited to your workstation fy %T„•mп
E4      0        31250   31250           1       0        DR      0
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E5      1       33125   33125           1       0        DR      0
О‡@•     L`DTLB MISS t0)%-7--T„l…эЯ
E6      0        41250   41250           1       0        DR      0
О‡@
E7      1       43125   43125           1       0        DR      0
О‡@l…     L`EXCEPTION7)-+0--)40%
€(%
€(RLНџџџ ArialdšБНПНЙКL„L”LЄLДMўNNЦNжOфPрP№RRRМRЬRмSЪU>VjWdWtW„W”Y2Zђ[Р[а^0`zcehgьjbl2mьnn@nPn`nŠnоnюnўo(oRoboroœoЦo№ppp p0p@%TXЭЄ
ю
E8      X       43750   43750           1       0        DR      0
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О‡@ЭЄLP12%%&%W$дЧцšнан‘%€(%€%€V,Ж‡ќ‡нќЖ‡‡&%%€W$ъШќѓбѓ„%€(&%%€W$Е‘
ЧЯОЦОš
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SIGNAL  iwb_CYC_O
О     МЙЗЕГБ§АћЏјЎѕЎѓЎ№ЎэЎъЏшАхБуГсЕпЗоЙмМлОкСкФкЦ&%%€W$ъ{ќІѓ„ѓ%€(%€%€V,Ь““ѓЬ““%
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DIRECTION       output
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RADIX   hex
 Arialre distributed by one of notypeеs licensees.
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
This software is a valuable asset of Montype. Unless you have entered ic%T”jНД
Clock   Unclocked
О‡@
EdgeLevel       neg
О‡@jLdPADDR[31:13]--000%%%%&%W(ОCGыЧLЧт>т%€(&%%€W$5й3ы>т*т%€(%€%€V,!Л–     !Л–т!       !ЛRLНџџџ Arialent you received with theoftware or contact Monotype for a copy of the license agreement
Set     Not Used
Clear   Not Used
Monotype can be contacted a %(%€%T~ІT№
ClockEnable     Not Used
О‡@
ActiveLowSetClear       True
О‡@~ІLdPAGE OFFSETo--4-4))--)T F1
AsyncSetClear   True
О‡@
ActiveLowClockEnable    True
О‡@ FLdPADDR[12:0]m--000%%%%
€(RLЮџџџ ArialalNormalerty of Monotype pography and its use by you is covered under the terms of a licnse agreement. You have obtaineo%(RLпџџџ Arialr together with software stributed by one of Monotypeеs licensees.
VhdlType        std_logic
VerilogType     wire
This software is avaluable asset of Monotype. Unlr%(%
€(RLЮџџџ Arialonal rights, your use of is software is limited to your workstation for your own publishng use. You may not copy or dis%T`
SystemCType     sc_logic
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TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
з
StateEquation   Hex(Inc(0,2,5))
О‡@
HighVoltageThreshold    5
О‡@
LowVoltageThreshold     0
ŸLTlogRLпџџџ Arialracteristics than many of its predecessors and as  is more in tune with the mood of the last decades of the twentieth century.  The overall treatment of curves is softer and fuer than in most industrial style sans serif faces.  Terminal sch%TTF
SignalActionType        0
АW
MSB     0
е
LSB     0
О‡@
isFallingEdgeSensitive  False
О‡@F
isRisingEdgeSensitive   False
АLP2ilRLЮџџџ Arial presentations, magazines etc, and for display usenewspapers, advertising and promotions.http://www.monotype.com/html/mtname/ms_arial.htmlhttp://www.monotype.com/html/mtname/mselcome.htmlNOTIFICATION OF LICENSE AGREEMENT
DrawAnalog      0
BooleanEquation
This typeface ap%T X
NegTolerance    0
Ÿьз
PosTolerance    0
О‡@
UserSpecifiedSizeRatio  1
О‡@X
VerilogCode
ŸLh(DTLB_SETS)+12$!!!!&%W$дЧ      йана%€(%&"WMFCx€%€V0zžb
§z§b
§b
žzžz§%€RLНџџџ Arial or distribute this software.
VHDLCode
PROPS!
If you have any qion concerning your rights you should review the license agreement you received with the software or contact Monotype for a co of the license agreement.
E0      0        3125    3125            1       0        DR      0
E1      1       43125   43125           1       0        DR      0
Monotype can be contacted at:
E2      0        43750   43750           1       0        DR      0

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О‡@ƒфLlD & A attributes0--%%%%"&%%€V0`
SIGNAL  iwb_ERR_I
ЂКfa
DIRECTION       input
eЙeЙЃa
RADIX   hex
Ѓa
GRID    0        1       0        1       0        16711680        0        0
e%€(%
€(%€RLНџџџ Arialpe:Arial Regular:Version 76 (Microsoft)ArialVersion 2.76ArialMTArialЎ Trademark of The Mnotype Corporation plc register&%TˆМ
ENDGRID -1
˜]т
Clock   Unclocked
О‡@
EdgeLevel       neg
О‡@М
Set     Not Used
˜
Clear   Not Used
L`PAGE FAULT--4-)-0%)&%W$0џ    B      9і    9%€(%€%€V,ь a
ClockEnable     Not Used
`ь     a
ActiveLowSetClear       True
9ь     `ь     &%%€W$0  9     %€(%
€(%€%€V0mžЅMmMЅMЅžmžmM%€RLНџџџЬ Arialf curves is softer and fuer than in most industrial style sans serif faces.  Terminal stokes are cut on the diagonal wh %Txvфœ.
AsyncSetClear   True
О‡@
ActiveLowClockEnable    True
О‡@vфL\SR[SUPV -0-0--TT4~
VhdlType        std_logic
О‡@
VerilogType     wire
О‡@4LP]u&%W$    ыџ §     єі     є%€(%€%€V,ь Эa
SystemCType     sc_logic
ь     Эa
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
єь     ь     Э&%%€W$     ы      є     %€(%
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€(%
€(%€%€V0}ќЂ Ћ}ЋЂ ЋЂ     ќ}ќ}ЋRLНџџџ ArialRRRМRЬRмSЪU>VjWdWtW„W”Y2[Р[а^0`zcehgьjbl2mьnn@nPn`nŠnДnоnюnўo(oRoboroœoЦo№ppp p0p@pzpŠpšpФpюqqBqlq–qРqъrr>rhr’%(%€RLНџџџ ArialxPxzxЄxЮxјy"yLyvzzZzаzњ{${x{Ђ{Ь{і| |J|t|ž|Ш|ђ}}F}p}š}Ф}ю~~B~l~–~Р~є(\€xz‚Jƒ.ƒtƒК„(„ж…F††к‡Вˆn‰Š(Šм‹^‹И‹јŽ`ј%Tp†B™ Œ
StateEquation   Hex(Inc(0,2,5))
О‡@
HighVoltageThreshold    5
О‡@†BLXACCESS-00---TdИ’g        м
LowVoltageThreshold     0
О‡@
SignalActionType        0
О‡@И’LTTYPE)---&%W$
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MSB     0
О‡@
LSB     0
О‡@z
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isFallingEdgeSensitive  False
L`PROTECTION-04)-0)40Tˆ…
ш&2
isRisingEdgeSensitive   False
О‡@
DrawAnalog      0
О‡@…
ш
BooleanEquation
L`ATTRIBUTES-))0-0)--&%W$„\–Іe%€(%€%€V,f“ДД“f“Д“RLНџџџŒ
NegTolerance    0
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PosTolerance    0
 Arialecific license agreement anting you additional rights, your use of this software is limied to your workstation for yours%(§џџџ                                
UserSpecifiedSizeRatio  1
                  
                                                       ўџџџe                                     !     "     #     $     %     &	'	(	)	*	+	,	-	.	/	0	1	2	3	4	5	6	7	8	9	:	;     <	=	>      ?     @     ўџџџB C     D     E     F     G     H     I     J     K     L     M     N     O     P     Q     R     S     T     U     V     W     X     Y     Z     [     \     ]     ^     _     `     a     b     c     d     ўџџџ… g     h     i     j     k     l     m     n     o     p     ўџџџr s     t     u     v     w     x     y     z     {     |     }     ~               %€RLНџџџŒ
VerilogCode
Œ
VHDLCode
 Arial
PROPS!
If you have any questioconcerning your rights you should review the license agreement ou received with the software oe%T„ёшŒ
2
E0      0        43125   43125           1       0        DR      0
О‡@
E1      X       43750   43750           1       0        DR      0
О‡@ёш     L`DMMU PAGE 0770--4-TlQL$–
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SIGNAL  iwb_RTY_I
О‡@
DIRECTION       input
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RADIX   hex
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GRID    0        1       0        1       0        16711680        0        0
КММНН§НћМјМѕКѓЙ№ЗюЖьДъБшЏчЌцЊхЇхЄхЁхŸхœц™ч—ш•ъ“ь‘ю№ŽѓѕŒјŒћ‹§Œ.ќ-ћC Arial???????-2
ENDGRID -1
y!SET 0--)%2
Clock   Unclocked
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EdgeLevel       neg
щ       b...ћC Arial?????????????????????????-2
Set     Not Used
        
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Clear   Not Used
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њџџџ-№ћC Arial???????????????????????†?-№ћC Arial?????????????????????????-№ћC Arial?????????????????????????-№ћC Arial???????????5???4?????????-№ћ2 Arial????????????????????lNegr-№ћ2 ArialType Solutions Inc. 1990--№ћ2 Arialion plc registered in the-№-ћC Arial?A?A?A?A?A?A?A?A?A?A?A?A?-2
ClockEnable     Not Used
[КVPN 0--0%2
ActiveLowSetClear       True
ЋКVPN 1--0%ћCМ Arial?????????????????????????-2
AsyncSetClear   True
Ы       џ...ћC Arial?????????????????????????-  №-2
ActiveLowClockEnable    True
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шVPN!!$2
VhdlType        std_logic
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vDTLB_SETS-1$!!!!њ--$kLЫ LЫ     ЖkЖkL-№-ћCМ Arial?????????????????????????-!2
VerilogType     wire
ЗEFFECTIVE ADDRESS(-))-0(---000---њ-
SystemCType     sc_logic
-$Gš
5  š
5     ќGќGš
-№
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
ћC Arialranting you additional ri-
StateEquation   Hex(Inc(0,2,5))
№ћC Arialany question concerning y-№ћC Arialn be contacted at:
HighVoltageThreshold    5
LowVoltageThreshold     0
USA-№ћC ArialrdNormalNormalnyNorma????-№ћC Arialrosoft)ArialVersion 2.76A-№      ћC Arial?????? ??????????`?- №ћC Arial?????????????????????????-№
SignalActionType        0
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MSB     0
№ћ       М"SystemНџ ѕcЖpXђЯ/-№-ћC Arial????4?????????????????†??-2
LSB     0
o]PPN 0--0%2
isFallingEdgeSensitive  False
П]PPN 1--0%-2
isRisingEdgeSensitive   False
п       Ђ...ћC Arial?????????????????????????-2
DrawAnalog      0
џ’PPN DTLB_SETS-2--00)%-%--)-%2
BooleanEquation
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’PPN DTLB_SETS-1--00)%-%--)-%-№њ--$Ы LЙLЙЖЫ     ЖЫ     L-№-№-№        њ--$ЙLдLдЖЙЖЙL-№њ--%L--ђ-№њ--%YќУќУš
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NegTolerance    0
-№--$ЉдЫдЫ%Љ%Љд-ћC Arialontains more humanist cha-2
PosTolerance    0
kБTLB SET)%---)2
UserSpecifiedSizeRatio  1
ЛдINDEX00-+њ-%—
VerilogCode
X
VHDLCode
-№-ќ-$Nя       У
PROPS!
N=
E0      0        43125   43125           1       0        DR      0
Nя     њ-  -$ЕБЕБггЕ-№     --
2
E1      X       43750   43750           1       0        DR      0
XћCOMP047-њ-      %ЄђЄh-№ --$Ы^Єг}^Ы^њ- -%š
h-№ --$B^гє^B^њ- -$я„Б„БЃяЃя„-№     -№--2
!
'˜INV0-њ-%`Е`7-№--$‡.`Ѓ9.‡.-№
ћCŒ
MARKER  MARK1
Œ
ATTACH  iwb_SEL_O       NULL    S6
 Arial-№-№--2
TIME    17500.000000
й•HIT 00)%-№ћC Arial-
RELATIVETIME    0.000000
2
DISPLAYAS       5
Є‘31%%ћ2 Arial-2
MARKERTYPE      Timebreak(Curved)
ŸЊlogћ! Arial-               2
WHILERETURN
Аю2јћ2 Arial? ??? ???????? ???? ??? ?-
REPEATNUMBER
№-
SNAPTO  0
2
COMPRESSTIME    0.000000
Ÿ(DTLB_SETS)+13$!!!!-№ћC Arial?????????????????????????-
COMMENT
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џџџџџџџџ|PRINTџџџџ€џџџџ†`НCompObjџџџџџџџџ}qObjInfoџџџџ‚џџџџOCXNAMEџџџџƒџџџџўџџџcontentsџџџџ„џџџџўџџџVisioDocumentџџџџ…џџџџхMNVisioInformation"џџџџ†џџџџ€SummaryInformation(џџџџ‡џџџџFDocumentSummaryInformation8џџџџџџџџџџџџоOle
 
џџџџ‰џџџџ‰PRINTџџџџŠџџџџ5ј;CompObjџџџџ‹џџџџŠqObjInfoџџџџŒџџџџŒOCXNAMEџџџџџџџџўџџџcontentsџџџџŽџџџџўџџџVisioDocumentџџџџџџџџSЊAVisioInformation"џџџџџџџџSummaryInformation(џџџџ‘џџџџŽDocumentSummaryInformation8џџџџџџџџџџџџ“МOle
 
џџџџ“џџџџšCompObjџџџџ”џџџџ›qObjInfoџџџџ•џџџџOCXNAMEџџџџ–џџџџўџџџcontentsџџџџ—џџџџўџџџVisioDocumentџџџџ˜џџџџvЕBVisioInformation"џџџџ™џџџџžSummaryInformation(џџџџšџџџџŸDocumentSummaryInformation8џџџџџџџџџџџџЄМ_-1316877540џџџџœІРFўџџџ_-1316996300џџџџџџџџРFўџџџOle
 
џџџџžџџџџЋCompObjџџџџŸџџџџЌqObjInfoџџџџ џџџџЎOCXNAMEџџџџЁџџџџўџџџcontentsџџџџЂџџџџўџџџVisioDocumentџџџџЃџџџџ›2VisioInformation"џџџџЄџџџџЏSummaryInformation(џџџџЅџџџџЕ DocumentSummaryInformation8џџџџџџџџџџџџАЈOle
 
џџџџЇџџџџЗPRINTџџџџЈџџџџЦ( CompObjџџџџЉџџџџИqObjInfoџџџџЊџџџџКOCXNAMEџџџџЋџџџџўџџџcontentsџџџџЌџџџџўџџџVisioDocumentџџџџ­џџџџ    ЪNVisioInformation"џџџџЎџџџџЛSummaryInformation(џџџџЏџџџџA FDocumentSummaryInformation8џџџџџџџџџџџџМоOle
 
 

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