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OpenRISC 1200
IP Core
Specification


Author: Damjan Lampret
lampret@opencores.org


Rev. 0.11
January, 2011




Preliminary Draft
Revision History

Rev.DateAuthorDescription0.128/3/01Damjan LampretFirst Draft0.216/4/01Damjan LampretFirst time published0.329/4/01Damjan LampretAll chapters almost finished. Some bugs hidden waiting for an update. Awaiting feedback.0.416/5/01Damjan LampretSynchronization with OR1K Arch Manual0.524/5/01Damjan LampretFixed bugs0.628/5/01Damjan LampretChanged some SPR addresses.0.706/9/01Damjan LampretSimplified debug unit.0.830/08/10Julius BaxterAdding information about FPU implementation, data cache write-back capability.
PIC behavior update.
Instruction list update.
Update of bits in config registers, bringing into line with latest OR1200   not entirely complete.0.912/9/10Julius BaxterClarified supported parts of OR1K instruction set
Updated core clock input information
Fixed up reference to instruction execute stage cycle table
Added divide cycles to execute stage cycle table
0.101/11/10Julius BaxterAdded FF1/FL1 instructions to supported instructions table.0.1119/1/11Julius BaxterCache information update
Wishbone behavior clarification
Serial integer multiply/divide update
Reset address clarificationTable Of Contents

 TOC \o "1-2" \t "Headeing 1 Name;1" \h HYPERLINK  \l "_toc272"Table Of Contents        3
 HYPERLINK  \l "_toc332"Table Of Figures   5
 HYPERLINK  \l "_toc351"Table Of Tables     6
 HYPERLINK  \l "_toc389"1 7
Introduction 7
 HYPERLINK  \l "_toc395"OpenRISC Family       7
 HYPERLINK  \l "_toc403"OpenRISC 1200 8
 HYPERLINK  \l "_toc414"Features   8
 HYPERLINK  \l "_toc422"2 9
Architecture 9
 HYPERLINK  \l "_toc441"CPU/FPU/DSP       10
 HYPERLINK  \l "_toc511"Data Cache     13
 HYPERLINK  \l "_toc566"Instruction Cache       16
 HYPERLINK  \l "_toc624"Data MMU 18
 HYPERLINK  \l "_toc676"Instruction MMU   20
 HYPERLINK  \l "_toc728"Programmable Interrupt Controller       22
 HYPERLINK  \l "_toc739"Tick Timer     22
 HYPERLINK  \l "_toc751"Power Management Support 23
 HYPERLINK  \l "_toc804"Debug unit     23
 HYPERLINK  \l "_toc813"Clocks & Reset	24
 HYPERLINK  \l "_toc819"WISHBONE Interfaces	24
 HYPERLINK  \l "_toc825"3	26
Operation	26
 HYPERLINK  \l "_toc830"Reset	26
 HYPERLINK  \l "_toc846"CPU/FPU/DSP	27
 HYPERLINK  \l "_toc1733"Data Cache Operation	33
 HYPERLINK  \l "_toc1816"Instruction Cache Operation	36
 HYPERLINK  \l "_toc1864"Data MMU	38
 HYPERLINK  \l "_toc2001"Instruction MMU	42
 HYPERLINK  \l "_toc2125"Programmable Interrupt Controller	45
 HYPERLINK  \l "_toc2143"Tick Timer	45
 HYPERLINK  \l "_toc2149"Power Management	45
 HYPERLINK  \l "_toc2185"Debug Unit	47
 HYPERLINK  \l "_toc2199"Development Interface	47
 HYPERLINK  \l "_toc2446"4	51
Registers	51
 HYPERLINK  \l "_toc2451"Registers list	51
 HYPERLINK  \l "_toc3163"Register VR description	52
 HYPERLINK  \l "_toc3234"Register UPR description	53
 HYPERLINK  \l "_toc3436"Register CPUCFGR description	53
 HYPERLINK  \l "_toc3549"Register DMMUCFGR description	54
 HYPERLINK  \l "_toc3660"Register IMMUCFGR description	54
 HYPERLINK  \l "_toc3771"Register DCCFGR description	55
 HYPERLINK  \l "_toc3924"Register ICCFGR description	56
 HYPERLINK  \l "_toc4074"Register DCFGR description	56
 HYPERLINK  \l "_toc4123"5	58
IO ports	58
 HYPERLINK  \l "_toc4136"Instruction WISHBONE Master Interface	58
 HYPERLINK  \l "_toc4300"Data WISHBONE Master Interface	59
 HYPERLINK  \l "_toc4464"System Interface	59
 HYPERLINK  \l "_toc2199"Development Interface	60
 HYPERLINK  \l "_toc4708"Power Management Interface	60
 HYPERLINK  \l "_toc4881"Interrupt Interface	61
 HYPERLINK  \l "_toc4912"A	62
Core HW Configuration	62
Table Of Figures

 TOC \c "FIGURE" Figure 1. Core's Architecture	9
Figure 2. CPU/FPU/DSP Block Diagram	10
Figure 3. Block Diagram of Debug Unit	24
Figure 4. Power-Up and Reset Sequence	26
Figure 5. Power-Up and Reset Sequence w/ Gated Clock	26
Figure 6. WISHBONE Write Cycle	33
Figure 7. WISHBONE Block Read Cycle	34
Figure 8. WISHBONE Block Read/Write Cycle	34
Figure 9. WISHBONE Block Read Cycle	37
Figure 10. 32-bit Address Translation Mechanism using Two-Level Page Table	39
Figure 11. 32-bit Address Translation Mechanism using Two-Level Page Table	42
Figure 12. Development Interface Cycles	48
Figure 13. Assertion of External Watchpoint Trigger	50
Figure 14. Core s Interfaces	58 
Table Of Tables

 TOC \c "TABLE" Table 1. Possible Data Cache Configurations of OR1200	13
Table 2. Possible Instruction Cache Configurations of OR1200	16
Table 3. Possible Data TLB Configurations of OR1200	18
Table 4. Possible Instruction TLB Configurations of OR1200	20
Table 5. Block Diagram of the Interrupt Controller	22
Table 6. Power Consumption	23
Table 7: Instructions implemented in OR1200	28
Table 8. Execution Time of Integer Instructions	30
Table 9: Execution time of floating point instructions	31
Table 10. List of Implemented Exceptions	32
Table 11. Protection Attributes for Load/Store Accesses	40
Table 12.  Cached and uncached regions	41
Table 13. Protection Attributes for Instruction Fetch Accesses	43
Table 14.  Cached and uncached regions	44
Table 15. Development Interface Operation Commands	48
Table 16. Status of the Load/Store Unit	49
Table 17. Status of the Instruction Unit	49
Table 18. List of All Registers	52
Table 19. VR Register	53
Table 20. UPR Register	53
Table 21. CPUCFGR Register	54
Table 22. DMMUCFGR Register	54
Table 23. IMMUCFGR Register	55
Table 24. DCCFGR Register	56
Table 25. ICCFGR Register	56
Table 26. DCFGR Register	57
Table 27. Instruction WISHBONE Master Interface  Signals	59
Table 28. Data WISHBONE Master Interface  Signals	59
Table 29. System Interface Signals	60
Table 30. Development Interface	60
Table 31. Power Management Interface	61
Table 32. Interrupt Interface	61
Table 33: Core HW configuration table	62
1
Introduction

Purpose of this document is to define specifications of the OpenRISC 1200 implementation. This specification defines all implementation specific variables that are not part of the general architecture specification. This includes type and size of data and instruction caches, type and size of data and instruction MMUs, details of all execution pipelines, implementation of exception unit, interrupt controller and other supplemental units.
This document does not cover general architecture topics like instruction set, memory addressing modes and other architectural definitions. See OpenRISC 1000 System Architecture Manual for more information about architecture.

OpenRISC Family

OpenRISC 1000 is architecture for a family of free, open source RISC processor cores. As architecture, OpenRISC 1000 allows for a spectrum of chip and system implementations at a variety of price/performance points for a range of applications. It is a 32/64-bit load and store RISC architecture designed with emphasis on performance, simplicity, low power requirements, scalability and versatility. OpenRISC 1000 architecture targets medium and high performance networking, embedded, automotive and portable computer environments.
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All OpenRISC implementations, whose first digit in identification number is  1 , belong to OpenRISC 1000 family. Second digit defines which features of OpenRISC 1000 architecture are implemented and in which way they are implemented. Last two digits define how an implementation is configured before it is used in a real application.

However, at present the OR1200 is the only major RTL implementation of the OR1K architecture spec, and the OR1200 name has stuck, despite the high level of reconfigurability possible that would, strictly speaking, mean the core is either a OR1000, OR1300, etc. So, despite the various features that may or may not be implemented, the core is still only referred to as the OR1200.

OpenRISC 1200

The OR1200 is a 32-bit scalar RISC with Harvard microarchitecture, 5 stage integer pipeline, virtual memory support (MMU) and basic DSP capabilities.
Default caches are 1-way direct-mapped 8KB data cache and 1-way direct-mapped 8KB instruction cache, each with 16-byte line size. Both caches are physically tagged.
By default MMUs are implemented and they are constructed of 64-entry hash based 1-way direct-mpped data TLB and 64-entry hash based 1-way direct-mapped instruction TLB.
Supplemental facilities include debug unit for real-time debugging, high resolution tick timer, programmable interrupt controller and power management support.
When implemented in a typical 0.18u 6LM process it should provide over 300 dhrystone 2.1 MIPS at 300MHz and 300 DSP MAC 32x32 operations, at least 20% more than any other competitor in this class. OR1200 in default configuration has about 1M transistors.

OR1200 is intended for embedded, portable and networking applications. It can successfully compete with latest scalar 32-bit RISC processors in his class and can efficiently run any modern operating system.
Competitors include ARM10, ARC and Tensilica RISC processors.

Features

The following lists the main features of OR1200 IP core:
All major characteristics of the core can be set by the user
High performance of 300 Dhrystone 2.1 MIPS at 300 MHz using 0.18u process
High performance cache and MMU subsystems
WISHBONE SoC Interconnection Rev. B3 compliant interface
 
2
Architecture

 REF _Ref511206923 \h Figure 1 below shows general architecture of OR1200 IP core. It consists of several building blocks: 
CPU/FPU/DSP central block
Direct-mapped data cache
Direct-mapped instruction cache
Data MMU based on hash based DTLB
Instruction MMU based on hash based ITLB
Power management unit and power management interface
Tick timer
Debug unit and development interface
Interrupt controller and interrupt interface
Instruction and Data WISHBONE host interfaces

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Figure  SEQ "Figure" \*Arabic 1. Core's Architecture


CPU/FPU/DSP

CPU/FPU/DSP is a central part of the OR1200 RISC processor.  REF _Ref511208730 \h Figure 2 shows basic block diagram of the CPU/DSP. Not pictured are the FPU components.
OR1200 CPU/FPU/DSP ony implements sections of the ORBIS32 and ORFPX32 instruction set. No ORBIS64, ORFBX64 or ORVDX64 instructions are  implemented in OR1200.

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Figure  SEQ "Figure" \*Arabic 2. CPU/FPU/DSP Block Diagram

Instruction unit

The instruction unit implements the basic instruction pipeline, fetches instructions from the memory subsystem, dispatches them to available execution units, and maintains a state history to ensure a precise exception model and that operations finish in order. It also executes conditional branch and unconditional jump instructions.
The sequencer can dispatch a sequential instruction on each clock if the appropriate execution unit is available. The execution unit must discern whether source data is available and to ensure that no other instruction is targeting the same destination register.

Instruction unit handles only ORBIS32 and, optionally, a subset of the ORFPX32 instruction class. Some ORFPX32 and all ORFPX3264 and ORVDX64 instruction classes are not supported by the OR1200 at present.

General-Purpose Registers

OpenRISC 1200 implements 32 general-purpose 32-bit registers. OpenRISC 1000 architecture also support shadow copies of register file to implement fast switching between working contexts, however this feature is not implemented in current OR1200 implementation.

OR1200 implements general-purpose register file as two synchronous dual-port memories with capacity of 32 words by 32 bits per word.

Load/Store Unit

The load/store unit (LSU) transfers all data between the GPRs and the CPU's internal bus. It is implemented as an independent execution unit so that stalls in memory subsystem only affect master pipeline if there is a data dependency.
The following are LSU's main features:
all load/store instruction implemented in hardware (atomic instructions included)
address entry buffer
pipelined operation
aligned accesses for fast memory access

When load and store instructions are issued, the LSU determines if all operands are available. These operands include the following:
address register operand
source data register operand (for store instructions)
destination data register operand (for load instructions)

Integer Execution Pipeline

The core implements the following types of 32-bit integer instructions:
Arithmetic instructions
Compare instructions
Logical instructions
Rotate and shift instructions

Most integer instructions can execute in one cycle. For details about timing see Table 8. Execution Time of Integer Instructions .

MAC Unit

The MAC unit executes DSP MAC operations. MAC operations are 32x32 with 48-bit accumulator. MAC unit is fully pipelined and can accept new MAC operation in each new clock cycle.

Floating Point Unit

The FPU implementation is based on two other FPUs available from OpenCores.org For the comparison and conversion functions, parts were taken from the FPU project by Rudolf Usselmann, and for the arithmetic operations, the fpu100 project by Jidan Al-Eryani was converted to Verilog HDL.

All ORFPX32 instructions except for lf.madd.s and lf.rem.s are supported when the FPU is enabled in the OR1200 configuration.

System Unit

The system unit connects all other signals of the CPU/FPU/DSP that are not connected through instruction and data interfaces. It also implements all system special-purpose registers (e.g. supervisor register).

Exceptions

Core exceptions can be generated when an exception condition occurs. Exception sources in OR1200 include the following:
External interrupt request
Certain memory access condition
Internal errors, such as an attempt to execute unimplemented opcode
System call
Internal exception, such as breakpoint exceptions

Exception handling is transparent to user software and uses the same mechanism to handle all types of exceptions. When an exception is taken, control is transferred to an exception handler at an offset defined by for the type of exception encountered. Exceptions are handled in supervisor mode.

Data Cache

The default configuration of OR1200 data cache is 8-Kbyte, 1-way direct-mapped data cache, which allows rapid core access to data. However data cache can be configured according to the  REF _Ref512098491 \h Table 1.

Direct mapped16B/line, 256 lines, 1 way4KB16B/line, 512 lines, 1 way8KB (default)16B/line, 1024 lines, 1 way16KB32B/line, 1024 lines, 1 way32KBTable  SEQ "Table" \*Arabic 1. Possible Data Cache Configurations of OR1200

It is possible to operate the data cache with write-through or write-back strategies, however write-back is currently experimental.

Features:
data cache is separate from instruction cache (Harvard architecture)
data cache implements a least-recently used (LRU) replacement algorithm within each set
the cache directory is physically addressed. The physical address tag is stored in the cache directory
write-through or write-back operation
entire cache can be disabled, lines invalidated, flushed or forced to be written back, by writing to cache special purpose registers

On a miss, and appropriate conditions, the cache line is filled or emptied (written back) with 16-byte bursts. The burst fill is performed as a critical-word-first operation; the critical word is simultaneously written to the cache and forwarded to the requesting unit, thus minimizing stalls due to cache fill latency. Data cache provides storage for cache tags and performs cache line replacement function.
Data cache is tightly coupled to external interface to allow efficient access to the system memory controller.
The data cache supplies data to the GPRs by means of a 32-bit interface to the load/store unit. The LSU provides all logic required to calculate effective addresses, handles data alignment to and from the data cache, and provides sequencing for load and store operations. Write operations to the data cache can be performed on a byte, half-word or word basis.

 EMBED Microsoft Visio Drawing 

Each line contains four contiguous words from memory that are loaded from a cache line aligned boundary. As a result, cache lines are aligned with page boundaries.

Instruction Cache

The default configuration of OR1200 instruction cache is 8-Kbyte, 1-way direct mapped instruction cache, which allows rapid core access to instructions. However instruction cache can be configured according to the  REF _Ref512099081 \h .

Direct mapped16B/line, 32 lines, 1 way512B16B/line, 256 lines, 1 way4KB16B/line, 512 lines, 1 way8KB (Default)16B/line, 1024 lines, 1 way16KB32B/line, 1024 lines, 1 way32KBTable  SEQ "Table" \*Arabic 2. Possible Instruction Cache Configurations of OR1200

Features:
instruction cache is separate from data cache (Harvard architecture)
instruction cache implements a least-recently used (LRU) replacement algorithm within each set
the cache directory is physically addressed. The physical address tag is stored in the cache directory
it can be disabled or invalidated by writing to cache special purpose registers

On a miss, the cache is filled in with 16-byte bursts. The burst fill is performed as a critical-word-first operation; the critical word is simultaneously written to the cache and forwarded to the requesting unit, thus minimizing stalls due to cache fill latency. Instruction cache provides storage for cache tags and performs cache line replacement function.
Instruction cache is tightly coupled to external interface to allow efficient access to the system memory controller.
The instruction cache supplies instructions to the instruction sequencer by means of a 32-bit interface to the instruction fetch subunit. The instruction fetch subunit provides all logic required to calculate effective addresses.

 EMBED Microsoft Visio Drawing 

Each line contains four contiguous words from memory that are loaded from a line-size       
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 !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~  aligned boundary. As a result, cache lines are aligned with page boundaries.

Data MMU

The OR1200 implements a virtual memory management scheme that provides memory access protection and effective-to-physical address translation. Protection granularity is as defined by OpenRISC 1000 architecture - 8-Kbyte and 16-Mbyte pages.

Direct mapped16 entries per way16 DTLB entries32 entries per way32 DTLB entries64 entries per way64 DTLB entries (default)128 entries per way128 DTLB entriesTable  SEQ "Table" \*Arabic 3. Possible Data TLB Configurations of OR1200

Features:
data MMU is separate from instruction MMU
page size 8-Kbyte
comprehensive page protection scheme
direct mapped hash based translation lookaside buffer (DTLB) with the default of 1 way and the following features:
miss and fault exceptions
software tablewalk
high performance because of hashed based design
variable number DTLB entries with default of 64 per each way

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The MMU hardware supports two-level software tablewalk.

Instruction MMU

The OR1200 implements a virtual memory management scheme that provides memory access protection and effective-to-physical address translation. Protection granularity is as defined by OpenRISC 1000 architecture - 8-Kbyte and 16-Mbyte pages.

Direct mapped16 entries per way16 DTLB entries32 entries per way32 DTLB entries64 entries per way64 DTLB entries (default)128 entries per way128 DTLB entriesTable  SEQ "Table" \*Arabic 4. Possible Instruction TLB Configurations of OR1200

Features:
instruction MMU is separate from data MMU
pages size 8-Kbyte
comprehensive page protection scheme
1 way direct-mapped hash based translation lookaside buffer (ITLB) with the following features:
miss and fault exceptions
software tablewalk
high performance because of hashed based design
Variable number of ITLB entries with default of 64 entries per way

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The MMU hardware supports two-level software tablewalk.

Programmable Interrupt Controller

The interrupt controller receives interrupts from external sources and forwards them as low or high priority interrupt exception to the CPU core.


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Table  SEQ "Table" \*Arabic 5. Block Diagram of the Interrupt Controller

Programmable interrupt controller has three special-purpose registers and 32 interrupt inputs. Interrupt input 0 and 1 are always enabled and connected to high and low priority interrupt input, respectively.
30 other interrupt inputs can be masked and assigned low or high priority through programming special-purpose registers.

Tick Timer

OR1200 implements tick timer facility. Basically this is a timer that is clocked by RISC clock and is used by the operating system to precisely measure time and schedule system tasks.

OR1200 precisely follow architectural definition of the tick timer facility:
Maximum timer count of 2^32 clock cycles
Maximum time period of 2^28 clock cycles between interrupts
Maskable tick timer interrupt
Single run, restartable or continues timer

Tick timer operates from independent clock source so that doze power management mode can be implemented.

Power Management Support

To optimize power consumption, the OR1200 provides low-power modes that can be used to dynamically activate and deactivate certain internal modules.

OR1200 has three major features to minimize power consumption:
Slow and Idle Modes (SW controlled clock freq reduction)
Doze and Sleep Modes (interrupt wake-up)

Power Minimization FeatureApprox Power Consumption ReductionSlow and Idle mode2x   10xDoze mode100xSleep mode200xDynamic clock gatingN/ATable  SEQ "Table" \*Arabic 6. Power Consumption

Slow down mode takes advantage of the low-power dividers in external clock generation circuitry to enable full functionality, but at a lower frequency so that a power consumption is reduced.
PMR[SDF] 4 bits are broadcasted on pm_clksd and external clock generation for the RISC should adapt RISC clock frequency according to the value on pm_clksd.

When software initiates the doze mode, software processing on the core suspends. The clocks to the RISC internal modules are disabled except to the tick timer. However any other on-chip blocks can continue to function as normal.
The OR1200 will leave doze mode and enter normal mode when a pending interrupt occurs.

In sleep mode, all OR1200 internal units are disabled and clocks gated. Optionally implementation may choose to lower the operating voltage of the OR1200 core.
The OR1200 should leave sleep mode and enter normal mode when a pending interrupt occurs.

Dynamic Clock gating (unit clock gating on clock by clock basis) is not supported by OR1200.

Debug unit

Debug unit assists software developers to debug their systems. It provides support only for basic debugging and does not have support for more advanced debug features of OpenRISC 1000 architecture such as watchpoints, breakpoints and program-flow control registers.

 EMBED Microsoft Visio Drawing 
Figure  SEQ "Figure" \*Arabic 3. Block Diagram of Debug Unit

Watchpoints and breakpoints are events triggered by program- or data-flow matching the conditions programmed in the debug registers. Breakpoints unlike watchpoints also suspend execution of the current program-flow and start breakpoint exception.

Clocks & Reset

The OR1200 core has a clock input each for the instruction and data Wishbone interface logic, and for the CPU core. Clock input clk_cpu clocks everything inside the Wishbone interfaces. Data Wishbone interface is clocked by dwb_clk_i, instruction Wishbone interface is clocked by iwb_clk_i.

OR1200 has asynchronous reset signal. Reset signal rst, when asserted high, immediately resets all flip-flops inside OR1200. When deasserted, OR1200 will start reset exception.

WISHBONE Interfaces

Two WISHBONE interfaces connect OR1200 core to external peripherals and external memory subsystem. They are WISHBONE SoC Interconnection specification Rev. B3 compliant. The implementation implements a 32-bit bus width and does not support other bus widths.
Wishbone registered-feedback incrementing burst accesses occur when not disabled, and cache lines are filled. The burst size (beats) is determined by the cache line size.


3
Operation

This section describes the operation of the OR1200 core. For operations that pertain to the architectural definitions, see OpenRISC 1000 System Architecture Manual.

Reset

OR1200 has one asynchronous reset signal that can be used by a soft and hard reset on a higher system hierarchy levels.

 EMBED  
Figure  SEQ "Figure" \*Arabic 4. Power-Up and Reset Sequence

 REF _Ref513206810 \h Figure 4 shows how asynchronous reset is applied after powering up the OR1200 core. Reset is connected to asynchronous reset of almost all flip-flops inside RISC core. Special care must be taken to ensure hold and setup times of all flip-flops compared to main RISC clock.

If system implements gated clocks, then clock gating can be used to ensure proper reset timing.

 EMBED  
Figure  SEQ "Figure" \*Arabic 5. Power-Up and Reset Sequence w/ Gated Clock

The address the PC assumes at hard reset (assertion of external reset signal) is definable at synthesis time, via the OR1200_BOOT_ADR define. This is not to be confused with the ability to set the exception prefix address with the EPH bit.

CPU/FPU/DSP

CPU/FPU/DSP is implementation of the 32-bit part of the OpenRISC 1000 architecture and only a subset of all features is implemented.


Instructions

The following table lists the instructions implemented in the OR1200. Those optionally implemented are indicated as such.
Instruction 
mnemonicOpt.Instruction 
mnemonicOpt.Instruction 
mnemonicOpt.Instruction 
mnemonicOpt.l.addl.macrcYl.shlf.sflt.sYl.addcYl.msbYl.slllf.sfne.sYl.addil.mfsprl.sllilf.sub.sYl.andl.movhil.sral.andil.mtsprl.srail.bfl.mulYl.srll.bnfl.muliYl.srlil.divYl.nopl.subYl.ff1Yl.orl.swl.fl1Yl.oril.sysl.jl.rfel.trapl.jall.roril.xorl.jalrl.sbl.xoril.jrl.sfeqlf.add.sYl.lbsl.sfgeslf.div.sYl.lbzl.sfgeulf.ftoi.sYl.lhsl.sfgtslf.itof.sYl.lhzl.sfgtulf.mul.sYl.lwsl.sfleulf.sfeq.sYl.lwzl.sfltslf.sfge.sYl.macYl.sfltulf.sfgt.sYl.maciYl.sfnelf.sfle.sYTable  SEQ "Table" \*Arabic 7: Instructions implemented in OR1200
For a complete description of each instruction's format refer to the OpenRISC 1000 System Architecture Manual.

Instruction Unit

Instruction unit generates instruction fetch effective address and fetches instructions from instruction cache. Each clock cycle one instruction can be fetched. Instruction fetch EA is further translated into physical address by IMMU.

General-Purpose Registers

General-purpose register file can supply two read operands each clock cycle and store one result in a destination register.

GPRs can be also read and written through development interface.

Load/Store Unit

LSU can execute one load instruction every two clock cycles assuming load instruction have a hit in the data cache. Execution of store instructions takes one clock cycle assuming they have a hit in the data cache.

LSU performs calculation of the load/store effective address. EA is further translated into physical address by DMMU.

Load/store effective address and load and store data can be also accessed through development interface.





















Integer Execution Pipeline

The core implements the following types of 32-bit integer instructions:
Arithmetic instructions
Compare instructions
Logical instructions
Rotate and shift instructions

Instruction GroupClock Cycles to ExecuteArithmetic except Multiply/Divide1Multiply3Divide32Compare1Logical1Rotate and Shift1Others1Table  SEQ "Table" \*Arabic 8. Execution Time of Integer Instructions

 REF _Ref513308588 \h Table 8 lists execution times for instructions executed by integer execution pipeline. Most instructions are executed in one clock cycle.

Integer multiply can be either serial or parallel implementations. Serial operations require one clock cycle per bit of operand, which is 32-cycles on the OR1200. At present no synthesis tools support division operators, and so the serial option must be used.

MAC Unit

MAC unit executes l.mac instructions. MAC unit implements 32x32 fully pipelined multiplier and 48-bit accumulator. MAC unit can accept one new l.mac instruction each clock cycle.
Care should be taken when executing l.macrc (MAC read and clear) too soon after the final l.mac instruction as the operation may still be underway and the result will not be valid in time. It is recommended at least 3 other instructions (or just l.nops) are inserted between the final l.mac and l.macrc.

Floating Point Unit
The floating point unit has a mechanism to stall the processor pipeline until processing has completed.
The following table indicates the number of cycles per operation

OperationCyclesAdd/subtract10Multiply38Divide37Compare2Convert7Table  SEQ "Table" \*Arabic 9: Execution time of floating point instructions

System Unit

System unit implements system control and status special-purpose registers and executes all l.mtspr/l.mfspr instructions.


























Exceptions

The core implements a precise exception model. This means that when an exception is taken, the following conditions are met:
Subsequent instructions in program flow are discarded
Previous instructions finish and write back their results
The address of faulting instruction is saved in EPCR registers and the machine state is saved to ESR registers

Exception TypeVector Offsetcausing conditionsReset0x100Caused by reset.Bus Error0x200Caused by an attempt to access invalid physical address.Data Page Fault0x300Generated artificially by DTLB miss exception handler when no matching PTE found in page tables or page protection violation for load/store operations.Instruction Page Fault0x400Generated artificially by ITLB miss exception handler when no matching PTE found in page tables or page protection violation for instruction fetch.Low Priority External Interrupt0x500Low priority external interrupt asserted.Alignment0x600Load/store access to naturally not aligned location.Illegal Instruction0x700Illegal instruction in the instruction stream.High Priority External Interrupt0x800High priority external interrupt asserted.D-TLB Miss0x900No matching entry in DTLB (DTLB miss).I-TLB Miss0xA00No matching entry in ITLB (ITLB miss).System Call0xC00System call initiated by software.Floating point exception0xD00FP operation caused flags in FPCSR to become set.Trap0xE00Trap instruction was decodedTable  SEQ "Table" \*Arabic 10. List of Implemented Exceptions
The OR1200 exception support does not include support for range exceptions or fast context switching.

Data Cache Operation

Data Cache Load/Store Access

Load/store unit requests data from the data cache and stores them into the general-purpose register file and forwards them to integer execution units. Therefore LSU is tightly coupled with the data cache.

If there is no data cache line miss nor DTLB miss, load operations take two clock cycles to execute and store operations take one clock cycle to execute. LSU does all the data alignment work.

Data can be written to the data cache on a word, half-word or byte basis. Since data cache only operates in write-through mode, all writes are immediately written back to main memory or to the next level of caches.

 EMBED  
Figure  SEQ "Figure" \*Arabic 6. WISHBONE Write Cycle

 REF _Ref513193242 \h Figure 6 shows how a write-through cycle on data WISHBONE interface is performed when a store instruction hits in the data cache.
If dwb_ERR_I or dwb_RTY_I is asserted instead of usual dwb_ACK_I, bus error exception is invoked.

Data Cache Line Fill Operation

When executing load instruction and a cache miss occurs, depending on whether the cache uses write-through or write-back strategy and the line is clean or invalid, a 4 beat sequential read burst with critical word first is performed. If the strategy is write-back and the line is dirty, the line is first written back to memory. The critical word is forwarded to the load/store unit to minimize performance loss because of the cache miss.

 EMBED  
Figure  SEQ "Figure" \*Arabic 7. WISHBONE Block Read Cycle

 REF _Ref513194821 \h Figure 7 shows how a cache line is read in WISHBONE read block cycle composed out of four read transfers.
If dwb_ERR_I or dwb_RTY_I is asserted instead of usual dwb_ACK_I, bus error exception is invoked.

When executing a store instruction with the cache in write-through strategy, and a cache miss occurs, the write is simply put on the bus and no caching occurs. If it is a miss and the cache is in write back strategy and the line is valid and clean or invalid,  a 4 beat sequential read burst to fill the line is performed, and the the write to cache occurs. If storing and a cache miss occurs, and the desired line is valid and dirty, it is first written back to memory before the desired line is read.


 EMBED  
Figure  SEQ "Figure" \*Arabic 8. WISHBONE Block Read/Write Cycle

 REF _Ref513195072 \h Figure 8 shows how a cache line is read in WISHBONE read block cycle followed by a write transfer.
If dwb_ERR_I or dwb_RTY_I is asserted instead of usual dwb_ACK_I, bus error exception is invoked.

Cache/Memory Coherency

Data cache in OR1200 operates in either write-through or write-back mode, definable at synthesis time, for default use, and runtime when DMMU is used. There is currently no coherency support between local data cache and caches of other processors.

Data Cache Enabling/Disabling

Data cache is disabled at power up. Entire data cache can be enabled by setting bit SR[DCE] to one. Before data cache is enabled, it must be invalidated.

Data Cache Invalidation

Data cache in OR1200 does not support invalidation of entire data cache. Normal procedure to invalidate entire data cache is to cycle through all data cache lines and invalidate each line separately.

Data Cache Locking

Data cache implements way locking bits in data cache control register DCCR. Bits LWx lock individual ways when they are set to one.

Data Cache Line Prefetch

Data cache line prefetch is optional in the OpenRISC 1000 architecture and is not implemented in OR1200.

Data Cache Line Flush

Operation is performed by writing effective address to the DCBFR register.

When a cache line is valid and clean, or the cache is in write-through strategy, the line is invalidated and no write-back occurs.

Data Cache Line Invalidate

Data cache line invalidate invalidates a single data cache line. Operation is performed by writing effective address to the DCBIR register.
If cache is in write-back strategy, it is best to use the line flush function.

Data Cache Line Write-back

Operation is performed by writing effective address to the DCBWR register.

If cache is in write-through strategy, this operation is ignored as no lines will be cached and dirty, capable of being written back.

Data Cache Line Lock

Locking of individual data cache lines is not implemented in OR1200.

Data Cache inhibit with address bit 31 set

If DMMU is disabled, by default all addresses with bit 31 of the address asserted high will cause the data cache to be inhibited, meaning no reads or writes are cached.

If the DMMU is enabled, it is possible for any address to be inhibited or not, and in these modes the cache behaves accordingly.


Instruction Cache Operation

Instruction Cache Instruction Fetch Access

Instruction unit requests instruction from the instruction cache and forwards them to the instruction queue inside instruction unit. Therefore instruction unit is tightly coupled with the instruction cache.

If there is no instruction cache line miss nor ITLB miss, instruction fetch operation takes one clock cycle to execute.

Instruction cache cannot be explicitly modified like data cache can be with store instructions.

Instruction Cache Line Fill Operation

On a cache miss, a 4 beat sequential read burst with critical word first is performed. Critical word is forwarded to the instruction unit to minimize performance loss because of the cache miss.

 EMBED  
Figure  SEQ "Figure" \*Arabic 9. WISHBONE Block Read Cycle

 REF _Ref513197552 \h Figure 9 shows how a cache line is read in WISHBONE read block cycle composed out of four read transfers.
If iwb_ERR_I or iwb_RTY_I is asserted instead of usual dwb_ACK_I, bus error exception is invoked.

Cache/Memory Coherency

OR1200 is not intended for use in multiprocessor environments. Therefore no support for coherency between local instruction cache and caches of other processors or main memory is implemented.

Instruction Cache Enabling/Disabling

Instruction cache is disabled at power up. Entire instruction cache can be enabled by setting bit SR[ICE] to one. Before instruction cache is enabled, it must be invalidated.

Instruction Cache Invalidation

Instruction cache in OR1200 does not support invalidation of entire instruction cache. Normal procedure to invalidate entire instruction cache is to cycle through all instruction cache lines and invalidate each line separately.

Instruction Cache Locking

Instruction cache implements way locking bits in instruction cache control register ICCR. Bits LWx lock individual ways when they are set to one.

Instruction Cache Line Prefetch

Instruction cache line prefetch is optional in the OpenRISC 1000 architecture and is not implemented in OR1200.

Instruction Cache Line Invalidate

Instruction cache line invalidate invalidates a single instruction cache line. Operation is performed by writing effective address to the ICBIR register.

Instruction Cache Line Lock

Locking of individual instruction cache lines is not implemented in OR1200.

Data MMU

Translation Disabled

Load/store address translation can be disabled by clearing bit SR[DME]. If translation is disabled, then physical address used to access data cache and optionally provided on dwb_ADDR_O, is the same as load/store effective address.

Translation Enabled

Load/store address translation can be enabled by setting bit SR[DME]. If translation is enabled, it provides load/store effective address to physical address translation and page protection for memory accesses.

 EMBED Microsoft Visio Drawing 
Figure  SEQ "Figure" \*Arabic 10. 32-bit Address Translation Mechanism using Two-Level Page Table

In OR1200 case, page tables must be managed by operating system s virtual memory management subsystem.  REF _Ref513343227 \h Figure 10 shows address translation using two-level page table. Refer to OpenRISC 1000 System Architecture Manual for one-level page table address translation as well as for details about address translation and page table content.

DMMUCR and Flush of Entire DTLB

DMMUCR is not implemented in OR1200. Therefore page table base pointer (PTBP) must be stored in software variable. Flush of entire DTLB must be performed by software flush of every DTLB entry separately. Software flush is performed by manually writing  bits from the TLB entries back to PTEs.

Page Protection

After a virtual address is determined to be within a page covered by the valid PTE, the access is validated by the memory protection mechanism. If this protection mechanism prohibits the access, a data page fault exception is generated.

The memory protection mechanism allows selectively granting read access and write access for both supervisor and user modes. The page protection mechanism provides protection at all page level granularities.

Protection attributeMeaningDTLBWyTR[SREx]Enable load operations in supervisor mode to the page.DTLBWyTR[SWEx]Enable store operations in supervisor mode to the page.DTLBWyTR[UREx]Enable load operations in user mode to the page.DTLBWyTR[UWEx]Enable store operations in user mode to the page.Table  SEQ "Table" \*Arabic 11. Protection Attributes for Load/Store Accesses

 REF _Ref513346094 \h Table 11 lists page protection attributes defined in DTLBWyTR pregister. For the individual page appropriate strategy out of seven possible strategies programmed with the PPI field of the PTE. Because OR1200 does not implement DMMUPR, translation of PTE[PPI] into suitable set of protection bits must be performed by software and written into DTLBWyTR.

DTLB Entry Reload

OR1200 does not implement DTLB entry reloads in hardware. Instead software routine must be used to search page table for correct page table entry (PTE) and copy it into the DTLB. Software is responsible for maintaining accessed and dirty bits in the page tables.

When LSU computes load/store effective address whose physical address is not already cached by DTLB, a DTLB miss exception is invoked.

DTLB reload routine must load the correct PTE to correct DTLBWyMR and DTLBWyTR register from one of possible DTLB ways.

DTLB Entry Invalidation

Special-purpose register DTLBEIR must be written with the effective address and corresponding DTLB entry will be invalidated in the local DTLB.

Locking DTLB Entries

Since all DTLB entry reloads are performed in software, there is no hardware locking of DTLB entries. Instead it is up to the software reload routine to avoid replacing some of the entries if so desired.

Page Attribute   Dirty (D)

Dirty (D) attribute is not implemented in OR1200 DTLB. It is up to the operating system to generate dirty attribute bit with page protection mechanism.

Page Attribute   Accessed (A)

Accessed (A) attribute is not implemented in OR1200 DTLB. It is up to the operating system to generate accessed attribute bit with page protection mechanism.

Page Attribute   Weakly Ordered Memory (WOM)

Weakly ordered memory (WOM) attribute is not needed in OR1200 because all memory accesses are serialized and therefore this attribute is not implemented.

Page Attribute   Write-Back Cache (WBC)

Write-back cache (WBC) attribute is not implemented as the data cache cannot be configured at run time to be write-back enabled if write-through strategy was selected at synthesis-time.

Page Attribute   Caching-Inhibited (CI)

Caching-inhibited (CI) attribute is not implemented in OR1200 DTLB. Cached and uncached regions are divided by bit 30 of data effective address.

Effective AddressRegion0x00000000 - 0x3FFFFFFFCached0x40000000 - 0x7FFFFFFFUncached0x80000000 - 0xBFFFFFFFCached0xC0000000 - 0xFFFFFFFFUncachedTable  SEQ "Table" \*Arabic 12.  Cached and uncached regions

Uncached accesses must be performed when I/O registers are memory mapped and all reads and writes must be always performed directly to the external interface and not to the data cache.

Page Attribute   Cache Coherency (CC)

Cache coherency (CC) attribute is not needed in OR1200 because it doesn t implement support for multiprocessor environments and because data cache operates only in write-through mode and therefore this attribute is not implemented.

Instruction MMU

Translation Disabled

Instruction fetch address translation can be disabled by clearing bit SR[IME]. If translation is disabled, then physical address used to access instruction cache and optionally provided on iwb_ADDR_O, is the same as instruction fetch effective address.

Translation Enabled

Instruction fetch address translation can be enabled by setting bit SR[IME]. If translation is enabled, it provides instruction fetch effective address to physical address translation and page protection for instruction fetch accesses.

 EMBED Microsoft Visio Drawing 
Figure  SEQ "Figure" \*Arabic 11. 32-bit Address Translation Mechanism using Two-Level Page Table

In OR1200 case, page tables must be managed by operating system s virtual memory management subsystem.  REF _Ref513343227 \h Figure 10 shows address translation using two-level page table. Refer to OpenRISC 1000 System Architecture Manual for one-level page table address translation as well as for details about address translation and page table content.

IMMUCR and Flush of Entire ITLB

IMMUCR is not implemented in OR1200. Therefore page table base pointer (PTBP) must be stored in software variable. Flush of entire ITLB must be performed by software flush of every ITLB entry separately. Software flush is performed by manually writing bits from the TLB entries back to PTEs.

Page Protection

After a virtual address is determined to be within a page covered by the valid PTE, the access is validated by the memory protection mechanism. If this protection mechanism prohibits the access, an instruction page fault exception is generated.

The memory protection mechanism allows selectively granting execute access for both supervisor and user modes. The page protection mechanism provides protection at all page level granularities.

Protection attributeMeaningITLBWyTR[SXEx]Enable execute operations in supervisor mode of the page.ITLBWyTR[UXEx]Enable execute operations in user mode of the page.Table  SEQ "Table" \*Arabic 13. Protection Attributes for Instruction Fetch Accesses

 REF _Ref513346094 \h Table 11 lists page protection attributes defined in ITLBWyTR pregister. For the individual page appropriate strategy out of seven possible strategies programmed with PPI field of the PTE. Because OR1200 does not implement IMMUPR, translation of PTE[PPI] into suitable set of protection bits must be performed by software and written into ITLBWyTR.


ITLB Entry Reload

OR1200 does not implement ITLB entry reloads in hardware. Instead software routine must be used to search page table for correct page table entry (PTE) and copy it into the ITLB. Software is responsible for maintaining accessed bit in the page tables.

When LSU computes instruction fetch effective address whose physical address is not already cached by ITLB, an ITLB miss exception is invoked.

ITLB reload routine must load the correct PTE to correct ITLBWyMR and ITLBWyTR register from one of possible ITLB ways.

ITLB Entry Invalidation

Special-purpose register ITLBEIR must be written with the effective address and corresponding ITLB entry will be invalidated in the local ITLB.

Locking ITLB Entries

Since all ITLB entry reloads are performed in software, there is no hardware locking of ITLB entries. Instead it is up to the software reload routine to avoid replacing some of the entries if so desired.

Page Attribute   Dirty (D)

Dirty (D) attribute resides in the PTE but it is not used by the IMMU.

Page Attribute   Accessed (A)

Accessed (A) attribute is not implemented in OR1200 ITLB. It is up to the operating system to generate accessed attribute bit with page protection mechanism.

Page Attribute   Weakly Ordered Memory (WOM)

Weakly ordered memory (WOM) attribute is not needed in OR1200 because all instruction fetch accesses are serialized and therefore this attribute is not implemented.

Page Attribute   Write-Back Cache (WBC)

Write-back cache (WBC) attribute resides in the PTE but it is not used by the IMMU.

Page Attribute   Caching-Inhibited (CI)

Caching-inhibited (CI) attribute is not implemented in OR1200 ITLB. Cached and uncached regions are divided by bit 30 of instruction effective address.

Effective AddressRegion0x00000000 - 0x3FFFFFFFCached0x40000000 - 0x7FFFFFFFUncached0x80000000 - 0xBFFFFFFFCached0xC0000000 - 0xFFFFFFFFUncachedTable  SEQ "Table" \*Arabic 14.  Cached and uncached regions

Page Attribute   Cache Coherency (CC)

Cache coherency (CC) attribute resides in the PTE but it is not used by the IMMU.

Programmable Interrupt Controller

PICMR special-purpose register is used to mask or unmask up to 30 programmable interrupt sources. PICPR special-purpose register is used to assign low or high priority to maximum of 30 interrupt sources.

PICSR special-purpose register is used to determine status of each interrupt input. Bits in PICSR represent status of the interrupt inputs and the actual interrupt must be cleared in the device that is the source of a pending interrupt.

The PIC implementation in the OR1200  differs from the architecture specification. The PIC instead offers a latched level-sensitive interrupt.

Once an interrupt line is latched (i.e. its value appears in PICSR), no new interrupts can be triggered for that line until its bit in PICSR is cleared. The usual sequence for an interrupt handler is then as follows.

Peripheral asserts interrupt, which is latched and triggers handler. 
Handler processes interrupt.
Handler notifies peripheral that the interrupt has been processed (typically via a memory mapped register).
 Peripheral deasserts interrupt.
Handler clears corresponding bit in PICSR and returns.

It is assumed that the peripheral will de-assert its interrupt promptly (within 1-2 cycles). Otherwise on exiting the interrupt handler, having cleared PICSR, the level sensitive interrupt will immediately retrigger.

Tick Timer

Tick timer facility is enabled with TTMR[M]. TTCR is incremented with each clock cycle and a high priority interrupt can be asserted whenever lower 28 bits of TTCR match TTMR[TP] and TTMR[IE] is set.

TTCR restarts counting from zero when match event happens and TTMR[M] is 0x1. If TTMR[M] is 0x2, TTCR is stoped when match event happens and TTCR must be changed to start counting again. When TTMR[M] is 0x3, TTCR keeps counting even when match event happens.

Power Management

Clock Gating and Frequency Changing Versus CPU Stalling

If system doesn t support clock gating and if changing clock frequency in slow down mode is not possible, CPU can be stalled for certain number of clock cycles. This is much lower benefit on power consumption however it still reduces power consumption.

Slow Down Mode

Slow down mode is software controlled with the 4-bit value in PMR[SDF]. Lower value specifies higher expected performance from the processor core. Usually PMR[SDF] is dynamically set by the operating system s idle routine, that monitors the usage of the processor core.

PMR[SDF] is broadcasted on pm_clksd. External clock generator should adjust clock frequency according to the value of pm_clksd. Exact slow down factors are not defined but 0xF should go all the way down to 32.768 KHz.

With pm_clksd equal to 0xF, pm_lvolt is asserted. This is an indication for the external power supply to lower the voltage.

Doze Mode

To switch to doze mode, software should set the PMR[DME]. Once an interrupt is received by the programmable interrupt controller (PIC), pm_wakeup is asserted and external clock generation circuitry should enable all clocks. Once clocks are running RISC is switched back again to the normal mode and PMR[DME] is cleared.

When doze mode is enabled, pm_dc_gate, pm_ic_gate, pm_dmmu_gate, pm_immu_gate and pm_cpugate are asserted. As a result all clocks except clk_tt should be gated by external clock generation circuitry.

Sleep Mode

To switch to sleep mode, software should set the PMR[SME]. Once an interrupt is received by the programmable interrupt controller (PIC), pm_wakeup is asserted and external clock generation should enable all clocks. Once clocks are running, RISC is switched back again to the normal mode and PMR[SME] is cleared.

When sleep mode is enabled, pm_dc_gate, pm_ic_gate, pm_dmmu_gate, pm_immu_gate, pm_cpu_gate and pm_tt_gate are asserted. As a result all clocks including clk_tt should be gated by external clock generation circuitry.

In sleep mode, pm_lvolt is asserted. This is an indication for the external power supply to lower the voltage.

Clock Gating

Clock gating feature is not implemented in OR1200 power management. 

Disabled Units Force Clock Gating

Units that are disabled in special-purpose register SR, have their clock gate signals asserted. Cleared bits SR[DCE], SR[ICE], SR[DME] and SR[IME] directly force assertion of pm_dc_gate, pm_ic_gate, pm_dmmu_gate and pm_immu_gate.

Debug Unit

Debug unit can be controlled through development interface or it can operate independently programmed and handled by the RISC s resident debug software.

Watchpoints

OR1200 debug unit does not implement OR12000 architecture watchpoints.

Breakpoint Exception

Which breakpointDMR2[WGB] bits specify which watchpoints invoke breakpoint exception. By invoking breakpoint exception, target resident debugger can be built.

Breakpoint is broadcasted on development interface on dbg_bp_o.

Development Interface

NOTE: The information in this section is to be reviewed. It is the author's opinion that the debug interface is now largely provided by the SPR mappings, and no special sideband functions exist aside from stalling and resetting the core.

An additional development and debug interface IP core may be used to connect OpenRISC 1200 to standard debuggers using IEEE.1149.1 (JTAG) protocol.

Debugging Through Development Interface

The DSR special-purpose register specifies which exceptions cause the core to stop the execution of the exception handler and turn over control to development interface. It can be programmed by the resident debug software or by the development interface.

The DRR special-purpose register is specifies which event caused the core to stop the execution of program flow and turned over control to the development interface. It should be cleared by the resident debug software or by the development interface.

The DIR special-purpose register is not implemented.

Reading PC, Load/Store EA, Load Data, Store Data, Instruction

Crucial information like program counter (PC), load/store effective address (LSEA), load data, store data and current instruction in execution pipeline can be asynchronously read through the development interface.

dbg_op_i[2:0]Meaning0x0Reading Program Counter (PC)0x1Reading Load/Store Effective Address0x2Reading Load Data0x3Reading Store Data0x4Reading SPR0x5Writing SPR0x6Reading Instruction in Execution Pipeline0x7ReservedTable  SEQ "Table" \*Arabic 15. Development Interface Operation Commands

 REF _Ref513329306 \h Table 15 lists operation commands that control what is read or written through development interface. All reads except reads and writes of SPRs are asynchronous.

Reading and Writing SPRs Through Development Interface

For reads and write to SPRs dbg_op_i must be set to 0x4 and 0x5, respectively.

 EMBED  
Figure  SEQ "Figure" \*Arabic 12. Development Interface Cycles

 REF _Ref513329852 \h Figure 12 shows development interface cycles. Writes must be synchronous to the main RISC clock positive edge and should take one clock cycle. Reads must take two clock cycles because access to synchronous cache lines or to TLB entries introduces one clock cycle of delay.

If required, external debugger can stop the CPU core by asserting dbg_stall_i. This way it can have enough time to read all interesting registers from the RISC or guarantee that writes into SPRs are performed without RISC writing to the same registers.

Tracking Data Flow

An external debugger can monitor and record data flow inside the RISC for debugging purposes and profiling analysis. This is accomplished by monitoring status of the load/store unit, load/store effective address and load/store data, all available at the development interface.

dbg_lss_o[3:0]Load/Store Instruction in Execution0x0No load/store instruction in execution0x1Reserved for load doubleword0x2Load byte and zero extend0x3Load byte and sign extend0x4Load halfword and zero extend0x5Load halfword and sign extend0x6Load singleword and zero extend0x7Load singleword and sign extend0x8Reserved for store doubleword0x9Reserved0xAStore byte0xBReserved0xCStore halfword0xDReserved0xEStore singleword0xFReservedTable  SEQ "Table" \*Arabic 16. Status of the Load/Store Unit

External trace buffer can capture all interesting data flow events by analyzing status of the load/store unit available on dbg_lss_o.  REF _Ref513326484 \h Table 16 lists different status encoding for the load/store unit.

Tracking Program Flow

An external debugger can monitor and record program flow inside the RISC for debugging purposes and profiling analysis. This is accomplished by monitoring status of the instruction unit, PC and fetched instruction word, all available at the development interface.

dbg_is_o[1:0]Instruction Fetch Status0x0No instruction fetch in progress0x1Normal instruction fetch0x2Executing branch instruction0x3Fetching instruction in delay slotTable  SEQ "Table" \*Arabic 17. Status of the Instruction Unit

External trace buffer can capture all interesting program flow events by analyzing status of the instruction unit available on dbg_is_o.  REF _Ref513326219 \h Table 17 lists different status encoding for the instruction unit.

Triggering External Watcpoint Event

 REF _Ref513324670 \h Figure 13 shows how development interface can assert dbg_ewt_I and cause watchpoint event. If programmed, external watchpoint event will cause a breakpoint exception.

 EMBED  
Figure  SEQ "Figure" \*Arabic 13. Assertion of External Watchpoint Trigger
4
Registers

This section describes all registers inside the OR1200 core. Shifting GRP number 11 bits left and adding REG number computes the address of each special-purpose register. All registers are 32 bits wide from software perspective. USER MODE and SUPV MODE specify the valid access types for each register in user mode and supervisor mode of operation. R/W stands for read and write access and R stands for read only access.

Registers list

Grp
#Reg #Reg NameUSER MODESUPV
MODEDescription00VR RVersion Register01UPR RUnit Present Register02CPUCFGR RCPU Configuration Register03DMMUCFGR RData MMU Configuration Register04IMMUCFGR RInstruction MMU Configuration Register05DCCFGR RData Cache Configuration Register06ICCFGR RInstruction Cache Configuration Register07DCFGR RDebug Configuration Register016PC R/WPC mapped to SPR space017SR R/WSupervision Register020FPCSR-R/WFP Control Status Register032EPCR0 R/WException PC Register048EEAR0 R/WException EA Register064ESR0 R/WException SR Register01024-1055GPR0-GPR31 R/WGPRs mapped to SPR space12DTLBEIR WData TLB Entry Invalidate Register11024-1151DTLBW0MR0-DTLBW0MR127 R/WData TLB Match Registers Way 011536-1663DTLBW0TR0-DTLBW0TR127 R/WData TLB Translate Registers Way 022ITLBEIR WInstruction TLB Entry Invalidate Register21024-1151ITLBW0MR0-ITLBW0MR127 R/WInstruction TLB Match Registers Way 021536-1663ITLBW0TR0-ITLBW0TR127 R/WInstruction TLB Translate Registers Way 030DCCR R/WDC Control Register32DCBFRWWDC Block Flush Register33DCBIRWWDC Block Invalidate Register34DCBWRWWDC Block Write-back register40ICCR R/WIC Control Register4256ICBIRWWIC Block Invalidate Register5256MACLOR/WR/WMAC Low5257MACHIR/WR/WMAC High616DMR1 R/WDebug Mode Register 1617DMR2 R/WDebug Mode Register 2620DSR R/WDebug Stop Register621DRR R/WDebug Reason Register80PMR R/WPower Management Register90PICMR R/WPIC Mask Register92PICSR R/WPIC Status Register100TTMR R/WTick Timer Mode Register101TTCRR*R/WTick Timer Count RegisterTable  SEQ "Table" \*Arabic 18. List of All Registers

 REF _Ref513309410 \h Table 18 lists all OpenRISC 1000 special-purpose registers implemented in OR1200. Registers VR and UPR are described below. For description of other registers refer to OpenRISC 1000 System Architecture Manual document.

Register VR description

Special-purpose register VR identifies the version (model) and revision level of the OpenRISC 1000 processor. It also specifies possible standard template on which this implementation is based.

Bit #AccessResetDescription5:0RRevisionREV
Revision number of this document.15:6R0x0Reserved23:16R0x00CFG
Configuration should be read from UPR and configuration registers31:24R0x12VER
Version number for OR1200 is fixed at 0x1200.Table  SEQ "Table" \*Arabic 19. VR Register

Register UPR description

Special-purpose register UPR identifies the units present in the processor. It has a bit for each implemented unit or functionality. Lower sixteen bits identify present units defined in the OpenRISC 1000 architecture. Upper sixteen bits define present custom units.

Bit #AccessResetDescription0R1UP
UPR present1R1DCP
Data cache present*2R1ICP
Instruction cache present*3R1DMP
Data MMU present*4R1IMP
Instruction MMU present*5R1MP
MAC present*6R1DUP
Debug unit present*7R0PCUP
Performance counters unit not present*8R1PMP
Power Management Present*9R1PICP
Programmable interrupt controller present10R1TTP
Tick timer present11R1FPP
Floating point present*23:12RXReserved31:24R0xXXXXCUP
The user of the OR1200 core adds custom units.Table  SEQ "Table" \*Arabic 20. UPR Register
* if enabled at synthesis time

Register CPUCFGR description

Special-purpose register CPUCFGR identifies the capabilities and configuration of the CPU. 

Bit #AccessResetDescription3:0R0x0NSGF
Zero number of shadow GPR files4R0HGF
No half GPR files*5R1OB32S
ORBIS32 supported6R0OB64S
ORBIS64 not supported7R1OF32S
ORFPX32 supported**8R0OF64S
ORFPX64 not supported9R0OV64S
ORVDX64 not supportedTable  SEQ "Table" \*Arabic 21. CPUCFGR Register
* If disabled at synthesis time
** If FPU enabled at synthesis time

Register DMMUCFGR description

Special-purpose register DMMUCFGR identifies the capabilities and configuration of the DMMU. 

Bit #AccessResetDescription1:0R0x0NTW
One DTLB way4:2R0x4   0x7NTS
16, 32, 64 or 128 DTLB sets7:5R0x0NAE
No ATB Entries8R0CRI
No DMMU control register implemented9R0PRI
No protection register implemented10R1TEIRI
DTLB entry invalidate register implemented11R0HTR
No hardware DTLB reloadTable  SEQ "Table" \*Arabic 22. DMMUCFGR Register

Register IMMUCFGR description

Special-purpose register IMMUCFGR identifies the capabilities and configuration of the IMMU. 

Bit #AccessResetDescription1:0R0x0NTW
One ITLB way4:2R0x4   0x7NTS
16, 32, 64 or 128 ITLB sets7:5R0x0NAE
No ATB Entries8R0CRI
No IMMU control register implemented9R0PRI
No protection register implemented10R1TEIRI
ITLB entry invalidate register implemented11R0HTR
No hardware ITLB reloadTable  SEQ "Table" \*Arabic 23. IMMUCFGR Register

Register DCCFGR description

Special-purpose register DCCFGR identifies the capabilities and configuration of the data cache. 

Bit #AccessResetDescription2:0R0x0NCW
One DC way6:3R0x4   0x7NCS
16, 32, 64 or 128 DC sets7R0x0CBS
16-byte cache block size8R0CWS
Cache write-through strategy*9R1CCRI
DC control register implemented10R1CBIRI
DC block invalidate register implemented11R0CBPRI
DC block prefetch register not implemented12R0CBLRI
DC block lock register not implemented13R1CBFRI
DC block flush register implemented14R1CBWBRI
DC block write-back register  implemented**Table  SEQ "Table" \*Arabic 24. DCCFGR Register
*If Write-through enabled at synthesis time
**If Write-through disabled at synthesis time


Register ICCFGR description

Special-purpose register ICCFGR identifies the capabilities and configuration of the instruction cache. 

Bit #AccessResetDescription2:0R0x0NCW
One IC way6:3R0x4   0x7NCS
16, 32, 64 or 128 IC sets7R0x0CBS
16-byte cache block size8R0CWS
Cache write-through strategy9R1CCRI
IC control register implemented10R1CBIRI
IC block invalidate register implemented11R0CBPRI
IC block prefetch register not implemented12R0CBLRI
IC block lock register not implemented13R1CBFRI
IC block flush register implemented14R0CBWBRI
IC block write-back register not implementedTable  SEQ "Table" \*Arabic 25. ICCFGR Register

Register DCFGR description

Special-purpose register DCFGR identifies the capabilities and configuration of the debut unit. 

Bit #AccessResetDescription3:0R0x0NDP
Zero DVR/DCR pairs*4R0 WPCI
Watchpoint counters not implementedTable  SEQ "Table" \*Arabic 26. DCFGR Register
* If hardware breakpoints disabled at synthesis time
      


5
IO ports

OR1200 IP core has several interfaces.  REF _Ref507257694 \h Figure 14 below shows all interfaces:
Instruction and data WISHBONE host interfaces
Power management interface
Development interface
Interrupts interface

 EMBED Microsoft Visio Drawing 

Figure  SEQ "Figure" \*Arabic 14. Core s Interfaces

Instruction WISHBONE Master Interface

OR1200 has two master WISHBONE Rev B compliant interfaces. Instruction interface is used to connect OR1200 core to memory subsystem for purpose of fetching instructions or instruction cache lines.

PortWidthDirectionDescriptioniwb_CLK_I1InputClock inputiwb_RST_I1InputReset inputiwb_CYC_O1OutputIndicates valid bus cycle (core select)iwb_ADR_O32OutputsAddress outputsiwb_DAT_I32InputsData inputsiwb_DAT_O32OutputsData outputsiwb_SEL_O4OutputsIndicates valid bytes on data bus (during valid cycle it must be 0xf)iwb_ACK_I1InputAcknowledgment input (indicates normal transaction termination)iwb_ERR_I1InputError acknowledgment input (indicates an abnormal transaction termination)iwb_RTY_I1InputIn OR1200 treated same way as iwb_ERR_I.iwb_WE_O1OutputWrite transaction when asserted highiwb_STB_O1OutputsIndicates valid data transfer cycleTable  SEQ "Table" \*Arabic 27. Instruction WISHBONE Master Interface  Signals

Data WISHBONE Master Interface

OR1200 has two master WISHBONE Rev B compliant interfaces. Data interface is used to connect OR1200 core to external peripherals and memory subsystem for purpose of reading and writing data or data cache lines.

PortWidthDirectionDescriptiondwb_CLK_I1InputClock inputdwb_RST_I1InputReset inputdwb_CYC_O1OutputIndicates valid bus cycle (core select)dwb_ADR_O32OutputsAddress outputsdwb_DAT_I32InputsData inputsdwb_DAT_O32OutputsData outputsdwb_SEL_O4OutputsIndicates valid bytes on data bus (during valid cycle it must be 0xf)dwb_ACK_I1InputAcknowledgment input (indicates normal transaction termination)dwb_ERR_I1InputError acknowledgment input (indicates an abnormal transaction termination)dwb_RTY_I1InputIn OR1200 treated same way as dwb_ERR_I.dwb_WE_O1OutputWrite transaction when asserted highdwb_STB_O1OutputsIndicates valid data transfer cycleTable  SEQ "Table" \*Arabic 28. Data WISHBONE Master Interface  Signals

System Interface

System interface connects reset, clock and other system signals to the OR1200 core.

PortWidthDirectionDescriptionRst1InputAsynchronous resetclk_cpu1InputMain clock input to the RISCclk_dc1InputData cache clockclk_ic1InputInstruction cache clockclk_dmmu1InputData MMU clockclk_immu1InputInstruction MMU clockclk_tt1InputTick timer clockTable  SEQ "Table" \*Arabic 29. System Interface Signals

Development Interface

Development interface connects external development port to the RISC s internal debug facility. Debug facility allows control over program execution inside RISC, setting of breakpoints and watchpoints, and tracing of instruction and data flows.

PortWidthDirectionDescriptiondbg_dat_o32OutputTransfer of data from RISC to external development interfacedbg_dat_i32InputTransfer of data from external development interface to RISCdbg_adr_i32InputAddress of special-purpose register to be read or writtendbg_op_I3InputOperation select for development interfacedbg_lss_o4OutputStatus of load/store unitdbg_is_o2OutputStatus of instruction fetch unitdbg_wp_o11OutputStatus of watchpointsdbg_bp_o1OutputStatus of the breakpointdbg_stall_i1InputStalls RISC CPU coredbg_ewt_i1InputExternal watchpoint triggerTable  SEQ "Table" \*Arabic 30. Development Interface

Power Management Interface

Power management interface provides signals for interfacing RISC core with external power management circuitry. External power management circuitry is required to implement functions that are technology specific and cannot be implemented inside OR1200 core.

PortWidthDirectionGenerationDescriptionpm_clksd4OutputStatic (in SW)Slow down outputs that control reduction of RISC clock frequencypm_cpustall1Input-Synchronous stall of the RISC s CPU corepm_dc_gate1OutputDynamic (in HW)Gating of data cache clockpm_ic_gate1OutputDynamic (in HW)Gating of instruction cache clockpm_dmmu_gate1OutputDynamic (in HW)Gating of data MMU clockpm_immu_gate1OutputDynamic (in HW)Gating of instruction MMU clockpm_tt_gate1OutputDynamic (in HW)Gating of tick timer clockpm_cpu_gate1OutputStatic (in SW)Gating of main CPU clockpm_wakeup1OutputDynamic (in HW)Activate all clockspm_lvolt1OutputStatic (in SW)Lower voltageTable  SEQ "Table" \*Arabic 31. Power Management Interface

Interrupt Interface

Interrupt interface has interrupt inputs for interfacing external peripheral s interrupt outputs to the RISC core. All interrupt inputs are evaluated on positive edge of main RISC clock.

PortWidthDirectionDescriptionpic_intsPIC_INTSInputExternal interruptsTable  SEQ "Table" \*Arabic 32. Interrupt Interface
A
Core HW Configuration

This section describes parameters that are set by the user of the core and define configuration of the core. Parameters must be set by the user before actual use of the core in simulation or synthesis.

Variable NameRangeDefaultDescriptionEADDR_WIDTH3232Effective address widthVADDR_WIDTH3232Virtual address widthPADDR_WIDTH24   3632Physical address widthDATA_WIDTH3232Data width / Operation widthDC_IMPL0   11Data cache implementationDC_SETS256-1024512Data cache number of setsDC_WAYS11Data cache number of waysDC_LINE16 - 3216Data cache line sizeIC_IMPL0   11Instruction cache implementationIC_SETS32-1024512Instruction cache number of setsIC_WAYS11Instruction cache number of waysIC_LINE16-3216Instruction cache line size in bytesDMMU_IMPL0   11Data MMU implementationDTLB_SETS6464Data TLB number of setsDTLB_WAYS11Data TLB number of waysIMMU_IMPL0   11Instruction MMU implementationITLB_SETS6464Instruction TLB number of setsITLB_WAYS11Instruction TLB number of waysPIC_INTS2   3220Number of interrupt inputsTable  SEQ "Table" \*Arabic 33: Core HW configuration table



OpenCores        TITLE OpenRISC 1200 IP Core  DATE \@"M/D/YY" 1/19/11

 HYPERLINK "http://www.opencores.org/"www.opencores.org       Rev 0.11 Preliminary        PAGE 62 of  NUMPAGES \*Arabic 62







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CORGROUP        $$clk_risc_BufferRising
SSS~%?~<&&f*G$,o;ٗbuvvB444z\NK7?~ү_bD	LHHURRo///_r%svv>|x"!!icc3o޼~+<=|ڴio޼~:d2>B***ׯ_UUUԤ|.@$--M-]\\튊,cǎqÇ?~BUUUEE#FǮ    >Ǐ=,]4**jW^Ν;򪪪<ORRrϞ=+V@<8}MMM  !EEEݻqAeee-_|cƌ
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웗qqqyyy#MB
Percent 100
!
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CORGROUP        $$clk_risc_BufferFalling
UTT?zOnܸ?>;;ao>s}\YYyƍgJHHhkkG,XbL奤kkkƘ1cI@зx⎎u
2c…3gδ2L///ccD@DDDz󃒒n޼0}zqq]ƕ+Wttt:::$%%%%%?!!!UUUSLA    'SS 988B={+BOuuŋ       !^tRgg"5FO)//4iRVVUUU/^,\PYY֭[|===P5k#;::lYFFFll_!--...]]]+tRiӦ~ذa-UVBq|}0
7^v_~UUUewϟ3gluu5DH0@߼zNNN쯬\UUuIj!d#E4KLLLLLL`wTUU/!LJBrrr455X@iTVVBƼ<Bmgg']hYYf
!dΜ9Kkjjp8O
Percent 100
Qn@@?B       !wׯ”)SLMM\0;v˗/UTTloܽ{wIIG      \rrr4f=@H#G455
           466B"##{tw8p /gmɒ%'Ottt|w̙3-*..F     xrzz)!DSS{T__ܹ9s hFU4'Md``#B6mT__ommقTKKfffۛ={Q^^>rHCCCP|Bŋ?}\2LQQQI&ٳGVVaT}8vXAA+Wlذ!;;[AABTT˄[[;v1TLLLFٹvڢǯ[nĉl6hߏGTޖ-[mfiiy̙}^dɒ!Cz4l_j)UUUׯ_'Qg(M2E^^]]]---* |֢Zeee:ޣgJJ
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CORGROUP        $$clk_risc_BufferRisingFalling
Percent 100
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CORGROUP        $$clk_risc_BufferRising
.\8~w"b4{:t(""bԨQ,hBHllɓnl6[IIIOOOLL˗555bbbB_/**zɓ'+**[ZZjժ!Clٲ%,,lk֬IMMmiiqvvC00@EDDp\++7oJKKS^|I񐛛Km`Iyŋݻc{l0HHH8p 33sٲeFg_ߍ-}||ٗ$''/XPPֆDPPZ1L\pEVV{%<{lСݣ$Θ1ŋ7311QTT@)F}գe͚5ٗm6BԩSٗNx~ɓ'^~-..߿q))))..Nh._ŅzCBѣG8	>^rrEgܹsF55ryyy555IIɒ7oB
Percent 100
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rrrg϶ B.+
CORGROUP        $$clk_risc_BufferFalling
kkk  !WfX?.///##C$%%
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Percent 100
`(//?!4RRR?22r'NucUU_EEE]]]ϧx"66ѣGT   FL,rssSRRrss={)))C            ׿U뵴z=̌R\\#www0[ZZt2U8iҤ3fQ7nܘ2e
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KW.\0**JEEmy<:8{{
CORGROUP        $$clk_risc_BufferRisingFalling
ǎ>|M3XywqСNUSScllsK͛7X[[GDD}@ uֈ#8NQQQnnn\\hWj@|>bcc߷Z}}!Ν;U3̇kiiݻwѢEhj0vlBU
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hj03TBϋ.uwwwttVVV޾};##Ξ={ժU=7HHHHNNVTT֖)--%x{{kjj[^^O>=aBHyyyNNNEEŵkתiVZZZF`aa!###nٲe׮]믃


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CLOCK   clk_risc
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PERIODE 1
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DUTY    50
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MAXUNCERTRISE   0
MAXUNCERTFALL   0
MINUNCERTRISE   0
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MINUNCERTFALL   0
BBٳg<O Bjjjb
JRISEE  0
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JFALLE  0
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GRID    1       1       1       2       2       16711680        0        0
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ENDGRID -1
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DIRECTION       input
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MASTERCLOCK     None
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Clock   Unclocked

EdgeLevel       neg
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Set     Not Used

Clear   Not Used

IHDRFrsRGB       pHYstIME     -
ClockEnable     Not Used
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ActiveLowSetClear       True
b,"Q
AsyncSetClear   True
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ActiveLowClockEnable    True
Jƾ鲲ׯjoooܸ'%%m6*X/O>}„       Æ
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VhdlType        std_logic
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VerilogType     wire
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
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StateEquation   Hex(Inc(0,2,5))
utt_zEqpp322‡}_j      訯w/Q222
HighVoltageThreshold    5
?~{常8--w޸q@     ?~|ٲeo߾%L4ʲg>~!d8qGUU566QKby{{B8%%%'':ŋ
LowVoltageThreshold     0
MSB     0
LSB     0
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isFallingEdgeSensitive  False
isRisingEdgeSensitive   True
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DrawAnalog      0
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BooleanEquation
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NegTolerance    0
z!>>~ԩ555§Nڸqcee|ii)Ͷۼyq!_
GDDL:U]]0J%%%f^$`sZZZTLyƍ
PosTolerance    0
UserSpecifiedSizeRatio  1
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Verilog3Code
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VHDLCode
PROPS!
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3Muu    rss=zdffFtss{AUUT)fo޼ym---IIٳg"8|]:;;,YBqrrz        á/]JqssZ\֭[͛WUUHP*++g̘)//Ͽ?{xxHJJB8aii9{lQQѧO>|YZZܹsر&X,/߯_M6M0ADDD[[{644ljj:{bWWN/--uuuqŋĈ'0AFFʕ+GZZZ燐رc̙.]qc~~?ɓ
SIGNAL  dbg_wp_o[11]
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VVV)))o߾rgZݹsg޽JHH˳011177~RRҠA/FZ`-"A8%""bŊ/{zzx<'''BȣG-[VTTgϞm۶-]SuUU!$,,2n870	V\\zׯwuuB,,,RSS/ҦN:lذS;Yɥ8p`Ŋԋȴq8˗9rQ@^ykh4uBBӥ

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DIRECTION       output
RADIX   hex
GRID    0        1       0        1       0        16711680        0        0
ҽ)Ϟ=|2
H!..O?TRggح[n߾_XX8e{{J99pFjϟ?cƌ_~dzɉ6m?
ENDGRID -1
Pǎ~۷oSkL&T7nƍӪ IDATEEEǏSUU?>B
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Clock   Unclocked
EdgeLevel       neg
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Set     Not Used
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4`޺uX__j9<<QfAÿMAAd&$$ܸqCEEEVV&444<7
Kt:bjj:lذE/0޽cǎٳg+++xxxܻwoʖ6|V0455
Clear   Not Used
HslllssŬY>!4i!BLLL޽vZ>0  >O:::w^UUcǎ{D߁83(##)$$Q\\ryqqq333AAwkkc066LJb1o޼tWl6!$`wQyP455{\op8/^عsuFFE_xqԩo߆gZ_BBRXXFaX'N(//<内yzzHII!$,"IJJ޽{СCBBB'::JJJ;wڵk߾}gԨQ[n1bfjjӧO9Έ#ӵ5X_ן:u"%%5x7o޼yFDDѣs%
ClockEnable     Not Used
#Y[[[YY?^ZZZHHjШh.lll\f
!JJJ{ikk:d2RG0|SRRn߾=rHBH~~U[Fݽ{wUQQqܹ7oHII͟?Ĉ#         C젠s8'$$\~/!$44tҤIw=CFx⊊
ActiveLowSetClear       True
DPMSSӓLra555NYYr׷Yl6{ɒ%{F0     8ŋmۖ%%%$""BUTUUM>ѣp8#..n͚5'OF04|ܹscbb훛ƍdɒŋ
AsyncSetClear   True
aaa@baaa>҄      .]tѷo.Xjkoo'="00F]xQMM߿Ԅ5驪#B6o\UU5w\$,,
ActiveLowClockEnable    True
!$`JNN>p@uu6lЛ!gddBtttٳghjj"["""'KǏ/[LRRrԩfjmm߽{wGGǒ%K;& IX,EEŦ{Κ5KCC
VhdlType        std_logic
ݻwƍ,+55@>_SSӈ#<==2dbss3EOap#B"##{\lnn6@ɸB-[?Qի7VTT~ZBB|ĉy3`qƍI&	WWWKIIuРp'Oo߾WPPX~yIo>        !AAA=/!ӓ899e˖:Nx[lYmm-   
VerilogType     wire
ڵk'OјfaaA)-- 8qMLLlћ7o9}ILT[f_B!dÆ
Te2[lljj*++\`+jkk:TWW` ;{'OoN;wNZZjjj/^$IJJW())Ao!t:UWWd27nܘhjjZ^^lkk$$$Nb&L`ffHw܉]x1-NgX/^=ŋQQQ222=255]hQmmTjZucc#Ղ)H+NNNݿ9rp~~'O!K,	!O>%|TLζZZ[[R$`3333[[ۧOBw]TT4nܸϞ=9::fS-~~~ÇC$>Xϊ駟222lll


!MMMTǿ|ٳgCiii9uի[nc04
!:`3<֌3h4چ
=zdnn>sL:KJJ򻥧755
6LIIرc222%((`ikk۲e˅jjj:::!WYf͟?ӛ7o>zMjjjvvׯ!L&!@&..f͚ٗrIBrlllpp0Fۻw/LLLtpp Xsι$%%)++cD	>LKKk]]]ϔBbV\)""?ϟ?ĉo޼qtt8 !!akkx @ȾfwA___OOOߝ=
&&&v
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H1.\pҥjB
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
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HighVoltageThreshold    5
`!|\A~~>!DJJرc+33˗rrr#F@P@\~"!!oݺddd̛7իW[nuttD0>OP׭['##[^zebb9slڴ   ':|0
e [WW2`GnܸQVV6&&fذa&*` KHH444tuu466Y̙3


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5t~5F662nB    L^INNSUnJrbn(M!V.      jHQln










OpenRISC 1200
IP Core
Specification


Author: Damjan Lampret
lampret@opencores.org


Rev. 0.11
January, 2011




Preliminary Draft
Revision History

Rev.DateAuthorDescription0.128/3/01Damjan LampretFirst Draft0.216/4/01Damjan LampretFirst time published0.329/4/01Damjan LampretAll chapters almost finished. Some bugs hidden waiting for an update. Awaiting feedback.0.416/5/01Damjan LampretSynchronization with OR1K Arch Manual0.524/5/01Damjan LampretFixed bugs0.628/5/01Damjan LampretChanged some SPR addresses.0.706/9/01Damjan LampretSimplified debug unit.0.830/08/10Julius BaxterAdding information about FPU implementation, data cache write-back capability.
PIC behavior update.
Instruction list update.
Update of bits in config registers, bringing into line with latest OR1200   not entirely complete.0.912/9/10Julius BaxterClarified supported parts of OR1K instruction set
Updated core clock input information
Fixed up reference to instruction execute stage cycle table
Added divide cycles to execute stage cycle table
0.101/11/10Julius BaxterAdded FF1/FL1 instructions to supported instructions table.0.1119/1/11Julius BaxterCache information update
Wishbone behavior clarification
Serial integer multiply/divide update
Reset address clarification
Table Of Contents

 TOC  HYPERLINK  \l "_toc273"Table Of Contents     3
 HYPERLINK  \l "_toc333"Table Of Figures   5
 HYPERLINK  \l "_toc352"Table Of Tables     6
 HYPERLINK  \l "_toc390"1 7
Introduction 7
 HYPERLINK  \l "_toc396"OpenRISC Family       7
 HYPERLINK  \l "_toc404"OpenRISC 1200 8
 HYPERLINK  \l "_toc415"Features   8
 HYPERLINK  \l "_toc423"2 9
Architecture 9
 HYPERLINK  \l "_toc442"CPU/FPU/DSP       10
 HYPERLINK  \l "_toc512"Data Cache     13
 HYPERLINK  \l "_toc567"Instruction Cache       16
 HYPERLINK  \l "_toc625"Data MMU 18
 HYPERLINK  \l "_toc677"Instruction MMU   20
 HYPERLINK  \l "_toc729"Programmable Interrupt Controller       22
 HYPERLINK  \l "_toc740"Tick Timer     22
 HYPERLINK  \l "_toc752"Power Management Support 23
 HYPERLINK  \l "_toc805"Debug unit     23
 HYPERLINK  \l "_toc814"Clocks & Reset     24
 HYPERLINK  \l "_toc820"WISHBONE Interfaces   24
 HYPERLINK  \l "_toc826"3       26
Operation     26
 HYPERLINK  \l "_toc831"Reset 26
 HYPERLINK  \l "_toc847"CPU/FPU/DSP   27
 HYPERLINK  \l "_toc1734"Data Cache Operation       33
 HYPERLINK  \l "_toc1817"Instruction Cache Operation 36
 HYPERLINK  \l "_toc1865"Data MMU       38
 HYPERLINK  \l "_toc2002"Instruction MMU 42
 HYPERLINK  \l "_toc2126"Programmable Interrupt Controller     45
 HYPERLINK  \l "_toc2144"Tick Timer   45
 HYPERLINK  \l "_toc2150"Power Management       45
 HYPERLINK  \l "_toc2186"Debug Unit   47
 HYPERLINK  \l "_toc2200"Development Interface     47
 HYPERLINK  \l "_toc2447"4     51
Registers     51
 HYPERLINK  \l "_toc2452"Registers list     51
 HYPERLINK  \l "_toc3164"Register VR description 52
 HYPERLINK  \l "_toc3235"Register UPR description       53
 HYPERLINK  \l "_toc3437"Register CPUCFGR description       53
 HYPERLINK  \l "_toc3550"Register DMMUCFGR description     54
 HYPERLINK  \l "_toc3661"Register IMMUCFGR description     54
 HYPERLINK  \l "_toc3772"Register DCCFGR description 55
 HYPERLINK  \l "_toc3925"Register ICCFGR description 56
 HYPERLINK  \l "_toc4075"Register DCFGR description   56
 HYPERLINK  \l "_toc4124"5     58
IO ports       58
 HYPERLINK  \l "_toc4137"Instruction WISHBONE Master Interface       58
 HYPERLINK  \l "_toc4301"Data WISHBONE Master Interface   59
 HYPERLINK  \l "_toc4465"System Interface       59
 HYPERLINK  \l "_toc2200"Development Interface     60
 HYPERLINK  \l "_toc4709"Power Management Interface   60
 HYPERLINK  \l "_toc4882"Interrupt Interface 61
 HYPERLINK  \l "_toc4913"A     62
Core HW Configuration     62
Table Of Figures

 TOC \c "FIGURE" Figure 1. Core's Architecture       9
Figure 2. CPU/FPU/DSP Block Diagram     10
Figure 3. Block Diagram of Debug Unit       24
Figure 4. Power-Up and Reset Sequence       26
Figure 5. Power-Up and Reset Sequence w/ Gated Clock 26
Figure 6. WISHBONE Write Cycle     33
Figure 7. WISHBONE Block Read Cycle   34
Figure 8. WISHBONE Block Read/Write Cycle       34
Figure 9. WISHBONE Block Read Cycle   37
Figure 10. 32-bit Address Translation Mechanism using Two-Level Page Table     39
Figure 11. 32-bit Address Translation Mechanism using Two-Level Page Table     42
Figure 12. Development Interface Cycles   48
Figure 13. Assertion of External Watchpoint Trigger   50
Figure 14. Core s Interfaces 58 
Table Of Tables

 TOC \c "TABLE" Table 1. Possible Data Cache Configurations of OR1200 13
Table 2. Possible Instruction Cache Configurations of OR1200 16
Table 3. Possible Data TLB Configurations of OR1200   18
Table 4. Possible Instruction TLB Configurations of OR1200     20
Table 5. Block Diagram of the Interrupt Controller     22
Table 6. Power Consumption     23
Table 7: Instructions implemented in OR1200   28
Table 8. Execution Time of Integer Instructions   30
Table 9: Execution time of floating point instructions     31
Table 10. List of Implemented Exceptions 32
Table 11. Protection Attributes for Load/Store Accesses   40
Table 12.  Cached and uncached regions     41
Table 13. Protection Attributes for Instruction Fetch Accesses     43
Table 14.  Cached and uncached regions     44
Table 15. Development Interface Operation Commands     48
Table 16. Status of the Load/Store Unit   49
Table 17. Status of the Instruction Unit 49
Table 18. List of All Registers   52
Table 19. VR Register       53
Table 20. UPR Register     53
Table 21. CPUCFGR Register     54
Table 22. DMMUCFGR Register   54
Table 23. IMMUCFGR Register   55
Table 24. DCCFGR Register       56
Table 25. ICCFGR Register       56
Table 26. DCFGR Register 57
Table 27. Instruction WISHBONE Master Interface  Signals 59
Table 28. Data WISHBONE Master Interface  Signals       59
Table 29. System Interface Signals     60
Table 30. Development Interface   60
Table 31. Power Management Interface 61
Table 32. Interrupt Interface       61
Table 33: Core HW configuration table       62
1
Introduction

Purpose of this document is to define specifications of the OpenRISC 1200 implementation. This specification defines all implementation specific variables that are not part of the general architecture specification. This includes type and size of data and instruction caches, type and size of data and instruction MMUs, details of all execution pipelines, implementation of exception unit, interrupt controller and other supplemental units.
This document does not cover general architecture topics like instruction set, memory addressing modes and other architectural definitions. See OpenRISC 1000 System Architecture Manual for more information about architecture.

OpenRISC Family

OpenRISC 1000 is architecture for a family of free, open source RISC processor cores. As architecture, OpenRISC 1000 allows for a spectrum of chip and system implementations at a variety of price/performance points for a range of applications. It is a 32/64-bit load and store RISC architecture designed with emphasis on performance, simplicity, low power requirements, scalability and versatility. OpenRISC 1000 architecture targets medium and high performance networking, embedded, automotive and portable computer environments.
 EMBED Microsoft Visio Drawing 
All OpenRISC implementations, whose first digit in identification number is  1 , belong to OpenRISC 1000 family. Second digit defines which features of OpenRISC 1000 architecture are implemented and in which way they are implemented. Last two digits define how an implementation is configured before it is used in a real application.

However, at present the OR1200 is the only major RTL implementation of the OR1K architecture spec, and the OR1200 name has stuck, despite the high level of reconfigurability possible that would, strictly speaking, mean the core is either a OR1000, OR1300, etc. So, despite the various features that may or may not be implemented, the core is still only referred to as the OR1200.

OpenRISC 1200

The OR1200 is a 32-bit scalar RISC with Harvard microarchitecture, 5 stage integer pipeline, virtual memory support (MMU) and basic DSP capabilities.
Default caches are 1-way direct-mapped 8KB data cache and 1-way direct-mapped 8KB instruction cache, each with 16-byte line size. Both caches are physically tagged.
By default MMUs are implemented and they are constructed of 64-entry hash based 1-way direct-mpped data TLB and 64-entry        
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Supplemental facilities include debug unit for real-time debugging, high resolution tick timer, programmable interrupt controller and power management support.
When implemented in a typical 0.18u 6LM process it should provide over 300 dhrystone 2.1 MIPS at 300MHz and 300 DSP MAC 32x32 operations, at least 20% more than any other competitor in this class. OR1200 in default configuration has about 1M transistors.

OR1200 is intended for embedded, portable and networking applications. It can successfully compete with latest scalar 32-bit RISC processors in his class and can efficiently run any modern operating system.
Competitors include ARM10, ARC and Tensilica RISC processors.

Features

The following lists the main features of OR1200 IP core:
All major characteristics of the core can be set by the user
High performance of 300 Dhrystone 2.1 MIPS at 300 MHz using 0.18u process
High performance cache and MMU subsystems
WISHBONE SoC Interconnection Rev. B3 compliant interface
 
2
Architecture

 REF _Ref511206923 \h Figure 1 below shows general architecture of OR1200 IP core. It consists of several building blocks: 
CPU/FPU/DSP central block
Direct-mapped data cache
Direct-mapped instruction cache
Data MMU based on hash based DTLB
Instruction MMU based on hash based ITLB
Power management unit and power management interface
Tick timer
Debug unit and development interface
Interrupt controller and interrupt interface
Instruction and Data WISHBONE host interfaces

 EMBED Microsoft Visio Drawing 
Figure  SEQ "Figure" \*Arabic 1. Core's Architecture


CPU/FPU/DSP

CPU/FPU/DSP is a central part of the OR1200 RISC processor.  REF _Ref511208730 \h Figure 2 shows basic block diagram of the CPU/DSP. Not pictured are the FPU components.
OR1200 CPU/FPU/DSP ony implements sections of the ORBIS32 and ORFPX32 instruction set. No ORBIS64, ORFBX64 or ORVDX64 instructions are  implemented in OR1200.

 EMBED Microsoft Visio Drawing 
Figure  SEQ "Figure" \*Arabic 2. CPU/FPU/DSP Block Diagram

Instruction unit

The instruction unit implements the basic instruction pipeline, fetches instructions from the memory subsystem, dispatches them to available execution units, and maintains a state history to ensure a precise exception model and that operations finish in order. It also executes conditional branch and unconditional jump instructions.
The sequencer can dispatch a sequential instruction on each clock if the appropriate execution unit is available. The execution unit must discern whether source data is available and to ensure that no other instruction is targeting the same destination register.

Instruction unit handles only ORBIS32 and, optionally, a subset of the ORFPX32 instruction class. Some ORFPX32 and all ORFPX3264 and ORVDX64 instruction classes are not supported by the OR1200 at present.

General-Purpose Registers

OpenRISC 1200 implements 32 general-purpose 32-bit registers. OpenRISC 1000 architecture also support shadow copies of register file to implement fast switching between working contexts, however this feature is not implemented in current OR1200 implementation.

OR1200 implements general-purpose register file as two synchronous dual-port memories with capacity of 32 words by 32 bits per word.

Load/Store Unit

The load/store unit (LSU) transfers all data between the GPRs and the CPU's internal bus. It is implemented as an independent execution unit so that stalls in memory subsystem only affect master pipeline if there is a data dependency.
The following are LSU's main features:
all load/store instruction implemented in hardware (atomic instructions included)
address entry buffer
pipelined operation
aligned accesses for fast memory access

When load and store instructions are issued, the LSU determines if all operands are available. These operands include the following:
address register operand
source data register operand (for store instructions)
destination data register operand (for load instructions)

Integer Execution Pipeline

The core implements the following types of 32-bit integer instructions:
Arithmetic instructions
Compare instructions
Logical instructions
Rotate and shift instructions

Most integer instructions can execute in one cycle. For details about timing see Table 8. Execution Time of Integer Instructions .

MAC Unit

The MAC unit executes DSP MAC operations. MAC operations are 32x32 with 48-bit accumulator. MAC unit is fully pipelined and can accept new MAC operation in each new clock cycle.

Floating Point Unit

The FPU implementation is based on two other FPUs available from OpenCores.org For the comparison and conversion functions, parts were taken from the FPU project by Rudolf Usselmann, and for the arithmetic operations, the fpu100 project by Jidan Al-Eryani was converted to Verilog HDL.

All ORFPX32 instructions except for lf.madd.s and lf.rem.s are supported when the FPU is enabled in the OR1200 configuration.

System Unit

The system unit connects all other signals of the CPU/FPU/DSP that are not connected through instruction and data interfaces. It also implements all system special-purpose registers (e.g. supervisor register).

Exceptions

Core exceptions can be generated when an exception condition occurs. Exception sources in OR1200 include the following:
External interrupt request
Certain memory access condition
Internal errors, such as an attempt to execute unimplemented opcode
System call
Internal exception, such as breakpoint exceptions

Exception handling is transparent to user software and uses the same mechanism to handle all types of exceptions. When an exception is taken, control is transferred to an exception handler at an offset defined by for the type of exception encountered. Exceptions are handled in supervisor mode.

Data Cache

The default configuration of OR1200 data cache is 8-Kbyte, 1-way direct-mapped data cache, which allows rapid core access to data. However data cache can be configured according to the  REF _Ref512098491 \h Table 1.

Direct mapped16B/line, 256 lines, 1 way4KB16B/line, 512 lines, 1 way8KB (default)16B/line, 1024 lines, 1 way16KB32B/line, 1024 lines, 1 way32KBTable  SEQ "Table" \*Arabic 1. Possible Data Cache Configurations of OR1200

It is possible to operate the data cache with write-through or write-back strategies, however write-back is currently experimental.

Features:
data cache is separate from instruction cache (Harvard architecture)
data cache implements a least-recently used (LRU) replacement algorithm within each set
the cache directory is physically addressed. The physical address tag is stored in the cache directory
write-through or write-back operation
entire cache can be disabled, lines invalidated, flushed or forced to be written back, by writing to cache special purpose registers

On a miss, and appropriate conditions, the cache line is filled or emptied (written back) with 16-byte bursts. The burst fill is performed as a critical-word-first operation; the critical word is simultaneously written to the cache and forwarded to the requesting unit, thus minimizing stalls due to cache fill latency. Data cache provides storage for cache tags and performs cache line replacement function.
Data cache is tightly coupled to external interface to allow efficient access to the system memory controller.
The data cache supplies data to the GPRs by means of a 32-bit interface to the load/store unit. The LSU provides all logic required to calculate effective addresses, handles data alignment to and from the data cache, and provides sequencing for load and store operations. Write operations to the data cache can be performed on a byte, half-word or word basis.

 EMBED Microsoft Visio Drawing 

Each line contains four contiguous words from memory that are loaded from a cache line aligned boundary. As a result, cache lines are aligned with page boundaries.

Instruction Cache

The default configuration of OR1200 instruction cache is 8-Kbyte, 1-way direct mapped instruction cache, which allows rapid core access to instructions. However instruction cache can be configured according to the  REF _Ref512099081 \h .

Direct mapped16B/line, 32 lines, 1 way512B16B/line, 256 lines, 1 way4KB16B/line, 512 lines, 1 way8KB (Default)16B/line, 1024 lines, 1 way16KB32B/line, 1024 lines, 1 way32KBTable  SEQ "Table" \*Arabic 2. Possible Instruction Cache Configurations of OR1200

Features:
instruction cache is separate from data cache (Harvard architecture)
instruction cache implements a least-recently used (LRU) replacement algorithm within each set
the cache directory is physically addressed. The physical address tag is stored in the cache directory
it can be disabled or invalidated by writing to cache special purpose registers

On a miss, the cache is filled in with 16-byte bursts. The burst fill is performed as a critical-word-first operation; the critical word is simultaneously written to the cache and forwarded to the requesting unit, thus minimizing stalls due to cache fill latency. Instruction cache provides storage for cache tags and performs cache line replacement function.
Instruction cache is tightly coupled to external interface to allow efficient access to the system memory controller.
The instruction cache supplies instructions to the instruction sequencer by means of a 32-bit interface to the instruction fetch subunit. The instruction fetch subunit provides all logic required to calculate effective addresses.

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Each line contains four contiguous words from memory that are loaded from a line-size  aligned boundary. As a result, cache lines are aligned with page boundaries.

Data MMU

The OR1200 implements a virtual memory management scheme that provides memory access protection and effective-to-physical address translation. Protection granularity is as defined by OpenRISC 1000 architecture - 8-Kbyte and 16-Mbyte pages.

Direct mapped16 entries per way16 DTLB entries32 entries per way32 DTLB entries64 entries per way64 DTLB entries (default)128 entries per way128 DTLB entriesTable  SEQ "Table" \*Arabic 3. Possible Data TLB Configurations of OR1200

Features:
data MMU is separate from instruction MMU
page size 8-Kbyte
comprehensive page protection scheme
direct mapped hash based translation lookaside buffer (DTLB) with the default of 1 way and the following features:
miss and fault exceptions
software tablewalk
high performance because of hashed based design
variable number DTLB entries with default of 64 per each way

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The MMU hardware supports two-level software tablewalk.

Instruction MMU

The OR1200 implements a virtual memory management scheme that provides memory access protection and effective-to-physical address translation. Protection granularity is as defined by OpenRISC 1000 architecture - 8-Kbyte and 16-Mbyte pages.

Direct mapped16 entries per way16 DTLB entries32 entries per way32 DTLB entries64 entries per way64 DTLB entries (default)128 entries per way128 DTLB entriesTable  SEQ "Table" \*Arabic 4. Possible Instruction TLB Configurations of OR1200

Features:
instruction MMU is separate from data MMU
pages size 8-Kbyte
comprehensive page protection scheme
1 way direct-mapped hash based translation lookaside buffer (ITLB) with the following features:
miss and fault exceptions
software tablewalk
high performance because of hashed based design
Variable number of ITLB entries with default of 64 entries per way

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The MMU hardware supports two-level software tablewalk.

Programmable Interrupt Controller

The interrupt controller receives interrupts from external sources and forwards them as low or high priority interrupt exception to the CPU core.


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Table  SEQ "Table" \*Arabic 5. Block Diagram of the Interrupt Controller

Programmable interrupt controller has three special-purpose registers and 32 interrupt inputs. Interrupt input 0 and 1 are always enabled and connected to high and low priority interrupt input, respectively.
30 other interrupt inputs can be masked and assigned low or high priority through programming special-purpose registers.

Tick Timer

OR1200 implements tick timer facility. Basically this is a timer that is clocked by RISC clock and is used by the operating system to precisely measure time and schedule system tasks.

OR1200 precisely follow architectural definition of the tick timer facility:
Maximum timer count of 2^32 clock cycles
Maximum time period of 2^28 clock cycles between interrupts
Maskable tick timer interrupt
Single run, restartable or continues timer

Tick timer operates from independent clock source so that doze power management mode can be implemented.

Power Management Support

To optimize power consumption, the OR1200 provides low-power modes that can be used to dynamically activate and deactivate certain internal modules.

OR1200 has three major features to minimize power consumption:
Slow and Idle Modes (SW controlled clock freq reduction)
Doze and Sleep Modes (interrupt wake-up)

Power Minimization FeatureApprox Power Consumption ReductionSlow and Idle mode2x   10xDoze mode100xSleep mode200xDynamic clock gatingN/ATable  SEQ "Table" \*Arabic 6. Power Consumption

Slow down mode takes advantage of the low-power dividers in external clock generation circuitry to enable full functionality, but at a lower frequency so that a power consumption is reduced.
PMR[SDF] 4 bits are broadcasted on pm_clksd and external clock generation for the RISC should adapt RISC clock frequency according to the value on pm_clksd.

When software initiates the doze mode, software processing on the core suspends. The clocks to the RISC internal modules are disabled except to the tick timer. However any other on-chip blocks can continue to function as normal.
The OR1200 will leave doze mode and enter normal mode when a pending interrupt occurs.

In sleep mode, all OR1200 internal units are disabled and clocks gated. Optionally implementation may choose to lower the operating voltage of the OR1200 core.
The OR1200 should leave sleep mode and enter normal mode when a pending interrupt occurs.

Dynamic Clock gating (unit clock gating on clock by clock basis) is not supported by OR1200.

Debug unit

Debug unit assists software developers to debug their systems. It provides support only for basic debugging and does not have support for more advanced debug features of OpenRISC 1000 architecture such as watchpoints, breakpoints and program-flow control registers.

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Figure  SEQ "Figure" \*Arabic 3. Block Diagram of Debug Unit

Watchpoints and breakpoints are events triggered by program- or data-flow matching the conditions programmed in the debug registers. Breakpoints unlike watchpoints also suspend execution of the current program-flow and start breakpoint exception.

Clocks & Reset

The OR1200 core has a clock input each for the instruction and data Wishbone interface logic, and for the CPU core. Clock input clk_cpu clocks everything inside the Wishbone interfaces. Data Wishbone interface is clocked by dwb_clk_i, instruction Wishbone interface is clocked by iwb_clk_i.

OR1200 has asynchronous reset signal. Reset signal rst, when asserted high, immediately resets all flip-flops inside OR1200. When deasserted, OR1200 will start reset exception.

WISHBONE Interfaces

Two WISHBONE interfaces connect OR1200 core to external peripherals and external memory subsystem. They are WISHBONE SoC Interconnection specification Rev. B3 compliant. The implementation implements a 32-bit bus width and does not support other bus widths.
Wishbone registered-feedback incrementing burst accesses occur when not disabled, and cache lines are filled. The burst size (beats) is determined by the cache line size.


3
Operation

This section describes the operation of the OR1200 core. For operations that pertain to the architectural definitions, see OpenRISC 1000 System Architecture Manual.

Reset

OR1200 has one asynchronous reset signal that can be used by a soft and hard reset on a higher system hierarchy levels.

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Figure  SEQ "Figure" \*Arabic 4. Power-Up and Reset Sequence

 REF _Ref513206810 \h Figure 4 shows how asynchronous reset is applied after powering up the OR1200 core. Reset is connected to asynchronous reset of almost all flip-flops inside RISC core. Special care must be taken to ensure hold and setup times of all flip-flops compared to main RISC clock.

If system implements gated clocks, then clock gating can be used to ensure proper reset timing.

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Figure  SEQ "Figure" \*Arabic 5. Power-Up and Reset Sequence w/ Gated Clock

The address the PC assumes at hard reset (assertion of external reset signal) is definable at synthesis time, via the OR1200_BOOT_ADR define. This is not to be confused with the ability to set the exception prefix address with the EPH bit.

CPU/FPU/DSP

CPU/FPU/DSP is implementation of the 32-bit part of the OpenRISC 1000 architecture and only a subset of all features is implemented.


Instructions

The following table lists the instructions implemented in the OR1200. Those optionally implemented are indicated as such.
Instruction 
mnemonicOpt.Instruction 
mnemonicOpt.Instruction 
mnemonicOpt.Instruction 
mnemonicOpt.l.addl.macrcYl.shlf.sflt.sYl.addcYl.msbYl.slllf.sfne.sYl.addil.mfsprl.sllilf.sub.sYl.andl.movhil.sral.andil.mtsprl.srail.bfl.mulYl.srll.bnfl.muliYl.srlil.divYl.nopl.subYl.ff1Yl.orl.swl.fl1Yl.oril.sysl.jl.rfel.trapl.jall.roril.xorl.jalrl.sbl.xoril.jrl.sfeqlf.add.sYl.lbsl.sfgeslf.div.sYl.lbzl.sfgeulf.ftoi.sYl.lhsl.sfgtslf.itof.sYl.lhzl.sfgtulf.mul.sYl.lwsl.sfleulf.sfeq.sYl.lwzl.sfltslf.sfge.sYl.macYl.sfltulf.sfgt.sYl.maciYl.sfnelf.sfle.sYTable  SEQ "Table" \*Arabic 7: Instructions implemented in OR1200
For a complete description of each instruction's format refer to the OpenRISC 1000 System Architecture Manual.

Instruction Unit

Instruction unit generates instruction fetch effective address and fetches instructions from instruction cache. Each clock cycle one instruction can be fetched. Instruction fetch EA is further translated into physical address by IMMU.

General-Purpose Registers

General-purpose register file can supply two read operands each clock cycle and store one result in a destination register.

GPRs can be also read and written through development interface.

Load/Store Unit

LSU can execute one load instruction every two clock cycles assuming load instruction have a hit in the data cache. Execution of store instructions takes one clock cycle assuming they have a hit in the data cache.

LSU performs calculation of the load/store effective address. EA is further translated into physical address by DMMU.

Load/store effective address and load and store data can be also accessed through development interface.





















Integer Execution Pipeline

The core implements the following types of 32-bit integer instructions:
Arithmetic instructions
Compare instructions
Logical instructions
Rotate and shift instructions

Instruction GroupClock Cycles to ExecuteArithmetic except Multiply/Divide1Multiply3Divide32Compare1Logical1Rotate and Shift1Others1Table  SEQ "Table" \*Arabic 8. Execution Time of Integer Instructions

 REF _Ref513308588 \h Table 8 lists execution times for instructions executed by integer execution pipeline. Most instructions are executed in one clock cycle.

Integer multiply can be either serial or parallel implementations. Serial operations require one clock cycle per bit of operand, which is 32-cycles on the OR1200. At present no synthesis tools support division operators, and so the serial option must be used.

MAC Unit

MAC unit executes l.mac instructions. MAC unit implements 32x32 fully pipelined multiplier and 48-bit accumulator. MAC unit can accept one new l.mac instruction each clock cycle.
Care should be taken when executing l.macrc (MAC read and clear) too soon after the final l.mac instruction as the operation may still be underway and the result will not be valid in time. It is recommended at least 3 other instructions (or just l.nops) are inserted between the final l.mac and l.macrc.

Floating Point Unit
The floating point unit has a mechanism to stall the processor pipeline until processing has completed.
The following table indicates the number of cycles per operation

OperationCyclesAdd/subtract10Multiply38Divide37Compare2Convert7Table  SEQ "Table" \*Arabic 9: Execution time of floating point instructions

System Unit

System unit implements system control and status special-purpose registers and executes all l.mtspr/l.mfspr instructions.


























Exceptions

The core implements a precise exception model. This means that when an exception is taken, the following conditions are met:
Subsequent instructions in program flow are discarded
Previous instructions finish and write back their results
The address of faulting instruction is saved in EPCR registers and the machine state is saved to ESR registers

Exception TypeVector Offsetcausing conditionsReset0x100Caused by reset.Bus Error0x200Caused by an attempt to access invalid physical address.Data Page Fault0x300Generated artificially by DTLB miss exception handler when no matching PTE found in page tables or page protection violation for load/store operations.Instruction Page Fault0x400Generated artificially by ITLB miss exception handler when no matching PTE found in page tables or page protection violation for instruction fetch.Low Priority External Interrupt0x500Low priority external interrupt asserted.Alignment0x600Load/store access to naturally not aligned location.Illegal Instruction0x700Illegal instruction in the instruction stream.High Priority External Interrupt0x800High priority external interrupt asserted.D-TLB Miss0x900No matching entry in DTLB (DTLB miss).I-TLB Miss0xA00No matching entry in ITLB (ITLB miss).System Call0xC00System call initiated by software.Floating point exception0xD00FP operation caused flags in FPCSR to become set.Trap0xE00Trap instruction was decodedTable  SEQ "Table" \*Arabic 10. List of Implemented Exceptions
The OR1200 exception support does not include support for range exceptions or fast context switching.

Data Cache Operation

Data Cache Load/Store Access

Load/store unit requests data from the data cache and stores them into the general-purpose register file and forwards them to integer execution units. Therefore LSU is tightly coupled with the data cache.

If there is no data cache line miss nor DTLB miss, load operations take two clock cycles to execute and store operations take one clock cycle to execute. LSU does all the data alignment work.

Data can be written to the data cache on a word, half-word or byte basis. Since data cache only operates in write-through mode, all writes are immediately written back to main memory or to the next level of caches.

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Figure  SEQ "Figure" \*Arabic 6. WISHBONE Write Cycle

 REF _Ref513193242 \h Figure 6 shows how a write-through cycle on data WISHBONE interface is performed when a store instruction hits in the data cache.
If dwb_ERR_I or dwb_RTY_I is asserted instead of usual dwb_ACK_I, bus error exception is invoked.

Data Cache Line Fill Operation

When executing load instruction and a cache miss occurs, depending on whether the cache uses write-through or write-back strategy and the line is clean or invalid, a 4 beat sequential read burst with critical word first is performed. If the strategy is write-back and the line is dirty, the line is first written back to memory. The critical word is forwarded to the load/store unit to minimize performance loss because of the cache miss.

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Figure  SEQ "Figure" \*Arabic 7. WISHBONE Block Read Cycle

 REF _Ref513194821 \h Figure 7 shows how a cache line is read in WISHBONE read block cycle composed out of four read transfers.
If dwb_ERR_I or dwb_RTY_I is asserted instead of usual dwb_ACK_I, bus error exception is invoked.

When executing a store instruction with the cache in write-through strategy, and a cache miss occurs, the write is simply put on the bus and no caching occurs. If it is a miss and the cache is in write back strategy and the line is valid and clean or invalid,  a 4 beat sequential read burst to fill the line is performed, and the the write to cache occurs. If storing and a cache miss occurs, and the desired line is valid and dirty, it is first written back to memory before the desired line is read.


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Figure  SEQ "Figure" \*Arabic 8. WISHBONE Block Read/Write Cycle

 REF _Ref513195072 \h Figure 8 shows how a cache line is read in WISHBONE read block cycle followed by a write transfer.
If dwb_ERR_I or dwb_RTY_I is asserted instead of usual dwb_ACK_I, bus error exception is invoked.

Cache/Memory Coherency

Data cache in OR1200 operates in either write-through or write-back mode, definable at synthesis time, for default use, and runtime when DMMU is used. There is currently no coherency support between local data cache and caches of other processors.

Data Cache Enabling/Disabling

Data cache is disabled at power up. Entire data cache can be enabled by setting bit SR[DCE] to one. Before data cache is enabled, it must be invalidated.

Data Cache Invalidation

Data cache in OR1200 does not support invalidation of entire data cache. Normal procedure to invalidate entire data cache is to cycle through all data cache lines and invalidate each line separately.

Data Cache Locking

Data cache implements way locking bits in data cache control register DCCR. Bits LWx lock individual ways when they are set to one.

Data Cache Line Prefetch

Data cache line prefetch is optional in the OpenRISC 1000 architecture and is not implemented in OR1200.

Data Cache Line Flush

Operation is performed by writing effective address to the DCBFR register.

When a cache line is valid and clean, or the cache is in write-through strategy, the line is invalidated and no write-back occurs.

Data Cache Line Invalidate

Data cache line invalidate invalidates a single data cache line. Operation is performed by writing effective address to the DCBIR register.
If cache is in write-back strategy, it is best to use the line flush function.

Data Cache Line Write-back

Operation is performed by writing effective address to the DCBWR register.

If cache is in write-through strategy, this operation is ignored as no lines will be cached and dirty, capable of being written back.

Data Cache Line Lock

Locking of individual data cache lines is not implemented in OR1200.

Data Cache inhibit with address bit 31 set

If DMMU is disabled, by default all addresses with bit 31 of the address asserted high will cause the data cache to be inhibited, meaning no reads or writes are cached.

If the DMMU is enabled, it is possible for any address to be inhibited or not, and in these modes the cache behaves accordingly.


Instruction Cache Operation

Instruction Cache Instruction Fetch Access

Instruction unit requests instruction from the instruction cache and forwards them to the instruction queue inside instruction unit. Therefore instruction unit is tightly coupled with the instruction cache.

If there is no instruction cache line miss nor ITLB miss, instruction fetch operation takes one clock cycle to execute.

Instruction cache cannot be explicitly modified like data cache can be with store instructions.

Instruction Cache Line Fill Operation

On a cache miss, a 4 beat sequential read burst with critical word first is performed. Critical word is forwarded to the instruction unit to minimize performance loss because of the cache miss.

 EMBED  
Figure  SEQ "Figure" \*Arabic 9. WISHBONE Block Read Cycle

 REF _Ref513197552 \h Figure 9 shows how a cache line is read in WISHBONE read block cycle composed out of four read transfers.
If iwb_ERR_I or iwb_RTY_I is asserted instead of usual dwb_ACK_I, bus error exception is invoked.

Cache/Memory Coherency

OR1200 is not intended for use in multiprocessor environments. Therefore no support for coherency between local instruction cache and caches of other processors or main memory is implemented.

Instruction Cache Enabling/Disabling

Instruction cache is disabled at power up. Entire instruction cache can be enabled by setting bit SR[ICE] to one. Before instruction cache is enabled, it must be invalidated.

Instruction Cache Invalidation

Instruction cache in OR1200 does not support invalidation of entire instruction cache. Normal procedure to invalidate entire instruction cache is to cycle through all instruction cache lines and invalidate each line separately.

Instruction Cache Locking

Instruction cache implements way locking bits in instruction cache control register ICCR. Bits LWx lock individual ways when they are set to one.

Instruction Cache Line Prefetch

Instruction cache line prefetch is optional in the OpenRISC 1000 architecture and is not implemented in OR1200.

Instruction Cache Line Invalidate

Instruction cache line invalidate invalidates a single instruction cache line. Operation is performed by writing effective address to the ICBIR register.

Instruction Cache Line Lock

Locking of individual instruction cache lines is not implemented in OR1200.

Data MMU

Translation Disabled

Load/store address translation can be disabled by clearing bit SR[DME]. If translation is disabled, then physical address used to access data cache and optionally provided on dwb_ADDR_O, is the same as load/store effective address.

Translation Enabled

Load/store address translation can be enabled by setting bit SR[DME]. If translation is enabled, it provides load/store effective address to physical address translation and page protection for memory accesses.

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Figure  SEQ "Figure" \*Arabic 10. 32-bit Address Translation Mechanism using Two-Level Page Table

In OR1200 case, page tables must be managed by operating system s virtual memory management subsystem.  REF _Ref513343227 \h Figure 10 shows address translation using two-level page table. Refer to OpenRISC 1000 System Architecture Manual for one-level page table address translation as well as for details about address translation and page table content.

DMMUCR and Flush of Entire DTLB

DMMUCR is not implemented in OR1200. Therefore page table base pointer (PTBP) must be stored in software variable. Flush of entire DTLB must be performed by software flush of every DTLB entry separately. Software flush is performed by manually writing  bits from the TLB entries back to PTEs.

Page Protection

After a virtual address is determined to be within a page covered by the valid PTE, the access is validated by the memory protection mechanism. If this protection mechanism prohibits the access, a data page fault exception is generated.

The memory protection mechanism allows selectively granting read access and write access for both supervisor and user modes. The page protection mechanism provides protection at all page level granularities.

Protection attributeMeaningDTLBWyTR[SREx]Enable load operations in supervisor mode to the page.DTLBWyTR[SWEx]Enable store operations in supervisor mode to the page.DTLBWyTR[UREx]Enable load operations in user mode to the page.DTLBWyTR[UWEx]Enable store operations in user mode to the page.Table  SEQ "Table" \*Arabic 11. Protection Attributes for Load/Store Accesses

 REF _Ref513346094 \h Table 11 lists page protection attributes defined in DTLBWyTR pregister. For the individual page appropriate strategy out of seven possible strategies programmed with the PPI field of the PTE. Because OR1200 does not implement DMMUPR, translation of PTE[PPI] into suitable set of protection bits must be performed by software and written into DTLBWyTR.

DTLB Entry Reload

OR1200 does not implement DTLB entry reloads in hardware. Instead software routine must be used to search page table for correct page table entry (PTE) and copy it into the DTLB. Software is responsible for maintaining accessed and dirty bits in the page tables.

When LSU computes load/store effective address whose physical address is not already cached by DTLB, a DTLB miss exception is invoked.

DTLB reload routine must load the correct PTE to correct DTLBWyMR and DTLBWyTR register from one of possible DTLB ways.

DTLB Entry Invalidation

Special-purpose register DTLBEIR must be written with the effective address and corresponding DTLB entry will be invalidated in the local DTLB.

Locking DTLB Entries

Since all DTLB entry reloads are performed in software, there is no hardware locking of DTLB entries. Instead it is up to the software reload routine to avoid replacing some of the entries if so desired.

Page Attribute   Dirty (D)

Dirty (D) attribute is not implemented in OR1200 DTLB. It is up to the operating system to generate dirty attribute bit with page protection mechanism.

Page Attribute   Accessed (A)

Accessed (A) attribute is not implemented in OR1200 DTLB. It is up to the operating system to generate accessed attribute bit with page protection mechanism.

Page Attribute   Weakly Ordered Memory (WOM)

Weakly ordered memory (WOM) attribute is not needed in OR1200 because all memory accesses are serialized and therefore this attribute is not implemented.

Page Attribute   Write-Back Cache (WBC)

Write-back cache (WBC) attribute is not implemented as the data cache cannot be configured at run time to be write-back enabled if write-through strategy was selected at synthesis-time.

Page Attribute   Caching-Inhibited (CI)

Caching-inhibited (CI) attribute is not implemented in OR1200 DTLB. Cached and uncached regions are divided by bit 30 of data effective address.

Effective AddressRegion0x00000000 - 0x3FFFFFFFCached0x40000000 - 0x7FFFFFFFUncached0x80000000 - 0xBFFFFFFFCached0xC0000000 - 0xFFFFFFFFUncachedTable  SEQ "Table" \*Arabic 12.  Cached and uncached regions

Uncached accesses must be performed when I/O registers are memory mapped and all reads and writes must be always performed directly to the external interface and not to the data cache.

Page Attribute   Cache Coherency (CC)

Cache coherency (CC) attribute is not needed in OR1200 because it doesn t implement support for multiprocessor environments and because data cache operates only in write-through mode and therefore this attribute is not implemented.

Instruction MMU

Translation Disabled

Instruction fetch address translation can be disabled by clearing bit SR[IME]. If translation is disabled, then physical address used to access instruction cache and optionally provided on iwb_ADDR_O, is the same as instruction fetch effective address.

Translation Enabled

Instruction fetch address translation can be enabled by setting bit SR[IME]. If translation is enabled, it provides instruction fetch effective address to physical address translation and page protection for instruction fetch accesses.

 EMBED Microsoft Visio Drawing 
Figure  SEQ "Figure" \*Arabic 11. 32-bit Address Translation Mechanism using Two-Level Page Table

In OR1200 case, page tables must be managed by operating system s virtual memory management subsystem.  REF _Ref513343227 \h Figure 10 shows address translation using two-level page table. Refer to OpenRISC 1000 System Architecture Manual for one-level page table address translation as well as for details about address translation and page table content.

IMMUCR and Flush of Entire ITLB

IMMUCR is not implemented in OR1200. Therefore page table base pointer (PTBP) must be stored in software variable. Flush of entire ITLB must be performed by software flush of every ITLB entry separately. Software flush is performed by manually writing bits from the TLB entries back to PTEs.

Page Protection

After a virtual address is determined to be within a page covered by the valid PTE, the access is validated by the memory protection mechanism. If this protection mechanism prohibits the access, an instruction page fault exception is generated.

The memory protection mechanism allows selectively granting execute access for both supervisor and user modes. The page protection mechanism provides protection at all page level granularities.

Protection attributeMeaningITLBWyTR[SXEx]Enable execute operations in supervisor mode of the page.ITLBWyTR[UXEx]Enable execute operations in user mode of the page.Table  SEQ "Table" \*Arabic 13. Protection Attributes for Instruction Fetch Accesses

 REF _Ref513346094 \h Table 11 lists page protection attributes defined in ITLBWyTR pregister. For the individual page appropriate strategy out of seven possible strategies programmed with PPI field of the PTE. Because OR1200 does not implement IMMUPR, translation of PTE[PPI] into suitable set of protection bits must be performed by software and written into ITLBWyTR.


ITLB Entry Reload

OR1200 does not implement ITLB entry reloads in hardware. Instead software routine must be used to search page table for correct page table entry (PTE) and copy it into the ITLB. Software is responsible for maintaining accessed bit in the page tables.

When LSU computes instruction fetch effective address whose physical address is not already cached by ITLB, an ITLB miss exception is invoked.

ITLB reload routine must load the correct PTE to correct ITLBWyMR and ITLBWyTR register from one of possible ITLB ways.

ITLB Entry Invalidation

Special-purpose register ITLBEIR must be written with the effective address and corresponding ITLB entry will be invalidated in the local ITLB.

Locking ITLB Entries

Since all ITLB entry reloads are performed in software, there is no hardware locking of ITLB entries. Instead it is up to the software reload routine to avoid replacing some of the entries if so desired.

Page Attribute   Dirty (D)

Dirty (D) attribute resides in the PTE but it is not used by the IMMU.

Page Attribute   Accessed (A)

Accessed (A) attribute is not implemented in OR1200 ITLB. It is up to the operating system to generate accessed attribute bit with page protection mechanism.

Page Attribute   Weakly Ordered Memory (WOM)

Weakly ordered memory (WOM) attribute is not needed in OR1200 because all instruction fetch accesses are serialized and therefore this attribute is not implemented.

Page Attribute   Write-Back Cache (WBC)

Write-back cache (WBC) attribute resides in the PTE but it is not used by the IMMU.

Page Attribute   Caching-Inhibited (CI)

Caching-inhibited (CI) attribute is not implemented in OR1200 ITLB. Cached and uncached regions are divided by bit 30 of instruction effective address.

Effective AddressRegion0x00000000 - 0x3FFFFFFFCached0x40000000 - 0x7FFFFFFFUncached0x80000000 - 0xBFFFFFFFCached0xC0000000 - 0xFFFFFFFFUncachedTable  SEQ "Table" \*Arabic 14.  Cached and uncached regions

Page Attribute   Cache Coherency (CC)

Cache coherency (CC) attribute resides in the PTE but it is not used by the IMMU.

Programmable Interrupt Controller

PICMR special-purpose register is used to mask or unmask up to 30 programmable interrupt sources. PICPR special-purpose register is used to assign low or high priority to maximum of 30 interrupt sources.

PICSR special-purpose register is used to determine status of each interrupt input. Bits in PICSR represent status of the interrupt inputs and the actual interrupt must be cleared in the device that is the source of a pending interrupt.

The PIC implementation in the OR1200  differs from the architecture specification. The PIC instead offers a latched level-sensitive interrupt.

Once an interrupt line is latched (i.e. its value appears in PICSR), no new interrupts can be triggered for that line until its bit in PICSR is cleared. The usual sequence for an interrupt handler is then as follows.

Peripheral asserts interrupt, which is latched and triggers handler. 
Handler processes interrupt.
Handler notifies peripheral that the interrupt has been processed (typically via a memory mapped register).
 Peripheral deasserts interrupt.
Handler clears corresponding bit in PICSR and returns.

It is assumed that the peripheral will de-assert its interrupt promptly (within 1-2 cycles). Otherwise on exiting the interrupt handler, having cleared PICSR, the level sensitive interrupt will immediately retrigger.

Tick Timer

Tick timer facility is enabled with TTMR[M]. TTCR is incremented with each clock cycle and a high priority interrupt can be asserted whenever lower 28 bits of TTCR match TTMR[TP] and TTMR[IE] is set.

TTCR restarts counting from zero when match event happens and TTMR[M] is 0x1. If TTMR[M] is 0x2, TTCR is stoped when match event happens and TTCR must be changed to start counting again. When TTMR[M] is 0x3, TTCR keeps counting even when match event happens.

Power Management

Clock Gating and Frequency Changing Versus CPU Stalling

If system doesn t support clock gating and if changing clock frequency in slow down mode is not possible, CPU can be stalled for certain number of clock cycles. This is much lower benefit on power consumption however it still reduces power consumption.

Slow Down Mode

Slow down mode is software controlled with the 4-bit value in PMR[SDF]. Lower value specifies higher expected performance from the processor core. Usually PMR[SDF] is dynamically set by the operating system s idle routine, that monitors the usage of the processor core.

PMR[SDF] is broadcasted on pm_clksd. External clock generator should adjust clock frequency according to the value of pm_clksd. Exact slow down factors are not defined but 0xF should go all the way down to 32.768 KHz.

With pm_clksd equal to 0xF, pm_lvolt is asserted. This is an indication for the external power supply to lower the voltage.

Doze Mode

To switch to doze mode, software should set the PMR[DME]. Once an interrupt is received by the programmable interrupt controller (PIC), pm_wakeup is asserted and external clock generation circuitry should enable all clocks. Once clocks are running RISC is switched back again to the normal mode and PMR[DME] is cleared.

When doze mode is enabled, pm_dc_gate, pm_ic_gate, pm_dmmu_gate, pm_immu_gate and pm_cpugate are asserted. As a result all clocks except clk_tt should be gated by external clock generation circuitry.

Sleep Mode

To switch to sleep mode, software should set the PMR[SME]. Once an interrupt is received by the programmable interrupt controller (PIC), pm_wakeup is asserted and external clock generation should enable all clocks. Once clocks are running, RISC is switched back again to the normal mode and PMR[SME] is cleared.

When sleep mode is enabled, pm_dc_gate, pm_ic_gate, pm_dmmu_gate, pm_immu_gate, pm_cpu_gate and pm_tt_gate are asserted. As a result all clocks including clk_tt should be gated by external clock generation circuitry.

In sleep mode, pm_lvolt is asserted. This is an indication for the external power supply to lower the voltage.

Clock Gating

Clock gating feature is not implemented in OR1200 power management. 

Disabled Units Force Clock Gating

Units that are disabled in special-purpose register SR, have their clock gate signals asserted. Cleared bits SR[DCE], SR[ICE], SR[DME] and SR[IME] directly force assertion of pm_dc_gate, pm_ic_gate, pm_dmmu_gate and pm_immu_gate.

Debug Unit

Debug unit can be controlled through development interface or it can operate independently programmed and handled by the RISC s resident debug software.

Watchpoints

OR1200 debug unit does not implement OR12000 architecture watchpoints.

Breakpoint Exception

Which breakpointDMR2[WGB] bits specify which watchpoints invoke breakpoint exception. By invoking breakpoint exception, target resident debugger can be built.

Breakpoint is broadcasted on development interface on dbg_bp_o.

Development Interface

NOTE: The information in this section is to be reviewed. It is the author's opinion that the debug interface is now largely provided by the SPR mappings, and no special sideband functions exist aside from stalling and resetting the core.

An additional development and debug interface IP core may be used to connect OpenRISC 1200 to standard debuggers using IEEE.1149.1 (JTAG) protocol.

Debugging Through Development Interface

The DSR special-purpose register specifies which exceptions cause the core to stop the execution of the exception handler and turn over control to development interface. It can be programmed by the resident debug software or by the development interface.

The DRR special-purpose register is specifies which event caused the core to stop the execution of program flow and turned over control to the development interface. It should be cleared by the resident debug software or by the development interface.

The DIR special-purpose register is not implemented.

Reading PC, Load/Store EA, Load Data, Store Data, Instruction

Crucial information like program counter (PC), load/store effective address (LSEA), load data, store data and current instruction in execution pipeline can be asynchronously read through the development interface.

dbg_op_i[2:0]Meaning0x0Reading Program Counter (PC)0x1Reading Load/Store Effective Address0x2Reading Load Data0x3Reading Store Data0x4Reading SPR0x5Writing SPR0x6Reading Instruction in Execution Pipeline0x7ReservedTable  SEQ "Table" \*Arabic 15. Development Interface Operation Commands

 REF _Ref513329306 \h Table 15 lists operation commands that control what is read or written through development interface. All reads except reads and writes of SPRs are asynchronous.

Reading and Writing SPRs Through Development Interface

For reads and write to SPRs dbg_op_i must be set to 0x4 and 0x5, respectively.

 EMBED  
Figure  SEQ "Figure" \*Arabic 12. Development Interface Cycles

 REF _Ref513329852 \h Figure 12 shows development interface cycles. Writes must be synchronous to the main RISC clock positive edge and should take one clock cycle. Reads must take two clock cycles because access to synchronous cache lines or to TLB entries introduces one clock cycle of delay.

If required, external debugger can stop the CPU core by asserting dbg_stall_i. This way it can have enough time to read all interesting registers from the RISC or guarantee that writes into SPRs are performed without RISC writing to the same registers.

Tracking Data Flow

An external debugger can monitor and record data flow inside the RISC for debugging purposes and profiling analysis. This is accomplished by monitoring status of the load/store unit, load/store effective address and load/store data, all available at the development interface.

dbg_lss_o[3:0]Load/Store Instruction in Execution0x0No load/store instruction in execution0x1Reserved for load doubleword0x2Load byte and zero extend0x3Load byte and sign extend0x4Load halfword and zero extend0x5Load halfword and sign extend0x6Load singleword and zero extend0x7Load singleword and sign extend0x8Reserved for store doubleword0x9Reserved0xAStore byte0xBReserved0xCStore halfword0xDReserved0xEStore singleword0xFReservedTable  SEQ "Table" \*Arabic 16. Status of the Load/Store Unit

External trace buffer can capture all interesting data flow events by analyzing status of the load/store unit available on dbg_lss_o.  REF _Ref513326484 \h Table 16 lists different status encoding for the load/store unit.

Tracking Program Flow

An external debugger can monitor and record program flow inside the RISC for debugging purposes and profiling analysis. This is accomplished by monitoring status of the instruction unit, PC and fetched instruction word, all available at the development interface.

dbg_is_o[1:0]Instruction Fetch Status0x0No instruction fetch in progress0x1Normal instruction fetch0x2Executing branch instruction0x3Fetching instruction in delay slotTable  SEQ "Table" \*Arabic 17. Status of the Instruction Unit

External trace buffer can capture all interesting program flow events by analyzing status of the instruction unit available on dbg_is_o.  REF _Ref513326219 \h Table 17 lists different status encoding for the instruction unit.

Triggering External Watcpoint Event

 REF _Ref513324670 \h Figure 13 shows how development interface can assert dbg_ewt_I and cause watchpoint event. If programmed, external watchpoint event will cause a breakpoint exception.

 EMBED  
Figure  SEQ "Figure" \*Arabic 13. Assertion of External Watchpoint Trigger
4
Registers

This section describes all registers inside the OR1200 core. Shifting GRP number 11 bits left and adding REG number computes the address of each special-purpose register. All registers are 32 bits wide from software perspective. USER MODE and SUPV MODE specify the valid access types for each register in user mode and supervisor mode of operation. R/W stands for read and write access and R stands for read only access.

Registers list

Grp
#Reg #Reg NameUSER MODESUPV
MODEDescription00VR RVersion Register01UPR RUnit Present Register02CPUCFGR RCPU Configuration Register03DMMUCFGR RData MMU Configuration Register04IMMUCFGR RInstruction MMU Configuration Register05DCCFGR RData Cache Configuration Register06ICCFGR RInstruction Cache Configuration Register07DCFGR RDebug Configuration Register016PC R/WPC mapped to SPR space017SR R/WSupervision Register020FPCSR-R/WFP Control Status Register032EPCR0 R/WException PC Register048EEAR0 R/WException EA Register064ESR0 R/WException SR Register01024-1055GPR0-GPR31 R/WGPRs mapped to SPR space12DTLBEIR WData TLB Entry Invalidate Register11024-1151DTLBW0MR0-DTLBW0MR127 R/WData TLB Match Registers Way 011536-1663DTLBW0TR0-DTLBW0TR127 R/WData TLB Translate Registers Way 022ITLBEIR WInstruction TLB Entry Invalidate Register21024-1151ITLBW0MR0-ITLBW0MR127 R/WInstruction TLB Match Registers Way 021536-1663ITLBW0TR0-ITLBW0TR127 R/WInstruction TLB Translate Registers Way 030DCCR R/WDC Control Register32DCBFRWWDC Block Flush Register33DCBIRWWDC Block Invalidate Register34DCBWRWWDC Block Write-back register40ICCR R/WIC Control Register4256ICBIRWWIC Block Invalidate Register5256MACLOR/WR/WMAC Low5257MACHIR/WR/WMAC High616DMR1 R/WDebug Mode Register 1617DMR2 R/WDebug Mode Register 2620DSR R/WDebug Stop Register621DRR R/WDebug Reason Register80PMR R/WPower Management Register90PICMR R/WPIC Mask Register92PICSR R/WPIC Status Register100TTMR R/WTick Timer Mode Register101TTCRR*R/WTick Timer Count RegisterTable  SEQ "Table" \*Arabic 18. List of All Registers

 REF _Ref513309410 \h Table 18 lists all OpenRISC 1000 special-purpose registers implemented in OR1200. Registers VR and UPR are described below. For description of other registers refer to OpenRISC 1000 System Architecture Manual document.

Register VR description

Special-purpose register VR identifies the version (model) and revision level of the OpenRISC 1000 processor. It also specifies possible standard template on which this implementation is based.

Bit #AccessResetDescription5:0RRevisionREV
Revision number of this document.15:6R0x0Reserved23:16R0x00CFG
Configuration should be read from UPR and configuration registers31:24R0x12VER
Version number for OR1200 is fixed at 0x1200.Table  SEQ "Table" \*Arabic 19. VR Register

Register UPR description

Special-purpose register UPR identifies the units present in the processor. It has a bit for each implemented unit or functionality. Lower sixteen bits identify present units defined in the OpenRISC 1000 architecture. Upper sixteen bits define present custom units.

Bit #AccessResetDescription0R1UP
UPR present1R1DCP
Data cache present*2R1ICP
Instruction cache present*3R1DMP
Data MMU present*4R1IMP
Instruction MMU present*5R1MP
MAC present*6R1DUP
Debug unit present*7R0PCUP
Performance counters unit not present*8R1PMP
Power Management Present*9R1PICP
Programmable interrupt controller present10R1TTP
Tick timer present11R1FPP
Floating point present*23:12RXReserved31:24R0xXXXXCUP
The user of the OR1200 core adds custom units.Table  SEQ "Table" \*Arabic 20. UPR Register
* if enabled at synthesis time

Register CPUCFGR description

Special-purpose register CPUCFGR identifies the capabilities and configuration of the CPU. 

Bit #AccessResetDescription3:0R0x0NSGF
Zero number of shadow GPR files4R0HGF
No half GPR files*5R1OB32S
ORBIS32 supported6R0OB64S
ORBIS64 not supported7R1OF32S
ORFPX32 supported**8R0OF64S
ORFPX64 not supported9R0OV64S
ORVDX64 not supportedTable  SEQ "Table" \*Arabic 21. CPUCFGR Register
* If disabled at synthesis time
** If FPU enabled at synthesis time

Register DMMUCFGR description

Special-purpose register DMMUCFGR identifies the capabilities and configuration of the DMMU. 

Bit #AccessResetDescription1:0R0x0NTW
One DTLB way4:2R0x4   0x7NTS
16, 32, 64 or 128 DTLB sets7:5R0x0NAE
No ATB Entries8R0CRI
No DMMU control register implemented9R0PRI
No protection register implemented10R1TEIRI
DTLB entry invalidate register implemented11R0HTR
No hardware DTLB reloadTable  SEQ "Table" \*Arabic 22. DMMUCFGR Register

Register IMMUCFGR description

Special-purpose register IMMUCFGR identifies the capabilities and configuration of the IMMU. 

Bit #AccessResetDescription1:0R0x0NTW
One ITLB way4:2R0x4   0x7NTS
16, 32, 64 or 128 ITLB sets7:5R0x0NAE
No ATB Entries8R0CRI
No IMMU control register implemented9R0PRI
No protection register implemented10R1TEIRI
ITLB entry invalidate register implemented11R0HTR
No hardware ITLB reloadTable  SEQ "Table" \*Arabic 23. IMMUCFGR Register

Register DCCFGR description

Special-purpose register DCCFGR identifies the capabilities and configuration of the data cache. 

Bit #AccessResetDescription2:0R0x0NCW
One DC way6:3R0x4   0x7NCS
16, 32, 64 or 128 DC sets7R0x0CBS
16-byte cache block size8R0CWS
Cache write-through strategy*9R1CCRI
DC control register implemented10R1CBIRI
DC block invalidate register implemented11R0CBPRI
DC block prefetch register not implemented12R0CBLRI
DC block lock register not implemented13R1CBFRI
DC block flush register implemented14R1CBWBRI
DC block write-back register  implemented**Table  SEQ "Table" \*Arabic 24. DCCFGR Register
*If Write-through enabled at synthesis time
**If Write-through disabled at synthesis time


Register ICCFGR description

Special-purpose register ICCFGR identifies the capabilities and configuration of the instruction cache. 

Bit #AccessResetDescription2:0R0x0NCW
One IC way6:3R0x4   0x7NCS
16, 32, 64 or 128 IC sets7R0x0CBS
16-byte cache block size8R0CWS
Cache write-through strategy9R1CCRI
IC control register implemented10R1CBIRI
IC block invalidate register implemented11R0CBPRI
IC block prefetch register not implemented12R0CBLRI
IC block lock register not implemented13R1CBFRI
IC block flush register implemented14R0CBWBRI
IC block write-back register not implementedTable  SEQ "Table" \*Arabic 25. ICCFGR Register

Register DCFGR description

Special-purpose register DCFGR identifies the capabilities and configuration of the debut unit. 

Bit #AccessResetDescription3:0R0x0NDP
Zero DVR/DCR pairs*4R0 WPCI
Watchpoint counters not implementedTable  SEQ "Table" \*Arabic 26. DCFGR Register
* If hardware breakpoints disabled at synthesis time
        


5
IO ports

OR1200 IP core has several interfaces.  REF _Ref507257694 \h Figure 14 below shows all interfaces:
Instruction and data WISHBONE host interfaces
Power management interface
Development interface
Interrupts interface

 EMBED Microsoft Visio Drawing 

Figure  SEQ "Figure" \*Arabic 14. Core s Interfaces

Instruction WISHBONE Master Interface

OR1200 has two master WISHBONE Rev B compliant interfaces. Instruction interface is used to connect OR1200 core to memory subsystem for purpose of fetching instructions or instruction cache lines.

PortWidthDirectionDescriptioniwb_CLK_I1InputClock inputiwb_RST_I1InputReset inputiwb_CYC_O1OutputIndicates valid bus cycle (core select)iwb_ADR_O32OutputsAddress outputsiwb_DAT_I32InputsData inputsiwb_DAT_O32OutputsData outputsiwb_SEL_O4OutputsIndicates valid bytes on data bus (during valid cycle it must be 0xf)iwb_ACK_I1InputAcknowledgment input (indicates normal transaction termination)iwb_ERR_I1InputError acknowledgment input (indicates an abnormal transaction termination)iwb_RTY_I1InputIn OR1200 treated same way as iwb_ERR_I.iwb_WE_O1OutputWrite transaction when asserted highiwb_STB_O1OutputsIndicates valid data transfer cycleTable  SEQ "Table" \*Arabic 27. Instruction WISHBONE Master Interface  Signals

Data WISHBONE Master Interface

OR1200 has two master WISHBONE Rev B compliant interfaces. Data interface is used to connect OR1200 core to external peripherals and memory subsystem for purpose of reading and writing data or data cache lines.

PortWidthDirectionDescriptiondwb_CLK_I1InputClock inputdwb_RST_I1InputReset inputdwb_CYC_O1OutputIndicates valid bus cycle (core select)dwb_ADR_O32OutputsAddress outputsdwb_DAT_I32InputsData inputsdwb_DAT_O32OutputsData outputsdwb_SEL_O4OutputsIndicates valid bytes on data bus (during valid cycle it must be 0xf)dwb_ACK_I1InputAcknowledgment input (indicates normal transaction termination)dwb_ERR_I1InputError acknowledgment input (indicates an abnormal transaction termination)dwb_RTY_I1InputIn OR1200 treated same way as dwb_ERR_I.dwb_WE_O1OutputWrite transaction when asserted highdwb_STB_O1OutputsIndicates valid data transfer cycleTable  SEQ "Table" \*Arabic 28. Data WISHBONE Master Interface  Signals

System Interface

System interface connects reset, clock and other system signals to the OR1200 core.

PortWidthDirectionDescriptionRst1InputAsynchronous resetclk_cpu1InputMain clock input to the RISCclk_dc1InputData cache clockclk_ic1InputInstruction cache clockclk_dmmu1InputData MMU clockclk_immu1InputInstruction MMU clockclk_tt1InputTick timer clockTable  SEQ "Table" \*Arabic 29. System Interface Signals

Development Interface

Development interface connects external development port to the RISC s internal debug facility. Debug facility allows control over program execution inside RISC, setting of breakpoints and watchpoints, and tracing of instruction and data flows.

PortWidthDirectionDescriptiondbg_dat_o32OutputTransfer of data from RISC to external development interfacedbg_dat_i32InputTransfer of data from external development interface to RISCdbg_adr_i32InputAddress of special-purpose register to be read or writtendbg_op_I3InputOperation select for development interfacedbg_lss_o4OutputStatus of load/store unitdbg_is_o2OutputStatus of instruction fetch unitdbg_wp_o11OutputStatus of watchpointsdbg_bp_o1OutputStatus of the breakpointdbg_stall_i1InputStalls RISC CPU coredbg_ewt_i1InputExternal watchpoint triggerTable  SEQ "Table" \*Arabic 30. Development Interface

Power Management Interface

Power management interface provides signals for interfacing RISC core with external power management circuitry. External power management circuitry is required to implement functions that are technology specific and cannot be implemented inside OR1200 core.

PortWidthDirectionGenerationDescriptionpm_clksd4OutputStatic (in SW)Slow down outputs that control reduction of RISC clock frequencypm_cpustall1Input-Synchronous stall of the RISC s CPU corepm_dc_gate1OutputDynamic (in HW)Gating of data cache clockpm_ic_gate1OutputDynamic (in HW)Gating of instruction cache clockpm_dmmu_gate1OutputDynamic (in HW)Gating of data MMU clockpm_immu_gate1OutputDynamic (in HW)Gating of instruction MMU clockpm_tt_gate1OutputDynamic (in HW)Gating of tick timer clockpm_cpu_gate1OutputStatic (in SW)Gating of main CPU clockpm_wakeup1OutputDynamic (in HW)Activate all clockspm_lvolt1OutputStatic (in SW)Lower voltageTable  SEQ "Table" \*Arabic 31. Power Management Interface

Interrupt Interface

Interrupt interface has interrupt inputs for interfacing external peripheral s interrupt outputs to the RISC core. All interrupt inputs are evaluated on positive edge of main RISC clock.

PortWidthDirectionDescriptionpic_intsPIC_INTSInputExternal interruptsTable  SEQ "Table" \*Arabic 32. Interrupt Interface
A
Core HW Configuration

This section describes parameters that are set by the user of the core and define configuration of the core. Parameters must be set by the user before actual use of the core in simulation or synthesis.

Variable NameRangeDefaultDescriptionEADDR_WIDTH3232Effective address widthVADDR_WIDTH3232Virtual address widthPADDR_WIDTH24   3632Physical address widthDATA_WIDTH3232Data width / Operation widthDC_IMPL0   11Data cache implementationDC_SETS256-1024512Data cache number of setsDC_WAYS11Data cache number of waysDC_LINE16 - 3216Data cache line sizeIC_IMPL0   11Instruction cache implementationIC_SETS32-1024512Instruction cache number of setsIC_WAYS11Instruction cache number of waysIC_LINE16-3216Instruction cache line size in bytesDMMU_IMPL0   11Data MMU implementationDTLB_SETS6464Data TLB number of setsDTLB_WAYS11Data TLB number of waysIMMU_IMPL0   11Instruction MMU implementationITLB_SETS6464Instruction TLB number of setsITLB_WAYS11Instruction TLB number of waysPIC_INTS2   3220Number of interrupt inputsTable  SEQ "Table" \*Arabic 33: Core HW configuration table



OpenCores        TITLE OpenRISC 1200 IP Core  DATE \@"M/D/YY" 9/1/11



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$If$a$G$$IfG$|$$If\vTj!     (p(44444f4$IfG$&(2B^Tzog_WOG$IfG$$IfG$$IfG$$IfG$$IfG$
Timing Diagram Editor v7.1g - Output File
$If$a$G$$IfG$|$$If\vTj!     (p(44444f4TVX|~Lzsqke_Y
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LibPath

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EntireTime      YES

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|"xZH
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Nh6
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PrintTo 2

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PrintFileName   C:\DOCS\dbg_readwritespr.wmf

!
PreviewInterchange      YES

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PreviewTIFF5    NO

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!
PrintTimeLine   NO

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DefaultClock    Unclocked

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DefaultEdgeLevel        neg

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DefaultSet      Not Used

!
DefaultClear    Not Used

!
DefaultClockEnable      Not Used

!
DefaultClockToOutLH     0

!
DefaultClockToOutHL     0

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PROPS!

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&F$
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!
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&F$
!
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t1162223:3v333,4f445556b6
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!
DIAGRAMTESTBENCHSETTINGS

!
FilesBeforeDiagramModel

!
FilesInsideDiagramModelDeclarationSection

!
AbortHdlCodeEnabled     1

!
DelayHdlCodeEnabled     1

!
SampleHdlCodeEnabled    1

!
MarkerHdlCodeEnabled    1

!
VerboseSamples  0

!
VerboseDelays   0

!
VerboseFileInput        0

!
VerboseSequenceVerification     0

!
IncludeDelayTime        1

!
ExecuteFromTopLevel     1

!
TimeOutInDiagramLengths 0

!
DefaultCycleClock       Unclocked
b6666677:P<R<r<t<@@~CCxFzFFFG$a$$a$$a$
DefaultCycleEdge        neg
&F$a$$a$$a$
!
&F$
!

!
MACROS

!
!
GI`JKMM>OOOOOBPPPQQRRR8R:R$a$
&F$$a$
CORGROUP        $$CLK_I_BufferRising
&F$a$
Percent 100
&F
$a$$a$
!
&F$a$$a$$a$$a$$a$:R:SnSSS$TvTTT@UUUU@VVVVVV*XhYjYY$a$$a$$a$$a$
&F$a$$a$$a$$$a$
CORGROUP        $$CLK_I_BufferFalling
&F$a$$a$Y.Z0ZRZTZ\^_````bbcc
Percent 100
dde0f$a$$a$
!
&F$a$$a$$a$$a$$a$$a$$a$$a$$a$$a$$a$
&F$a$0fff&gvgxghh iiiii^jjjjk k&l(l:l$a$$a$$a$
CORGROUP        $$CLK_I_BufferRisingFalling
&F$a$$a$$a$
Percent 100
&F$a$
!
&F$a$$a$$a$
&F$a$:l
CORGROUP        $$CLK_I_BufferRising
pqq q"qrrrrstFtttJu
Percent 100
&F$a$$a$$a$$a$$a$$a$$a$
!
&F$a$$a$$a$JuLuwwwwlynypyyynR$$If0
      p44l44l4f4T$If$a$G$x$If$a$G$x$a$$a$
CORGROUP        $$CLK_I_BufferFalling
&F$a$$a$$a$
Percent 100
yyyyz zp$If$a$G$x$If$a$G$xR$$If0
!
      p44l44l4f4T$If$a$G$x$If$a$G$x z"zZzdzfz;R$$If0
      p44l44l4f4T$If$a$G$x$If$a$G$xR$$If0
CORGROUP        $$CLK_I_BufferRisingFalling
      p44l44l4f4TfzzzzH{J{R|T|h||}p~~~vvvvv
Percent 100
&F$a$$a$$a$R$$If0
!
      p44l44l4f4T$If$a$G$x$If$a$G$x
؃<>bdHJLh$If$a$G$x$If$a$G$x$a$$a$
&F$a$$a$$a$$a$$a$$a$$a$$a$$a$hj;R$$If0
CORGROUP        $$CLK_I_BufferRising
      p44l44l4f4T$If$a$G$x$If$a$G$xR$$If0
Percent 100
      p44l44l4f4T <p$If$a$G$x$If$a$G$xR$$If0
!
      p44l44l4f4T$If$a$G$x$If$a$G$x<>v;R$$If0
      p44l44l4f4T$If$a$G$x$If$a$G$xR$$If0
CORGROUP        $$CLK_I_BufferFalling
      p44l44l4f4TċƋrtЍ>@zzzzup$a$$a$
Percent 100
&F$a$$a$$a$R$$If0
!
      p44l44l4f4T$If$a$G$x$If$a$G$xȔʔ\^prRTVr$If$a$G$x$If$a$G$x$a$$a$
&F$a$$a$$a$$a$$a$$a$$a$
rt;R$$If0  p44l44l4f4T$If$a$G$x$If$a$G$xR$$If0       p44l44l4f4T*^p$If$a$G$x$If$a$G$xR$$If0     p44l44l4f4T$If$a$G$x$If$a$G$x^`F;6$a$R$$If0       p44l44l4f4T$If$a$G$x$If$a$G$xR$$If0       p44l44l4f4TFH\Ԛ8^8:$If$a$G$x$a$$a$
CORGROUP        $$CLK_I_BufferRisingFalling
&F$a$$a$$a$$a$$a$
Percent 100
&F$a$
!
&F$a$$a$@`$If$a$G$x$If$a$G$xR$$If0	p44l44l4f4T$If$a$G$x`b;R$$If0  p44l44l4f4T$If$a$G$x$If$a$G$xR$$If0       p44l44l4f4TР.Pp$If$a$G$x$If$a$G$xR$$If0     p44l44l4f4T$If$a$G$x$If$a$G$xPRdԢȣNԤ֤$a$$a$
&F$a$
CORGROUP        $$CLK_I_BufferRising
&F$a$$a$$a$R$$If0       p44l44l4f4T ֥إHtv$a$$a$
Percent 100
&F$a$$a$$a$$a$$a$$a$$$a$$a$$a$$a$
!
&F$a$$a$$a$dʮ̮*,np
$If$a$G$
CORGROUP        $$CLK_I_BufferFalling
$If$a$G$$a$
Percent 100
&F$a$$a$$a$$a$$a$
!
&F$a$$a$
&F$a$$a$&(<C8
CORGROUP        $$CLK_I_BufferRisingFalling
$If$a$G$R$$If0 p44l44l4f4T
Percent 100
$If$a$G$
!
$If$a$G$R$$If0 p44l44l4f4T<FH^hj8R$$If0 p44l44l4f4T
$If$a$G$
CORGROUP        $$CLK_I_BufferRising
$If$a$G$R$$If0 p44l44l4f4T
Percent 100
$If$a$G$jµ:<|zupk$a$$a$$a$$a$$a$$a$$a$$a$R$$If0     p44l44l4f4T$If$a$G$$
!
$If$a$G$|02dԿֿ<>$a$$a$$a$$a$$a$
&F$a$$a$$a$$a$$a$$$a$$a$$a$
CORGROUP        $$CLK_I_BufferFalling
&F$a$&*,0DF,.$a$$a$$a$$a$$$a$$a$$a$$a$$a$
Percent 100
&F$$a$$a$$a$
!
&FFHb
&(6   $If$a$$a$$a$
CORGROUP        $$CLK_I_BufferRisingFalling
&F$

Percent 100
&F1$*$7$5$9D$a$$a$$a$
!
&F$a$$a$$a$$a$$a$$$a$$a$$a$6HRl~       $If$a$
$If$a$x*
$If$a$x$$Ifִ
#)    PpP474747474f4"$8<
$If$a$x<>LP*
$If$a$x$$Ifִ
CORGROUP        $$CLK_I_BufferRising
#)    PpP474747474f4P\`ln
$If$a$x*
$If$a$x$$Ifִ
Percent 100
#)    PpP474747474f4
$If$a$x*
$If$a$x$$Ifִ
!
#)    PpP474747474f4
$If$a$x*
$If$a$x$$Ifִ
#)    PpP474747474f4&(68:<
$If$a$x<>HJ*
$If$a$x$$Ifִ
CORGROUP        $$CLK_I_BufferFalling
#)    PpP474747474f4JVZfhjl
$If$a$xlnz|*
$If$a$x$$Ifִ
Percent 100
#)    PpP474747474f4|
$If$a$x*
$If$a$x$$Ifִ
!
#)    PpP474747474f4
$If$a$x*
$If$a$x$$Ifִ
#)    PpP474747474f4
$If$a$x*
$If$a$x$$Ifִ
CORGROUP        $$CLK_I_BufferRisingFalling
#)    PpP474747474f4"$0246
$If$a$x68@B*
$If$a$x$$Ifִ
Percent 100
#)    PpP474747474f4BNP^`bd
$If$a$xdfrt*
$If$a$x$$Ifִ
!
#)    PpP474747474f4t
$If$a$x*
$If$a$x$$Ifִ
#)    PpP474747474f4
$If$a$x*
$If$a$x$$Ifִ
CORGROUP        $$CLK_RISC_BufferRising
#)    PpP474747474f4
$If$a$x*
$If$a$x$$Ifִ
Percent 100
#)    PpP474747474f4 "48:<
$If$a$x<>JL*
$If$a$x$$Ifִ
!
#)    PpP474747474f4L\^rvxz
$If$a$xz|*
$If$a$x$$Ifִ
#)    PpP474747474f4
$If$a$x*
$If$a$x$$Ifִ
CORGROUP        $$CLK_RISC_BufferFalling
#)    PpP474747474f4
$If$a$x*
$If$a$x$$Ifִ
Percent 100
#)    PpP474747474f4*.02
$If$a$x24@B*
$If$a$x$$Ifִ
!
#)    PpP474747474f4BRThlnp
$If$a$xpr~*
$If$a$x$$Ifִ
#)    PpP474747474f4
$If$a$x*
$If$a$x$$Ifִ
CORGROUP        $$CLK_RISC_BufferRisingFalling
#)    PpP474747474f4
$If$a$x|Z*(#$a$$$Ifִ
Percent 100
#)    PpP474747474f4Z\~VX
!
,.$a$$a$$a$$a$$a$$a$$a$$a$$a$$a$$a$$a$$a$$a$$a$
&F$a$$a$$a$$a$$a$$a$$a$$a$$a$$a$$a$$a$$a$$a$$a$$a$$a$$a$$a$NPt$If$a$G$x$If$a$G$x$a$
CORGROUP        $$CLK_RISC_BufferRising
&F$a$$a$
Percent 100
&F$a$$a$>/$If$a$G$xR$$If0(	p44l44l4f4T$If$a$G$x$IfG$xR$$If0(	p44l44l4f4T$If$a$G$x$If$a$G$xR$$If0(	p44l44l4f4T$If$a$G$x.24;R$$If0(  p44l44l4f4T$If$a$G$x$If$a$G$xR$$If0(       p44l44l4f4T4DHJlpp$If$a$G$x$If$a$G$xR$$If0(     p44l44l4f4T$If$a$G$x$If$a$G$xpr:5$a$R$$If0( p44l44l4f4T$If$a$G$x$$If$a$G$xR$$If0(     p44l44l4f4TbdlnHJrB$Ifx$$Ifx$$a$$a$$a$$a$
!
&F$a$$a$$a$$a$$a$
A5$Ifx$R$$If0Wb        p474747474f4T$Ifx$$Ifx$R$$If0Wb   p474747474f4T$&4:<5R$$If0Wb       p474747474f4T$Ifx$$Ifx$R$$If0Wb   p474747474f4T$Ifx$<LPRbf|$Ifx$$Ifx$R$$If0Wb p474747474f4T$Ifx$$Ifx$fh
CORGROUP        $$CLK_RISC_BufferFalling
"$ "$&($a$$a$$a$
Percent 100
&F$a$$a$R$$If0Wb       p474747474f4T(*,.02468:<>@BDFHJLbd^
!
&F$a$$a$$a$
&F><X~aU$IfG$xf$$IfF$       !        p44l44l4f4$If$a$G$x$If$a$G$x$If$a$G$x
CORGROUP        $$CLK_RISC_BufferRisingFalling
&F$a$N}qbV$IfG$x$If$a$G$x$IfG$xf$$IfF$       !        p44l44l4f4$IfG$x$If$a$G$xNPp|}u$IfG$$If$a$G$x$IfG$xf$$IfF$    !        p44l44l4f4}u$IfG$$If$a$G$x$IfG$xf$$IfF$  !        p44l44l4f4R^}q$IfG$x$If$a$G$x$IfG$xf$$IfF$  !        p44l44l4f4>}u$IfG$$If$a$G$x$IfG$xf$$IfF$  !        p44l44l4f4>@ht}q$IfG$x$If$a$G$x$IfG$xf$$IfF$  !        p44l44l4f4"x}q$IfG$x$If$a$G$x$IfG$xf$$IfF$  !        p44l44l4f4xz}q$IfG$x$If$a$G$x$IfG$xf$$IfF$  !        p44l44l4f4\}q$IfG$x$If$a$G$x$IfG$xf$$IfF$  !        p44l44l4f4\^v}p
$IfG$x$$If$a$G$x$IfG$xf$$IfF$  !        p44l44l4f4l}u$IfG$$If$a$G$x$IfG$xf$$IfF$  !        p44l44l4f4lnx}u$IfG$$If$a$G$x$IfG$xf$$IfF$  !        p44l44l4f4D<>xzwrmh$a$$a$$a$
Percent 100
&F$a$
!
&F
&F$a$$a$$a$f$$IfF$       !        p44l44l4f4FHb$          $a$$a$$a$$a$$a$$$a$$a$$a$
CORGROUP        $$CLK_I_BufferRising
&F$a$$a$$a$$a$$a$$a$$$a$$a$$a$            



~z>@np`b$a$$a$$a$$a$
Percent 100
&F$a$$a$$a$$a$$a$$$a$$a$$a$$a$$a$$a$$a$$a$$a$$a$$a$
!
&F$a$$a$$a$$a$$a$$a$
&F$a$$a$`bnp&(~   !!
CORGROUP        $$CLK_I_BufferFalling
&F$a$$a$$a$$a$$a$$a$
Percent 100
&F$a$$a$!j!l!
!
####$$%%&&&*','4(((()$a$$a$$a$$a$$a$$a$$$a$$a$$a$$a$$a$$a$$a$$a$$a$
&F$a$
CORGROUP        $$CLK_I_BufferRisingFalling
&F()*)****V,X,,,`.b...///000&1(1$a$
Percent 100
&F$a$$a$$a$$a$$a$$a$
!
&F$a$$a$$a$(1\2^2220323D3F3p3r3B5D5l5n577^7(8*8:$a$$a$$a$$a$$$a$$a$$a$$a$
&F
CORGROUP        $$CLK_RISC_BufferRising
&F$a$$a$::>;@;====??*A,AVAfA$If$a$
G$x$If$a$G$x$a$$a$$a$$a$$a$$a$
Percent 100
&F$a$
fAhAAAAB>/$If$a$G$xR$$If01              p44l44l4f4T$IfG$x$If$a$G$xR$$If01               p44l44l4f4TBBBBCC2R$$If01               p44l44l4f4T$IfG$x$If$a$G$xR$$If01               p44l44l4f4T$IfG$xC&CCC.D0D&G(GLGNG\I^I|wrmh$a$$a$$a$
!
&F$a$$a$$a$$a$R$$If01              p44l44l4f4T
$IfG$x$$If$a$G$x^IlJnJ^K`KKKLLLLxNzNNNOO P"P^Q$a$$a$$a$$a$$a$$a$$a$$a$
&F$a$$a$$a$
CORGROUP        $$CLK_RISC_BufferFalling
&F$a$$a$$a$$a$^Q`QQQRRBSDSTT
Percent 100
UU.V0VTVbV$If$a$
G$x$If$a$G$x$a$$a$$a$$a$$a$$a$$a$$a$
!
&F$a$bVdVVVV;R$$If0   p44l44l4f4T$If$a$G$x$If$a$G$xR$$If0        p44l44l4f4TVVVVW&Wp$If$a$G$x$If$a$G$xR$$If0      p44l44l4f4T$If$a$G$x$If$a$G$x&W(WXWjWlWW:5$a$R$$If0  p44l44l4f4T$If$a$G$x$$If$a$G$xR$$If0      p44l44l4f4TWW`YbYYY[[[[[[]]]]__```$a$$a$$a$$$a$$a$$a$$a$
&F$a$$a$
CORGROUP        $$CLK_RISC_BufferRisingFalling
&F$a$$a$$a$`ccccBfDfdfffPhRhiijj$If$a$
G$x$If$a$G$x$a$$a$$a$$a$$a$$a$
Percent 100
&F$a$$a$jj2jjjj>/$If$a$G$xR$$If0        p44l44l4f4T$IfG$x$If$a$G$xR$$If0      p44l44l4f4Tj.k0kkknnnnnppr}xsn$a$$a$$a$$a$
!
&F$a$$a$$a$$a$$a$R$$If0        p44l44l4f4T$IfG$xrrss6s8sXtZtttv vVvXvvv$w&wbxdx$a$$a$$a$$a$$a$$a$$a$$a$$a$
&F$a$$a$$a$
CORGROUP        $$CLK_I_BufferRising
&F$a$$a$$a$dxxx
Percent 100
zz\z^z{{X{Z{||||$If$a$
G$x$If$a$G$x$a$$a$$a$$a$$a$$a$$a$
!
&F||||};R$$If0   p44l44l4f4T$If$a$G$x$If$a$G$xR$$If0        p44l44l4f4T}0}B}D}t}}p$If$a$G$x$If$a$G$xR$$If0      p44l44l4f4T$If$a$G$x$If$a$G$x}}}}}H~:5$a$R$$If0  p44l44l4f4T$If$a$G$x$$If$a$G$xR$$If0      p44l44l4f4TH~J~~~<>̅΅Zl
&F$a$$a$$a$$a$$a$$a$$a$$a$$a$$a$
CORGROUP        $$CLK_I_BufferFalling
&F$a$$a$
Percent 100
&F$a$Љ҉z|46RT$a$$a$$a$$a$
!
&F$a$$a$$a$$a$$a$
&F$a$
CORGROUP        $$CLK_I_BufferRisingFalling
&F$a$
Percent 100
,.DFjlJLfh$a$$a$$a$$a$$a$$a$$a$$a$$a$$a$$a$
!
&F$a$$a$$a$h8: RTln(*hj$a$$a$$a$$a$$a$$a$$a$
&F$a$$a$$a$
CORGROUP        $$CLK_RISC_BufferRising
&F$a$ "rtrtjl֬جTV 
Percent 100
$If$a$G$
!
&F$a$$a$$a$$a$$a$$a$$a$
&F$a$
CORGROUP        $$CLK_RISC_BufferFalling
&F 02:tv~>6$IfG$R$$If0B       p44l44l4f4T$IfG$$IfG$R$$If0B   p44l44l4f4T
Percent 100
$If$a$G$~ȯʯүA9$IfG$R$$If0B     p44l44l4f4T$IfG$$IfG$R$$If0B   p44l44l4f4T$IfG$&(0HJRA9$IfG$R$$If0B       p44l44l4f4T$IfG$$IfG$R$$If0B   p44l44l4f4T$IfG$RjltȰʰҰA9$IfG$R$$If0B       p44l44l4f4T$IfG$$IfG$R$$If0B   p44l44l4f4T$IfG$Ұ~hj
!
$~xs$a$$a$$
&F$a$
CORGROUP        $$CLK_RISC_BufferRisingFalling
&F$a$$a$$a$$a$R$$If0B       p44l44l4f4T      $IfG$$$&PRpiR$$If0B        p44l44l4f4T
Percent 100
$If$a$G$
!
$If$a$G$$a$$a$$a$
&F$a$$a$$a$$a$$a$»TV9R$$If0B       p44l44l4f4T$IfG$$IfG$R$$If0B   p44l44l4f4T$IfG$$IfG$V^мҼ9R$$If0B       p44l44l4f4T$IfG$$IfG$R$$If0B   p44l44l4f4T$IfG$$IfG$Ҽڼ \^9R$$If0B       p44l44l4f4T$IfG$$IfG$R$$If0B   p44l44l4f4T$IfG$$IfG$^f9R$$If0B       p44l44l4f4T$IfG$$IfG$R$$If0B   p44l44l4f4T$IfG$$IfG$68@RT9R$$If0B       p44l44l4f4T$IfG$$IfG$R$$If0B   p44l44l4f4T$IfG$$IfG$T\rt|9R$$If0B       p44l44l4f4T$IfG$$IfG$R$$If0B   p44l44l4f4T$IfG$$IfG$ҾԾ9R$$If0B       p44l44l4f4T$IfG$$IfG$R$$If0B   p44l44l4f4T$IfG$$IfG$Ծܾ8R$$If0B p44l44l4f4T      $IfG$$$IfG$R$$If0B    p44l44l4f4T$IfG$$IfG$dfqi$IfG$R$$If0B       p44l44l4f4T
CORGROUP        $$CLK_I_BufferRising
$If$a$G$
Percent 100
$If$a$G$$a$$a$$a$
!
&F$a$$a$$a$@BJ|~A9$IfG$R$$If0B	p44l44l4f4T$IfG$$IfG$R$$If0B	p44l44l4f4T$IfG$@;$a$R$$If0B  p44l44l4f4T      $IfG$$$IfG$R$$If0B    p44l44l4f4T$IfG$df24NNPnpx|    $If$a$
$If$a$G$
CORGROUP        $$CLK_I_BufferFalling
&F$a$       $a$*$5$9D
Percent 100
&F$$a$$a$$$a$$a$$a$
!
&F$a$$a$$a$|
$If$a$G$    $If$a$
CORGROUP        $$CLK_I_BufferRisingFalling
$If$a$G$
Percent 100
$If$a$G$
!
$If$a$G$
$If$a$G$VK@8-
CORGROUP        $$CLK_RISC_BufferRising
$If$a$G$$IfG$
Percent 100
$If$a$G$
!
$If$a$G$$$Ifֈ
&! <p<44l44l4f4C8-
$If$a$G$
CORGROUP        $$CLK_RISC_BufferFalling
$If$a$G$$$Ifֈ
&! <p<44l44l4f4$IfG$
Percent 100
$If$a$G$&*.Z\0$$Ifֈ
&!       <p<44l44l4f4$IfG$
!
$If$a$G$
$If$a$G$$IfG$\`dtx|$IfG$
CORGROUP        $$CLK_RISC_BufferRisingFalling
$If$a$G$
Percent 100
$If$a$G$$IfG$
!
$If$a$G$
$If$a$G$VK@8-
CORGROUP        $$CLK_RISC_BufferRising
$If$a$G$$IfG$
Percent 100
$If$a$G$
!
$If$a$G$$$Ifֈ
&! <p<44l44l4f4 C8-
$If$a$G$
CORGROUP        $$CLK_RISC_BufferFalling
$If$a$G$$$Ifֈ
&! <p<44l44l4f4$IfG$
Percent 100
$If$a$G$ 26:0$$Ifֈ
&!       <p<44l44l4f4$IfG$
!
$If$a$G$
$If$a$G$$IfG$$IfG$
CORGROUP        $$CLK_RISC_BufferRisingFalling
$If$a$G$
Percent 100
$If$a$G$$IfG$
!
$If$a$G$
$If$a$G$VK@8-
CORGROUP        $$CLK_RISC_BufferRising
$If$a$G$$IfG$
Percent 100
$If$a$G$
!
$If$a$G$$$Ifֈ
&! <p<44l44l4f4^`dhC8-
$If$a$G$
CORGROUP        $$CLK_RISC_BufferFalling
$If$a$G$$$Ifֈ
&! <p<44l44l4f4$IfG$
Percent 100
$If$a$G$htx|0$$Ifֈ
&!       <p<44l44l4f4$IfG$
!
$If$a$G$
$If$a$G$$IfG$$IfG$
CORGROUP        $$CLK_RISC_BufferRisingFalling
$If$a$G$
Percent 100
$If$a$G$$IfG$
!
$If$a$G$
$If$a$G$VK@8-
CORGROUP        $$CLK_RISC_BufferRising
$If$a$G$$IfG$
Percent 100
$If$a$G$
!
$If$a$G$$$Ifֈ
&! <p<44l44l4f4 JLPVC8-
$If$a$G$
CORGROUP        $$CLK_RISC_BufferFalling
$If$a$G$$$Ifֈ
&! <p<44l44l4f4$IfG$
Percent 100
$If$a$G$Vbfn0$$Ifֈ
&!       <p<44l44l4f4$IfG$
!
$If$a$G$
$If$a$G$$IfG$$IfG$
CORGROUP        $$CLK_RISC_BufferRisingFalling
$If$a$G$
Percent 100
$If$a$G$$IfG$
!
$If$a$G$
$If$a$G$VK@8-
CORGROUP        $$CLK_RISC_BufferRising
$If$a$G$$IfG$
Percent 100
$If$a$G$
!
$If$a$G$$$Ifֈ
&! <p<44l44l4f4DFJPC8-
$If$a$G$
CORGROUP        $$CLK_RISC_BufferFalling
$If$a$G$$$Ifֈ
&! <p<44l44l4f4$IfG$
Percent 100
$If$a$G$PZ^f0$$Ifֈ
&!       <p<44l44l4f4$IfG$
!
$If$a$G$
$If$a$G$$IfG$$IfG$
CORGROUP        $$CLK_RISC_BufferRisingFalling
$If$a$G$
Percent 100
$If$a$G$$IfG$
!
$If$a$G$
$If$a$G$
CORGROUP        $$CLK_RISC_BufferRising
VK@8-
Percent 100
$If$a$G$$IfG$
!
$If$a$G$
$If$a$G$$$Ifֈ
&! <p<44l44l4f4"hjnC8-
CORGROUP        $$CLK_RISC_BufferFalling
$If$a$G$
Percent 100
$If$a$G$$$Ifֈ
&! <p<44l44l4f4$IfG$
!
$If$a$G$0$$Ifֈ
&!       <p<44l44l4f4$IfG$
$If$a$G$
CORGROUP        $$CLK_RISC_BufferRisingFalling
$If$a$G$$IfG$>BJ$IfG$
Percent 100
$If$a$G$
!
$If$a$G$$IfG$
$If$a$G$
CORGROUP        $$CLK_RISC_BufferRising
$If$a$G$VK@8-
Percent 100
$If$a$G$$IfG$
!
$If$a$G$
$If$a$G$$$Ifֈ
&! <p<44l44l4f4 C8-
CORGROUP        $$CLK_RISC_BufferFalling
$If$a$G$
Percent 100
$If$a$G$$$Ifֈ
&! <p<44l44l4f4$IfG$
!
$If$a$G$ LPX0$$Ifֈ
&!       <p<44l44l4f4$IfG$
$If$a$G$
CORGROUP        $$CLK_RISC_BufferRisingFalling
$If$a$G$$IfG$J$IfG$
Percent 100
$If$a$G$
!
$If$a$G$$IfG$
$If$a$G$
CORGROUP        $$CLK_RISC_BufferRising
$If$a$G$JLPT^bVK@8-
Percent 100
$If$a$G$$IfG$
!
$If$a$G$
$If$a$G$$$Ifֈ
&! <p<44l44l4f4bj?4
CORGROUP        $$CLK_RISC_BufferFalling
$If$a$G$$$Ifֈ
&! <p<44l44l4f4$If
!G$
Percent 100
$If$a$G$$IfG$
!
$If$a$G$
$If$a$G$$IfG$
CORGROUP        $$CLK_RISC_BufferRisingFalling
$If$a$G$VK@8-
Percent 100
$If$a$G$$IfG$
!
$If$a$G$
$If$a$G$$$Ifֈ
&! <p<44l44l4f48:>BC8-
CORGROUP        $$CLK_RISC_BufferRising
$If$a$G$
Percent 100
$If$a$G$$$Ifֈ
&! <p<44l44l4f4$IfG$
!
$If$a$G$BNRV0$$Ifֈ
&!       <p<44l44l4f4$IfG$
$If$a$G$
CORGROUP        $$CLK_RISC_BufferFalling
$If$a$G$$IfG$$IfG$
Percent 100
$If$a$G$
!
$If$a$G$$IfG$
$If$a$G$
CORGROUP        $$CLK_RISC_BufferRisingFalling
$If$a$G$VK@8-
Percent 100
$If$a$G$$IfG$
!
$If$a$G$
$If$a$G$$$Ifֈ
&! <p<44l44l4f446:BC8-
CORGROUP        $$CLK_RISC_BufferRising
$If$a$G$
Percent 100
$If$a$G$$$Ifֈ
&! <p<44l44l4f4$IfG$
!
$If$a$G$BNV^np0$$Ifֈ
&!       <p<44l44l4f4$IfG$
$If$a$G$
CORGROUP        $$CLK_RISC_BufferFalling
$If$a$G$$IfG$pt|$IfG$
Percent 100
$If$a$G$
!
$If$a$G$$IfG$
$If$a$G$
CORGROUP        $$CLK_RISC_BufferRisingFalling
$If$a$G$VK@8-
Percent 100
$If$a$G$$IfG$
!
$If$a$G$
$If$a$G$$$Ifֈ
&! <p<44l44l4f4C8-
CORGROUP        $$CLK_RISC_BufferRising
$If$a$G$
Percent 100
$If$a$G$$$Ifֈ
&! <p<44l44l4f4$IfG$
!
$If$a$G$FH0$$Ifֈ
&!       <p<44l44l4f4$IfG$
$If$a$G$
CORGROUP        $$CLK_RISC_BufferFalling
$If$a$G$$IfG$HLRZ^f$IfG$
Percent 100
$If$a$G$
!
$If$a$G$$IfG$
$If$a$G$
CORGROUP        $$CLK_RISC_BufferRisingFalling
$If$a$G$VK@8-
Percent 100
$If$a$G$$IfG$
!
$If$a$G$
$If$a$G$$$Ifֈ
&! <p<44l44l4f4C8-
CORGROUP        $$clk_risc_BufferRising
$If$a$G$
Percent 100
$If$a$G$$$Ifֈ
&! <p<44l44l4f4$IfG$
!
$If$a$G$,.0$$Ifֈ
&!       <p<44l44l4f4$IfG$
$If$a$G$
CORGROUP        $$clk_risc_BufferFalling
$If$a$G$$IfG$.26BFNr$IfG$
Percent 100
$If$a$G$
!
$If$a$G$$IfG$
$If$a$G$
CORGROUP        $$clk_risc_BufferRisingFalling
$If$a$G$rtx|VK@8-
Percent 100
$If$a$G$$IfG$
!
$If$a$G$
$If$a$G$$$Ifֈ
&! <p<44l44l4f4C8-
CORGROUP        $$clk_risc_BufferRising
$If$a$G$
Percent 100
$If$a$G$$$Ifֈ
&! <p<44l44l4f4$IfG$
!
$If$a$G$0$$Ifֈ
&!       <p<44l44l4f4$IfG$
$If$a$G$
CORGROUP        $$clk_risc_BufferFalling
$If$a$G$$IfG$&,4h$IfG$
Percent 100
$If$a$G$
!
$If$a$G$$IfG$
$If$a$G$
CORGROUP        $$clk_risc_BufferRisingFalling
$If$a$G$hjVQLGE@
Percent 100
&F$a$$a$$a$$$Ifֈ
&!       <p<44l44l4f4S|$$If\Lp$      !      (p(44444f4$IfG$$IfG$$IfG$$IfG$$a$$a$$a$,.8<RJ$IfG$|$$If\Lp$      !      (p(44444f4      $If$a$
!
$If$a$G$$IfG$$IfG$$If
!G$<DVXdhrzoc[SH
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4
CLOCK   clk_risc
$If$a$G$$IfG$z"~yme]R
PERIODE 1
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4      $If$a$~(*6D}{vqlg_W$IfG$$IfG$$a$$a$$a$
DUTY    50
&F$a$|$$If\Lp$       !      (p(44444f4     DPhjnrv|rf^VK
OFFSETE 0
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4$IfG$$IfG$|yme]R
INITIAL LOW
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4      $If$a$vnf[R $If$a$
MAXUNCERTRISE   0
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4 $(,4Xvnf[R        $If$a$
MAXUNCERTFALL   0
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4XZ^bfnvnf[R        $If$a$
MINUNCERTRISE   0
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4vnf[R        $If$a$
MINUNCERTFALL   0
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4vnf[R        $If$a$
JRISEE  0
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4$rvnf[R        $If$a$
JFALLE  0
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4rtx|vnf[R        $If$a$
GRID    1       1       1       2       2       16711680        0        0
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4(vnf[R        $If$a$
ENDGRID -1
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4(*048@fvnf[R        $If$a$
DIRECTION       input
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4fhnrv~vnf[P
MASTERCLOCK     None
$If$a$G$
Clock   Unclocked
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4vnf[
EdgeLevel       neg
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4\vnf[R        $If$a$
Set     Not Used
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4\^8:}xvqlgbZ$IfG$$a$$a$$a$
Clear   Not Used
&F$a$$a$|$$If\Lp$       !      (p(44444f4     24<@Hj^VN$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4$IfG$$IfG$$IfG$HRnbZRG
ClockEnable     Not Used
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4      $If$a$
ActiveLowSetClear       True
$If$a$G$vnf[R      $If$a$
AsyncSetClear   True
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4&Rvnf[R        $If$a$
ActiveLowClockEnable    True
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4RTX\`lvnf[R        $If$a$
VhdlType        std_logic
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4vnf[R        $If$a$
VerilogType     wire
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4 vnf[R        $If$a$
SystemCType     sc_logic
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4 "PR}xsqlgb]$a$$a$$a$
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
&F$a$$a$$a$|$$If\Lp$       !      (p(44444f4     *6NPX\bVN$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4$IfG$$IfG$$IfG$$IfG$\dlfZRJ$IfG$$IfG$$If
!G$|$$If\Lp$    !      (p(44444f4      $If$a$
StateEquation   Hex(Inc(0,2,5))
$If$a$G$$IfG$$nbZRG
HighVoltageThreshold    5
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4      $If$a$
LowVoltageThreshold     0
$If$a$G$$&*.2:vnf[R      $If$a$
MSB     0
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4vnf[R        $If$a$
LSB     0
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4Rvnf[R        $If$a$
isFallingEdgeSensitive  False
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4RTZ^bjvnf[R        $If$a$
isRisingEdgeSensitive   True
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4DF}{vqlg_W$IfG$$IfG$$a$$a$$a$
DrawAnalog      0
&F$a$|$$If\Lp$       !      (p(44444f4     *BDLPX`rf^VK
BooleanEquation
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4$IfG$$IfG$`z|yme]R
NegTolerance    0
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4      $If$a$vnf[R $If$a$
PosTolerance    0
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4"&.xvnf[R        $If$a$
UserSpecifiedSizeRatio  1
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4xz~vnf[R        $If$a$
VerilogCode
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4Fvnf[R        $If$a$
VHDLCode
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4FHNRV^vnf[R        $If$a$
PROPS!
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f446}xsnid\T$IfG$$IfG$$a$$a$$a$
E5      1       2500    2500            1       0        DR      0
&F$a$$a$|$$If\Lp$       !      (p(44444f4     ":<DHPXrf^VK
E6      0        3000    3000            1       0        DR      0
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4$IfG$$IfG$Xnpx|yme]R
!
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4      $If$a$vnf[R $If$a$
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4"&.jvnf[R        $If$a$
SIGNAL  dbg_adr_i
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4jlptxvnf[R        $If$a$
DIRECTION       input
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f40vnf[R        $If$a$
RADIX   hex
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4028<@Lvnf[R        $If$a$
GRID    0        1       0        1       0        16711680        0        0
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4vnf[R        $If$a$
ENDGRID -1
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4(pvnf[R        $If$a$
Clock   Unclocked
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4prx|vnf[R        $If$a$
EdgeLevel       neg
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4N>@}xskfa\W$a$$a$
Set     Not Used
&F$a$
Clear   Not Used
&F$a$$a$$a$$a$|$$If\Lp$       !      (p(44444f4      .:RT\`]QI$IfG$$If
!G$|$$If\Lp$  !      (p(44444f4$IfG$$IfG$$IfG$$IfG$$a$`hpfZRJ$IfG$$IfG$$If
!G$|$$If\Lp$  !      (p(44444f4      $If$a$
ClockEnable     Not Used
$If$a$G$$IfG$0nbZRG
ActiveLowSetClear       True
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4      $If$a$
AsyncSetClear   True
$If$a$G$026:>Fvnf[R      $If$a$
ActiveLowClockEnable    True
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4vnf[R        $If$a$
VhdlType        std_logic
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4Fvnf[R        $If$a$
VerilogType     wire
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4FHNRVbvnf[R        $If$a$
SystemCType     sc_logic
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4"vnf[R        $If$a$
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4"$*.2>vnf[R        $If$a$
StateEquation   Hex(Inc(0,2,5))
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4vnf[R        $If$a$
HighVoltageThreshold    5
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4fhbdp~}xsnid\T$IfG$$IfG$$a$$a$$a$
LowVoltageThreshold     0
&F$a$$a$|$$If\Lp$       !      (p(44444f4     ~rf^VK
LSB     0
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4$IfG$$IfG$Jyme]R
MSB     31
$If$a$G$$IfG$$IfG$$If
!G$|$$If\Lp$        !      (p(44444f4      $If$a$JL "&8:}xsnib`^\
SignalActionType        0
&F$$a$$a$$a$$a$$a$|$$If\Lp$       !      (p(44444f4
isFallingEdgeSensitive  False
d:<$IfG$$IfG$$IfG$$IfG$
isRisingEdgeSensitive   False
&F$a$$a$$a$$a$
DrawAnalog      0
&Fvkc[$IfG$$IfG$
BooleanEquation
$If$a$G$$If
!G$|$$If\Nr!     (p(44444f4 ,Dzog_$IfG$$IfG$
NegTolerance    0
$If$a$G$$IfG$|$$If\Nr!     (p(44444f4DFZ^lzog_$IfG$$IfG$
PosTolerance    0
$If$a$G$$IfG$|$$If\Nr!     (p(44444f4       zog_$IfG$$IfG$
UserSpecifiedSizeRatio  1
$If$a$G$$IfG$|$$If\Nr!     (p(44444f4   
VerilogCode
             $     2     J     zog_$IfG$$IfG$
VHDLCode
$If$a$G$$IfG$|$$If\Nr!     (p(44444f4J   L     `     f     v          zog_$IfG$$IfG$
PROPS!
$If$a$G$$IfG$|$$If\Nr!     (p(44444f4                       F
E0      X       750     750             1       0        DR      0
zog_$IfG$$IfG$
E1      V       1750    1750    A20     1       0        DR      0
$If$a$G$$IfG$|$$If\Nr!     (p(44444f4F
E2      V       3750    3750    A100    1       0        DR      0
H
E3      X       5750    5750            1       0        DR      0
\
!
`
l
SIGNAL  dbg_dat_i

DIRECTION       input
zog_$IfG$$IfG$
RADIX   hex
$If$a$G$$IfG$|$$If\Nr!     (p(44444f4
GRID    0        1       0        1       0        16711680        0        0

ENDGRID -1
zog_$IfG$$IfG$
Clock
$If$a$G$$IfG$|$$If\Nr!     (p(44444f4 zog_$IfG$$IfG$
EdgeLevel       neg
$If$a$G$$IfG$|$$If\Nr!     (p(44444f4 "48Fzog_$IfG$$IfG$
Set     Not Used
$If$a$G$$IfG$|$$If\Nr!     (p(44444f4
zog_$IfG$$IfG$
Clear   Not Used
$If$a$G$$IfG$|$$If\Nr!     (p(44444f4





}{vtrph`X$IfG$$IfG$$IfG$
ClockEnable     Not Used
&F$a$|$$If\Nr!       (p(44444f4
ActiveLowSetClear       True
znc[S$IfG$$IfG$
AsyncSetClear   True
$If$a$G$$If
!G$|$$If\Nr!     (p(44444f4$IfG$(,8Pzog_$IfG$$IfG$
ActiveLowClockEnable    True
$If$a$G$$IfG$|$$If\Nr!     (p(44444f4PRfjxzog_$IfG$$IfG$
VhdlType        std_logic
$If$a$G$$IfG$|$$If\Nr!     (p(44444f4zog_$IfG$$IfG$
VerilogType     wire
$If$a$G$$IfG$|$$If\Nr!     (p(44444f4*0>Vzog_$IfG$$IfG$
SystemCType     sc_logic
$If$a$G$$IfG$|$$If\Nr!     (p(44444f4VXlrzog_$IfG$$IfG$
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
$If$a$G$$IfG$|$$If\Nr!     (p(44444f4Rzog_$IfG$$IfG$
StateEquation   Hex(Inc(0,2,5))
$If$a$G$$IfG$|$$If\Nr!     (p(44444f4RThlxzog_$IfG$$IfG$
HighVoltageThreshold    5
$If$a$G$$IfG$|$$If\Nr!     (p(44444f4zog_$IfG$$IfG$
LowVoltageThreshold     0
$If$a$G$$IfG$|$$If\Nr!     (p(44444f4,zog_$IfG$$IfG$
LSB     0
$If$a$G$$IfG$|$$If\Nr!     (p(44444f4,.@DRzog_$IfG$$IfG$
MSB     31
$If$a$G$$IfG$|$$If\Nr!     (p(44444f4zog_$IfG$$IfG$
SignalActionType        0
$If$a$G$$IfG$|$$If\Nr!     (p(44444f4tv}{vtrph`X$IfG$$IfG$$IfG$
isFallingEdgeSensitive  False
&F$a$|$$If\Nr!       (p(44444f4
isRisingEdgeSensitive   False
znc[S$IfG$$IfG$
DrawAnalog      0
$If$a$G$$If
!G$|$$If\Nr!     (p(44444f4$IfG$
BooleanEquation
Tzog_$IfG$$IfG$
NegTolerance    0
$If$a$G$$IfG$|$$If\Nr!     (p(44444f4TVdhtzog_$IfG$$IfG$
PosTolerance    0
$If$a$G$$IfG$|$$If\Nr!     (p(44444f4zog_$IfG$$IfG$
UserSpecifiedSizeRatio  1
$If$a$G$$IfG$|$$If\Nr!     (p(44444f4
VerilogCode
(zog_$IfG$$IfG$
VHDLCode
$If$a$G$$IfG$|$$If\Nr!     (p(44444f4(*<@Lxzog_$IfG$$IfG$
VhdlMapping     DefaultVhdlMapping
$If$a$G$$IfG$|$$If\Nr!     (p(44444f4xzzog_$IfG$$IfG$
PROPS!
$If$a$G$$IfG$|$$If\Nr!     (p(44444f446bdNPZf}{vtome]$IfG$$IfG$$a$
E0      X       750     750             1       0        DR      0
&F$a$|$$If\Nr!       (p(44444f4     fz6rf[SK$IfG$$IfG$
E1      V       1750    1750    D20     1       0        DR      0
$If$a$G$$If
!G$|$$If\
E2      X       5750    5750            1       0        DR      0
!      (p(44444f4$IfG$$IfG$68LR^vkc[$IfG$$IfG$
!
$If$a$G$$If
!G$|$$If\
!      (p(44444f4tvkc[$IfG$$IfG$
SIGNAL  dbg_dat_o
$If$a$G$$If
!G$|$$If\
DIRECTION       output
!      (p(44444f4tvzog_$IfG$$IfG$
RADIX   hex
$If$a$G$$IfG$|$$If\
GRID    0        1       0        1       0        16711680        0        0
!      (p(44444f4Jzog_$IfG$$IfG$
ENDGRID -1
$If$a$G$$IfG$|$$If\
Clock
!      (p(44444f4JL^bpzog_$IfG$$IfG$
EdgeLevel       neg
$If$a$G$$IfG$|$$If\
Set     Not Used
!      (p(44444f4zog_$IfG$$IfG$
Clear   Not Used
$If$a$G$$IfG$|$$If\
ClockEnable     Not Used
!      (p(44444f4,^zog_$IfG$$IfG$
ActiveLowSetClear       True
$If$a$G$$IfG$|$$If\
AsyncSetClear   True
!      (p(44444f4^`x|zog_$IfG$$IfG$
ActiveLowClockEnable    True
$If$a$G$$IfG$|$$If\
VhdlType        std_logic
!      (p(44444f4 zog_$IfG$$IfG$
VerilogType     wire
$If$a$G$$IfG$|$$If\
SystemCType     sc_logic
!      (p(44444f4      """"}{vtome]$IfG$$IfG$$a$
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
&F$a$|$$If\
StateEquation   Hex(Inc(0,2,5))
!      (p(44444f4     ""###0#4#TH=
HighVoltageThreshold    5
$If$a$G$$If
!G$$$IfrT!       
LowVoltageThreshold     0
2p244444f4$IfG$$IfG$$IfG$4#B#`####$TH=
LSB     0
$If$a$G$$If
!G$$$IfrT!       
MSB     31
2p244444f4$IfG$$IfG$$IfG$$$$b$d$z$~$TH=
SignalActionType        0
$If$a$G$$If
!G$$$IfrT!       
isFallingEdgeSensitive  False
2p244444f4$IfG$$IfG$$IfG$~$$$$$$$TLA
isRisingEdgeSensitive   True
$If$a$G$$IfG$$$IfrT!       
DrawAnalog      0
2p244444f4$IfG$$IfG$$IfG$$%,%p%r%%%TLA
BooleanEquation
$If$a$G$$IfG$$$IfrT!       
NegTolerance    0
2p244444f4$IfG$$IfG$$IfG$%%%%%&&TLA
PosTolerance    0
$If$a$G$$IfG$$$IfrT!       
UserSpecifiedSizeRatio  1
2p244444f4$IfG$$IfG$$IfG$&&>&~&&&&TLA
VerilogCode
$If$a$G$$IfG$$$IfrT!       
VHDLCode
2p244444f4$IfG$$IfG$$IfG$&&&&'''TLA
VhdlMapping     DefaultVhdlMapping
$If$a$G$$IfG$$$IfrT!       
PROPS!
2p244444f4$IfG$$IfG$$IfG$'*'H'z'|'''TLA
E0      V       -1      -1              1       0        DR      0
$If$a$G$$IfG$$$IfrT!       
E1      V       750     750     PC      1       0        DR      0
2p244444f4$IfG$$IfG$$IfG$''''''(TLA
E2      X       2750    2750            1       0        DR      0
$If$a$G$$IfG$$$IfrT!       
E3      V       3750    3750    D100    1       0        DR      0
2p244444f4$IfG$$IfG$$IfG$((.(J(L((((TOMH
E4      V       4750    4750    L/S EA  1       0        DR      0
&F$a$$$IfrT!       
E5      V       5750    5750    LOAD DATA       1       0        DR      0
2p244444f4$IfG$$IfG$$IfG$((j*l*v*****Y|$$If\>!       (p(44444f4$IfG$$IfG$$IfG$$IfG$$a$****+
!
+x+|++[VOM
&F$$a$|$$If\>!       (p(44444f4$IfG$$IfG$
SIGNAL  dbg_op_i
$If$a$G$$If
!G$++>-@-\-h-x---P|$$If\S?;"   (p(44l44l4f4$IfG$
DIRECTION       input
$If$a$G$
RADIX   hex
$If$a$G$
GRID    0        1       0        1       0        16711680        0        0
$If$a$G$$a$------..VK@
ENDGRID -1
$If$a$G$
Clock   Unclocked
$If$a$G$|$$If\S?;"     (p(44l44l4f4
EdgeLevel       neg
$If$a$G$
Set     Not Used
$If$a$G$
Clear   Not Used
$If$a$G$
ClockEnable     Not Used
$If$a$G$..8.:.R.b.h..laVK@
ActiveLowSetClear       True
$If$a$G$
AsyncSetClear   True
$If$a$G$
ActiveLowClockEnable    True
$If$a$G$
VhdlType        std_logic
$If$a$G$|$$If\S?;"     (p(44l44l4f4
VerilogType     wire
$If$a$G$
SystemCType     sc_logic
$If$a$G$......wlaV
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
$If$a$G$
StateEquation   Hex(Inc(0,2,5))
$If$a$G$
HighVoltageThreshold    5
$If$a$G$
LowVoltageThreshold     0
$If$a$G$|$$If\S?;"     (p(44l44l4f4......wlaV
SignalActionType        0
$If$a$G$
MSB     3
$If$a$G$
LSB     0
$If$a$G$
isFallingEdgeSensitive  False
$If$a$G$|$$If\S?;"     (p(44l44l4f4./// /T/wlaV
isRisingEdgeSensitive   False
$If$a$G$
DrawAnalog      0
$If$a$G$
BooleanEquation
$If$a$G$
NegTolerance    0
$If$a$G$|$$If\S?;"     (p(44l44l4f4T/V/f/x///wlaV
PosTolerance    0
$If$a$G$
UserSpecifiedSizeRatio  1
$If$a$G$
VerilogCode
$If$a$G$
VHDLCode
$If$a$G$|$$If\S?;"     (p(44l44l4f4/////0wlaV
PROPS!
$If$a$G$
E0      V       750     750     READ PC 0x0     1       0        DR      0
$If$a$G$
E1      V       1750    1750    WRITE SPR 0x5   1       0        DR      0
$If$a$G$
E2      V       3750    3750    READ SPR == 0x4 1       0        DR      0
$If$a$G$|$$If\S?;"     (p(44l44l4f4000$0*0T0wlaV
E3      V       4750    4750    READ LSEA 0x1   1       0        DR      0
$If$a$G$
E4      V       5750    5750    READ LDAT 0x2   1       0        DR      0
$If$a$G$
!
$If$a$G$
$If$a$G$|$$If\S?;"     (p(44l44l4f4T0V0X0Z0\0^0wlaV
SIGNAL  dbg_stall_i
$If$a$G$
DIRECTION       input
$If$a$G$
RADIX   hex
$If$a$G$
GRID    0        1       0        1       0        16711680        0        0
$If$a$G$|$$If\S?;"     (p(44l44l4f4^0`0p0|000wlaV
ENDGRID -1
$If$a$G$
Clock   Unclocked
$If$a$G$
EdgeLevel       neg
$If$a$G$
Set     Not Used
$If$a$G$|$$If\S?;"     (p(44l44l4f400000.1wlaV
Clear   Not Used
$If$a$G$
ClockEnable     Not Used
$If$a$G$
ActiveLowSetClear       True
$If$a$G$
AsyncSetClear   True
$If$a$G$|$$If\S?;"     (p(44l44l4f4.101@1D1H11wlaV
ActiveLowClockEnable    True
$If$a$G$
VhdlType        std_logic
$If$a$G$
VerilogType     wire
$If$a$G$
SystemCType     sc_logic
$If$a$G$|$$If\S?;"     (p(44l44l4f4111111wlaV
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
$If$a$G$
StateEquation   Hex(Inc(0,2,5))
$If$a$G$
HighVoltageThreshold    5
$If$a$G$
LowVoltageThreshold     0
$If$a$G$|$$If\S?;"     (p(44l44l4f4111122wlaV
SignalActionType        0
$If$a$G$
MSB     0
$If$a$G$
LSB     0
$If$a$G$
isFallingEdgeSensitive  False
$If$a$G$|$$If\S?;"     (p(44l44l4f4222$2(2X2wlaV
isRisingEdgeSensitive   False
$If$a$G$
DrawAnalog      0
$If$a$G$
BooleanEquation
$If$a$G$
NegTolerance    0
$If$a$G$|$$If\S?;"     (p(44l44l4f4X2Z2n2t2z22wlaV
PosTolerance    0
$If$a$G$
UserSpecifiedSizeRatio  1
$If$a$G$
VerilogCode
$If$a$G$
VHDLCode
$If$a$G$|$$If\S?;"     (p(44l44l4f4222222wlaV
PROPS!
$If$a$G$
E0      0        5750    5750            1       0        DR      0
$If$a$G$
!
$If$a$G$
$If$a$G$|$$If\S?;"     (p(44l44l4f4222233wlaV
FQ/  %8&" WMFCcR P3PSxU>FQ/ EMFPSXVISIODrawing
$If$a$G$
 Y=&%%V0JJJJ%(%RL Arialdx		_VarMemberFlagsVB_Var@?>=<;:98%T+.g=*A*A+.
$If$a$G$
L`Context ID          T|5>\M*A*A5>L\(4 bits)&%%V0}JJ}J}J%(%RL Arial%T.<=*A*A.LpPage Index Level 1	T|>M*A*A>L\(8 bits)&%%V0}iJ}JiJi}}J%(%RL Arial%T.(=*A*A.LpPage Index Level 2  T> M*A*A>     L`(11 bits)&%%V0iUJiJUJUiiJ%(%RL Arial%T.=*A*A.LdPage Offset     
$If$a$G$
T>M*A*A>     L`(13 bits)RL Arial%TX"*A*ALP35RL Arial%(%TX"*A*ALP31%
(RL Arial%TXbo"*A*AbLP24%
(RL Arial'xx
'#
$If$a$G$|$$If\S?;"     (p(44l44l4f4333$3(3f3wlaV

P#ArialArial%TX"*A*ALP23RL ArialP#Aririalc,,yMMHM,,,%TXQ^"*A*AQLP13%
(RL Arialr,HM(%MMM@MMm,BBBc
$If$a$G$

$If$a$G$

$If$a$G$

$If$a$G$|$$If\S?;"     (p(44l44l4f4f3h3|3333wlaV

$If$a$G$
H
$If$a$G$
c,,,,,,y,,,,,,,,,,,%c,,,,,88288782T8887!2%TXu"*A*AuLP12%
(RL Arial)@)GF)FF^F_F%TTFL"*A*AFLP0&%%V0i::i:i:%(%
(%
(%RL ArialGH@GHFH)Arial%Tw-*A*ALtPhysical Page Number             T.L=*A*A.     L`(22 bits)x&%%V0iU:i:U:Uii:%(RL Arial'xx
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P#ArialArial&" WMFC PPS%(%%T.*A*ALdPage Offset     
$If$a$G$|$$If\S?;"     (p(44l44l4f433333"4wlaV
T/>*A*A/     L`(13 bits)%
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(RL Arial%TTFL*A*AFLP0&%W$JJ%(%%V,&%%V&M&(-5@LZhv!.:CvJhMZMLJ@C5:-.(!&%(RL Arial%(%RL Arial%TA*A*AA
$If$a$G$
L`Page Table     T8*A*A8LdBase Address          T;.*A*A;Lddepending onTA/>*A*AA/Ldcurrent CID      &%%VX
$If$a$G$

$If$a$G$
%(%
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(%RL Arial&ByValKt(CallGu*CasetL,CBool~Dirge?Dir$\@Do4ADoEventsDo
BDoubleuEachV;DElse%TT*A*ALP+f&%W,%(%%V,&%%W$JJ%(%%V,&%%W$JJ%(%%V,&%%V0::::%(     &rWMFCPPS&%%V0:6:66::6%(RL Arial !"#$%&'()*+,./01234%(%RL ArialFGHIJKLMNOPQRSTUVWXial,%TdY.x=*A*AY.LTPTE2   &     %     %V0:6:6:6:%(     %
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$If$a$G$|$$If\S?;"     (p(44l44l4f4"4$4&4(4*4,4wlaV
     
                         
$If$a$G$
      %T@*A*A@
LhL2 Page Table       & %     W,-**-*%(     %%V,,&:/,&:*,/,&& %     %W06***66%(     %%V,1::61:%RL      Arial     KK!!#8dd2!^KKB88888!J%8:!J7(7!!!:6C% T+q*A*A+qLVirtual Page Number  (VPN)                          &
$If$a$G$
%
$If$a$G$
W,IJIIJI[I[I%(
$If$a$G$|$$If\S?;"     (p(44l44l4f4,4.4@4N4T44wlaV
%%V,ENNIEN&
$If$a$G$
%
$If$a$G$
%W,aiyayiyia%(
$If$a$G$
%
(RL Arial%(%
(%%T`*A*ALT255RL Arial%TT*A*ALP0%
(RL Arial%TT*A*ALP0%
(%
(RL Arial@?>=<:987543210/.-,+ri%Td*A*ALT2047<Y--$JJJ-.-
 Arial-2
$If$a$G$|$$If\S?;"     (p(44l44l4f4444444wlaV
.+
$If$a$G$
Context ID          2
$If$a$G$
>5(4 bits)--$J}J}J--
 Arial?????????????????????????-"2
$If$a$G$
.Page Index Level 1      2
$If$a$G$|$$If\S?;"     (p(44l44l4f4444444wlaV
>(8 bits)--$}JiJi}}J--
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$If$a$G$
.Page Index Level 2      2
$If$a$G$
>    (11 bits)--$iJUJUiiJ--
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$If$a$G$
.Page Offset    
$If$a$G$|$$If\S?;"     (p(44l44l4f4444444wlaV
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>    (13 bits)
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$If$a$G$
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$If$a$G$
35
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$If$a$G$|$$If\S?;"     (p(44l44l4f4444444wlaV
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$If$a$G$
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$If$a$G$|$$If\S?;"     (p(44l44l4f444254565855555{vqca_]
$d%d&d'd$a$$a$$a$|$$If\S?;"    (p(44l44l4f4     566666666$a$
$d%d&d'd8/ =!"#$2P1h0p3P(20;/ =!"#$2P1h0p3P(2(2    0;/ =!"#$2P1h0p3P(20    0;/ =!"#$2P1h0p3P(2(2    0;/ =!"#$2P1h0p3P(20    0;/ =!"#$2P1h0p3P(2(2    0;/ =!"#$2P1h0p3P(20    0n_KFvHPNG
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PROJECT
BaseTimeUnit    1
CLOCK   clk_risc
DisplayTimeUnit 2
PERIODE 1
TextGridX       625.000000
DUTY    50
TextGridY       6
OFFSETE 0
EdgeGridX       625.000000
INITIAL LOW
ImportStartTime 0.000000
MAXUNCERTRISE   0
ImportEndTime   281474976710656.000000
MAXUNCERTFALL   0
TimePerPixel    50.000000
MINUNCERTRISE   0
Visible DELAYS  SETUPS  HOLDS   SAMPLES TEXT    HIDDENATTACHMENTS       CRITICALPATHS   GRIDLINES       UNCERTAINTY
MINUNCERTFALL   0
ColWidths       144,216,288,423,488
JRISEE  0
ScrollPos       0.000000,0.000000,0.000000
JFALLE  0
DefDelayRule    1
GRID    1       1       1       2       2       16711680        0        0
NoEventOverlap  NO
ENDGRID -1
SigLabelFontHeight      10
DIRECTION       input
LabelHeight     12
MASTERCLOCK     None
LoadLibsToMem   1
Clock   Unclocked
UseFullPathNames        1
EdgeLevel       neg
LibPath
Set     Not Used
EntireTime      YES
Clear   Not Used
PrintTimeSpecified      NO
ClockEnable     Not Used
FromTime        0
ActiveLowSetClear       True
ToTime  43.75
AsyncSetClear   True
AllSignals      YES
ActiveLowClockEnable    True
CurrSelSigs     NO
VhdlType        std_logic
PrintTo 2
VerilogType     wire
PrintFileName   C:\DOCS\wb_fetchblock_typ.wmf
SystemCType     sc_logic
PreviewInterchange      YES
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
PreviewTIFF5    NO
StateEquation   Hex(Inc(0,2,5))
UseMargins      NO
HighVoltageThreshold    5
PrintTimeLine   NO
LowVoltageThreshold     0
PrintBorderBox  YES
MSB     0
PrintSigNames   YES
LSB     0
PrintSigNamesOnEachPage YES
isFallingEdgeSensitive  False
AddPreviewToEPS NO
isRisingEdgeSensitive   True
PreviewRes      150
DrawAnalog      0
MarginLR        1.25
BooleanEquation
MifImageWidth   6.00
NegTolerance    0
MarginTB        Auto
PosTolerance    0
Header  %d %t;%f;%p
UserSpecifiedSizeRatio  1
Footer
VerilogCode
ScaleHorz       100
VHDLCode
ScaleVert       100
PROPS!
ScaleHPage      1
!
PrintImage      DIAGRAM
DefaultTimingModel      minmax
SIGNAL  dbg_wp_o[11]
DefaultClock    Unclocked
DIRECTION       output
DefaultEdgeLevel        neg
RADIX   hex
DefaultSet      Not Used
GRID    0        1       0        1       0        16711680        0        0
DefaultClear    Not Used
ENDGRID -1
DefaultClockEnable      Not Used
Clock   Unclocked
DefaultClockToOutLH     0
EdgeLevel       neg
DefaultClockToOutHL     0
Set     Not Used
DefaultSetup    0
Clear   Not Used
DefaultHold     0
ClockEnable     Not Used
DefaultRegStartupState  unknown
ActiveLowSetClear       True
DefaultPodSize  8
AsyncSetClear   True
DefaultActiveLowSetClear        True
ActiveLowClockEnable    True
DefaultAsyncSetClear    True
VhdlType        std_logic
DefaultActiveLowClockEnable     True
VerilogType     wire
SigLabelFontHeight      10
SystemCType     sc_logic
PROPS!
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
STYLE
LowVoltageThreshold     0
DefaultFont     USER    {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
SignalActionType        0
DrawWndFont     DEFAULT
MSB     0
DrawWndColor    DEFAULT
LSB     0
GridWndFont     DEFAULT
isFallingEdgeSensitive  False
GridWndColor    DEFAULT
isRisingEdgeSensitive   False
LabelWndFont    USER    {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
DrawAnalog      0
LabelWndColor   DEFAULT
BooleanEquation
ParamDispPref   0
NegTolerance    0
ParamWndCellDisplay     0
PosTolerance    0
CustDispString  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
UserSpecifiedSizeRatio  1
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
VerilogCode
MarkerDispPref  4
VHDLCode
MarkerCustDispString    %n v=%mv,%Mv d=%md %t
PROPS!
MarkerCustomDisplayStringRTF    {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
E0      0        1750    1750            1       0        DR      0
SignalColor     2
E1      1       3750    3750            1       0        DR      0
LabelOffset     2
E2      0        4750    4750            1       0        DR      0
BusDisplay      0
!
WaveFormWidth   0.500000
WaveFormColor   0
SIGNAL  dbg_bp_o
InputWaveFormColor      16711680
DIRECTION       output
SlantedEdges    1
RADIX   hex
SlantAngle      75
GRID    0        1       0        1       0        16711680        0        0
RightJustifySigNames    1
ENDGRID -1
AutosplitEnabled        1
Clock   Unclocked
AutosplitChar   _
EdgeLevel       neg
DynamSizedSignals       1
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
DIAGRAMTESTBENCHSETTINGS
ActiveLowSetClear       True
FilesBeforeDiagramModel
AsyncSetClear   True
FilesInsideDiagramModelDeclarationSection
ActiveLowClockEnable    True
AbortHdlCodeEnabled     1
VhdlType        std_logic
DelayHdlCodeEnabled     1
VerilogType     wire
SampleHdlCodeEnabled    1
SystemCType     sc_logic
MarkerHdlCodeEnabled    1
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
VerboseSamples  0
StateEquation   Hex(Inc(0,2,5))
VerboseDelays   0
HighVoltageThreshold    5
VerboseFileInput        0
LowVoltageThreshold     0
VerboseSequenceVerification     0
SignalActionType        0
IncludeDelayTime        1
MSB     0
ExecuteFromTopLevel     1
LSB     0
TimeOutInDiagramLengths 0
isFallingEdgeSensitive  False
DefaultCycleClock       Unclocked
isRisingEdgeSensitive   False
DefaultCycleEdge        neg
DrawAnalog      0
!
BooleanEquation
NegTolerance    0
MACROS
PosTolerance    0
!
UserSpecifiedSizeRatio  1
VerilogCode
CORGROUP        $$CLK_I_BufferRising
VHDLCode
Percent 100
PROPS!
!
E0      0        2750    2750            1       0        DR      0
E1      1       4750    4750    If Enabled      1       0        DR      0
CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
!
SIGNAL  dbg_ewt_i
DIRECTION       input
CORGROUP        $$CLK_I_BufferRisingFalling
RADIX   hex
Percent 100
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock   Unclocked
CORGROUP        $$CLK_I_BufferRising
EdgeLevel       neg
Percent 100
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
CORGROUP        $$CLK_I_BufferFalling
ActiveLowSetClear       True
Percent 100
AsyncSetClear   True
!
ActiveLowClockEnable    True
VhdlType        std_logic
CORGROUP        $$CLK_I_BufferRisingFalling
VerilogType     wire
Percent 100
SystemCType     sc_logic
!
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
CORGROUP        $$CLK_I_BufferRising
HighVoltageThreshold    5
Percent 100
LowVoltageThreshold     0
!
SignalActionType        0
MSB     0
CORGROUP        $$CLK_I_BufferFalling
LSB     0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   False
DrawAnalog      0
CORGROUP        $$CLK_I_BufferRisingFalling
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$CLK_I_BufferRising
VerilogCode
Percent 100
VHDLCode
!
PROPS!
E0      0        1250    1250            1       0        DR      0
CORGROUP        $$CLK_I_BufferFalling
E1      1       3750    3750            1       0        DR      0
Percent 100
E2      0        4750    4750            1       0        DR      0
!
!
CORGROUP        $$CLK_I_BufferRisingFalling
MARKER  MARK10
Percent 100
ATTACH  dbg_wp_o[11]    NULL    S1
!
TIME    1610.903040
RELATIVETIME    0.000000
CORGROUP        $$CLK_I_BufferRising
DISPLAYAS       5
Percent 100
MARKERTYPE      Timebreak(Curved)
!
WHILERETURN
REPEATNUMBER
CORGROUP        $$CLK_I_BufferFalling
SNAPTO  0
Percent 100
COMPRESSTIME    0.000000
!
COMMENT aaa
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
MARKER  MARK20
!
ATTACH  dbg_bp_o        NULL    S2
TIME    2644.928640
CORGROUP        $$CLK_I_BufferRising
RELATIVETIME    0.000000
Percent 100
DISPLAYAS       5
!
MARKERTYPE      Timebreak(Curved)
WHILERETURN
CORGROUP        $$CLK_I_BufferFalling
REPEATNUMBER
Percent 100
SNAPTO  0
!
COMPRESSTIME    0.000000
COMMENT
CORGROUP        $$CLK_I_BufferRisingFalling
!
Percent 100
!
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CORGROUP        $$dwb_CLK_I_BufferRising
U2Ep77
RUlL\6@?%v7RD;U$
Percent 100
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-H*9(TYkPEQ/,GuideTheDocPage-1Gesture FormatVisio 90ConnectorVisio 00Visio 01Visio 02Visio 03Visio 10Visio 11Visio 12Visio 13Visio 20Visio 21Visio 22Visio 23Visio 50Visio 51Visio 52Visio 53Visio 70Visio 80BasicBasic ShadowRectangleSchemeNameRectangle.28Rectangle.4Rectangle.5Rectangle.6Rectangle.7Rectangle.8Rectangle.9Rectangle.10Rectangle.11Dynamic conn?ectorRectangle.16Rectangle.17Rectangle.18Rectangle.24Rectangle.25_%,3:
CORGROUP        $$dwb_CLK_I_BufferFalling
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Percent 100
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!
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CORGROUP        $$dwb_CLK_I_BufferRisingFalling
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Percent 100
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!
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CORGROUP        $$dwb_CLK_RISC_BufferRising
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Percent 100
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!
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CORGROUP        $$dwb_CLK_RISC_BufferFalling
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Percent 100
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!


CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling

Percent 100

!
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CORGROUP        $$dwb_CLK_I_BufferRising
AJ-37A_*<N@:?GRVg
Percent 100
H<(
!
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CORGROUP        $$dwb_CLK_I_BufferFalling
Ru&O(!B  U[I>l8B>O9BNo5Og^$f$
Percent 100
'7SN8)49J1=𜻗`2<V?W, FD_#C}=\f.U ՜.+,D՜.+,(@LXd
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!
RectangleDynamic connector 0lx_VPID_ALTERNATENAMESB`_PID_LINKBASEA     
Q<=KuyTiming DiagramTiming.Document.19qTiming Diagram
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
Q<=KuyTiming DiagramTiming.Document.19qTiming DiagramTiming Diagram Editor v7.1g - Output File
Percent 100
!
PROJECT
BaseTimeUnit    1
CORGROUP        $$dwb_CLK_RISC_BufferRising
DisplayTimeUnit 2
Percent 100
TextGridX       625.000000
!
TextGridY       6
EdgeGridX       625.000000
CORGROUP        $$dwb_CLK_RISC_BufferFalling
ImportStartTime 0.000000
Percent 100
ImportEndTime   281474976710656.000000
!
TimePerPixel    61.428571
Visible DELAYS  SETUPS  HOLDS   SAMPLES TEXT    HIDDENATTACHMENTS       CRITICALPATHS   GRIDLINES       UNCERTAINTY
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
ColWidths       144,216,288,423,488
Percent 100
ScrollPos       0.000000,0.000000,0.000000
!
DefDelayRule    1
NoEventOverlap  NO
CORGROUP        $$dwb_CLK_I_BufferRising
SigLabelFontHeight      10
Percent 100
LabelHeight     12
!
LoadLibsToMem   1
UseFullPathNames        1
CORGROUP        $$dwb_CLK_I_BufferFalling
LibPath
Percent 100
EntireTime      YES
!
PrintTimeSpecified      NO
FromTime        0
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
ToTime  53.75
Percent 100
AllSignals      YES
!
CurrSelSigs     NO
PrintTo 2
CORGROUP        $$dwb_CLK_RISC_BufferRising
PrintFileName   C:\DOCS\wb_writeblock_typ.wmf
Percent 100
PreviewInterchange      YES
!
PreviewTIFF5    NO
UseMargins      NO
CORGROUP        $$dwb_CLK_RISC_BufferFalling
PrintTimeLine   NO
Percent 100
PrintBorderBox  YES
!
PrintSigNames   YES
PrintSigNamesOnEachPage YES
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
AddPreviewToEPS NO
Percent 100
PreviewRes      150
!
MarginLR        1.25
MifImageWidth   6.00
CORGROUP        $$dwb_CLK_I_BufferRising
MarginTB        Auto
Percent 100
Header  %d %t;%f;%p
!
Footer
ScaleHorz       100
CORGROUP        $$dwb_CLK_I_BufferFalling
ScaleVert       100
Percent 100
ScaleHPage      1
!
PrintImage      DIAGRAM
DefaultTimingModel      minmax
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
DefaultClock    Unclocked
Percent 100
DefaultEdgeLevel        neg
!
DefaultSet      Not Used
DefaultClear    Not Used
CORGROUP        $$CLK_RISC_BufferRising
DefaultClockEnable      Not Used
Percent 100
DefaultClockToOutLH     0
!
DefaultClockToOutHL     0
DefaultSetup    0
CORGROUP        $$CLK_RISC_BufferFalling
DefaultHold     0
Percent 100
DefaultRegStartupState  unknown
!
DefaultPodSize  8
DefaultActiveLowSetClear        True
CORGROUP        $$CLK_RISC_BufferRisingFalling
DefaultAsyncSetClear    True
Percent 100
DefaultActiveLowClockEnable     True
!
SigLabelFontHeight      10
PROPS!
CORGROUP        $$iwb_CLK_I_BufferRising
!
Percent 100
!
STYLE
DefaultFont     USER    {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
CORGROUP        $$iwb_CLK_I_BufferFalling
DrawWndFont     DEFAULT
Percent 100
DrawWndColor    DEFAULT
!
GridWndFont     DEFAULT
GridWndColor    DEFAULT
CORGROUP        $$iwb_CLK_I_BufferRisingFalling
LabelWndFont    USER    {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
Percent 100
LabelWndColor   DEFAULT
!
ParamDispPref   0
ParamWndCellDisplay     0
CLOCK   CLK_RISC
CustDispString  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
PERIODE 2.5
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
DUTY    50
MarkerDispPref  4
OFFSETE 0
MarkerCustDispString    %n v=%mv,%Mv d=%md %t
INITIAL HIGH
MarkerCustomDisplayStringRTF    {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
MAXUNCERTRISE   0
SignalColor     2
MAXUNCERTFALL   0
LabelOffset     2
MINUNCERTRISE   0
BusDisplay      0
MINUNCERTFALL   0
WaveFormWidth   0.500000
JRISEE  0
WaveFormColor   0
JFALLE  0
InputWaveFormColor      16711680
GRID    0        1       0        2       0        16711680        0        0
SlantedEdges    1
ENDGRID -1
SlantAngle      75
DIRECTION       internal
RightJustifySigNames    1
MASTERCLOCK     None
AutosplitEnabled        1
Clock   Unclocked
AutosplitChar   _
EdgeLevel       neg
DynamSizedSignals       1
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
DIAGRAMTESTBENCHSETTINGS
ActiveLowSetClear       True
FilesBeforeDiagramModel
AsyncSetClear   True
FilesInsideDiagramModelDeclarationSection
ActiveLowClockEnable    True
AbortHdlCodeEnabled     1
VhdlType        std_logic
DelayHdlCodeEnabled     1
VerilogType     wire
SampleHdlCodeEnabled    1
SystemCType     sc_logic
MarkerHdlCodeEnabled    1
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
VerboseSamples  0
StateEquation   Hex(Inc(0,2,5))
VerboseDelays   0
HighVoltageThreshold    5
VerboseFileInput        0
LowVoltageThreshold     0
VerboseSequenceVerification     0
MSB     0
IncludeDelayTime        1
LSB     0
ExecuteFromTopLevel     1
isFallingEdgeSensitive  False
TimeOutInDiagramLengths 0
isRisingEdgeSensitive   False
DefaultCycleClock       Unclocked
DrawAnalog      0
DefaultCycleEdge        neg
BooleanEquation
!
NegTolerance    0
PosTolerance    0
MACROS
UserSpecifiedSizeRatio  1
!
VerilogCode
VHDLCode
CORGROUP        $$CLK_I_BufferRising
PROPS!
Percent 100
!
!
CLOCK   iwb_CLK_I
CORGROUP        $$CLK_I_BufferFalling
PERIODE 5
Percent 100
DUTY    50
!
OFFSETE 0
INITIAL LOW
CORGROUP        $$CLK_I_BufferRisingFalling
MAXUNCERTRISE   0
Percent 100
MAXUNCERTFALL   0
!
MINUNCERTRISE   0
MINUNCERTFALL   0
CORGROUP        $$CLK_I_BufferRising
JRISEE  0
Percent 100
JFALLE  0
!
GRID    1       1       1       2       2       16711680        0        0
ENDGRID -1
CORGROUP        $$CLK_I_BufferFalling
DIRECTION       input
Percent 100
MASTERCLOCK     None
!
Clock   Unclocked
EdgeLevel       neg
CORGROUP        $$CLK_I_BufferRisingFalling
Set     Not Used
Percent 100
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CORGROUP        $$CLK_I_BufferRising
AsyncSetClear   True
Percent 100
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
CORGROUP        $$CLK_I_BufferFalling
SystemCType     sc_logic
Percent 100
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
CORGROUP        $$CLK_I_BufferRisingFalling
LowVoltageThreshold     0
Percent 100
MSB     0
!
LSB     0
isFallingEdgeSensitive  False
CORGROUP        $$CLK_I_BufferRising
isRisingEdgeSensitive   True
Percent 100
DrawAnalog      0
!
BooleanEquation
NegTolerance    0
CORGROUP        $$CLK_I_BufferFalling
PosTolerance    0
Percent 100
UserSpecifiedSizeRatio  1
!
VerilogCode
VHDLCode
CORGROUP        $$CLK_I_BufferRisingFalling
PROPS!
Percent 100
!
!
SIGNAL  iwb_ADR_O
CORGROUP        $$CLK_I_BufferRising
DIRECTION       output
Percent 100
RADIX   hex
!
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
CORGROUP        $$CLK_I_BufferFalling
Clock
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$CLK_I_BufferRisingFalling
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$CLK_I_BufferRising
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$CLK_I_BufferFalling
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
LSB     0
CORGROUP        $$CLK_I_BufferRisingFalling
MSB     31
Percent 100
SignalActionType        0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   True
CORGROUP        $$CLK_RISC_BufferRising
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$CLK_RISC_BufferFalling
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
VhdlMapping     DefaultVhdlMapping
CORGROUP        $$CLK_RISC_BufferRisingFalling
PROPS!
Percent 100
E0      V       -1      -1              1       0        DR      0
!
E1      X       3125    3125            1       0        DR      0
E2      V       3126    3126    A0      1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRising
E3      X       3750    3750            1       0        DR      0
Percent 100
E4      V       13125   13125     A0    1       0        DR      0
!
E5      X       13625   13625           1       0        DR      0
E6      V       23125   23125     A4    1       0        DR      0
CORGROUP        $$CLK_RISC_BufferFalling
E7      X       23625   23625           1       0        DR      0
Percent 100
E8      V       33125   33125     A8    1       0        DR      0
!
E9      X       33625   33625           1       0        DR      0
E10     V       43125   43125     A12   1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRisingFalling
E11     X       43750   43750           1       0        DR      0
Percent 100
!
!
SIGNAL  iwb_DAT_I
CORGROUP        $$CLK_I_BufferRising
DIRECTION       input
Percent 100
RADIX   hex
!
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
CORGROUP        $$CLK_I_BufferFalling
Clock
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$CLK_I_BufferRisingFalling
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$CLK_RISC_BufferRising
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$CLK_RISC_BufferFalling
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
LSB     0
CORGROUP        $$CLK_RISC_BufferRisingFalling
MSB     31
Percent 100
SignalActionType        0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
CORGROUP        $$CLK_I_BufferRising
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$CLK_I_BufferFalling
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
VhdlMapping     DefaultVhdlMapping
CORGROUP        $$CLK_I_BufferRisingFalling
PROPS!
Percent 100
E0      X       11250   11250           1       0        DR      0
!
E1      V       13125   13125   D0      1       0        DR      0
E2      X       21250   21250           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRising
E3      V       23125   23125   D4      1       0        DR      0
Percent 100
E4      X       31250   31250           1       0        DR      0
!
E5      V       33125   33125   D8      1       0        DR      0
E6      X       41250   41250           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferFalling
E7      V       43125   43125   D12     1       0        DR      0
Percent 100
E8      X       43750   43750           1       0        DR      0
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
SIGNAL  iwb_DAT_O
Percent 100
DIRECTION       output
!
RADIX   hex
GRID    0        1       0        1       0        16711680        0        0
CORGROUP        $$CLK_I_BufferRising
ENDGRID -1
Percent 100
Clock   Unclocked
!
EdgeLevel       neg
Set     Not Used
CORGROUP        $$CLK_I_BufferFalling
Clear   Not Used
Percent 100
ClockEnable     Not Used
!
ActiveLowSetClear       True
AsyncSetClear   True
CORGROUP        $$CLK_I_BufferRisingFalling
ActiveLowClockEnable    True
Percent 100
VhdlType        std_logic
!
VerilogType     wire
SystemCType     sc_logic
CORGROUP        $$CLK_RISC_BufferRising
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Percent 100
StateEquation   Hex(Inc(0,2,5))
!
HighVoltageThreshold    5
LowVoltageThreshold     0
CORGROUP        $$CLK_RISC_BufferFalling
LSB     0
Percent 100
MSB     31
!
SignalActionType        0
isFallingEdgeSensitive  False
CORGROUP        $$CLK_RISC_BufferRisingFalling
isRisingEdgeSensitive   False
Percent 100
DrawAnalog      0
!
BooleanEquation
NegTolerance    0
CORGROUP        $$CLK_I_BufferRising
PosTolerance    0
Percent 100
UserSpecifiedSizeRatio  1
!
VerilogCode
VHDLCode
CORGROUP        $$CLK_I_BufferFalling
PROPS!
Percent 100
E0      X       43750   43750           1       0        DR      0
!
!
CORGROUP        $$CLK_I_BufferRisingFalling
SIGNAL  iwb_WE_O
Percent 100
DIRECTION       output
!
RADIX   hex
GRID    0        1       0        1       0        16711680        0        0
CORGROUP        $$CLK_RISC_BufferRising
ENDGRID -1
Percent 100
Clock   Unclocked
!
EdgeLevel       neg
Set     Not Used
CORGROUP        $$CLK_RISC_BufferFalling
Clear   Not Used
Percent 100
ClockEnable     Not Used
!
ActiveLowSetClear       True
AsyncSetClear   True
CORGROUP        $$CLK_RISC_BufferRisingFalling
ActiveLowClockEnable    True
Percent 100
VhdlType        std_logic
!
VerilogType     wire
SystemCType     sc_logic
CORGROUP        $$CLK_I_BufferRising
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Percent 100
StateEquation   Hex(Inc(0,2,5))
!
HighVoltageThreshold    5
LowVoltageThreshold     0
CORGROUP        $$CLK_I_BufferFalling
SignalActionType        0
Percent 100
MSB     0
!
LSB     0
isFallingEdgeSensitive  False
CORGROUP        $$CLK_I_BufferRisingFalling
isRisingEdgeSensitive   False
Percent 100
DrawAnalog      0
!
BooleanEquation
NegTolerance    0
CORGROUP        $$CLK_RISC_BufferRising
PosTolerance    0
Percent 100
UserSpecifiedSizeRatio  1
!
VerilogCode
VHDLCode
CORGROUP        $$CLK_RISC_BufferFalling
PROPS!
Percent 100
E0      X       3125    3125            1       0        DR      0
!
E1      1       3126    3126            1       0        DR      0
E2      0        13125   13125           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRisingFalling
E3      X       13625   13625           1       0        DR      0
Percent 100
E4      0        23125   23125           1       0        DR      0
!
E5      X       23625   23625           1       0        DR      0
E6      0        33125   33125           1       0        DR      0
CORGROUP        $$CLK_I_BufferRising
E7      X       33625   33625           1       0        DR      0
Percent 100
E8      0        43125   43125           1       0        DR      0
!
E9      X       43625   43625           1       0        DR      0
!
CORGROUP        $$CLK_I_BufferFalling
Percent 100
SIGNAL  iwb_SEL_O
!
DIRECTION       output
RADIX   hex
CORGROUP        $$CLK_I_BufferRisingFalling
GRID    0        1       0        1       0        16711680        0        0
Percent 100
ENDGRID -1
!
Clock   Unclocked
EdgeLevel       neg
CORGROUP        $$CLK_RISC_BufferRising
Set     Not Used
Percent 100
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CORGROUP        $$CLK_RISC_BufferFalling
AsyncSetClear   True
Percent 100
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
CORGROUP        $$CLK_RISC_BufferRisingFalling
SystemCType     sc_logic
Percent 100
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
CORGROUP        $$CLK_I_BufferRising
LowVoltageThreshold     0
Percent 100
LSB     0
!
MSB     3
SignalActionType        0
CORGROUP        $$CLK_I_BufferFalling
isFallingEdgeSensitive  False
Percent 100
isRisingEdgeSensitive   False
!
DrawAnalog      0
BooleanEquation
CORGROUP        $$CLK_I_BufferRisingFalling
NegTolerance    0
Percent 100
PosTolerance    0
!
UserSpecifiedSizeRatio  1
VerilogCode
CORGROUP        $$CLK_RISC_BufferRising
VHDLCode
Percent 100
PROPS!
!
E0      V       0        0           Valid        1       0        DR      0
E1      X       3750    3750            1       0        DR      0
CORGROUP        $$CLK_RISC_BufferFalling
E2      V       13125   13125       Valid       1       0        DR      0
Percent 100
E3      X       13625   13625           1       0        DR      0
!
E4      V       23125   23125     Valid 1       0        DR      0
E5      X       23625   23625           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRisingFalling
E6      V       33125   33125     Valid 1       0        DR      0
Percent 100
E7      X       33625   33625           1       0        DR      0
!
E8      V       43125   43125     Valid 1       0        DR      0
E9      X       43750   43750           1       0        DR      0
CORGROUP        $$CLK_I_BufferRising
!
Percent 100
!
SIGNAL  iwb_STB_O
DIRECTION       output
CORGROUP        $$CLK_I_BufferFalling
RADIX   hex
Percent 100
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock   Unclocked
CORGROUP        $$CLK_I_BufferRisingFalling
EdgeLevel       neg
Percent 100
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
CORGROUP        $$CLK_RISC_BufferRising
ActiveLowSetClear       True
Percent 100
AsyncSetClear   True
!
ActiveLowClockEnable    True
VhdlType        std_logic
CORGROUP        $$CLK_RISC_BufferFalling
VerilogType     wire
Percent 100
SystemCType     sc_logic
!
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
CORGROUP        $$CLK_RISC_BufferRisingFalling
HighVoltageThreshold    5
Percent 100
LowVoltageThreshold     0
!
SignalActionType        0
MSB     0
CORGROUP        $$CLK_I_BufferRising
LSB     0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   False
DrawAnalog      0
CORGROUP        $$CLK_I_BufferFalling
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$CLK_I_BufferRisingFalling
VerilogCode
Percent 100
VHDLCode
!
PROPS!
E0      0        3750    3750            1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRising
E1      1       13125   13125           1       0        DR      0
Percent 100
E2      0        13625   13625           1       0        DR      0
!
E3      1       23125   23125           1       0        DR      0
E4      0        23625   23625           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferFalling
E5      1       33125   33125           1       0        DR      0
Percent 100
E6      0        33625   33625           1       0        DR      0
!
E7      1       43125   43125           1       0        DR      0
E8      X       43750   43750           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
SIGNAL  iwb_ACK_I
DIRECTION       input
CORGROUP        $$CLK_I_BufferRising
RADIX   hex
Percent 100
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock   Unclocked
CORGROUP        $$CLK_I_BufferFalling
EdgeLevel       neg
Percent 100
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
CORGROUP        $$CLK_I_BufferRisingFalling
ActiveLowSetClear       True
Percent 100
AsyncSetClear   True
!
ActiveLowClockEnable    True
VhdlType        std_logic
CORGROUP        $$CLK_RISC_BufferRising
VerilogType     wire
Percent 100
SystemCType     sc_logic
!
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
CORGROUP        $$CLK_RISC_BufferFalling
HighVoltageThreshold    5
Percent 100
LowVoltageThreshold     0
!
SignalActionType        0
MSB     0
CORGROUP        $$CLK_RISC_BufferRisingFalling
LSB     0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   False
DrawAnalog      0
CORGROUP        $$CLK_I_BufferRising
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$CLK_I_BufferFalling
VerilogCode
Percent 100
VHDLCode
!
PROPS!
E0      0        11250   11250           1       0        DR      0
CORGROUP        $$CLK_I_BufferRisingFalling
E1      1       13125   13125           1       0        DR      0
Percent 100
E2      0        21250   21250           1       0        DR      0
!
E3      1       23125   23125           1       0        DR      0
E4      0        31250   31250           1       0        DR      0
CORGROUP        $$dwb_CLK_RISC_BufferRising
E5      1       33125   33125           1       0        DR      0
Percent 100
E6      0        41250   41250           1       0        DR      0
!
E7      1       43125   43125           1       0        DR      0
E8      X       43750   43750           1       0        DR      0
CORGROUP        $$dwb_CLK_RISC_BufferFalling
!
Percent 100
!
SIGNAL  iwb_CYC_O
DIRECTION       output
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
RADIX   hex
Percent 100
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock   Unclocked
CORGROUP        $$dwb_CLK_I_BufferRising
EdgeLevel       neg
Percent 100
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
CORGROUP        $$dwb_CLK_I_BufferFalling
ActiveLowSetClear       True
Percent 100
AsyncSetClear   True
!
ActiveLowClockEnable    True
VhdlType        std_logic
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
VerilogType     wire
Percent 100
SystemCType     sc_logic
!
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
CORGROUP        $$dwb_CLK_RISC_BufferRising
HighVoltageThreshold    5
Percent 100
LowVoltageThreshold     0
!
SignalActionType        0
MSB     0
CORGROUP        $$dwb_CLK_RISC_BufferFalling
LSB     0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   False
DrawAnalog      0
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$dwb_CLK_I_BufferRising
VerilogCode
Percent 100
VHDLCode
!
PROPS!
E0      0        3125    3125            1       0        DR      0
CORGROUP        $$dwb_CLK_I_BufferFalling
E1      1       43125   43125           1       0        DR      0
Percent 100
E2      0        43750   43750           1       0        DR      0
!
!
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
SIGNAL  iwb_ERR_I
Percent 100
DIRECTION       input
!
RADIX   hex
GRID    0        1       0        1       0        16711680        0        0
CORGROUP        $$dwb_CLK_RISC_BufferRising
ENDGRID -1
Percent 100
Clock   Unclocked
!
EdgeLevel       neg
Set     Not Used
CORGROUP        $$dwb_CLK_RISC_BufferFalling
Clear   Not Used
Percent 100
ClockEnable     Not Used
!
ActiveLowSetClear       True
AsyncSetClear   True
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
ActiveLowClockEnable    True
Percent 100
VhdlType        std_logic
!
VerilogType     wire
SystemCType     sc_logic
CORGROUP        $$dwb_CLK_I_BufferRising
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Percent 100
StateEquation   Hex(Inc(0,2,5))
!
HighVoltageThreshold    5
LowVoltageThreshold     0
CORGROUP        $$dwb_CLK_I_BufferFalling
SignalActionType        0
Percent 100
MSB     0
!
LSB     0
isFallingEdgeSensitive  False
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
isRisingEdgeSensitive   False
Percent 100
DrawAnalog      0
!
BooleanEquation
NegTolerance    0
CORGROUP        $$dwb_CLK_RISC_BufferRising
PosTolerance    0
Percent 100
UserSpecifiedSizeRatio  1
!
VerilogCode
VHDLCode
CORGROUP        $$dwb_CLK_RISC_BufferFalling
PROPS!
Percent 100
E0      0        43125   43125           1       0        DR      0
!
E1      X       43750   43750           1       0        DR      0
!
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
Percent 100
SIGNAL  iwb_RTY_I
!
DIRECTION       input
RADIX   hex
CORGROUP        $$dwb_CLK_I_BufferRising
GRID    0        1       0        1       0        16711680        0        0
Percent 100
ENDGRID -1
!
Clock   Unclocked
EdgeLevel       neg
CORGROUP        $$dwb_CLK_I_BufferFalling
Set     Not Used
Percent 100
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
AsyncSetClear   True
Percent 100
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
CORGROUP        $$dwb_CLK_RISC_BufferRising
SystemCType     sc_logic
Percent 100
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
CORGROUP        $$dwb_CLK_RISC_BufferFalling
LowVoltageThreshold     0
Percent 100
SignalActionType        0
!
MSB     0
LSB     0
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
isFallingEdgeSensitive  False
Percent 100
isRisingEdgeSensitive   False
!
DrawAnalog      0
BooleanEquation
CORGROUP        $$dwb_CLK_I_BufferRising
NegTolerance    0
Percent 100
PosTolerance    0
!
UserSpecifiedSizeRatio  1
VerilogCode
CORGROUP        $$dwb_CLK_I_BufferFalling
VHDLCode
Percent 100
PROPS!
!
E0      0        43125   43125           1       0        DR      0
E1      X       43750   43750           1       0        DR      0
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
!
Percent 100
!
MARKER  MARK1
ATTACH  iwb_SEL_O       NULL    S6
CORGROUP        $$dwb_CLK_RISC_BufferRising
TIME    17500.000000
Percent 100
RELATIVETIME    0.000000
!
DISPLAYAS       5
MARKERTYPE      Timebreak(Curved)
CORGROUP        $$dwb_CLK_RISC_BufferFalling
WHILERETURN
Percent 100
REPEATNUMBER
!
SNAPTO  0
COMPRESSTIME    0.000000
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
COMMENT
Percent 100
!
!
MARKER  MARK2
CORGROUP        $$dwb_CLK_I_BufferRising
ATTACH  iwb_STB_O       NULL    S7
Percent 100
TIME    27500.000000
!
RELATIVETIME    0.000000
DISPLAYAS       5
CORGROUP        $$dwb_CLK_I_BufferFalling
MARKERTYPE      Timebreak(Curved)
Percent 100
WHILERETURN
!
REPEATNUMBER
SNAPTO  0
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
COMPRESSTIME    0.000000
Percent 100
COMMENT
!
!
CORGROUP        $$CLK_RISC_BufferRising
MARKER  MARK3
Percent 100
ATTACH  iwb_STB_O       NULL    S7
!
TIME    37500.000000
RELATIVETIME    0.000000
CORGROUP        $$CLK_RISC_BufferFalling
DISPLAYAS       5
Percent 100
MARKERTYPE      Timebreak(Curved)
!
WHILERETURN
REPEATNUMBER
CORGROUP        $$CLK_RISC_BufferRisingFalling
SNAPTO  0
Percent 100
COMPRESSTIME    0.000000
!
COMMENT
!
CORGROUP        $$dwb_CLK_I_BufferRising
Percent 100
MARKER  MARK0
!
ATTACH  iwb_CLK_I       NULL    S1
TIME    7494.285714
CORGROUP        $$dwb_CLK_I_BufferFalling
RELATIVETIME    0.000000
Percent 100
DISPLAYAS       5
!
MARKERTYPE      Timebreak(Curved)
WHILERETURN
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
REPEATNUMBER
Percent 100
SNAPTO  0
!
COMPRESSTIME    0.000000
COMMENT
CLOCK   CLK_RISC
!
PERIODE 2.5
DUTY    50

OFFSETE 0
Q<=KuyTiming DiagramTiming.Document.19qTiming Diagram
INITIAL HIGH
Q<=KuyTiming DiagramTiming.Document.19qTiming DiagramTiming Diagram Editor v7.1g - Output File
MAXUNCERTRISE   0
MAXUNCERTFALL   0
PROJECT
MINUNCERTRISE   0
BaseTimeUnit    1
MINUNCERTFALL   0
DisplayTimeUnit 2
JRISEE  0
TextGridX       625.000000
JFALLE  0
TextGridY       6
GRID    0        1       0        2       0        16711680        0        0
EdgeGridX       625.000000
ENDGRID -1
ImportStartTime 0.000000
DIRECTION       internal
ImportEndTime   281474976710656.000000
MASTERCLOCK     None
TimePerPixel    61.428571
Clock   Unclocked
Visible DELAYS  SETUPS  HOLDS   SAMPLES TEXT    HIDDENATTACHMENTS       CRITICALPATHS   GRIDLINES       UNCERTAINTY
EdgeLevel       neg
ColWidths       144,216,288,423,488
Set     Not Used
ScrollPos       0.000000,0.000000,0.000000
Clear   Not Used
DefDelayRule    1
ClockEnable     Not Used
NoEventOverlap  NO
ActiveLowSetClear       True
SigLabelFontHeight      10
AsyncSetClear   True
LabelHeight     12
ActiveLowClockEnable    True
LoadLibsToMem   1
VhdlType        std_logic
UseFullPathNames        1
VerilogType     wire
LibPath
SystemCType     sc_logic
EntireTime      YES
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
PrintTimeSpecified      NO
StateEquation   Hex(Inc(0,2,5))
FromTime        0
HighVoltageThreshold    5
ToTime  53.75
LowVoltageThreshold     0
AllSignals      YES
MSB     0
CurrSelSigs     NO
LSB     0
PrintTo 2
isFallingEdgeSensitive  False
PrintFileName   C:\DOCS\wb_writeblock_typ.wmf
isRisingEdgeSensitive   False
PreviewInterchange      YES
DrawAnalog      0
PreviewTIFF5    NO
BooleanEquation
UseMargins      NO
NegTolerance    0
PrintTimeLine   NO
PosTolerance    0
PrintBorderBox  YES
UserSpecifiedSizeRatio  1
PrintSigNames   YES
VerilogCode
PrintSigNamesOnEachPage YES
VHDLCode
AddPreviewToEPS NO
PROPS!
PreviewRes      150
!
MarginLR        1.25
MifImageWidth   6.00
CLOCK   dwb_CLK_I
MarginTB        Auto
PERIODE 5
Header  %d %t;%f;%p
DUTY    50
Footer
OFFSETE 0
ScaleHorz       100
INITIAL LOW
ScaleVert       100
MAXUNCERTRISE   0
ScaleHPage      1
MAXUNCERTFALL   0
PrintImage      DIAGRAM
MINUNCERTRISE   0
DefaultTimingModel      minmax
MINUNCERTFALL   0
DefaultClock    Unclocked
JRISEE  0
DefaultEdgeLevel        neg
JFALLE  0
DefaultSet      Not Used
GRID    1       1       1       2       2       16711680        0        0
DefaultClear    Not Used
ENDGRID -1
DefaultClockEnable      Not Used
DIRECTION       input
DefaultClockToOutLH     0
MASTERCLOCK     None
DefaultClockToOutHL     0
Clock   Unclocked
DefaultSetup    0
EdgeLevel       neg
DefaultHold     0
Set     Not Used
DefaultRegStartupState  unknown
Clear   Not Used
DefaultPodSize  8
ClockEnable     Not Used
DefaultActiveLowSetClear        True
ActiveLowSetClear       True
DefaultAsyncSetClear    True
AsyncSetClear   True
DefaultActiveLowClockEnable     True
ActiveLowClockEnable    True
SigLabelFontHeight      10
VhdlType        std_logic
PROPS!
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
STYLE
StateEquation   Hex(Inc(0,2,5))
DefaultFont     USER    {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
HighVoltageThreshold    5
DrawWndFont     DEFAULT
LowVoltageThreshold     0
DrawWndColor    DEFAULT
MSB     0
GridWndFont     DEFAULT
LSB     0
GridWndColor    DEFAULT
isFallingEdgeSensitive  False
LabelWndFont    USER    {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
isRisingEdgeSensitive   True
LabelWndColor   DEFAULT
DrawAnalog      0
ParamDispPref   0
BooleanEquation
ParamWndCellDisplay     0
NegTolerance    0
CustDispString  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
PosTolerance    0
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
UserSpecifiedSizeRatio  1
MarkerDispPref  4
VerilogCode
MarkerCustDispString    %n v=%mv,%Mv d=%md %t
VHDLCode
MarkerCustomDisplayStringRTF    {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
PROPS!
SignalColor     2
!
LabelOffset     2
BusDisplay      0
SIGNAL  dwb_ADR_O
WaveFormWidth   0.500000
DIRECTION       output
WaveFormColor   0
RADIX   hex
InputWaveFormColor      16711680
GRID    0        1       0        1       0        16711680        0        0
SlantedEdges    1
ENDGRID -1
SlantAngle      75
Clock
RightJustifySigNames    1
EdgeLevel       neg
AutosplitEnabled        1
Set     Not Used
AutosplitChar   _
Clear   Not Used
DynamSizedSignals       1
ClockEnable     Not Used
!
ActiveLowSetClear       True
AsyncSetClear   True
DIAGRAMTESTBENCHSETTINGS
ActiveLowClockEnable    True
FilesBeforeDiagramModel
VhdlType        std_logic
FilesInsideDiagramModelDeclarationSection
VerilogType     wire
AbortHdlCodeEnabled     1
SystemCType     sc_logic
DelayHdlCodeEnabled     1
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
SampleHdlCodeEnabled    1
StateEquation   Hex(Inc(0,2,5))
MarkerHdlCodeEnabled    1
HighVoltageThreshold    5
VerboseSamples  0
LowVoltageThreshold     0
VerboseDelays   0
LSB     0
VerboseFileInput        0
MSB     31
VerboseSequenceVerification     0
SignalActionType        0
IncludeDelayTime        1
isFallingEdgeSensitive  False
ExecuteFromTopLevel     1
isRisingEdgeSensitive   True
TimeOutInDiagramLengths 0
DrawAnalog      0
DefaultCycleClock       Unclocked
BooleanEquation
DefaultCycleEdge        neg
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
MACROS
VerilogCode
!
VHDLCode
VhdlMapping     DefaultVhdlMapping
CORGROUP        $$CLK_I_BufferRising
PROPS!
Percent 100
E0      V       -1      -1              1       0        DR      0
!
E1      X       3123    3123            1       0        DR      0
E2      V       13125   13125     A0    1       0        DR      0
CORGROUP        $$CLK_I_BufferFalling
E3      X       13625   13625           1       0        DR      0
Percent 100
E4      V       23125   23125     A4    1       0        DR      0
!
E5      X       23625   23625           1       0        DR      0
E6      V       33125   33125     A8    1       0        DR      0
CORGROUP        $$CLK_I_BufferRisingFalling
E7      X       33625   33625           1       0        DR      0
Percent 100
E8      V       43125   43125     A12   1       0        DR      0
!
E9      X       43750   43750           1       0        DR      0
E10     V       53125   53125    A0     1       0        DR      0
CORGROUP        $$CLK_I_BufferRising
E11     X       53750   53750           1       0        DR      0
Percent 100
!
!
SIGNAL  dwb_DAT_I
CORGROUP        $$CLK_I_BufferFalling
DIRECTION       input
Percent 100
RADIX   hex
!
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
CORGROUP        $$CLK_I_BufferRisingFalling
Clock
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$CLK_I_BufferRising
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$CLK_I_BufferFalling
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$CLK_I_BufferRisingFalling
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
LSB     0
CORGROUP        $$CLK_I_BufferRising
MSB     31
Percent 100
SignalActionType        0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
CORGROUP        $$CLK_I_BufferFalling
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$CLK_I_BufferRisingFalling
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
VhdlMapping     DefaultVhdlMapping
CORGROUP        $$CLK_I_BufferRising
PROPS!
Percent 100
E0      X       11250   11250           1       0        DR      0
!
E1      V       13125   13125   D0      1       0        DR      0
E2      X       21250   21250           1       0        DR      0
CORGROUP        $$CLK_I_BufferFalling
E3      V       23125   23125   D4      1       0        DR      0
Percent 100
E4      X       31250   31250           1       0        DR      0
!
E5      V       33125   33125   D8      1       0        DR      0
E6      X       41250   41250           1       0        DR      0
CORGROUP        $$CLK_I_BufferRisingFalling
E7      V       43125   43125   D12     1       0        DR      0
Percent 100
E8      X       53750   53750           1       0        DR      0
!
!
CORGROUP        $$CLK_I_BufferRising
SIGNAL  dwb_DAT_O
Percent 100
DIRECTION       output
!
RADIX   hex
GRID    0        1       0        1       0        16711680        0        0
CORGROUP        $$CLK_I_BufferFalling
ENDGRID -1
Percent 100
Clock   Unclocked
!
EdgeLevel       neg
Set     Not Used
CORGROUP        $$CLK_I_BufferRisingFalling
Clear   Not Used
Percent 100
ClockEnable     Not Used
!
ActiveLowSetClear       True
AsyncSetClear   True
CORGROUP        $$CLK_RISC_BufferRising
ActiveLowClockEnable    True
Percent 100
VhdlType        std_logic
!
VerilogType     wire
SystemCType     sc_logic
CORGROUP        $$CLK_RISC_BufferFalling
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Percent 100
StateEquation   Hex(Inc(0,2,5))
!
HighVoltageThreshold    5
LowVoltageThreshold     0
CORGROUP        $$CLK_RISC_BufferRisingFalling
LSB     0
Percent 100
MSB     31
!
SignalActionType        0
isFallingEdgeSensitive  False
CORGROUP        $$CLK_RISC_BufferRising
isRisingEdgeSensitive   False
Percent 100
DrawAnalog      0
!
BooleanEquation
NegTolerance    0
CORGROUP        $$CLK_RISC_BufferFalling
PosTolerance    0
Percent 100
UserSpecifiedSizeRatio  1
!
VerilogCode
VHDLCode
CORGROUP        $$CLK_RISC_BufferRisingFalling
PROPS!
Percent 100
E0      X       3125    3125            1       0        DR      0
!
E1      V       3126    3126    D0      1       0        DR      0
E2      X       43125   43125           1       0        DR      0
CORGROUP        $$CLK_I_BufferRising
E3      V       53124   53124     D0    1       0        DR      0
Percent 100
E4      X       53750   53750           1       0        DR      0
!
!
CORGROUP        $$CLK_I_BufferFalling
SIGNAL  dwb_WE_O
Percent 100
DIRECTION       output
!
RADIX   hex
GRID    0        1       0        1       0        16711680        0        0
CORGROUP        $$CLK_I_BufferRisingFalling
ENDGRID -1
Percent 100
Clock   Unclocked
!
EdgeLevel       neg
Set     Not Used
CORGROUP        $$CLK_RISC_BufferRising
Clear   Not Used
Percent 100
ClockEnable     Not Used
!
ActiveLowSetClear       True
AsyncSetClear   True
CORGROUP        $$CLK_RISC_BufferFalling
ActiveLowClockEnable    True
Percent 100
VhdlType        std_logic
!
VerilogType     wire
SystemCType     sc_logic
CORGROUP        $$CLK_RISC_BufferRisingFalling
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Percent 100
StateEquation   Hex(Inc(0,2,5))
!
HighVoltageThreshold    5
LowVoltageThreshold     0
CORGROUP        $$CLK_I_BufferRising
SignalActionType        0
Percent 100
MSB     0
!
LSB     0
isFallingEdgeSensitive  False
CORGROUP        $$CLK_I_BufferFalling
isRisingEdgeSensitive   False
Percent 100
DrawAnalog      0
!
BooleanEquation
NegTolerance    0
CORGROUP        $$CLK_I_BufferRisingFalling
PosTolerance    0
Percent 100
UserSpecifiedSizeRatio  1
!
VerilogCode
VHDLCode
CORGROUP        $$CLK_RISC_BufferRising
PROPS!
Percent 100
E0      X       3126    3126            1       0        DR      0
!
E1      0        13125   13125           1       0        DR      0
E2      X       13625   13625           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferFalling
E3      0        23125   23125           1       0        DR      0
Percent 100
E4      X       23625   23625           1       0        DR      0
!
E5      0        33125   33125           1       0        DR      0
E6      X       33750   33750           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRisingFalling
E7      0        43125   43125           1       0        DR      0
Percent 100
E8      1       53125   53125           1       0        DR      0
!
E9      0        53750   53750           1       0        DR      0
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
SIGNAL  dwb_SEL_O
!
DIRECTION       output
RADIX   hex
CORGROUP        $$CLK_I_BufferFalling
GRID    0        1       0        1       0        16711680        0        0
Percent 100
ENDGRID -1
!
Clock   Unclocked
EdgeLevel       neg
CORGROUP        $$CLK_I_BufferRisingFalling
Set     Not Used
Percent 100
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CORGROUP        $$CLK_RISC_BufferRising
AsyncSetClear   True
Percent 100
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
CORGROUP        $$CLK_RISC_BufferFalling
SystemCType     sc_logic
Percent 100
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
CORGROUP        $$CLK_RISC_BufferRisingFalling
LowVoltageThreshold     0
Percent 100
LSB     0
!
MSB     3
SignalActionType        0
CORGROUP        $$CLK_I_BufferRising
isFallingEdgeSensitive  False
Percent 100
isRisingEdgeSensitive   False
!
DrawAnalog      0
BooleanEquation
CORGROUP        $$CLK_I_BufferFalling
NegTolerance    0
Percent 100
PosTolerance    0
!
UserSpecifiedSizeRatio  1
VerilogCode
CORGROUP        $$CLK_I_BufferRisingFalling
VHDLCode
Percent 100
PROPS!
!
E0      X       3123    3123            1       0        DR                                  
             
                                                                                                 !     "     #     $     %     &	'	(	)	*	+	,	-	.	/	0	1	3	4	5	6	7	8	9	:	;     <	=	>      ?     z B     C     D     E     F     G     H     I     J     K     L     M     N     O     P     Q     R     S     T     U     V     W     X     Y     [ \     ]     ^     _     `     a     b     c     d     e     f     g     h     i     j     k     l     m     n     o     p     q     r     s     t     u     v     w     x     y      |     }     ~               0
CORGROUP        $$CLK_RISC_BufferRising
E1      V       13125   13125       Valid       1       0        DR      0
Percent 100
E2      X       13625   13625           1       0        DR      0
!
E3      V       23125   23125     Valid 1       0        DR      0
E4      X       23625   23625           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferFalling
E5      V       33125   33125     Valid 1       0        DR      0
Percent 100
E6      X       33625   33625           1       0        DR      0
!
E7      V       43125   43125     Valid 1       0        DR      0
E8      X       43750   43750           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRisingFalling
E9      V       53124   53124      Valid        1       0        DR      0
Percent 100
E10     X       53750   53750           1       0        DR      0
!
!
CORGROUP        $$CLK_I_BufferRising
SIGNAL  dwb_STB_O
Percent 100
DIRECTION       output
!
RADIX   hex
GRID    0        1       0        1       0        16711680        0        0
CORGROUP        $$CLK_I_BufferFalling
ENDGRID -1
Percent 100
Clock   Unclocked
!
EdgeLevel       neg
Set     Not Used
CORGROUP        $$CLK_I_BufferRisingFalling
Clear   Not Used
Percent 100
ClockEnable     Not Used
!
ActiveLowSetClear       True
AsyncSetClear   True
CORGROUP        $$CLK_RISC_BufferRising
ActiveLowClockEnable    True
Percent 100
VhdlType        std_logic
!
VerilogType     wire
SystemCType     sc_logic
CORGROUP        $$CLK_RISC_BufferFalling
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Percent 100
StateEquation   Hex(Inc(0,2,5))
!
HighVoltageThreshold    5
LowVoltageThreshold     0
CORGROUP        $$CLK_RISC_BufferRisingFalling
SignalActionType        0
Percent 100
MSB     0
!
LSB     0
isFallingEdgeSensitive  False
CORGROUP        $$CLK_I_BufferRising
isRisingEdgeSensitive   False
Percent 100
DrawAnalog      0
!
BooleanEquation
NegTolerance    0
CORGROUP        $$CLK_I_BufferFalling
PosTolerance    0
Percent 100
UserSpecifiedSizeRatio  1
!
VerilogCode
VHDLCode
CORGROUP        $$CLK_I_BufferRisingFalling
PROPS!
Percent 100
E0      0        3750    3750            1       0        DR      0
!
E1      1       13125   13125           1       0        DR      0
E2      0        13625   13625           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRising
E3      1       23125   23125           1       0        DR      0
Percent 100
E4      0        23625   23625           1       0        DR      0
!
E5      1       33125   33125           1       0        DR      0
E6      0        33625   33625           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferFalling
E7      1       43124   43124           1       0        DR      0
Percent 100
E8      0        44466   44466           1       0        DR      0
!
E9      1       53124   53124           1       0        DR      0
E10     X       53750   53750           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
SIGNAL  dwb_ACK_I
DIRECTION       input
CORGROUP        $$CLK_I_BufferRising
RADIX   hex
Percent 100
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock   Unclocked
CORGROUP        $$CLK_I_BufferFalling
EdgeLevel       neg
Percent 100
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
CORGROUP        $$CLK_I_BufferRisingFalling
ActiveLowSetClear       True
Percent 100
AsyncSetClear   True
!
ActiveLowClockEnable    True
VhdlType        std_logic
CORGROUP        $$CLK_RISC_BufferRising
VerilogType     wire
Percent 100
SystemCType     sc_logic
!
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
CORGROUP        $$CLK_RISC_BufferFalling
HighVoltageThreshold    5
Percent 100
LowVoltageThreshold     0
!
SignalActionType        0
MSB     0
CORGROUP        $$CLK_RISC_BufferRisingFalling
LSB     0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   False
DrawAnalog      0
CORGROUP        $$CLK_I_BufferRising
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$CLK_I_BufferFalling
VerilogCode
Percent 100
VHDLCode
!
PROPS!
E0      0        11250   11250           1       0        DR      0
CORGROUP        $$CLK_I_BufferRisingFalling
E1      1       13125   13125           1       0        DR      0
Percent 100
E2      0        21250   21250           1       0        DR      0
!
E3      1       23125   23125           1       0        DR      0
E4      0        31250   31250           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRising
E5      1       33125   33125           1       0        DR      0
Percent 100
E6      0        41250   41250           1       0        DR      0
!
E7      1       43124   43124           1       0        DR      0
E8      0        51875   51875           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferFalling
E9      1       53124   53124           1       0        DR      0
Percent 100
E10     X       53750   53750           1       0        DR      0
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
SIGNAL  dwb_CYC_O
Percent 100
DIRECTION       output
!
RADIX   hex
GRID    0        1       0        1       0        16711680        0        0
CORGROUP        $$CLK_I_BufferRising
ENDGRID -1
Percent 100
Clock   Unclocked
!
EdgeLevel       neg
Set     Not Used
CORGROUP        $$CLK_I_BufferFalling
Clear   Not Used
Percent 100
ClockEnable     Not Used
!
ActiveLowSetClear       True
AsyncSetClear   True
CORGROUP        $$CLK_I_BufferRisingFalling
ActiveLowClockEnable    True
Percent 100
VhdlType        std_logic
!
VerilogType     wire
SystemCType     sc_logic
CORGROUP        $$CLK_RISC_BufferRising
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Percent 100
StateEquation   Hex(Inc(0,2,5))
!
HighVoltageThreshold    5
LowVoltageThreshold     0
CORGROUP        $$CLK_RISC_BufferFalling
SignalActionType        0
Percent 100
MSB     0
!
LSB     0
isFallingEdgeSensitive  False
CORGROUP        $$CLK_RISC_BufferRisingFalling
isRisingEdgeSensitive   False
Percent 100
DrawAnalog      0
!
BooleanEquation
NegTolerance    0
CORGROUP        $$CLK_I_BufferRising
PosTolerance    0
Percent 100
UserSpecifiedSizeRatio  1
!
VerilogCode
VHDLCode
CORGROUP        $$CLK_I_BufferFalling
PROPS!
Per     
E0      0        3125    3125            1       0        DR      0

 !"#$%&'()*+,-./0123456789:;<=>?@AtDEFGHIJKLMNOPQRSTUVWXYZ[\]^`abcdefghijklmnopqrsvwxyz{|}~cent      100
E1      1       43125   43125           1       0        DR      0
!
E2      0        44375   44375           1       0        DR      0
E3      1       53125   53125           1       0        DR      0
CORGROUP        $$CLK_I_BufferRisingFalling
E4      0        53750   53750           1       0        DR      0
Percent 100
!
!
SIGNAL  dwb_ERR_I
CORGROUP        $$CLK_RISC_BufferRising
DIRECTION       input
Percent 100
RADIX   hex
!
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
CORGROUP        $$CLK_RISC_BufferFalling
Clock   Unclocked
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$CLK_RISC_BufferRisingFalling
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$CLK_I_BufferRising
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$CLK_I_BufferFalling
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
SignalActionType        0
CORGROUP        $$CLK_I_BufferRisingFalling
MSB     0
Percent 100
LSB     0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
CORGROUP        $$dwb_CLK_RISC_BufferRising
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$dwb_CLK_RISC_BufferFalling
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
PROPS!
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
E0      0        53125   53125           1       0        DR      0
Percent 100
E1      X       53750   53750           1       0        DR      0
!
!
CORGROUP        $$dwb_CLK_I_BufferRising
SIGNAL  dwb_RTY_I
Percent 100
DIRECTION       input
!
RADIX   hex
GRID    0        1       0        1       0        16711680        0        0
CORGROUP        $$dwb_CLK_I_BufferFalling
ENDGRID -1
Percent 100
Clock   Unclocked
!
EdgeLevel       neg
Set     Not Used
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
Clear   Not Used
Percent 100
ClockEnable     Not Used
!
ActiveLowSetClear       True
AsyncSetClear   True
CORGROUP        $$dwb_CLK_RISC_BufferRising
ActiveLowClockEnable    True
Percent 100
VhdlType        std_logic
!
VerilogType     wire
SystemCType     sc_logic
CORGROUP        $$dwb_CLK_RISC_BufferFalling
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Percent 100
StateEquation   Hex(Inc(0,2,5))
!
HighVoltageThreshold    5
LowVoltageThreshold     0
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
SignalActionType        0
Percent 100
MSB     0
!
LSB     0
isFallingEdgeSensitive  False
CORGROUP        $$dwb_CLK_I_BufferRising
isRisingEdgeSensitive   False
Percent 100
DrawAnalog      0
!
BooleanEquation
NegTolerance    0
CORGROUP        $$dwb_CLK_I_BufferFalling
PosTolerance    0
Percent 100
UserSpecifiedSizeRatio  1
!
VerilogCode
VHDLCode
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
PROPS!
Percent 100
E0      0        53125   53125           1       0        DR      0
!
E1      X       53750   53750           1       0        DR      0
!
CORGROUP        $$dwb_CLK_RISC_BufferRising
Percent 100
MARKER  MARK1
!
ATTACH  dwb_SEL_O       NULL    S6
TIME    17500.000000
CORGROUP        $$dwb_CLK_RISC_BufferFalling
RELATIVETIME    0.000000
Percent 100
DISPLAYAS       5
!
MARKERTYPE      Timebreak(Curved)
WHILERETURN
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
REPEATNUMBER
Percent 100
SNAPTO  0
!
COMPRESSTIME    0.000000
COMMENT
CORGROUP        $$dwb_CLK_I_BufferRising
!
Percent 100
!
MARKER  MARK2
ATTACH  dwb_STB_O       NULL    S7
CORGROUP        $$dwb_CLK_I_BufferFalling
TIME    27500.000000
Percent 100
RELATIVETIME    0.000000
!
DISPLAYAS       5
MARKERTYPE      Timebreak(Curved)
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
WHILERETURN
Percent 100
REPEATNUMBER
!
SNAPTO  0
COMPRESSTIME    0.000000
CORGROUP        $$dwb_CLK_RISC_BufferRising
COMMENT
Percent 100
!
!
MARKER  MARK3
CORGROUP        $$dwb_CLK_RISC_BufferFalling
ATTACH  dwb_STB_O       NULL    S7
Percent 100
TIME    37500.000000
!
RELATIVETIME    0.000000
DISPLAYAS       5
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
MARKERTYPE      Timebreak(Curved)
Percent 100
WHILERETURN
!
REPEATNUMBER
SNAPTO  0
CORGROUP        $$dwb_CLK_I_BufferRising
COMPRESSTIME    0.000000
Percent 100
COMMENT
!
!
CORGROUP        $$dwb_CLK_I_BufferFalling
MARKER  MARK0
Percent 100
ATTACH  dwb_CLK_I       NULL    S1
!
TIME    7500.000000
RELATIVETIME    0.000000
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
DISPLAYAS       5
Percent 100
MARKERTYPE      Timebreak(Curved)
!
WHILERETURN
REPEATNUMBER
CORGROUP        $$dwb_CLK_RISC_BufferRising
SNAPTO  0
Percent 100
COMPRESSTIME    0.000000
!
COMMENT
!
CORGROUP        $$dwb_CLK_RISC_BufferFalling
Percent 100
MARKER  MARK4
!
ATTACH  dwb_ADR_O       NULL    S2
TIME    47500.000000
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
RELATIVETIME    0.000000
Percent 100
DISPLAYAS       5
!
MARKERTYPE      Timebreak(Curved)
WHILERETURN
CORGROUP        $$dwb_CLK_I_BufferRising
REPEATNUMBER
Percent 100
SNAPTO  0
!
COMPRESSTIME    0.000000
COMMENT
CORGROUP        $$dwb_CLK_I_BufferFalling
!
Percent 100
!
Timing Diagram Editor v7.1g - Output File
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
PROJECT
Percent 100
BaseTimeUnit    1
!
DisplayTimeUnit 2
TextGridX       625.000000
CORGROUP        $$dwb_CLK_RISC_BufferRising
TextGridY       6
Percent 100
EdgeGridX       625.000000
!
ImportStartTime 0.000000
ImportEndTime   281474976710656.000000
CORGROUP        $$dwb_CLK_RISC_BufferFalling
TimePerPixel    50.000000
Percent 100
Visible DELAYS  SETUPS  HOLDS   SAMPLES TEXT    HIDDENATTACHMENTS       CRITICALPATHS   GRIDLINES       UNCERTAINTY
!
ColWidths       144,216,288,423,488
ScrollPos       0.000000,0.000000,0.000000
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
DefDelayRule    1
Percent 100
NoEventOverlap  NO
!
SigLabelFontHeight      10
LabelHeight     12
CORGROUP        $$dwb_CLK_I_BufferRising
LoadLibsToMem   1
Percent 100
UseFullPathNames        1
!
LibPath
EntireTime      YES
CORGROUP        $$dwb_CLK_I_BufferFalling
PrintTimeSpecified      NO
Percent 100
FromTime        0
!
ToTime  43.75
AllSignals      YES
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
CurrSelSigs     NO
Percent 100
PrintTo 2
!
PrintFileName   C:\DOCS\wb_readblock_typ.wmf
PreviewInterchange      YES
CORGROUP        $$CLK_RISC_BufferRising
PreviewTIFF5    NO
Percent 100
UseMargins      NO
!
PrintTimeLine   NO
PrintBorderBox  YES
CORGROUP        $$CLK_RISC_BufferFalling
PrintSigNames   YES
Percent 100
PrintSigNamesOnEachPage YES
!
AddPreviewToEPS NO
PreviewRes      150
CORGROUP        $$CLK_RISC_BufferRisingFalling
MarginLR        1.25
Percent 100
MifImageWidth   6.00
!
MarginTB        Auto
Header  %d %t;%f;%p
CORGROUP        $$dwb_CLK_I_BufferRising
Footer
Percent 100
ScaleHorz       100
!
ScaleVert       100
ScaleHPage      1
CORGROUP        $$dwb_CLK_I_BufferFalling
PrintImage      DIAGRAM
Percent 100
DefaultTimingModel      minmax
!
DefaultClock    Unclocked
DefaultEdgeLevel        neg
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
DefaultSet      Not Used
Percent 100
DefaultClear    Not Used
!
DefaultClockEnable      Not Used
DefaultClockToOutLH     0
CLOCK   CLK_RISC
DefaultClockToOutHL     0
PERIODE 2.5
DefaultSetup    0
DUTY    50
DefaultHold     0
OFFSETE 0
DefaultRegStartupState  unknown
INITIAL HIGH
DefaultPodSize  8
MAXUNCERTRISE   0
DefaultActiveLowSetClear        True
MAXUNCERTFALL   0
DefaultAsyncSetClear    True
MINUNCERTRISE   0
DefaultActiveLowClockEnable     True
MINUNCERTFALL   0
SigLabelFontHeight      10
JRISEE  0
PROPS!
JFALLE  0
!
GRID    0        1       0        2       0        16711680        0        0
ENDGRID -1
STYLE
DIRECTION       internal
DefaultFont     USER    {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
MASTERCLOCK     None
DrawWndFont     DEFAULT
Clock   Unclocked
DrawWndColor    DEFAULT
EdgeLevel       neg
GridWndFont     DEFAULT
Set     Not Used
GridWndColor    DEFAULT
Clear   Not Used
LabelWndFont    USER    {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
ClockEnable     Not Used
LabelWndColor   DEFAULT
ActiveLowSetClear       True
ParamDispPref   0
AsyncSetClear   True
ParamWndCellDisplay     0
ActiveLowClockEnable    True
CustDispString  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
VhdlType        std_logic
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
VerilogType     wire
MarkerDispPref  4
SystemCType     sc_logic
MarkerCustDispString    %n v=%mv,%Mv d=%md %t
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
MarkerCustomDisplayStringRTF    {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
StateEquation   Hex(Inc(0,2,5))
SignalColor     2
HighVoltageThreshold    5
LabelOffset     2
LowVoltageThreshold     0
BusDisplay      0
MSB     0
WaveFormWidth   0.500000
LSB     0
WaveFormColor   0
isFallingEdgeSensitive  False
InputWaveFormColor      16711680
isRisingEdgeSensitive   False
SlantedEdges    1
DrawAnalog      0
SlantAngle      75
BooleanEquation
RightJustifySigNames    1
NegTolerance    0
AutosplitEnabled        1
PosTolerance    0
AutosplitChar   _
UserSpecifiedSizeRatio  1
DynamSizedSignals       1
VerilogCode
!
VHDLCode
PROPS!
DIAGRAMTESTBENCHSETTINGS
!
FilesBeforeDiagramModel
FilesInsideDiagramModelDeclarationSection
CLOCK   dwb_CLK_I
AbortHdlCodeEnabled     1
PERIODE 5
DelayHdlCodeEnabled     1
DUTY    50
SampleHdlCodeEnabled    1
OFFSETE 0
MarkerHdlCodeEnabled    1
INITIAL LOW
VerboseSamples  0
MAXUNCERTRISE   0
VerboseDelays   0
MAXUNCERTFALL   0
VerboseFileInput        0
MINUNCERTRISE   0
VerboseSequenceVerification     0
MINUNCERTFALL   0
IncludeDelayTime        1
JRISEE  0
ExecuteFromTopLevel     1
JFALLE  0
TimeOutInDiagramLengths 0
GRID    1       1       1       2       2       16711680        0        0
DefaultCycleClock       Unclocked
ENDGRID -1
DefaultCycleEdge        neg
DIRECTION       input
!
MASTERCLOCK     None
Clock   Unclocked
MACROS
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$CLK_I_BufferRising
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$CLK_I_BufferFalling
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$CLK_I_BufferRisingFalling
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
MSB     0
CORGROUP        $$CLK_I_BufferRising
LSB     0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   True
DrawAnalog      0
CORGROUP        $$CLK_I_BufferFalling
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$CLK_I_BufferRisingFalling
VerilogCode
Percent 100
VHDLCode
!
PROPS!
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
SIGNAL  dwb_ADR_O
!
DIRECTION       output
RADIX   hex
CORGROUP        $$CLK_I_BufferFalling
GRID    0        1       0        1       0        16711680        0        0
Percent 100
ENDGRID -1
!
Clock
EdgeLevel       neg
CORGROUP        $$CLK_I_BufferRisingFalling
Set     Not Used
Percent 100
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CORGROUP        $$CLK_I_BufferRising
AsyncSetClear   True
Percent 100
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
CORGROUP        $$CLK_I_BufferFalling
SystemCType     sc_logic
Percent 100
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
CORGROUP        $$CLK_I_BufferRisingFalling
LowVoltageThreshold     0
Percent 100
LSB     0
!
MSB     31
SignalActionType        0
CORGROUP        $$CLK_I_BufferRising
isFallingEdgeSensitive  False
Percent 100
isRisingEdgeSensitive   True
!
DrawAnalog      0
BooleanEquation
CORGROUP        $$CLK_I_BufferFalling
NegTolerance    0
Percent 100
PosTolerance    0
!
UserSpecifiedSizeRatio  1
VerilogCode
CORGROUP        $$CLK_I_BufferRisingFalling
VHDLCode
Percent 100
VhdlMapping     DefaultVhdlMapping
!
PROPS!
E0      V       -1      -1              1       0        DR      0
CORGROUP        $$CLK_I_BufferRising
E1      X       3123    3123            1       0        DR      0
Percent 100
E2      V       13125   13125     A0    1       0        DR      0
!
E3      X       13625   13625           1       0        DR      0
E4      V       23125   23125     A4    1       0        DR      0
CORGROUP        $$CLK_I_BufferFalling
E5      X       23625   23625           1       0        DR      0
Percent 100
E6      V       33125   33125     A8    1       0        DR      0
!
E7      X       33625   33625           1       0        DR      0
E8      V       43125   43125     A12   1       0        DR      0
CORGROUP        $$CLK_I_BufferRisingFalling
E9      X       43750   43750           1       0        DR      0
Percent 100
E10     V       53125   53125    A0     1       0        DR      0
!
E11     X       53750   53750           1       0        DR      0
!
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
SIGNAL  dwb_DAT_I
!
DIRECTION       input
RADIX   hex
CORGROUP        $$CLK_RISC_BufferFalling
GRID    0        1       0        1       0        16711680        0        0
Percent 100
ENDGRID -1
!
Clock
EdgeLevel       neg
CORGROUP        $$CLK_RISC_BufferRisingFalling
Set     Not Used
Percent 100
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CORGROUP        $$CLK_RISC_BufferRising
AsyncSetClear   True
Percent 100
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
CORGROUP        $$CLK_RISC_BufferFalling
SystemCType     sc_logic
Percent 100
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
CORGROUP        $$CLK_RISC_BufferRisingFalling
LowVoltageThreshold     0
Percent 100
LSB     0
!
MSB     31
SignalActionType        0
CORGROUP        $$CLK_I_BufferRising
isFallingEdgeSensitive  False
Percent 100
isRisingEdgeSensitive   False
!
DrawAnalog      0
BooleanEquation
CORGROUP        $$CLK_I_BufferFalling
NegTolerance    0
Percent 100
PosTolerance    0
!
UserSpecifiedSizeRatio  1
VerilogCode
CORGROUP        $$CLK_I_BufferRisingFalling
VHDLCode
Percent 100
VhdlMapping     DefaultVhdlMapping
!
PROPS!
E0      X       11250   11250           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRising
E1      V       13125   13125   D0      1       0        DR      0
Percent 100
E2      X       21250   21250           1       0        DR      0
!
E3      V       23125   23125   D4      1       0        DR      0
E4      X       31250   31250           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferFalling
E5      V       33125   33125   D8      1       0        DR      0
Percent 100
E6      X       41250   41250           1       0        DR      0
!
E7      V       43125   43125   D12     1       0        DR      0
E8      X       53750   53750           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRisingFalling
!
Percent 100
!
SIGNAL  dwb_DAT_O
DIRECTION       output
CORGROUP        $$CLK_I_BufferRising
RADIX   hex
Percent 100
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock   Unclocked
CORGROUP        $$CLK_I_BufferFalling
EdgeLevel       neg
Percent 100
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
CORGROUP        $$CLK_I_BufferRisingFalling
ActiveLowSetClear       True
Percent 100
AsyncSetClear   True
!
ActiveLowClockEnable    True
VhdlType        std_logic
CORGROUP        $$CLK_RISC_BufferRising
VerilogType     wire
Percent 100
SystemCType     sc_logic
!
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
CORGROUP        $$CLK_RISC_BufferFalling
HighVoltageThreshold    5
Percent 100
LowVoltageThreshold     0
!
LSB     0
MSB     31
CORGROUP        $$CLK_RISC_BufferRisingFalling
SignalActionType        0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   False
DrawAnalog      0
CORGROUP        $$CLK_I_BufferRising
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$CLK_I_BufferFalling
VerilogCode
Percent 100
VHDLCode
!
PROPS!
E0      X       3125    3125            1       0        DR      0
CORGROUP        $$CLK_I_BufferRisingFalling
E1      V       3126    3126    D0      1       0        DR      0
Percent 100
E2      X       43125   43125           1       0        DR      0
!
E3      V       53124   53124     D0    1       0        DR      0
E4      X       53750   53750           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRising
!
Percent 100
!
SIGNAL  dwb_WE_O
DIRECTION       output
CORGROUP        $$CLK_RISC_BufferFalling
RADIX   hex
Percent 100
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock   Unclocked
CORGROUP        $$CLK_RISC_BufferRisingFalling
EdgeLevel       neg
Percent 100
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
CORGROUP        $$CLK_I_BufferRising
ActiveLowSetClear       True
Percent 100
AsyncSetClear   True
!
ActiveLowClockEnable    True
VhdlType        std_logic
CORGROUP        $$CLK_I_BufferFalling
VerilogType     wire
Percent 100
SystemCType     sc_logic
!
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
CORGROUP        $$CLK_I_BufferRisingFalling
HighVoltageThreshold    5
Percent 100
LowVoltageThreshold     0
!
SignalActionType        0
MSB     0
CORGROUP        $$CLK_RISC_BufferRising
LSB     0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   False
DrawAnalog      0
CORGROUP        $$CLK_RISC_BufferFalling
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$CLK_RISC_BufferRisingFalling
VerilogCode
Percent 100
VHDLCode
!
PROPS!
E0      X       3126    3126            1       0        DR      0
CORGROUP        $$CLK_I_BufferRising
E1      0        13125   13125           1       0        DR      0
Percent 100
E2      X       13625   13625           1       0        DR      0
!
E3      0        23125   23125           1       0        DR      0
E4      X       23625   23625           1       0        DR      0
CORGROUP        $$CLK_I_BufferFalling
E5      0        33125   33125           1       0        DR      0
Percent 100
E6      X       33750   33750           1       0        DR      0
!
E7      0        43125   43125           1       0        DR      0
E8      1       53125   53125           1       0        DR      0
CORGROUP        $$CLK_I_BufferRisingFalling
E9      0        53750   53750           1       0        DR      0
Percent 100
!
!
SIGNAL  dwb_SEL_O
CORGROUP        $$CLK_RISC_BufferRising
DIRECTION       output
Percent 100
RADIX   hex
!
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
CORGROUP        $$CLK_RISC_BufferFalling
Clock   Unclocked
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$CLK_RISC_BufferRisingFalling
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$CLK_I_BufferRising
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$CLK_I_BufferFalling
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
LSB     0
CORGROUP        $$CLK_I_BufferRisingFalling
MSB     3
Percent 100
SignalActionType        0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
CORGROUP        $$CLK_RISC_BufferRising
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$CLK_RISC_BufferFalling
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
PROPS!
CORGROUP        $$CLK_RISC_BufferRisingFalling
E0      X       3123    3123            1       0        DR      0
Percent 100
E1      V       13125   13125       Valid       1       0        DR      0
!
E2      X       13625   13625           1       0        DR      0
E3      V       23125   23125     Valid 1       0        DR      0
CORGROUP        $$CLK_I_BufferRising
E4      X       23625   23625           1       0        DR      0
Percent 100
E5      V       33125   33125     Valid 1       0        DR      0
!
E6      X       33625   33625           1       0        DR      0
E7      V       43125   43125     Valid 1       0        DR      0
CORGROUP        $$CLK_I_BufferFalling
E8      X       43750   43750           1       0        DR      0
Percent 100
E9      V       53124   53124      Valid        1       0        DR      0
!
E10     X       53750   53750           1       0        DR      0
!
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
SIGNAL  dwb_STB_O
!
DIRECTION       output
RADIX   hex
CORGROUP        $$CLK_RISC_BufferRising
GRID    0        1       0        1       0        16711680        0        0
Percent 100
ENDGRID -1
!
Clock   Unclocked
EdgeLevel       neg
CORGROUP        $$CLK_RISC_BufferFalling
Set     Not Used
Percent 100
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CORGROUP        $$CLK_RISC_BufferRisingFalling
AsyncSetClear   True
Percent 100
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
CORGROUP        $$CLK_I_BufferRising
SystemCType     sc_logic
Percent 100
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
CORGROUP        $$CLK_I_BufferFalling
LowVoltageThreshold     0
Percent 100
SignalActionType        0
!
MSB     0
LSB     0
CORGROUP        $$CLK_I_BufferRisingFalling
isFallingEdgeSensitive  False
Percent 100
isRisingEdgeSensitive   False
!
DrawAnalog      0
BooleanEquation
CORGROUP        $$CLK_RISC_BufferRising
NegTolerance    0
Percent 100
PosTolerance    0
!
UserSpecifiedSizeRatio  1
VerilogCode
CORGROUP        $$CLK_RISC_BufferFalling
VHDLCode
Percent 100
PROPS!
!
E0      0        3750    3750            1       0        DR      0
E1      1       13125   13125           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRisingFalling
E2      0        13625   13625           1       0        DR      0
Percent 100
E3      1       23125   23125           1       0        DR      0
!
E4      0        23625   23625           1       0        DR      0
E5      1       33125   33125           1       0        DR      0
CORGROUP        $$CLK_I_BufferRising
E6      0        33625   33625           1       0        DR      0
Percent 100
E7      1       43124   43124           1       0        DR      0
!
E8      0        44466   44466           1       0        DR      0
E9      1       53124   53124           1       0        DR      0
CORGROUP        $$CLK_I_BufferFalling
E10     X       53750   53750           1       0        DR      0
Percent 100
!
!
SIGNAL  dwb_ACK_I
CORGROUP        $$CLK_I_BufferRisingFalling
DIRECTION       input
Percent 100
RADIX   hex
!
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
CORGROUP        $$CLK_RISC_BufferRising
Clock   Unclocked
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$CLK_RISC_BufferFalling
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$CLK_RISC_BufferRisingFalling
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$CLK_I_BufferRising
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
SignalActionType        0
CORGROUP        $$CLK_I_BufferFalling
MSB     0
Percent 100
LSB     0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
CORGROUP        $$CLK_I_BufferRisingFalling
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$CLK_RISC_BufferRising
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
PROPS!
CORGROUP        $$CLK_RISC_BufferFalling
E0      0        11250   11250           1       0        DR      0
Percent 100
E1      1       13125   13125           1       0        DR      0
!
E2      0        21250   21250           1       0        DR      0
E3      1       23125   23125           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRisingFalling
E4      0        31250   31250           1       0        DR      0
Percent 100
E5      1       33125   33125           1       0        DR      0
!
E6      0        41250   41250           1       0        DR      0
E7      1       43124   43124           1       0        DR      0
CORGROUP        $$CLK_I_BufferRising
E8      0        51875   51875           1       0        DR      0
Percent 100
E9      1       53124   53124           1       0        DR      0
!
E10     X       53750   53750           1       0        DR      0
!
CORGROUP        $$CLK_I_BufferFalling
Percent 100
SIGNAL  dwb_CYC_O
!
DIRECTION       output
RADIX   hex
CORGROUP        $$CLK_I_BufferRisingFalling
GRID    0        1       0        1       0        16711680        0        0
Percent 100
ENDGRID -1
!
Clock   Unclocked
EdgeLevel       neg
CORGROUP        $$dwb_CLK_RISC_BufferRising
Set     Not Used
Percent 100
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CORGROUP        $$dwb_CLK_RISC_BufferFalling
AsyncSetClear   True
Percent 100
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
SystemCType     sc_logic
Percent 100
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
CORGROUP        $$dwb_CLK_I_BufferRising
LowVoltageThreshold     0
Percent 100
SignalActionType        0
!
MSB     0
LSB     0
CORGROUP        $$dwb_CLK_I_BufferFalling
isFallingEdgeSensitive  False
Percent 100
isRisingEdgeSensitive   False
!
DrawAnalog      0
BooleanEquation
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
NegTolerance    0
Percent 100
PosTolerance    0
!
UserSpecifiedSizeRatio  1
VerilogCode
CORGROUP        $$dwb_CLK_RISC_BufferRising
VHDLCode
Percent 100
PROPS!
!
E0      0        3125    3125            1       0        DR      0
E1      1       43125   43125           1       0        DR      0
CORGROUP        $$dwb_CLK_RISC_BufferFalling
E2      0        44375   44375           1       0        DR      0
Percent 100
E3      1       53125   53125           1       0        DR      0
!
E4      0        53750   53750           1       0        DR      0
!
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
Percent 100
SIGNAL  dwb_ERR_I
!
DIRECTION       input
RADIX   hex
CORGROUP        $$dwb_CLK_I_BufferRising
GRID    0        1       0        1       0        16711680        0        0
Percent 100
ENDGRID -1
!
Clock   Unclocked
EdgeLevel       neg
CORGROUP        $$dwb_CLK_I_BufferFalling
Set     Not Used
Percent 100
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
AsyncSetClear   True
Percent 100
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
CORGROUP        $$dwb_CLK_RISC_BufferRising
SystemCType     sc_logic
Percent 100
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
CORGROUP        $$dwb_CLK_RISC_BufferFalling
LowVoltageThreshold     0
Percent 100
SignalActionType        0
!
MSB     0
LSB     0
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
isFallingEdgeSensitive  False
Percent 100
isRisingEdgeSensitive   False
!
DrawAnalog      0
BooleanEquation
CORGROUP        $$dwb_CLK_I_BufferRising
NegTolerance    0
Percent 100
PosTolerance    0
!
UserSpecifiedSizeRatio  1
VerilogCode
CORGROUP        $$dwb_CLK_I_BufferFalling
VHDLCode
Percent 100
PROPS!
!
E0      0        53125   53125           1       0        DR      0
E1      X       53750   53750           1       0        DR      0
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
!
Percent 100
!
SIGNAL  dwb_RTY_I
DIRECTION       input
CORGROUP        $$dwb_CLK_RISC_BufferRising
RADIX   hex
Percent 100
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock   Unclocked
CORGROUP        $$dwb_CLK_RISC_BufferFalling
EdgeLevel       neg
Percent 100
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
ActiveLowSetClear       True
Percent 100
AsyncSetClear   True
!
ActiveLowClockEnable    True
VhdlType        std_logic
CORGROUP        $$dwb_CLK_I_BufferRising
VerilogType     wire
Percent 100
SystemCType     sc_logic
!
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
CORGROUP        $$dwb_CLK_I_BufferFalling
HighVoltageThreshold    5
Percent 100
LowVoltageThreshold     0
!
SignalActionType        0
MSB     0
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
LSB     0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   False
DrawAnalog      0
CORGROUP        $$dwb_CLK_RISC_BufferRising
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$dwb_CLK_RISC_BufferFalling
VerilogCode
Percent 100
VHDLCode
!
PROPS!
E0      0        53125   53125           1       0        DR      0
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
E1      X       53750   53750           1       0        DR      0
Percent 100
!
!
MARKER  MARK1
CORGROUP        $$dwb_CLK_I_BufferRising
ATTACH  dwb_SEL_O       NULL    S6
Percent 100
TIME    17500.000000
!
RELATIVETIME    0.000000
DISPLAYAS       5
CORGROUP        $$dwb_CLK_I_BufferFalling
MARKERTYPE      Timebreak(Curved)
Percent 100
WHILERETURN
!
REPEATNUMBER
SNAPTO  0
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
COMPRESSTIME    0.000000
Percent 100
COMMENT
!
!
CORGROUP        $$CLK_RISC_BufferRising
MARKER  MARK2
Percent 100
ATTACH  dwb_STB_O       NULL    S7
!
TIME    27500.000000
RELATIVETIME    0.000000
CORGROUP        $$CLK_RISC_BufferFalling
DISPLAYAS       5
Percent 100
MARKERTYPE      Timebreak(Curved)
!
WHILERETURN
REPEATNUMBER
CORGROUP        $$CLK_RISC_BufferRisingFalling
SNAPTO  0
Percent 100
COMPRESSTIME    0.000000
!
COMMENT
!
CORGROUP        $$dwb_CLK_I_BufferRising
Percent 100
MARKER  MARK3
!
ATTACH  dwb_STB_O       NULL    S7
TIME    37500.000000
CORGROUP        $$dwb_CLK_I_BufferFalling
RELATIVETIME    0.000000
Percent 100
DISPLAYAS       5
!
MARKERTYPE      Timebreak(Curved)
WHILERETURN
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
REPEATNUMBER
Percent 100
SNAPTO  0
!
COMPRESSTIME    0.000000
COMMENT
CLOCK   CLK_RISC
!
PERIODE 2.5
DUTY    50
MARKER  MARK0
OFFSETE 0
ATTACH  dwb_CLK_I       NULL    S1
INITIAL HIGH
TIME    7500.000000
MAXUNCERTRISE   0
RELATIVETIME    0.000000
MAXUNCERTFALL   0
DISPLAYAS       5
MINUNCERTRISE   0
MARKERTYPE      Timebreak(Curved)
MINUNCERTFALL   0
WHILERETURN
JRISEE  0
REPEATNUMBER
JFALLE  0
SNAPTO  0
GRID    0        1       0        2       0        16711680        0        0
COMPRESSTIME    0.000000
ENDGRID -1
COMMENT
DIRECTION       internal
!
MASTERCLOCK     None
Clock   Unclocked
MARKER  MARK4
EdgeLevel       neg
ATTACH  dwb_ADR_O       NULL    S2
Set     Not Used
TIME    47500.000000
Clear   Not Used
RELATIVETIME    0.000000
ClockEnable     Not Used
DISPLAYAS       5
ActiveLowSetClear       True
MARKERTYPE      Timebreak(Curved)
AsyncSetClear   True
WHILERETURN
ActiveLowClockEnable    True
REPEATNUMBER
VhdlType        std_logic
SNAPTO  0
VerilogType     wire
COMPRESSTIME    0.000000
SystemCType     sc_logic
COMMENT
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
Timing Diagram Editor v7.1g - Output File
LowVoltageThreshold     0
MSB     0
PROJECT
LSB     0
BaseTimeUnit    1
isFallingEdgeSensitive  False
DisplayTimeUnit 2
isRisingEdgeSensitive   False
TextGridX       625.000000
DrawAnalog      0
TextGridY       6
BooleanEquation
EdgeGridX       625.000000
NegTolerance    0
ImportStartTime 0.000000
PosTolerance    0
ImportEndTime   281474976710656.000000
UserSpecifiedSizeRatio  1
TimePerPixel    50.000000
VerilogCode
Visible DELAYS  SETUPS  HOLDS   SAMPLES TEXT    HIDDENATTACHMENTS       CRITICALPATHS   GRIDLINES       UNCERTAINTY
VHDLCode
ColWidths       144,216,288,423,488
PROPS!
ScrollPos       0.000000,0.000000,0.000000
!
DefDelayRule    1
NoEventOverlap  NO
CLOCK   dwb_CLK_I
SigLabelFontHeight      10
PERIODE 5
LabelHeight     12
DUTY    50
LoadLibsToMem   1
OFFSETE 0
UseFullPathNames        1
INITIAL LOW
LibPath
MAXUNCERTRISE   0
EntireTime      YES
MAXUNCERTFALL   0
PrintTimeSpecified      NO
MINUNCERTRISE   0
FromTime        0
MINUNCERTFALL   0
ToTime  43.75
JRISEE  0
AllSignals      YES
JFALLE  0
CurrSelSigs     NO
GRID    1       1       1       2       2       16711680        0        0
PrintTo 2
ENDGRID -1
PrintFileName   C:\DOCS\wb_readblock_typ.wmf
DIRECTION       input
PreviewInterchange      YES
MASTERCLOCK     None
PreviewTIFF5    NO
Clock   Unclocked
UseMargins      NO
EdgeLevel       neg
PrintTimeLine   NO
Set     Not Used
PrintBorderBox  YES
Clear   Not Used
PrintSigNames   YES
ClockEnable     Not Used
PrintSigNamesOnEachPage YES
ActiveLowSetClear       True
AddPreviewToEPS NO
AsyncSetClear   True
PreviewRes      150
ActiveLowClockEnable    True
MarginLR        1.25
VhdlType        std_logic
MifImageWidth   6.00
VerilogType     wire
MarginTB        Auto
SystemCType     sc_logic
Header  %d %t;%f;%p
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Footer
StateEquation   Hex(Inc(0,2,5))
ScaleHorz       100
HighVoltageThreshold    5
ScaleVert       100
LowVoltageThreshold     0
ScaleHPage      1
MSB     0
PrintImage      DIAGRAM
LSB     0
DefaultTimingModel      minmax
isFallingEdgeSensitive  False
DefaultClock    Unclocked
isRisingEdgeSensitive   True
DefaultEdgeLevel        neg
DrawAnalog      0
DefaultSet      Not Used
BooleanEquation
DefaultClear    Not Used
NegTolerance    0
DefaultClockEnable      Not Used
PosTolerance    0
DefaultClockToOutLH     0
UserSpecifiedSizeRatio  1
DefaultClockToOutHL     0
VerilogCode
DefaultSetup    0
VHDLCode
DefaultHold     0
PROPS!
DefaultRegStartupState  unknown
!
DefaultPodSize  8
DefaultActiveLowSetClear        True
SIGNAL  dwb_ADR_O
DefaultAsyncSetClear    True
DIRECTION       output
DefaultActiveLowClockEnable     True
RADIX   hex
SigLabelFontHeight      10
GRID    0        1       0        1       0        16711680        0        0
PROPS!
ENDGRID -1
!
Clock
EdgeLevel       neg
STYLE
Set     Not Used
DefaultFont     USER    {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
Clear   Not Used
DrawWndFont     DEFAULT
ClockEnable     Not Used
DrawWndColor    DEFAULT
ActiveLowSetClear       True
GridWndFont     DEFAULT
AsyncSetClear   True
GridWndColor    DEFAULT
ActiveLowClockEnable    True
LabelWndFont    USER    {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
VhdlType        std_logic
LabelWndColor   DEFAULT
VerilogType     wire
ParamDispPref   0
SystemCType     sc_logic
ParamWndCellDisplay     0
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CustDispString  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
StateEquation   Hex(Inc(0,2,5))
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
HighVoltageThreshold    5
MarkerDispPref  4
LowVoltageThreshold     0
MarkerCustDispString    %n v=%mv,%Mv d=%md %t
LSB     0
MarkerCustomDisplayStringRTF    {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
MSB     31
SignalColor     2
SignalActionType        0
LabelOffset     2
isFallingEdgeSensitive  False
BusDisplay      0
isRisingEdgeSensitive   True
WaveFormWidth   0.500000
DrawAnalog      0
WaveFormColor   0
BooleanEquation
InputWaveFormColor      16711680
NegTolerance    0
SlantedEdges    1
PosTolerance    0
SlantAngle      75
UserSpecifiedSizeRatio  1
RightJustifySigNames    1
VerilogCode
AutosplitEnabled        1
VHDLCode
AutosplitChar   _
VhdlMapping     DefaultVhdlMapping
DynamSizedSignals       1
PROPS!
!
E0      V       -1      -1              1       0        DR      0
E1      X       3125    3125            1       0        DR      0
DIAGRAMTESTBENCHSETTINGS
E2      V       3126    3126    A0      1       0        DR      0
FilesBeforeDiagramModel
E3      X       3750    3750            1       0        DR      0
FilesInsideDiagramModelDeclarationSection
E4      V       13125   13125     A0    1       0        DR      0
AbortHdlCodeEnabled     1
E5      X       13625   13625           1       0        DR      0
DelayHdlCodeEnabled     1
E6      V       23125   23125     A4    1       0        DR      0
SampleHdlCodeEnabled    1
E7      X       23625   23625           1       0        DR      0
MarkerHdlCodeEnabled    1
E8      V       33125   33125     A8    1       0        DR      0
VerboseSamples  0
E9      X       33625   33625           1       0        DR      0
VerboseDelays   0
E10     V       43125   43125     A12   1       0        DR      0
VerboseFileInput        0
E11     X       43750   43750           1       0        DR      0
VerboseSequenceVerification     0
!
IncludeDelayTime        1
ExecuteFromTopLevel     1
SIGNAL  dwb_DAT_I
TimeOutInDiagramLengths 0
DIRECTION       input
DefaultCycleClock       Unclocked
RADIX   hex
DefaultCycleEdge        neg
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock
MACROS
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$CLK_I_BufferRising
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$CLK_I_BufferFalling
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$CLK_I_BufferRisingFalling
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
LSB     0
CORGROUP        $$CLK_I_BufferRising
MSB     31
Percent 100
SignalActionType        0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
CORGROUP        $$CLK_I_BufferFalling
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$CLK_I_BufferRisingFalling
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
VhdlMapping     DefaultVhdlMapping
CORGROUP        $$CLK_I_BufferRising
PROPS!
Percent 100
E0      X       11250   11250           1       0        DR      0
!
E1      V       13125   13125   D0      1       0        DR      0
E2      X       21250   21250           1       0        DR      0
CORGROUP        $$CLK_I_BufferFalling
E3      V       23125   23125   D4      1       0        DR      0
Percent 100
E4      X       31250   31250           1       0        DR      0
!
E5      V       33125   33125   D8      1       0        DR      0
E6      X       41250   41250           1       0        DR      0
CORGROUP        $$CLK_I_BufferRisingFalling
E7      V       43125   43125   D12     1       0        DR      0
Percent 100
E8      X       43750   43750           1       0        DR      0
!
!
CORGROUP        $$CLK_I_BufferRising
SIGNAL  dwb_DAT_O
Percent 100
DIRECTION       output
!
RADIX   hex
GRID    0        1       0        1       0        16711680        0        0
CORGROUP        $$CLK_I_BufferFalling
ENDGRID -1
Percent 100
Clock   Unclocked
!
EdgeLevel       neg
Set     Not Used
CORGROUP        $$CLK_I_BufferRisingFalling
Clear   Not Used
Percent 100
ClockEnable     Not Used
!
ActiveLowSetClear       True
AsyncSetClear   True
CORGROUP        $$CLK_I_BufferRising
ActiveLowClockEnable    True
Percent 100
VhdlType        std_logic
!
VerilogType     wire
SystemCType     sc_logic
CORGROUP        $$CLK_I_BufferFalling
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Percent 100
StateEquation   Hex(Inc(0,2,5))
!
HighVoltageThreshold    5
LowVoltageThreshold     0
CORGROUP        $$CLK_I_BufferRisingFalling
LSB     0
Percent 100
MSB     31
!
SignalActionType        0
isFallingEdgeSensitive  False
CORGROUP        $$CLK_I_BufferRising
isRisingEdgeSensitive   False
Percent 100
DrawAnalog      0
!
BooleanEquation
NegTolerance    0
CORGROUP        $$CLK_I_BufferFalling
PosTolerance    0
Percent 100
UserSpecifiedSizeRatio  1
!
VerilogCode
VHDLCode
CORGROUP        $$CLK_I_BufferRisingFalling
PROPS!
Percent 100
E0      X       43750   43750           1       0        DR      0
!
!
CORGROUP        $$CLK_RISC_BufferRising
SIGNAL  dwb_WE_O
Percent 100
DIRECTION       output
!
RADIX   hex
GRID    0        1       0        1       0        16711680        0        0
CORGROUP        $$CLK_RISC_BufferFalling
ENDGRID -1
Percent 100
Clock   Unclocked
!
EdgeLevel       neg
Set     Not Used
CORGROUP        $$CLK_RISC_BufferRisingFalling
Clear   Not Used
Percent 100
ClockEnable     Not Used
!
ActiveLowSetClear       True
AsyncSetClear   True
CORGROUP        $$CLK_RISC_BufferRising
ActiveLowClockEnable    True
Percent 100
VhdlType        std_logic
!
VerilogType     wire
SystemCType     sc_logic
CORGROUP        $$CLK_RISC_BufferFalling
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Percent 100
StateEquation   Hex(Inc(0,2,5))
!
HighVoltageThreshold    5
LowVoltageThreshold     0
CORGROUP        $$CLK_RISC_BufferRisingFalling
SignalActionType        0
Percent 100
MSB     0
!
LSB     0
isFallingEdgeSensitive  False
CORGROUP        $$CLK_I_BufferRising
isRisingEdgeSensitive   False
Percent 100
DrawAnalog      0
!
BooleanEquation
NegTolerance    0
CORGROUP        $$CLK_I_BufferFalling
PosTolerance    0
Percent 100
UserSpecifiedSizeRatio  1
!
VerilogCode
VHDLCode
CORGROUP        $$CLK_I_BufferRisingFalling
PROPS!
Percent 100
E0      X       3125    3125            1       0        DR      0
!
E1      1       3126    3126            1       0        DR      0
E2      0        13125   13125           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRising
E3      X       13625   13625           1       0        DR      0
Percent 100
E4      0        23125   23125           1       0        DR      0
!
E5      X       23625   23625           1       0        DR      0
E6      0        33125   33125           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferFalling
E7      X       33625   33625           1       0        DR      0
Percent 100
E8      0        43125   43125           1       0        DR      0
!
E9      X       43625   43625           1       0        DR      0
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
SIGNAL  dwb_SEL_O
!
DIRECTION       output
RADIX   hex
CORGROUP        $$CLK_I_BufferRising
GRID    0        1       0        1       0        16711680        0        0
Percent 100
ENDGRID -1
!
Clock   Unclocked
EdgeLevel       neg
CORGROUP        $$CLK_I_BufferFalling
Set     Not Used
Percent 100
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CORGROUP        $$CLK_I_BufferRisingFalling
AsyncSetClear   True
Percent 100
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
CORGROUP        $$CLK_RISC_BufferRising
SystemCType     sc_logic
Percent 100
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
CORGROUP        $$CLK_RISC_BufferFalling
LowVoltageThreshold     0
Percent 100
LSB     0
!
MSB     3
SignalActionType        0
CORGROUP        $$CLK_RISC_BufferRisingFalling
isFallingEdgeSensitive  False
Percent 100
isRisingEdgeSensitive   False
!
DrawAnalog      0
BooleanEquation
CORGROUP        $$CLK_I_BufferRising
NegTolerance    0
Percent 100
PosTolerance    0
!
UserSpecifiedSizeRatio  1
VerilogCode
CORGROUP        $$CLK_I_BufferFalling
VHDLCode
Percent 100
PROPS!
!
E0      V       0        0           Valid        1       0        DR      0
E1      X       3750    3750            1       0        DR      0
CORGROUP        $$CLK_I_BufferRisingFalling
E2      V       13125   13125       Valid       1       0        DR      0
Percent 100
E3      X       13625   13625           1       0        DR      0
!
E4      V       23125   23125     Valid 1       0        DR      0
E5      X       23625   23625           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRising
E6      V       33125   33125     Valid 1       0        DR      0
Percent 100
E7      X       33625   33625           1       0        DR      0
!
E8      V       43125   43125     Valid 1       0        DR      0
E9      X       43750   43750           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferFalling
!
Percent 100
!
SIGNAL  dwb_STB_O
DIRECTION       output
CORGROUP        $$CLK_RISC_BufferRisingFalling
RADIX   hex
Percent 100
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock   Unclocked
CORGROUP        $$CLK_I_BufferRising
EdgeLevel       neg
Percent 100
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
CORGROUP        $$CLK_I_BufferFalling
ActiveLowSetClear       True
Percent 100
AsyncSetClear   True
!
ActiveLowClockEnable    True
VhdlType        std_logic
CORGROUP        $$CLK_I_BufferRisingFalling
VerilogType     wire
Percent 100
SystemCType     sc_logic
!
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
CORGROUP        $$CLK_RISC_BufferRising
HighVoltageThreshold    5
Percent 100
LowVoltageThreshold     0
!
SignalActionType        0
MSB     0
CORGROUP        $$CLK_RISC_BufferFalling
LSB     0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   False
DrawAnalog      0
CORGROUP        $$CLK_RISC_BufferRisingFalling
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$CLK_I_BufferRising
VerilogCode
Percent 100
VHDLCode
!
PROPS!
E0      0        3750    3750            1       0        DR      0
CORGROUP        $$CLK_I_BufferFalling
E1      1       13125   13125           1       0        DR      0
Percent 100
E2      0        13625   13625           1       0        DR      0
!
E3      1       23125   23125           1       0        DR      0
E4      0        23625   23625           1       0        DR      0
CORGROUP        $$CLK_I_BufferRisingFalling
E5      1       33125   33125           1       0        DR      0
Percent 100
E6      0        33625   33625           1       0        DR      0
!
E7      1       43125   43125           1       0        DR      0
E8      X       43750   43750           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRising
!
Percent 100
!
SIGNAL  dwb_ACK_I
DIRECTION       input
CORGROUP        $$CLK_RISC_BufferFalling
RADIX   hex
Percent 100
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock   Unclocked
CORGROUP        $$CLK_RISC_BufferRisingFalling
EdgeLevel       neg
Percent 100
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
CORGROUP        $$CLK_I_BufferRising
ActiveLowSetClear       True
Percent 100
AsyncSetClear   True
!
ActiveLowClockEnable    True
VhdlType        std_logic
CORGROUP        $$CLK_I_BufferFalling
VerilogType     wire
Percent 100
SystemCType     sc_logic
!
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
CORGROUP        $$CLK_I_BufferRisingFalling
HighVoltageThreshold    5
Percent 100
LowVoltageThreshold     0
!
SignalActionType        0
MSB     0
CORGROUP        $$CLK_RISC_BufferRising
LSB     0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   False
DrawAnalog      0
CORGROUP        $$CLK_RISC_BufferFalling
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$CLK_RISC_BufferRisingFalling
VerilogCode
Percent 100
VHDLCode
!
PROPS!
E0      0        11250   11250           1       0        DR      0
CORGROUP        $$CLK_I_BufferRising
E1      1       13125   13125           1       0        DR      0
Percent 100
E2      0        21250   21250           1       0        DR      0
!
E3      1       23125   23125           1       0        DR      0
E4      0        31250   31250           1       0        DR      0
CORGROUP        $$CLK_I_BufferFalling
E5      1       33125   33125           1       0        DR      0
Percent 100
E6      0        41250   41250           1       0        DR      0
!
E7      1       43125   43125           1       0        DR      0
E8      X       43750   43750           1       0        DR      0
CORGROUP        $$CLK_I_BufferRisingFalling
!
Percent 100
!
SIGNAL  dwb_CYC_O
DIRECTION       output
CORGROUP        $$CLK_RISC_BufferRising
RADIX   hex
Percent 100
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock   Unclocked
CORGROUP        $$CLK_RISC_BufferFalling
EdgeLevel       neg
Percent 100
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
CORGROUP        $$CLK_RISC_BufferRisingFalling
ActiveLowSetClear       True
Percent 100
AsyncSetClear   True
!
ActiveLowClockEnable    True
VhdlType        std_logic
CORGROUP        $$CLK_I_BufferRising
VerilogType     wire
Percent 100
SystemCType     sc_logic
!
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
CORGROUP        $$CLK_I_BufferFalling
HighVoltageThreshold    5
Percent 100
LowVoltageThreshold     0
!
SignalActionType        0
MSB     0
CORGROUP        $$CLK_I_BufferRisingFalling
LSB     0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   False
DrawAnalog      0
CORGROUP        $$CLK_RISC_BufferRising
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$CLK_RISC_BufferFalling
VerilogCode
Percent 100
VHDLCode
!
PROPS!
E0      0        3125    3125            1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRisingFalling
E1      1       43125   43125           1       0        DR      0
Percent 100
E2      0        43750   43750           1       0        DR      0
!
!
CORGROUP        $$CLK_I_BufferRising
SIGNAL  dwb_ERR_I
Percent 100
DIRECTION       input
!
RADIX   hex
GRID    0        1       0        1       0        16711680        0        0
CORGROUP        $$CLK_I_BufferFalling
ENDGRID -1
Percent 100
Clock   Unclocked
!
EdgeLevel       neg
Set     Not Used
CORGROUP        $$CLK_I_BufferRisingFalling
Clear   Not Used
Percent 100
ClockEnable     Not Used
!
ActiveLowSetClear       True
AsyncSetClear   True
CORGROUP        $$CLK_RISC_BufferRising
ActiveLowClockEnable    True
Percent 100
VhdlType        std_logic
!
VerilogType     wire
SystemCType     sc_logic
CORGROUP        $$CLK_RISC_BufferFalling
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Percent 100
StateEquation   Hex(Inc(0,2,5))
!
HighVoltageThreshold    5
LowVoltageThreshold     0
CORGROUP        $$CLK_RISC_BufferRisingFalling
SignalActionType        0
Percent 100
MSB     0
!
LSB     0
isFallingEdgeSensitive  False
CORGROUP        $$CLK_I_BufferRising
isRisingEdgeSensitive   False
Percent 100
DrawAnalog      0
!
BooleanEquation
NegTolerance    0
CORGROUP        $$CLK_I_BufferFalling
PosTolerance    0
Percent 100
UserSpecifiedSizeRatio  1
!
VerilogCode
VHDLCode
CORGROUP        $$CLK_I_BufferRisingFalling
PROPS!
Percent 100
E0      0        43125   43125           1       0        DR      0
!
E1      X       43750   43750           1       0        DR      0
!
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
SIGNAL  dwb_RTY_I
!
DIRECTION       input
RADIX   hex
CORGROUP        $$CLK_RISC_BufferFalling
GRID    0        1       0        1       0        16711680        0        0
Percent 100
ENDGRID -1
!
Clock   Unclocked
EdgeLevel       neg
CORGROUP        $$CLK_RISC_BufferRisingFalling
Set     Not Used
Percent 100
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CORGROUP        $$CLK_I_BufferRising
AsyncSetClear   True
Percent 100
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
CORGROUP        $$CLK_I_BufferFalling
SystemCType     sc_logic
Percent 100
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
CORGROUP        $$CLK_I_BufferRisingFalling
LowVoltageThreshold     0
Percent 100
SignalActionType        0
!
MSB     0
LSB     0
CORGROUP        $$dwb_CLK_RISC_BufferRising
isFallingEdgeSensitive  False
Percent 100
isRisingEdgeSensitive   False
!
DrawAnalog      0
BooleanEquation
CORGROUP        $$dwb_CLK_RISC_BufferFalling
NegTolerance    0
Percent 100
PosTolerance    0
!
UserSpecifiedSizeRatio  1
VerilogCode
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
VHDLCode
Percent 100
PROPS!
!
E0      0        43125   43125           1       0        DR      0
E1      X       43750   43750           1       0        DR      0
CORGROUP        $$dwb_CLK_I_BufferRising
!
Percent 100
!
MARKER  MARK1
ATTACH  dwb_SEL_O       NULL    S6
CORGROUP        $$dwb_CLK_I_BufferFalling
TIME    17500.000000
Percent 100
RELATIVETIME    0.000000
!
DISPLAYAS       5
MARKERTYPE      Timebreak(Curved)
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
WHILERETURN
Percent 100
REPEATNUMBER
!
SNAPTO  0
COMPRESSTIME    0.000000
CORGROUP        $$dwb_CLK_RISC_BufferRising
COMMENT
Percent 100
!
!
MARKER  MARK2
CORGROUP        $$dwb_CLK_RISC_BufferFalling
ATTACH  dwb_STB_O       NULL    S7
Percent 100
TIME    27500.000000
!
RELATIVETIME    0.000000
DISPLAYAS       5
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
MARKERTYPE      Timebreak(Curved)
Percent 100
WHILERETURN
!
REPEATNUMBER
SNAPTO  0
CORGROUP        $$dwb_CLK_I_BufferRising
COMPRESSTIME    0.000000
Percent 100
COMMENT
!
!
CORGROUP        $$dwb_CLK_I_BufferFalling
MARKER  MARK3
Percent 100
ATTACH  dwb_STB_O       NULL    S7
!
TIME    37500.000000
RELATIVETIME    0.000000
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
DISPLAYAS       5
Percent 100
MARKERTYPE      Timebreak(Curved)
!
WHILERETURN
REPEATNUMBER
CORGROUP        $$dwb_CLK_RISC_BufferRising
SNAPTO  0
Percent 100
COMPRESSTIME    0.000000
!
COMMENT
!
CORGROUP        $$dwb_CLK_RISC_BufferFalling
Percent 100
MARKER  MARK0
!
ATTACH  dwb_CLK_I       NULL    S1
TIME    7494.285714
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
RELATIVETIME    0.000000
Percent 100
DISPLAYAS       5
!
MARKERTYPE      Timebreak(Curved)
WHILERETURN
CORGROUP        $$dwb_CLK_I_BufferRising
REPEATNUMBER
Percent 100
SNAPTO  0
!
COMPRESSTIME    0.000000
COMMENT
CORGROUP        $$dwb_CLK_I_BufferFalling
!
Percent 100
!
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CORGROUP        $$dwb_CLK_I_BufferRisingFalling

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Percent 100

!

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CORGROUP        $$dwb_CLK_RISC_BufferRising
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Percent 100
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CORGROUP        $$dwb_CLK_RISC_BufferFalling
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Percent 100
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!
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CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
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Percent 100
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!
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CORGROUP        $$dwb_CLK_I_BufferRising
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Percent 100

!
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Percent 100
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!

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CORGROUP        $$dwb_CLK_I_BufferRisingFalling
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Percent 100
@kLTDSR0-0&%%V0!        $     $     $     %(%
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!
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CORGROUP        $$dwb_CLK_RISC_BufferRising
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Percent 100
@    kLTDRR000%
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!
     

CORGROUP        $$dwb_CLK_RISC_BufferFalling
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Percent 100
@
!
@LdBreakpoints, -%%"%%%"&%W$ &##%(g
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CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling

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Percent 100
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!
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CORGROUP        $$dwb_CLK_I_BufferRising
/1        "System!xx--%
Percent 100
HpH--C Arial-2
!

Breakpoints-%%"%%%"--$eoHe'eo--$$   $     $     --C Arial-2
CORGROUP        $$dwb_CLK_I_BufferFalling
v     DMR070-%
Percent 100

!
P---$---C Arial-2
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CORGROUP        $$dwb_CLK_I_BufferRisingFalling
k     DRR000---$ 
Percent 100

!
9     9     --C Arial?????????????????????????-2
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CORGROUP        $$CLK_RISC_BufferRising
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ѷ߉//߿)(9(TdE5E5E5Ŗ60v?O:??wavUa?!TaYaiUQa_"[n_b9oaeryavbq-
!
"kiF1"9v5GeOeUrtEgaeV Gqa28ebra0ƫʛPICSRioo(D['25U@R|dj/oooV-bpq\bbe?0v(~VE8-?DT!X?j?|??????r]&O9v*]FNOabǠ@_______To PFfa[mǯٯyTw?@rV+l.@Rdv`пIM|26*6]FMLDM\0߀Bߑfߒle/߭/////G t(x"E?W?'9I&fx*"=Ϭ&7'D?>&L7='V?OO_#_5_?Y_k_}_?QcuD$OIo    \k~b(:L^p@,fBv/"/4/F/X/j/|//@yQyf/V,FƷfwg"~fWw#}ga??????
OO.O@OROdOvOOOO OOOU!_3_E_+=OUUUo%o7oIo[omoooooğ@ƝFƺ%Z&ɧd-9K]o⏷ߘ_/ASZ_l_~__h_)@r8ӄ_!3EWi{DQӯأ-         qr(J'пU*8Ul4,Q֋/@t@
SIGNAL  dwb_ADR_O
@|9**A-3?7U2@$E*7CRH<(
DIRECTION       output
U2ET*7
RUlL\s(*@?%)R}D;U$
RADIX   hex
4(U1(UO"D&aU=QJf        )h"Ty+Uv'_Ʌ&aQ-
GRID    0        1       0        1       0        16711680        0        0
-H*9(TYgEQ/,GuideTheDocPage-1Gesture FormatBlock NormalVisio 10Block ShadowVisio 12Block HighltVisio 11ConnectorVisio 90Dot ConnectorConnector ArrowVisio 00Visio 01Visio 02Visio 03Visio 13Visio 20Visio 21Visio 22Visio 23Visio 50Visio 51Visio 52Visio 53Visio 70Visio 80_35+
ENDGRID -1
E-
Clock
G6_,$_U'c
<_4c
EdgeLevel       neg
UT_Eu
Set     Not Used
l_RcT_ju
Clear   Not Used
_wc_u
ClockEnable     Not Used
̪_cU_cU_u
ActiveLowSetClear       True
7u
AsyncSetClear   True
,%ܪu
ActiveLowClockEnable    True
D%u
VhdlType        std_logic
\%Zu
VerilogType     wire
t%-v  %Uq%q%U*q%7q%}Dq8QqU^q4kqULxqdq%A%&       0xRf!
SystemCType     sc_logic
EUjU        
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
U
UUUUl4,Q֋/@t@
StateEquation   Hex(Inc(0,2,5))
@.UC-H/AUl4,/
HighVoltageThreshold    5
AJ-37A_*<N@N/PRVg"q6uH<(
LowVoltageThreshold     0
H<(
LSB     0
_*<NE&0
RVg\"3q t>{
MSB     31
*   g"4pFX(_,9@(m@2Yy
SignalActionType        0
K_DO:]WR
isFallingEdgeSensitive  False
LQ|#u{&U]!BG?Q
> :B>Oko5Oĭ_$O'4*^N_/$+)0-1T==w=`22-fV?t8/FD$;@0P=
isRisingEdgeSensitive   True
OC     !_kG @Oh+'0@HhtValued Sony CustomerG<x/K  EMF4        XVISIODrawing
DrawAnalog      0
 &%%V0V>>V>V>%(%RL Arial%Td&<AA&LTICMR&%%V0VVV%(%RL Arial%T:AA
LhMask Function
BooleanEquation
NegTolerance    0

PosTolerance    0
UserSpecifiedSizeRatio  1
VerilogCode

VHDLCode
&%W$>>%(%%V,&%%V0zGzGGz%(&%%V0)ej))jeBe)%(&%%W$VV%(&%%W,)..).%(&%%W$GG%(&%%W$e..e..%(&%%W$%(%%V,%RL Arial%TJAA
VhdlMapping     DefaultVhdlMapping
L`INT [31:2] &%WX{rfYL?2'%(&%%WX{rfYL?2'%(&%%WX\~sib]\%(&%%WX\~sib^\%(&%%V0>>>>%(%RL Arial%Td&?<AA&LTICPR
&%W$)>))>)%(%%V,%..)%.&%%W$)\G\)\G\%(&%%W$G\GG\G%(%%V,BKKGBK&%%W$yzzy%(%%V,u~uy~u%RL Arial%Tl0AALXINT 0  &%W$jjjj%(%%V,fofjof%RL Arial%Tl}0AA}LXINT 1 &%W$LzLLzL%(%%V,yGQyGLyQyG%RL Arial%T_FnAA_LdLOWPRIO INT
PROPS!

      
E0      V       -1      -1              1       0        DR      0
     Tpo$~AAoLXEXCEPT            &%W$zz%(%%V,yyyy%
(%%TGAALdHIGHPRIO INT     
E1      X       3125    3125            1       0        DR      0
               
E2      V       3126    3126    A0      1       0        DR      0
     T:AA     L`EXCEPTION                
E3      X       3750    3750            1       0        DR      0
     ՜.+,D՜.+,@HP\ht
     PagesPage-18_VPID_ALTERNATENAMES^_VPID_PREVIEWS_PID_LINKBASE?     A
E4      V       13125   13125     A0    1       0        DR      0
Q<=KuyTiming DiagramTiming.Document.19qTiming Diagram
E5      X       13625   13625           1       0        DR      0
Q<=KuyTiming DiagramTiming.Document.19qTiming DiagramTiming Diagram Editor v7.1g - Output File
E6      V       23125   23125     A4    1       0        DR      0
E7      X       23625   23625           1       0        DR      0
PROJECT
E8      V       33125   33125     A8    1       0        DR      0
BaseTimeUnit    1
E9      X       33625   33625           1       0        DR      0
DisplayTimeUnit 2
E10     V       43125   43125     A12   1       0        DR      0
TextGridX       625.000000
E11     X       43750   43750           1       0        DR      0
TextGridY       6
!
EdgeGridX       625.000000
ImportStartTime 0.000000
SIGNAL  dwb_DAT_I
ImportEndTime   281474976710656.000000
DIRECTION       input
TimePerPixel    50.000000
RADIX   hex
Visible DELAYS  SETUPS  HOLDS   SAMPLES TEXT    HIDDENATTACHMENTS       CRITICALPATHS   GRIDLINES       UNCERTAINTY
GRID    0        1       0        1       0        16711680        0        0
ColWidths       144,216,288,423,488
ENDGRID -1
ScrollPos       0.000000,0.000000,0.000000
Clock
DefDelayRule    1
EdgeLevel       neg
NoEventOverlap  NO
Set     Not Used
SigLabelFontHeight      10
Clear   Not Used
LabelHeight     12
ClockEnable     Not Used
LoadLibsToMem   1
ActiveLowSetClear       True
UseFullPathNames        1
AsyncSetClear   True
LibPath
ActiveLowClockEnable    True
EntireTime      YES
VhdlType        std_logic
PrintTimeSpecified      NO
VerilogType     wire
FromTime        0
SystemCType     sc_logic
ToTime  43.75
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
AllSignals      YES
StateEquation   Hex(Inc(0,2,5))
CurrSelSigs     NO
HighVoltageThreshold    5
PrintTo 2
LowVoltageThreshold     0
PrintFileName   C:\DOCS\wb_fetchblock_typ.wmf
LSB     0
PreviewInterchange      YES
MSB     31
PreviewTIFF5    NO
SignalActionType        0
UseMargins      NO
isFallingEdgeSensitive  False
PrintTimeLine   NO
isRisingEdgeSensitive   False
PrintBorderBox  YES
DrawAnalog      0
PrintSigNames   YES
BooleanEquation
PrintSigNamesOnEachPage YES
NegTolerance    0
AddPreviewToEPS NO
PosTolerance    0
PreviewRes      150
UserSpecifiedSizeRatio  1
MarginLR        1.25
VerilogCode
MifImageWidth   6.00
VHDLCode
MarginTB        Auto
VhdlMapping     DefaultVhdlMapping
Header  %d %t;%f;%p
PROPS!
Footer
E0      X       11250   11250           1       0        DR      0
ScaleHorz       100
E1      V       13125   13125   D0      1       0        DR      0
ScaleVert       100
E2      X       21250   21250           1       0        DR      0
ScaleHPage      1
E3      V       23125   23125   D4      1       0        DR      0
PrintImage      DIAGRAM
E4      X       31250   31250           1       0        DR      0
DefaultTimingModel      minmax
E5      V       33125   33125   D8      1       0        DR      0
DefaultClock    Unclocked
E6      X       41250   41250           1       0        DR      0
DefaultEdgeLevel        neg
E7      V       43125   43125   D12     1       0        DR      0
DefaultSet      Not Used
E8      X       43750   43750           1       0        DR      0
DefaultClear    Not Used
!
DefaultClockEnable      Not Used
DefaultClockToOutLH     0
SIGNAL  dwb_DAT_O
DefaultClockToOutHL     0
DIRECTION       output
DefaultSetup    0
RADIX   hex
DefaultHold     0
GRID    0        1       0        1       0        16711680        0        0
DefaultRegStartupState  unknown
ENDGRID -1
DefaultPodSize  8
Clock   Unclocked
DefaultActiveLowSetClear        True
EdgeLevel       neg
DefaultAsyncSetClear    True
Set     Not Used
DefaultActiveLowClockEnable     True
Clear   Not Used
SigLabelFontHeight      10
ClockEnable     Not Used
PROPS!
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
STYLE
VhdlType        std_logic
DefaultFont     USER    {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
VerilogType     wire
DrawWndFont     DEFAULT
SystemCType     sc_logic
DrawWndColor    DEFAULT
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
GridWndFont     DEFAULT
StateEquation   Hex(Inc(0,2,5))
GridWndColor    DEFAULT
HighVoltageThreshold    5
LabelWndFont    USER    {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
LowVoltageThreshold     0
LabelWndColor   DEFAULT
LSB     0
ParamDispPref   0
MSB     31
ParamWndCellDisplay     0
SignalActionType        0
CustDispString  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
isFallingEdgeSensitive  False
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
isRisingEdgeSensitive   False
MarkerDispPref  4
DrawAnalog      0
MarkerCustDispString    %n v=%mv,%Mv d=%md %t
BooleanEquation
MarkerCustomDisplayStringRTF    {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
NegTolerance    0
SignalColor     2
PosTolerance    0
LabelOffset     2
UserSpecifiedSizeRatio  1
BusDisplay      0
VerilogCode
WaveFormWidth   0.500000
VHDLCode
WaveFormColor   0
PROPS!
InputWaveFormColor      16711680
E0      X       43750   43750           1       0        DR      0
SlantedEdges    1
!
SlantAngle      75
RightJustifySigNames    1
SIGNAL  dwb_WE_O
AutosplitEnabled        1
DIRECTION       output
AutosplitChar   _
RADIX   hex
DynamSizedSignals       1
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock   Unclocked
DIAGRAMTESTBENCHSETTINGS
EdgeLevel       neg
FilesBeforeDiagramModel
Set     Not Used
FilesInsideDiagramModelDeclarationSection
Clear   Not Used
AbortHdlCodeEnabled     1
ClockEnable     Not Used
DelayHdlCodeEnabled     1
ActiveLowSetClear       True
SampleHdlCodeEnabled    1
AsyncSetClear   True
MarkerHdlCodeEnabled    1
ActiveLowClockEnable    True
VerboseSamples  0
VhdlType        std_logic
VerboseDelays   0
VerilogType     wire
VerboseFileInput        0
SystemCType     sc_logic
VerboseSequenceVerification     0
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
IncludeDelayTime        1
StateEquation   Hex(Inc(0,2,5))
ExecuteFromTopLevel     1
HighVoltageThreshold    5
TimeOutInDiagramLengths 0
LowVoltageThreshold     0
DefaultCycleClock       Unclocked
SignalActionType        0
DefaultCycleEdge        neg
MSB     0
!
LSB     0
isFallingEdgeSensitive  False
MACROS
isRisingEdgeSensitive   False
!
DrawAnalog      0
BooleanEquation
CORGROUP        $$CLK_I_BufferRising
NegTolerance    0
Percent 100
PosTolerance    0
!
UserSpecifiedSizeRatio  1
VerilogCode
CORGROUP        $$CLK_I_BufferFalling
VHDLCode
Percent 100
PROPS!
!
E0      X       3125    3125            1       0        DR      0
E1      1       3126    3126            1       0        DR      0
CORGROUP        $$CLK_I_BufferRisingFalling
E2      0        13125   13125           1       0        DR      0
Percent 100
E3      X       13625   13625           1       0        DR      0
!
E4      0        23125   23125           1       0        DR      0
E5      X       23625   23625           1       0        DR      0
CORGROUP        $$CLK_I_BufferRising
E6      0        33125   33125           1       0        DR      0
Percent 100
E7      X       33625   33625           1       0        DR      0
!
E8      0        43125   43125           1       0        DR      0
E9      X       43625   43625           1       0        DR      0
CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
!
SIGNAL  dwb_SEL_O
DIRECTION       output
CORGROUP        $$CLK_I_BufferRisingFalling
RADIX   hex
Percent 100
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock   Unclocked
CORGROUP        $$CLK_I_BufferRising
EdgeLevel       neg
Percent 100
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
CORGROUP        $$CLK_I_BufferFalling
ActiveLowSetClear       True
Percent 100
AsyncSetClear   True
!
ActiveLowClockEnable    True
VhdlType        std_logic
CORGROUP        $$CLK_I_BufferRisingFalling
VerilogType     wire
Percent 100
SystemCType     sc_logic
!
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
CORGROUP        $$CLK_I_BufferRising
HighVoltageThreshold    5
Percent 100
LowVoltageThreshold     0
!
LSB     0
MSB     3
CORGROUP        $$CLK_I_BufferFalling
SignalActionType        0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   False
DrawAnalog      0
CORGROUP        $$CLK_I_BufferRisingFalling
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$CLK_I_BufferRising
VerilogCode
Percent 100
VHDLCode
!
PROPS!
E0      V       0        0           Valid        1       0        DR      0
CORGROUP        $$CLK_I_BufferFalling
E1      X       3750    3750            1       0        DR      0
Percent 100
E2      V       13125   13125       Valid       1       0        DR      0
!
E3      X       13625   13625           1       0        DR      0
E4      V       23125   23125     Valid 1       0        DR      0
CORGROUP        $$CLK_I_BufferRisingFalling
E5      X       23625   23625           1       0        DR      0
Percent 100
E6      V       33125   33125     Valid 1       0        DR      0
!
E7      X       33625   33625           1       0        DR      0
E8      V       43125   43125     Valid 1       0        DR      0
CORGROUP        $$CLK_I_BufferRising
E9      X       43750   43750           1       0        DR      0
Percent 100
!
!
SIGNAL  dwb_STB_O
CORGROUP        $$CLK_I_BufferFalling
DIRECTION       output
Percent 100
RADIX   hex
!
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
CORGROUP        $$CLK_I_BufferRisingFalling
Clock   Unclocked
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$CLK_RISC_BufferRising
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$CLK_RISC_BufferFalling
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$CLK_RISC_BufferRisingFalling
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
SignalActionType        0
CORGROUP        $$CLK_RISC_BufferRising
MSB     0
Percent 100
LSB     0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
CORGROUP        $$CLK_RISC_BufferFalling
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$CLK_RISC_BufferRisingFalling
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
PROPS!
CORGROUP        $$CLK_I_BufferRising
E0      0        3750    3750            1       0        DR      0
Percent 100
E1      1       13125   13125           1       0        DR      0
!
E2      0        13625   13625           1       0        DR      0
E3      1       23125   23125           1       0        DR      0
CORGROUP        $$CLK_I_BufferFalling
E4      0        23625   23625           1       0        DR      0
Percent 100
E5      1       33125   33125           1       0        DR      0
!
E6      0        33625   33625           1       0        DR      0
E7      1       43125   43125           1       0        DR      0
CORGROUP        $$CLK_I_BufferRisingFalling
E8      X       43750   43750           1       0        DR      0
Percent 100
!
!
SIGNAL  dwb_ACK_I
CORGROUP        $$CLK_RISC_BufferRising
DIRECTION       input
Percent 100
RADIX   hex
!
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
CORGROUP        $$CLK_RISC_BufferFalling
Clock   Unclocked
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$CLK_RISC_BufferRisingFalling
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$CLK_I_BufferRising
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$CLK_I_BufferFalling
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
SignalActionType        0
CORGROUP        $$CLK_I_BufferRisingFalling
MSB     0
Percent 100
LSB     0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
CORGROUP        $$CLK_RISC_BufferRising
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$CLK_RISC_BufferFalling
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
PROPS!
CORGROUP        $$CLK_RISC_BufferRisingFalling
E0      0        11250   11250           1       0        DR      0
Percent 100
E1      1       13125   13125           1       0        DR      0
!
E2      0        21250   21250           1       0        DR      0
E3      1       23125   23125           1       0        DR      0
CORGROUP        $$CLK_I_BufferRising
E4      0        31250   31250           1       0        DR      0
Percent 100
E5      1       33125   33125           1       0        DR      0
!
E6      0        41250   41250           1       0        DR      0
E7      1       43125   43125           1       0        DR      0
CORGROUP        $$CLK_I_BufferFalling
E8      X       43750   43750           1       0        DR      0
Percent 100
!
!
SIGNAL  dwb_CYC_O
CORGROUP        $$CLK_I_BufferRisingFalling
DIRECTION       output
Percent 100
RADIX   hex
!
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
CORGROUP        $$CLK_RISC_BufferRising
Clock   Unclocked
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$CLK_RISC_BufferFalling
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$CLK_RISC_BufferRisingFalling
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$CLK_I_BufferRising
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
SignalActionType        0
CORGROUP        $$CLK_I_BufferFalling
MSB     0
Percent 100
LSB     0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
CORGROUP        $$CLK_I_BufferRisingFalling
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$CLK_RISC_BufferRising
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
PROPS!
CORGROUP        $$CLK_RISC_BufferFalling
E0      0        3125    3125            1       0        DR      0
Percent 100
E1      1       43125   43125           1       0        DR      0
!
E2      0        43750   43750           1       0        DR      0
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
SIGNAL  dwb_ERR_I
!
DIRECTION       input
RADIX   hex
CORGROUP        $$CLK_I_BufferRising
GRID    0        1       0        1       0        16711680        0        0
Percent 100
ENDGRID -1
!
Clock   Unclocked
EdgeLevel       neg
CORGROUP        $$CLK_I_BufferFalling
Set     Not Used
Percent 100
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CORGROUP        $$CLK_I_BufferRisingFalling
AsyncSetClear   True
Percent 100
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
CORGROUP        $$CLK_RISC_BufferRising
SystemCType     sc_logic
Percent 100
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
CORGROUP        $$CLK_RISC_BufferFalling
LowVoltageThreshold     0
Percent 100
SignalActionType        0
!
MSB     0
LSB     0
CORGROUP        $$CLK_RISC_BufferRisingFalling
isFallingEdgeSensitive  False
Percent 100
isRisingEdgeSensitive   False
!
DrawAnalog      0
BooleanEquation
CORGROUP        $$CLK_I_BufferRising
NegTolerance    0
Percent 100
PosTolerance    0
!
UserSpecifiedSizeRatio  1
VerilogCode
CORGROUP        $$CLK_I_BufferFalling
VHDLCode
Percent 100
PROPS!
!
E0      0        43125   43125           1       0        DR      0
E1      X       43750   43750           1       0        DR      0
CORGROUP        $$CLK_I_BufferRisingFalling
!
Percent 100
!
SIGNAL  dwb_RTY_I
DIRECTION       input
CORGROUP        $$CLK_RISC_BufferRising
RADIX   hex
Percent 100
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock   Unclocked
CORGROUP        $$CLK_RISC_BufferFalling
EdgeLevel       neg
Percent 100
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
CORGROUP        $$CLK_RISC_BufferRisingFalling
ActiveLowSetClear       True
Percent 100
AsyncSetClear   True
!
ActiveLowClockEnable    True
VhdlType        std_logic
CORGROUP        $$CLK_I_BufferRising
VerilogType     wire
Percent 100
SystemCType     sc_logic
!
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
CORGROUP        $$CLK_I_BufferFalling
HighVoltageThreshold    5
Percent 100
LowVoltageThreshold     0
!
SignalActionType        0
MSB     0
CORGROUP        $$CLK_I_BufferRisingFalling
LSB     0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   False
DrawAnalog      0
CORGROUP        $$CLK_RISC_BufferRising
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$CLK_RISC_BufferFalling
VerilogCode
Percent 100
VHDLCode
!
PROPS!
E0      0        43125   43125           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRisingFalling
E1      X       43750   43750           1       0        DR      0
Percent 100
!
!
MARKER  MARK1
CORGROUP        $$CLK_I_BufferRising
ATTACH  dwb_SEL_O       NULL    S6
Percent 100
TIME    17500.000000
!
RELATIVETIME    0.000000
DISPLAYAS       5
CORGROUP        $$CLK_I_BufferFalling
MARKERTYPE      Timebreak(Curved)
Percent 100
WHILERETURN
!
REPEATNUMBER
SNAPTO  0
CORGROUP        $$CLK_I_BufferRisingFalling
COMPRESSTIME    0.000000
Percent 100
COMMENT
!
!
CORGROUP        $$CLK_RISC_BufferRising
MARKER  MARK2
Percent 100
ATTACH  dwb_STB_O       NULL    S7
!
TIME    27500.000000
RELATIVETIME    0.000000
CORGROUP        $$CLK_RISC_BufferFalling
DISPLAYAS       5
Percent 100
MARKERTYPE      Timebreak(Curved)
!
WHILERETURN
REPEATNUMBER
CORGROUP        $$CLK_RISC_BufferRisingFalling
SNAPTO  0
Percent 100
COMPRESSTIME    0.000000
!
COMMENT
!
CORGROUP        $$CLK_I_BufferRising
Percent 100
MARKER  MARK3
!
ATTACH  dwb_STB_O       NULL    S7
TIME    37500.000000
CORGROUP        $$CLK_I_BufferFalling
RELATIVETIME    0.000000
Percent 100
DISPLAYAS       5
!
MARKERTYPE      Timebreak(Curved)
WHILERETURN
CORGROUP        $$CLK_I_BufferRisingFalling
REPEATNUMBER
Percent 100
SNAPTO  0
!
COMPRESSTIME    0.000000
COMMENT
CORGROUP        $$CLK_RISC_BufferRising
!
Percent 100
!
MARKER  MARK0
ATTACH  dwb_CLK_I       NULL    S1
CORGROUP        $$CLK_RISC_BufferFalling
TIME    7494.285714
Percent 100
RELATIVETIME    0.000000
!
DISPLAYAS       5
MARKERTYPE      Timebreak(Curved)
CORGROUP        $$CLK_RISC_BufferRisingFalling
WHILERETURN
Percent 100
REPEATNUMBER
!
SNAPTO  0
COMPRESSTIME    0.000000
CORGROUP        $$CLK_I_BufferRising
COMMENT
Percent 100
!
!

CORGROUP        $$CLK_I_BufferFalling
Q<=KuyTiming DiagramTiming.Document.19qTiming Diagram
Percent 100
Q<=KuyTiming DiagramTiming.Document.19qTiming DiagramTiming Diagram Editor v7.1g - Output File
!
PROJECT
CORGROUP        $$CLK_I_BufferRisingFalling
BaseTimeUnit    1
Percent 100
DisplayTimeUnit 2
!
TextGridX       625.000000
TextGridY       6
CORGROUP        $$CLK_RISC_BufferRising
EdgeGridX       625.000000
Percent 100
ImportStartTime 0.000000
!
ImportEndTime   281474976710656.000000
TimePerPixel    17.543860
CORGROUP        $$CLK_RISC_BufferFalling
Visible DELAYS  SETUPS  HOLDS   SAMPLES TEXT    HIDDENATTACHMENTS       CRITICALPATHS   GRIDLINES       UNCERTAINTY
Percent 100
ColWidths       144,216,288,423,488
!
ScrollPos       0.000000,0.000000,0.000000
DefDelayRule    1
CORGROUP        $$CLK_RISC_BufferRisingFalling
NoEventOverlap  NO
Percent 100
SigLabelFontHeight      8
!
LabelHeight     10
LoadLibsToMem   1
CORGROUP        $$CLK_I_BufferRising
UseFullPathNames        1
Percent 100
LibPath
!
EntireTime      YES
PrintTimeSpecified      NO
CORGROUP        $$CLK_I_BufferFalling
FromTime        0
Percent 100
ToTime  15.625
!
AllSignals      YES
CurrSelSigs     NO
CORGROUP        $$CLK_I_BufferRisingFalling
PrintTo 2
Percent 100
PrintFileName   C:\DOCS\wb_writesingle.wmf
!
PreviewInterchange      YES
PreviewTIFF5    NO
CORGROUP        $$dwb_CLK_RISC_BufferRising
UseMargins      NO
Percent 100
PrintTimeLine   NO
!
PrintBorderBox  YES
PrintSigNames   YES
CORGROUP        $$dwb_CLK_RISC_BufferFalling
PrintSigNamesOnEachPage YES
Percent 100
AddPreviewToEPS NO
!
PreviewRes      150
MarginLR        1
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
MifImageWidth   6.00
Percent 100
MarginTB        Auto
!
Header  %d %t;%f;%p
Footer
CORGROUP        $$dwb_CLK_I_BufferRising
ScaleHorz       100
Percent 100
ScaleVert       100
!
ScaleHPage      1
PrintImage      DIAGRAM
CORGROUP        $$dwb_CLK_I_BufferFalling
DefaultTimingModel      minmax
Percent 100
DefaultClock    Unclocked
!
DefaultEdgeLevel        neg
DefaultSet      Not Used
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
DefaultClear    Not Used
Percent 100
DefaultClockEnable      Not Used
!
DefaultClockToOutLH     0
DefaultClockToOutHL     0
CORGROUP        $$dwb_CLK_RISC_BufferRising
DefaultSetup    0
Percent 100
DefaultHold     0
!
DefaultRegStartupState  unknown
DefaultPodSize  8
CORGROUP        $$dwb_CLK_RISC_BufferFalling
DefaultActiveLowSetClear        True
Percent 100
DefaultAsyncSetClear    True
!
DefaultActiveLowClockEnable     True
SigLabelFontHeight      10
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
PROPS!
Percent 100
!
!
STYLE
CORGROUP        $$dwb_CLK_I_BufferRising
DefaultFont     USER    {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
Percent 100
DrawWndFont     DEFAULT
!
DrawWndColor    DEFAULT
GridWndFont     DEFAULT
CORGROUP        $$dwb_CLK_I_BufferFalling
GridWndColor    DEFAULT
Percent 100
LabelWndFont    USER    {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
!
LabelWndColor   DEFAULT
ParamDispPref   0
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
ParamWndCellDisplay     0
Percent 100
CustDispString  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
!
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
MarkerDispPref  4
CORGROUP        $$dwb_CLK_RISC_BufferRising
MarkerCustDispString    %n v=%mv,%Mv d=%md %t
Percent 100
MarkerCustomDisplayStringRTF    {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
!
SignalColor     2
LabelOffset     2
CORGROUP        $$dwb_CLK_RISC_BufferFalling
BusDisplay      0
Percent 100
WaveFormWidth   0.500000
!
WaveFormColor   0
InputWaveFormColor      16711680
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
SlantedEdges    1
Percent 100
SlantAngle      75
!
RightJustifySigNames    1
AutosplitEnabled        1
CORGROUP        $$dwb_CLK_I_BufferRising
AutosplitChar   _
Percent 100
DynamSizedSignals       1
!
!
CORGROUP        $$dwb_CLK_I_BufferFalling
DIAGRAMTESTBENCHSETTINGS
Percent 100
FilesBeforeDiagramModel
!
FilesInsideDiagramModelDeclarationSection
AbortHdlCodeEnabled     1
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
DelayHdlCodeEnabled     1
Percent 100
SampleHdlCodeEnabled    1
!
MarkerHdlCodeEnabled    1
VerboseSamples  0
CORGROUP        $$dwb_CLK_RISC_BufferRising
VerboseDelays   0
Percent 100
VerboseFileInput        0
!
VerboseSequenceVerification     0
IncludeDelayTime        1
CORGROUP        $$dwb_CLK_RISC_BufferFalling
ExecuteFromTopLevel     1
Percent 100
TimeOutInDiagramLengths 0
!
DefaultCycleClock       Unclocked
DefaultCycleEdge        neg
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
!
Percent 100
!
MACROS
!
CORGROUP        $$dwb_CLK_I_BufferRising
Percent 100
CORGROUP        $$CLK_I_BufferRising
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferFalling
Percent 100
CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_I_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_RISC_BufferRising
Percent 100
CORGROUP        $$CLK_I_BufferRising
!
Percent 100
!
CORGROUP        $$dwb_CLK_RISC_BufferFalling
Percent 100
CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_RISC_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_I_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferRising
Percent 100
CORGROUP        $$CLK_I_BufferRising
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferFalling
Percent 100
CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
!
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_I_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
CORGROUP        $$CLK_I_BufferRising
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_I_BufferRisingFalling
!
Percent 100
!
CORGROUP        $$iwb_CLK_I_BufferRising
Percent 100
CORGROUP        $$CLK_I_BufferRising
!
Percent 100
!
CORGROUP        $$iwb_CLK_I_BufferFalling
Percent 100
CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
!
CORGROUP        $$iwb_CLK_I_BufferRisingFalling
Percent 100
CORGROUP        $$CLK_I_BufferRisingFalling
!
Percent 100
!
CLOCK   CLK_RISC
PERIODE 2.5
CORGROUP        $$CLK_I_BufferRising
DUTY    50
Percent 100
OFFSETE 0
!
INITIAL HIGH
MAXUNCERTRISE   0
CORGROUP        $$CLK_I_BufferFalling
MAXUNCERTFALL   0
Percent 100
MINUNCERTRISE   0
!
MINUNCERTFALL   0
JRISEE  0
CORGROUP        $$CLK_I_BufferRisingFalling
JFALLE  0
Percent 100
GRID    0        1       0        2       0        16711680        0        0
!
ENDGRID -1
DIRECTION       internal
CORGROUP        $$CLK_RISC_BufferRising
MASTERCLOCK     None
Percent 100
Clock   Unclocked
!
EdgeLevel       neg
Set     Not Used
CORGROUP        $$CLK_RISC_BufferFalling
Clear   Not Used
Percent 100
ClockEnable     Not Used
!
ActiveLowSetClear       True
AsyncSetClear   True
CORGROUP        $$CLK_RISC_BufferRisingFalling
ActiveLowClockEnable    True
Percent 100
VhdlType        std_logic
!
VerilogType     wire
SystemCType     sc_logic
CORGROUP        $$CLK_RISC_BufferRising
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Percent 100
StateEquation   Hex(Inc(0,2,5))
!
HighVoltageThreshold    5
LowVoltageThreshold     0
CORGROUP        $$CLK_RISC_BufferFalling
MSB     0
Percent 100
LSB     0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
CORGROUP        $$CLK_RISC_BufferRisingFalling
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$CLK_I_BufferRising
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
PROPS!
CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
!
CLOCK   iwb_CLK_I
PERIODE 5
CORGROUP        $$CLK_I_BufferRisingFalling
DUTY    50
Percent 100
OFFSETE 0
!
INITIAL LOW
MAXUNCERTRISE   0
CORGROUP        $$CLK_RISC_BufferRising
MAXUNCERTFALL   0
Percent 100
MINUNCERTRISE   0
!
MINUNCERTFALL   0
JRISEE  0
CORGROUP        $$CLK_RISC_BufferFalling
JFALLE  0
Percent 100
GRID    1       1       1       2       2       16711680        0        0
!
ENDGRID -1
DIRECTION       input
CORGROUP        $$CLK_RISC_BufferRisingFalling
MASTERCLOCK     None
Percent 100
Clock   Unclocked
!
EdgeLevel       neg
Set     Not Used
CORGROUP        $$CLK_I_BufferRising
Clear   Not Used
Percent 100
ClockEnable     Not Used
!
ActiveLowSetClear       True
AsyncSetClear   True
CORGROUP        $$CLK_I_BufferFalling
ActiveLowClockEnable    True
Percent 100
VhdlType        std_logic
!
VerilogType     wire
SystemCType     sc_logic
CORGROUP        $$CLK_I_BufferRisingFalling
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Percent 100
StateEquation   Hex(Inc(0,2,5))
!
HighVoltageThreshold    5
LowVoltageThreshold     0
CORGROUP        $$CLK_RISC_BufferRising
MSB     0
Percent 100
LSB     0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   True
CORGROUP        $$CLK_RISC_BufferFalling
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$CLK_RISC_BufferRisingFalling
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
PROPS!
CORGROUP        $$CLK_I_BufferRising
!
Percent 100
!
SIGNAL  iwb_ADR_O
DIRECTION       output
CORGROUP        $$CLK_I_BufferFalling
RADIX   hex
Percent 100
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock
CORGROUP        $$CLK_I_BufferRisingFalling
EdgeLevel       neg
Percent 100
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
CORGROUP        $$CLK_RISC_BufferRising
ActiveLowSetClear       True
Percent 100
AsyncSetClear   True
!
ActiveLowClockEnable    True
VhdlType        std_logic
CORGROUP        $$CLK_RISC_BufferFalling
VerilogType     wire
Percent 100
SystemCType     sc_logic
!
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
CORGROUP        $$CLK_RISC_BufferRisingFalling
HighVoltageThreshold    5
Percent 100
LowVoltageThreshold     0
!
LSB     0
MSB     31
CORGROUP        $$CLK_I_BufferRising
SignalActionType        0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   True
DrawAnalog      0
CORGROUP        $$CLK_I_BufferFalling
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$CLK_I_BufferRisingFalling
VerilogCode
Percent 100
VHDLCode
!
VhdlMapping     DefaultVhdlMapping
PROPS!
CORGROUP        $$CLK_RISC_BufferRising
E0      V       -1      -1              1       0        DR      0
Percent 100
E1      X       3125    3125            1       0        DR      0
!
E2      V       3126    3126    A0      1       0        DR      0
E3      X       3750    3750            1       0        DR      0
CORGROUP        $$CLK_RISC_BufferFalling
E4      V       13125   13125     A0    1       0        DR      0
Percent 100
E5      X       13625   13625           1       0        DR      0
!
E6      V       23125   23125     A4    1       0        DR      0
E7      X       23625   23625           1       0        DR      0
CORGROUP        $$CLK_RISC_BufferRisingFalling
E8      V       33125   33125     A8    1       0        DR      0
Percent 100
E9      X       33625   33625           1       0        DR      0
!
E10     V       43125   43125     A12   1       0        DR      0
E11     X       43750   43750           1       0        DR      0
CORGROUP        $$CLK_I_BufferRising
!
Percent 100
!
SIGNAL  iwb_DAT_I
DIRECTION       input
CORGROUP        $$CLK_I_BufferFalling
RADIX   hex
Percent 100
GRID    0        1       0        1       0        16711680        0        0
!
ENDGRID -1
Clock
CORGROUP        $$CLK_I_BufferRisingFalling
EdgeLevel       neg
Percent 100
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
CORGROUP        $$CLK_RISC_BufferRising
ActiveLowSetClear       True
Percent 100
AsyncSetClear   True
!
ActiveLowClockEnable    True
VhdlType        std_logic
CORGROUP        $$CLK_RISC_BufferFalling
VerilogType     wire
Percent 100
SystemCType     sc_logic
!
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
CORGROUP        $$CLK_RISC_BufferRisingFalling
HighVoltageThreshold    5
Percent 100
LowVoltageThreshold     0
!
LSB     0
MSB     31
CORGROUP        $$dwb_CLK_I_BufferRising
SignalActionType        0
Percent 100
isFallingEdgeSensitive  False
!
isRisingEdgeSensitive   False
DrawAnalog      0
CORGROUP        $$dwb_CLK_I_BufferFalling
BooleanEquation
Percent 100
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
CORGROUP        $$dwb_CLK_I_BufferRisingFalling
VerilogCode
Percent 100
VHDLCode
!
VhdlMapping     DefaultVhdlMapping
PROPS!
CLOCK   CLK_RISC
E0      X       11250   11250           1       0        DR      0
PERIODE 2.5
E1      V       13125   13125   D0      1       0        DR      0
DUTY    50
E2      X       21250   21250           1       0        DR      0
OFFSETE 0
E3      V       23125   23125   D4      1       0        DR      0
INITIAL HIGH
E4      X       31250   31250           1       0        DR      0
MAXUNCERTRISE   0
E5      V       33125   33125   D8      1       0        DR      0
MAXUNCERTFALL   0
E6      X       41250   41250           1       0        DR      0
MINUNCERTRISE   0
E7      V       43125   43125   D12     1       0        DR      0
MINUNCERTFALL   0
E8      X       43750   43750           1       0        DR      0
JRISEE  0
!
JFALLE  0
GRID    0        1       0        2       0        16711680        0        0
SIGNAL  iwb_DAT_O
ENDGRID -1
DIRECTION       output
DIRECTION       internal
RADIX   hex
MASTERCLOCK     None
GRID    0        1       0        1       0        16711680        0        0
Clock   Unclocked
ENDGRID -1
EdgeLevel       neg
Clock   Unclocked
Set     Not Used
EdgeLevel       neg
Clear   Not Used
Set     Not Used
ClockEnable     Not Used
Clear   Not Used
ActiveLowSetClear       True
ClockEnable     Not Used
AsyncSetClear   True
ActiveLowSetClear       True
ActiveLowClockEnable    True
AsyncSetClear   True
VhdlType        std_logic
ActiveLowClockEnable    True
VerilogType     wire
VhdlType        std_logic
SystemCType     sc_logic
VerilogType     wire
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
SystemCType     sc_logic
StateEquation   Hex(Inc(0,2,5))
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
HighVoltageThreshold    5
StateEquation   Hex(Inc(0,2,5))
LowVoltageThreshold     0
HighVoltageThreshold    5
MSB     0
LowVoltageThreshold     0
LSB     0
LSB     0
isFallingEdgeSensitive  False
MSB     31
isRisingEdgeSensitive   False
SignalActionType        0
DrawAnalog      0
isFallingEdgeSensitive  False
BooleanEquation
isRisingEdgeSensitive   False
NegTolerance    0
DrawAnalog      0
PosTolerance    0
BooleanEquation
UserSpecifiedSizeRatio  1
NegTolerance    0
VerilogCode
PosTolerance    0
VHDLCode
UserSpecifiedSizeRatio  1
PROPS!
VerilogCode
!
VHDLCode
PROPS!
CLOCK   dwb_CLK_I
E0      X       43750   43750           1       0        DR      0
PERIODE 5
!
DUTY    50
OFFSETE 0
SIGNAL  iwb_WE_O
INITIAL LOW
DIRECTION       output
MAXUNCERTRISE   0
RADIX   hex
MAXUNCERTFALL   0
GRID    0        1       0        1       0        16711680        0        0
MINUNCERTRISE   0
ENDGRID -1
MINUNCERTFALL   0
Clock   Unclocked
JRISEE  0
EdgeLevel       neg
JFALLE  0
Set     Not Used
GRID    1       1       1       2       2       16711680        0        0
Clear   Not Used
ENDGRID -1
ClockEnable     Not Used
DIRECTION       input
ActiveLowSetClear       True
MASTERCLOCK     None
AsyncSetClear   True
Clock   Unclocked
ActiveLowClockEnable    True
EdgeLevel       neg
VhdlType        std_logic
Set     Not Used
VerilogType     wire
Clear   Not Used
SystemCType     sc_logic
ClockEnable     Not Used
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
ActiveLowSetClear       True
StateEquation   Hex(Inc(0,2,5))
AsyncSetClear   True
HighVoltageThreshold    5
ActiveLowClockEnable    True
LowVoltageThreshold     0
VhdlType        std_logic
SignalActionType        0
VerilogType     wire
MSB     0
SystemCType     sc_logic
LSB     0
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
isFallingEdgeSensitive  False
StateEquation   Hex(Inc(0,2,5))
isRisingEdgeSensitive   False
HighVoltageThreshold    5
DrawAnalog      0
LowVoltageThreshold     0
BooleanEquation
MSB     0
NegTolerance    0
LSB     0
PosTolerance    0
isFallingEdgeSensitive  False
UserSpecifiedSizeRatio  1
isRisingEdgeSensitive   True
VerilogCode
DrawAnalog      0
VHDLCode
BooleanEquation
PROPS!
NegTolerance    0
E0      X       3125    3125            1       0        DR      0
PosTolerance    0
E1      1       3126    3126            1       0        DR      0
UserSpecifiedSizeRatio  1
E2      0        13125   13125           1       0        DR      0
VerilogCode
E3      X       13625   13625           1       0        DR      0
VHDLCode
E4      0        23125   23125           1       0        DR      0
PROPS!
E5      X       23625   23625           1       0        DR      0
!
E6      0        33125   33125           1       0        DR      0
E7      X       33625   33625           1       0        DR      0
SIGNAL  dwb_ADR_O
E8      0        43125   43125           1       0        DR      0
DIRECTION       output
E9      X       43625   43625           1       0        DR      0
RADIX   hex
!
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
SIGNAL  iwb_SEL_O
Clock
DIRECTION       output
EdgeLevel       neg
RADIX   hex
Set     Not Used
GRID    0        1       0        1       0        16711680        0        0
Clear   Not Used
ENDGRID -1
ClockEnable     Not Used
Clock   Unclocked
ActiveLowSetClear       True
EdgeLevel       neg
AsyncSetClear   True
Set     Not Used
ActiveLowClockEnable    True
Clear   Not Used
VhdlType        std_logic
ClockEnable     Not Used
VerilogType     wire
ActiveLowSetClear       True
SystemCType     sc_logic
AsyncSetClear   True
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
ActiveLowClockEnable    True
StateEquation   Hex(Inc(0,2,5))
VhdlType        std_logic
HighVoltageThreshold    5
VerilogType     wire
LowVoltageThreshold     0
SystemCType     sc_logic
LSB     0
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
MSB     31
StateEquation   Hex(Inc(0,2,5))
SignalActionType        0
HighVoltageThreshold    5
isFallingEdgeSensitive  False
LowVoltageThreshold     0
isRisingEdgeSensitive   True
LSB     0
DrawAnalog      0
MSB     3
BooleanEquation
SignalActionType        0
NegTolerance    0
isFallingEdgeSensitive  False
PosTolerance    0
isRisingEdgeSensitive   False
UserSpecifiedSizeRatio  1
DrawAnalog      0
VerilogCode
BooleanEquation
VHDLCode
NegTolerance    0
VhdlMapping     DefaultVhdlMapping
PosTolerance    0
PROPS!
UserSpecifiedSizeRatio  1
E0      V       -1      -1              1       0        DR      0
VerilogCode
E1      X       3125    3125            1       0        DR      0
VHDLCode
E2      V       13125   13125   Valid   1       0        DR      0
PROPS!
E3      X       15625   15625           1       0        DR      0
E0      V       0        0           Valid        1       0        DR      0
!
E1      X       3750    3750            1       0        DR      0
E2      V       13125   13125       Valid       1       0        DR      0
SIGNAL  dwb_DAT_I
E3      X       13625   13625           1       0        DR      0
DIRECTION       input
E4      V       23125   23125     Valid 1       0        DR      0
RADIX   hex
E5      X       23625   23625           1       0        DR      0
GRID    0        1       0        1       0        16711680        0        0
E6      V       33125   33125     Valid 1       0        DR      0
ENDGRID -1
E7      X       33625   33625           1       0        DR      0
Clock
E8      V       43125   43125     Valid 1       0        DR      0
EdgeLevel       neg
E9      X       43750   43750           1       0        DR      0
Set     Not Used
!
Clear   Not Used
ClockEnable     Not Used
SIGNAL  iwb_STB_O
ActiveLowSetClear       True
DIRECTION       output
AsyncSetClear   True
RADIX   hex
ActiveLowClockEnable    True
GRID    0        1       0        1       0        16711680        0        0
VhdlType        std_logic
ENDGRID -1
VerilogType     wire
Clock   Unclocked
SystemCType     sc_logic
EdgeLevel       neg
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Set     Not Used
StateEquation   Hex(Inc(0,2,5))
Clear   Not Used
HighVoltageThreshold    5
ClockEnable     Not Used
LowVoltageThreshold     0
ActiveLowSetClear       True
LSB     0
AsyncSetClear   True
MSB     31
ActiveLowClockEnable    True
SignalActionType        0
VhdlType        std_logic
isFallingEdgeSensitive  False
VerilogType     wire
isRisingEdgeSensitive   False
SystemCType     sc_logic
DrawAnalog      0
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
BooleanEquation
StateEquation   Hex(Inc(0,2,5))
NegTolerance    0
HighVoltageThreshold    5
PosTolerance    0
LowVoltageThreshold     0
UserSpecifiedSizeRatio  1
SignalActionType        0
VerilogCode
MSB     0
VHDLCode
LSB     0
VhdlMapping     DefaultVhdlMapping
isFallingEdgeSensitive  False
PROPS!
isRisingEdgeSensitive   False
E0      X       13125   13125           1       0        DR      0
DrawAnalog      0
E1      V       13126   13126   Valid   1       0        DR      0
BooleanEquation
E2      X       15625   15625           1       0        DR      0
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
SIGNAL  dwb_DAT_O
VerilogCode
DIRECTION       output
VHDLCode
RADIX   hex
PROPS!
GRID    0        1       0        1       0        16711680        0        0
E0      0        3750    3750            1       0        DR      0
ENDGRID -1
E1      1       13125   13125           1       0        DR      0
Clock   Unclocked
E2      0        13625   13625           1       0        DR      0
EdgeLevel       neg
E3      1       23125   23125           1       0        DR      0
Set     Not Used
E4      0        23625   23625           1       0        DR      0
Clear   Not Used
E5      1       33125   33125           1       0        DR      0
ClockEnable     Not Used
E6      0        33625   33625           1       0        DR      0
ActiveLowSetClear       True
E7      1       43125   43125           1       0        DR      0
AsyncSetClear   True
E8      X       43750   43750           1       0        DR      0
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
SIGNAL  iwb_ACK_I
SystemCType     sc_logic
DIRECTION       input
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
RADIX   hex
StateEquation   Hex(Inc(0,2,5))
GRID    0        1       0        1       0        16711680        0        0
HighVoltageThreshold    5
ENDGRID -1
LowVoltageThreshold     0
Clock   Unclocked
LSB     0
EdgeLevel       neg
MSB     31
Set     Not Used
SignalActionType        0
Clear   Not Used
isFallingEdgeSensitive  False
ClockEnable     Not Used
isRisingEdgeSensitive   False
ActiveLowSetClear       True
DrawAnalog      0
AsyncSetClear   True
BooleanEquation
ActiveLowClockEnable    True
NegTolerance    0
VhdlType        std_logic
PosTolerance    0
VerilogType     wire
UserSpecifiedSizeRatio  1
SystemCType     sc_logic
VerilogCode
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
VHDLCode
StateEquation   Hex(Inc(0,2,5))
PROPS!
HighVoltageThreshold    5
E0      X       3125    3125            1       0        DR      0
LowVoltageThreshold     0
E1      V       13125   13125   Valid   1       0        DR      0
SignalActionType        0
E2      X       15625   15625           1       0        DR      0
MSB     0
!
LSB     0
isFallingEdgeSensitive  False
SIGNAL  dwb_WE_O
isRisingEdgeSensitive   False
DIRECTION       output
DrawAnalog      0
RADIX   hex
BooleanEquation
GRID    0        1       0        1       0        16711680        0        0
NegTolerance    0
ENDGRID -1
PosTolerance    0
Clock   Unclocked
UserSpecifiedSizeRatio  1
EdgeLevel       neg
VerilogCode
Set     Not Used
VHDLCode
Clear   Not Used
PROPS!
ClockEnable     Not Used
E0      0        11250   11250           1       0        DR      0
ActiveLowSetClear       True
E1      1       13125   13125           1       0        DR      0
AsyncSetClear   True
E2      0        21250   21250           1       0        DR      0
ActiveLowClockEnable    True
E3      1       23125   23125           1       0        DR      0
VhdlType        std_logic
E4      0        31250   31250           1       0        DR      0
VerilogType     wire
E5      1       33125   33125           1       0        DR      0
SystemCType     sc_logic
E6      0        41250   41250           1       0        DR      0
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
E7      1       43125   43125           1       0        DR      0
StateEquation   Hex(Inc(0,2,5))
E8      X       43750   43750           1       0        DR      0
HighVoltageThreshold    5
!
LowVoltageThreshold     0
SignalActionType        0
SIGNAL  iwb_CYC_O
MSB     0
DIRECTION       output
LSB     0
RADIX   hex
isFallingEdgeSensitive  False
GRID    0        1       0        1       0        16711680        0        0
isRisingEdgeSensitive   False
ENDGRID -1
DrawAnalog      0
Clock   Unclocked
BooleanEquation
EdgeLevel       neg
NegTolerance    0
Set     Not Used
PosTolerance    0
Clear   Not Used
UserSpecifiedSizeRatio  1
ClockEnable     Not Used
VerilogCode
ActiveLowSetClear       True
VHDLCode
AsyncSetClear   True
PROPS!
ActiveLowClockEnable    True
E0      X       3125    3125            1       0        DR      0
VhdlType        std_logic
E1      0        3467    3467            1       0        DR      0
VerilogType     wire
E2      1       13125   13125           1       0        DR      0
SystemCType     sc_logic
E3      0        13126   13126           1       0        DR      0
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
E4      X       15625   15625           1       0        DR      0
StateEquation   Hex(Inc(0,2,5))
!
HighVoltageThreshold    5
LowVoltageThreshold     0
SIGNAL  dwb_SEL_O
SignalActionType        0
DIRECTION       output
MSB     0
RADIX   hex
LSB     0
GRID    0        1       0        1       0        16711680        0        0
isFallingEdgeSensitive  False
ENDGRID -1
isRisingEdgeSensitive   False
Clock   Unclocked
DrawAnalog      0
EdgeLevel       neg
BooleanEquation
Set     Not Used
NegTolerance    0
Clear   Not Used
PosTolerance    0
ClockEnable     Not Used
UserSpecifiedSizeRatio  1
ActiveLowSetClear       True
VerilogCode
AsyncSetClear   True
VHDLCode
ActiveLowClockEnable    True
PROPS!
VhdlType        std_logic
E0      0        3125    3125            1       0        DR      0
VerilogType     wire
E1      1       43125   43125           1       0        DR      0
SystemCType     sc_logic
E2      0        43750   43750           1       0        DR      0
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
SIGNAL  iwb_ERR_I
LowVoltageThreshold     0
DIRECTION       input
LSB     0
RADIX   hex
MSB     3
GRID    0        1       0        1       0        16711680        0        0
SignalActionType        0
ENDGRID -1
isFallingEdgeSensitive  False
Clock   Unclocked
isRisingEdgeSensitive   False
EdgeLevel       neg
DrawAnalog      0
Set     Not Used
BooleanEquation
Clear   Not Used
NegTolerance    0
ClockEnable     Not Used
PosTolerance    0
ActiveLowSetClear       True
UserSpecifiedSizeRatio  1
AsyncSetClear   True
VerilogCode
ActiveLowClockEnable    True
VHDLCode
VhdlType        std_logic
PROPS!
VerilogType     wire
E0      X       3125    3125            1       0        DR      0
SystemCType     sc_logic
E1      V       13125   13125   Valid   1       0        DR      0
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
E2      X       15625   15625           1       0        DR      0
StateEquation   Hex(Inc(0,2,5))
!
HighVoltageThreshold    5
LowVoltageThreshold     0
SIGNAL  dwb_STB_O
SignalActionType        0
DIRECTION       output
MSB     0
RADIX   hex
LSB     0
GRID    0        1       0        1       0        16711680        0        0
isFallingEdgeSensitive  False
ENDGRID -1
isRisingEdgeSensitive   False
Clock   Unclocked
DrawAnalog      0
EdgeLevel       neg
BooleanEquation
Set     Not Used
NegTolerance    0
Clear   Not Used
PosTolerance    0
ClockEnable     Not Used
UserSpecifiedSizeRatio  1
ActiveLowSetClear       True
VerilogCode
AsyncSetClear   True
VHDLCode
ActiveLowClockEnable    True
PROPS!
VhdlType        std_logic
E0      0        43125   43125           1       0        DR      0
VerilogType     wire
E1      X       43750   43750           1       0        DR      0
SystemCType     sc_logic
!
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
SIGNAL  iwb_RTY_I
HighVoltageThreshold    5
DIRECTION       input
LowVoltageThreshold     0
RADIX   hex
SignalActionType        0
GRID    0        1       0        1       0        16711680        0        0
MSB     0
ENDGRID -1
LSB     0
Clock   Unclocked
isFallingEdgeSensitive  False
EdgeLevel       neg
isRisingEdgeSensitive   False
Set     Not Used
DrawAnalog      0
Clear   Not Used
BooleanEquation
ClockEnable     Not Used
NegTolerance    0
ActiveLowSetClear       True
PosTolerance    0
AsyncSetClear   True
UserSpecifiedSizeRatio  1
ActiveLowClockEnable    True
VerilogCode
VhdlType        std_logic
VHDLCode
VerilogType     wire
PROPS!
SystemCType     sc_logic
E0      0        3125    3125            1       0        DR      0
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
E1      1       13125   13125           1       0        DR      0
StateEquation   Hex(Inc(0,2,5))
E2      0        15625   15625           1       0        DR      0
HighVoltageThreshold    5
!
LowVoltageThreshold     0
SignalActionType        0
SIGNAL  dwb_ACK_I
MSB     0
DIRECTION       input
LSB     0
RADIX   hex
isFallingEdgeSensitive  False
GRID    0        1       0        1       0        16711680        0        0
isRisingEdgeSensitive   False
ENDGRID -1
DrawAnalog      0
Clock   Unclocked
BooleanEquation
EdgeLevel       neg
NegTolerance    0
Set     Not Used
PosTolerance    0
Clear   Not Used
UserSpecifiedSizeRatio  1
ClockEnable     Not Used
VerilogCode
ActiveLowSetClear       True
VHDLCode
AsyncSetClear   True
PROPS!
ActiveLowClockEnable    True
E0      0        43125   43125           1       0        DR      0
VhdlType        std_logic
E1      X       43750   43750           1       0        DR      0
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
MARKER  MARK1
StateEquation   Hex(Inc(0,2,5))
ATTACH  iwb_SEL_O       NULL    S6
HighVoltageThreshold    5
TIME    17500.000000
LowVoltageThreshold     0
RELATIVETIME    0.000000
SignalActionType        0
DISPLAYAS       5
MSB     0
MARKERTYPE      Timebreak(Curved)
LSB     0
WHILERETURN
isFallingEdgeSensitive  False
REPEATNUMBER
isRisingEdgeSensitive   False
SNAPTO  0
DrawAnalog      0
COMPRESSTIME    0.000000
BooleanEquation
COMMENT
NegTolerance    0
!
PosTolerance    0
UserSpecifiedSizeRatio  1
MARKER  MARK2
VerilogCode
ATTACH  iwb_STB_O       NULL    S7
VHDLCode
TIME    27500.000000
PROPS!
RELATIVETIME    0.000000
E0      0        11250   11250           1       0        DR      0
DISPLAYAS       5
E1      1       13125   13125           1       0        DR      0
MARKERTYPE      Timebreak(Curved)
E2      0        15625   15625           1       0        DR      0
WHILERETURN
!
REPEATNUMBER
SNAPTO  0
SIGNAL  dwb_CYC_O
COMPRESSTIME    0.000000
DIRECTION       output
COMMENT
RADIX   hex
!
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
MARKER  MARK3
Clock   Unclocked
ATTACH  iwb_STB_O       NULL    S7
EdgeLevel       neg
TIME    37500.000000
Set     Not Used
RELATIVETIME    0.000000
Clear   Not Used
DISPLAYAS       5
ClockEnable     Not Used
MARKERTYPE      Timebreak(Curved)
ActiveLowSetClear       True
WHILERETURN
AsyncSetClear   True
REPEATNUMBER
ActiveLowClockEnable    True
SNAPTO  0
VhdlType        std_logic
COMPRESSTIME    0.000000
VerilogType     wire
COMMENT
SystemCType     sc_logic
!
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
MARKER  MARK0
HighVoltageThreshold    5
ATTACH  iwb_CLK_I       NULL    S1
LowVoltageThreshold     0
TIME    7494.285714
SignalActionType        0
RELATIVETIME    0.000000
MSB     0
DISPLAYAS       5
LSB     0
MARKERTYPE      Timebreak(Curved)
isFallingEdgeSensitive  False
WHILERETURN
isRisingEdgeSensitive   False
REPEATNUMBER
DrawAnalog      0
SNAPTO  0
BooleanEquation
COMPRESSTIME    0.000000
NegTolerance    0
COMMENT
PosTolerance    0
!
UserSpecifiedSizeRatio  1
VerilogCode
Timing Diagram Editor v7.1g - Output File
VHDLCode
PROPS!
PROJECT
E0      0        3125    3125            1       0        DR      0
BaseTimeUnit    1
E1      1       13125   13125           1       0        DR      0
DisplayTimeUnit 2
E2      0        15625   15625           1       0        DR      0
TextGridX       250.000000
!
TextGridY       6
EdgeGridX       250.000000
SIGNAL  dwb_ERR_I
ImportStartTime 0.000000
DIRECTION       input
ImportEndTime   281474976710656.000000
RADIX   hex
TimePerPixel    6.497175
GRID    0        1       0        1       0        16711680        0        0
Visible DELAYS  SETUPS  HOLDS   SAMPLES TEXT    HIDDENATTACHMENTS       CRITICALPATHS   GRIDLINES       UNCERTAINTY
ENDGRID -1
ColWidths       144,216,288,423,488
Clock   Unclocked
ScrollPos       0.000000,0.000009,0.000000
EdgeLevel       neg
DefDelayRule    1
Set     Not Used
NoEventOverlap  NO
Clear   Not Used
SigLabelFontHeight      10
ClockEnable     Not Used
LabelHeight     12
ActiveLowSetClear       True
LoadLibsToMem   1
AsyncSetClear   True
UseFullPathNames        1
ActiveLowClockEnable    True
LibPath
VhdlType        std_logic
EntireTime      YES
VerilogType     wire
PrintTimeSpecified      NO
SystemCType     sc_logic
FromTime        0
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
ToTime  5.75
StateEquation   Hex(Inc(0,2,5))
AllSignals      YES
HighVoltageThreshold    5
CurrSelSigs     NO
LowVoltageThreshold     0
PrintTo 2
SignalActionType        0
PrintFileName   C:\DOCS\reset.wmf
MSB     0
PreviewInterchange      YES
LSB     0
PreviewTIFF5    NO
isFallingEdgeSensitive  False
UseMargins      NO
isRisingEdgeSensitive   False
PrintTimeLine   NO
DrawAnalog      0
PrintBorderBox  YES
BooleanEquation
PrintSigNames   YES
NegTolerance    0
PrintSigNamesOnEachPage YES
PosTolerance    0
AddPreviewToEPS NO
UserSpecifiedSizeRatio  1
PreviewRes      150
VerilogCode
MarginLR        1.25
VHDLCode
MifImageWidth   6.00
PROPS!
MarginTB        Auto
E0      0        15625   15625           1       0        DR      0
Header  %d %t;%f;%p
!
Footer
ScaleHorz       100
SIGNAL  dwb_RTY_I
ScaleVert       100
DIRECTION       input
ScaleHPage      1
RADIX   hex
PrintImage      DIAGRAM
GRID    0        1       0        1       0        16711680        0        0
DefaultTimingModel      minmax
ENDGRID -1
DefaultClock    Unclocked
Clock   Unclocked
DefaultEdgeLevel        neg
EdgeLevel       neg
DefaultSet      Not Used
Set     Not Used
DefaultClear    Not Used
Clear   Not Used
DefaultClockEnable      Not Used
ClockEnable     Not Used
DefaultClockToOutLH     0
ActiveLowSetClear       True
DefaultClockToOutHL     0
AsyncSetClear   True
DefaultSetup    0
ActiveLowClockEnable    True
DefaultHold     0
VhdlType        std_logic
DefaultRegStartupState  unknown
VerilogType     wire
DefaultPodSize  8
SystemCType     sc_logic
DefaultActiveLowSetClear        True
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
DefaultAsyncSetClear    True
StateEquation   Hex(Inc(0,2,5))
DefaultActiveLowClockEnable     True
HighVoltageThreshold    5
SigLabelFontHeight      10
LowVoltageThreshold     0
PROPS!
SignalActionType        0
!
MSB     0
LSB     0
STYLE
isFallingEdgeSensitive  False
DefaultFont     USER    {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
isRisingEdgeSensitive   False
DrawWndFont     DEFAULT
DrawAnalog      0
DrawWndColor    DEFAULT
BooleanEquation
GridWndFont     DEFAULT
NegTolerance    0
GridWndColor    DEFAULT
PosTolerance    0
LabelWndFont    USER    {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
UserSpecifiedSizeRatio  1
LabelWndColor   DEFAULT
VerilogCode
ParamDispPref   0
VHDLCode
ParamWndCellDisplay     0
PROPS!
CustDispString  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
E0      0        15625   15625           1       0        DR      0
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
!
MarkerDispPref  4
MarkerCustDispString    %n v=%mv,%Mv d=%md %t
MARKER  MARK0
MarkerCustomDisplayStringRTF    {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
ATTACH  dwb_DAT_O       NULL    S4
SignalColor     2
TIME    7500.000000
LabelOffset     4
RELATIVETIME    0.000000
BusDisplay      0
DISPLAYAS       5
WaveFormWidth   0.500000
MARKERTYPE      Timebreak(Curved)
WaveFormColor   0
WHILERETURN
InputWaveFormColor      16711680
REPEATNUMBER
SlantedEdges    1
SNAPTO  0
SlantAngle      75
COMPRESSTIME    0.000000
RightJustifySigNames    1
COMMENT
AutosplitEnabled        1
!
AutosplitChar   _
DynamSizedSignals       1
Timing Diagram Editor v7.1g - Output File
!
PROJECT
DIAGRAMTESTBENCHSETTINGS
BaseTimeUnit    1
FilesBeforeDiagramModel
DisplayTimeUnit 2
FilesInsideDiagramModelDeclarationSection
TextGridX       250.000000
AbortHdlCodeEnabled     1
TextGridY       6
DelayHdlCodeEnabled     1
EdgeGridX       250.000000
SampleHdlCodeEnabled    1
ImportStartTime 0.000000
MarkerHdlCodeEnabled    1
ImportEndTime   281474976710656.000000
VerboseSamples  0
TimePerPixel    6.497175
VerboseDelays   0
Visible DELAYS  SETUPS  HOLDS   SAMPLES TEXT    HIDDENATTACHMENTS       CRITICALPATHS   GRIDLINES       UNCERTAINTY
VerboseFileInput        0
ColWidths       144,216,288,423,488
VerboseSequenceVerification     0
ScrollPos       0.000000,0.000000,0.000000
IncludeDelayTime        1
DefDelayRule    1
ExecuteFromTopLevel     1
NoEventOverlap  NO
TimeOutInDiagramLengths 0
SigLabelFontHeight      10
DefaultCycleClock       Unclocked
LabelHeight     12
DefaultCycleEdge        neg
LoadLibsToMem   1
!
UseFullPathNames        1
LibPath
MACROS
EntireTime      YES
!
PrintTimeSpecified      NO
FromTime        0
CORGROUP        $$CLK_I_BufferRising
ToTime  5.75
Percent 100
AllSignals      YES
!
CurrSelSigs     NO
PrintTo 2
CORGROUP        $$CLK_I_BufferFalling
PrintFileName   C:\DOCS\reset_gated.wmf
Percent 100
PreviewInterchange      YES
!
PreviewTIFF5    NO
UseMargins      NO
CORGROUP        $$CLK_I_BufferRisingFalling
PrintTimeLine   NO
Percent 100
PrintBorderBox  YES
!
PrintSigNames   YES
PrintSigNamesOnEachPage YES
CORGROUP        $$CLK_I_BufferRising
AddPreviewToEPS NO
Percent 100
PreviewRes      150
!
MarginLR        1.25
MifImageWidth   6.00
CORGROUP        $$CLK_I_BufferFalling
MarginTB        Auto
Percent 100
Header  %d %t;%f;%p
!
Footer
ScaleHorz       100
CORGROUP        $$CLK_I_BufferRisingFalling
ScaleVert       100
Percent 100
ScaleHPage      1
!
PrintImage      DIAGRAM
DefaultTimingModel      minmax
CORGROUP        $$CLK_I_BufferRising
DefaultClock    Unclocked
Percent 100
DefaultEdgeLevel        neg
!
DefaultSet      Not Used
DefaultClear    Not Used
CORGROUP        $$CLK_I_BufferFalling
DefaultClockEnable      Not Used
Percent 100
DefaultClockToOutLH     0
!
DefaultClockToOutHL     0
DefaultSetup    0
CORGROUP        $$CLK_I_BufferRisingFalling
DefaultHold     0
Percent 100
DefaultRegStartupState  unknown
!
DefaultPodSize  8
DefaultActiveLowSetClear        True
CORGROUP        $$CLK_I_BufferRising
DefaultAsyncSetClear    True
Percent 100
DefaultActiveLowClockEnable     True
!
SigLabelFontHeight      10
PROPS!
CORGROUP        $$CLK_I_BufferFalling
!
Percent 100
!
STYLE
DefaultFont     USER    {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
CORGROUP        $$CLK_I_BufferRisingFalling
DrawWndFont     DEFAULT
Percent 100
DrawWndColor    DEFAULT
!
GridWndFont     DEFAULT
GridWndColor    DEFAULT
CORGROUP        $$CLK_I_BufferRising
LabelWndFont    USER    {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
Percent 100
LabelWndColor   DEFAULT
!
ParamDispPref   0
ParamWndCellDisplay     0
CORGROUP        $$CLK_I_BufferFalling
CustDispString  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
Percent 100
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
!
MarkerDispPref  4
MarkerCustDispString    %n v=%mv,%Mv d=%md %t
CORGROUP        $$CLK_I_BufferRisingFalling
MarkerCustomDisplayStringRTF    {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
Percent 100
SignalColor     2
!
LabelOffset     4
BusDisplay      0
CORGROUP        $$CLK_I_BufferRising
WaveFormWidth   0.500000
Percent 100
WaveFormColor   0
!
InputWaveFormColor      16711680
SlantedEdges    1
CORGROUP        $$CLK_I_BufferFalling
SlantAngle      75
Percent 100
RightJustifySigNames    1
!
AutosplitEnabled        1
AutosplitChar   _
CORGROUP        $$CLK_I_BufferRisingFalling
DynamSizedSignals       1
Percent 100
!
!
DIAGRAMTESTBENCHSETTINGS
CORGROUP        $$CLK_RISC_BufferRising
FilesBeforeDiagramModel
Percent 100
FilesInsideDiagramModelDeclarationSection
!
AbortHdlCodeEnabled     1
DelayHdlCodeEnabled     1
CORGROUP        $$CLK_RISC_BufferFalling
SampleHdlCodeEnabled    1
Percent 100
MarkerHdlCodeEnabled    1
!
VerboseSamples  0
VerboseDelays   0
CORGROUP        $$CLK_RISC_BufferRisingFalling
VerboseFileInput        0
Percent 100
VerboseSequenceVerification     0
!
IncludeDelayTime        1
ExecuteFromTopLevel     1
CORGROUP        $$CLK_RISC_BufferRising
TimeOutInDiagramLengths 0
Percent 100
DefaultCycleClock       Unclocked
!
DefaultCycleEdge        neg
!
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
MACROS
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_I_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferRising
CORGROUP        $$CLK_I_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferFalling
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferRisingFalling
CORGROUP        $$CLK_I_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_I_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_I_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferRising
CORGROUP        $$CLK_I_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferFalling
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferRisingFalling
CORGROUP        $$CLK_I_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_I_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_I_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferRising
CORGROUP        $$CLK_I_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferFalling
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_I_BufferRisingFalling
CORGROUP        $$CLK_I_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_I_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_I_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_I_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_I_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_I_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_I_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_I_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRising
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferFalling
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$CLK_RISC_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferRising
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferFalling
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferRising
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferFalling
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferRising
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferFalling
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferRising
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferFalling
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferRising
CORGROUP        $$CLK_RISC_BufferFalling
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferFalling
CORGROUP        $$CLK_RISC_BufferRisingFalling
Percent 100
Percent 100
!
!
CORGROUP        $$clk_risc_BufferRisingFalling
CORGROUP        $$CLK_RISC_BufferRising
Percent 100
Percent 100
!
!
CLOCK   clk_risc
CORGROUP        $$CLK_RISC_BufferFalling
PERIODE 1
Percent 100
DUTY    50
!
OFFSETE 0
INITIAL LOW
CORGROUP        $$CLK_RISC_BufferRisingFalling
MAXUNCERTRISE   0
Percent 100
MAXUNCERTFALL   0
!
MINUNCERTRISE   0
MINUNCERTFALL   0
CORGROUP        $$CLK_RISC_BufferRising
JRISEE  0
Percent 100
JFALLE  0
!
GRID    1       1       1       2       2       16711680        0        0
ENDGRID -1
CORGROUP        $$CLK_RISC_BufferFalling
DIRECTION       input
Percent 100
MASTERCLOCK     None
!
Clock   Unclocked
EdgeLevel       neg
CORGROUP        $$CLK_RISC_BufferRisingFalling
Set     Not Used
Percent 100
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CORGROUP        $$CLK_RISC_BufferRising
AsyncSetClear   True
Percent 100
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
CORGROUP        $$CLK_RISC_BufferFalling
SystemCType     sc_logic
Percent 100
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
CORGROUP        $$CLK_RISC_BufferRisingFalling
LowVoltageThreshold     0
Percent 100
MSB     0
!
LSB     0
isFallingEdgeSensitive  False
CORGROUP        $$clk_risc_BufferRising
isRisingEdgeSensitive   True
Percent 100
DrawAnalog      0
!
BooleanEquation
NegTolerance    0
CORGROUP        $$clk_risc_BufferFalling
PosTolerance    0
Percent 100
UserSpecifiedSizeRatio  1
!
VerilogCode
VHDLCode
CORGROUP        $$clk_risc_BufferRisingFalling
PROPS!
Percent 100
E5      1       2500    2500            1       0        DR      0
!
E6      0        3000    3000            1       0        DR      0
E7      0        3500    3500            1       0        DR      0
CORGROUP        $$clk_risc_BufferRising
E9      1       4500    4500            1       0        DR      0
Percent 100
!
!
SIGNAL  rst
CORGROUP        $$clk_risc_BufferFalling
DIRECTION       input
Percent 100
RADIX   hex
!
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
CORGROUP        $$clk_risc_BufferRisingFalling
Clock   Unclocked
Percent 100
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
CORGROUP        $$clk_risc_BufferRising
ClockEnable     Not Used
Percent 100
ActiveLowSetClear       True
!
AsyncSetClear   True
ActiveLowClockEnable    True
CORGROUP        $$clk_risc_BufferFalling
VhdlType        std_logic
Percent 100
VerilogType     wire
!
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CORGROUP        $$clk_risc_BufferRisingFalling
StateEquation   Hex(Inc(0,2,5))
Percent 100
HighVoltageThreshold    5
!
LowVoltageThreshold     0
SignalActionType        0
CORGROUP        $$clk_risc_BufferRising
MSB     0
Percent 100
LSB     0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
CORGROUP        $$clk_risc_BufferFalling
DrawAnalog      0
Percent 100
BooleanEquation
!
NegTolerance    0
PosTolerance    0
CORGROUP        $$clk_risc_BufferRisingFalling
UserSpecifiedSizeRatio  1
Percent 100
VerilogCode
!
VHDLCode
PROPS!
CORGROUP        $$clk_risc_BufferRising
E0      0        1750    1750            1       0        DR      0
Percent 100
E1      1       3750    3750            1       0        DR      0
!
E2      0        5750    5750            1       0        DR      0
!
CORGROUP        $$clk_risc_BufferFalling
Percent 100
SIGNAL  dbg_dat_o
!
DIRECTION       output
RADIX   hex
CORGROUP        $$clk_risc_BufferRisingFalling
GRID    0        1       0        1       0        16711680        0        0
Percent 100
ENDGRID -1
!
Clock
EdgeLevel       neg
CORGROUP        $$clk_risc_BufferRising
Set     Not Used
Percent 100
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
CORGROUP        $$clk_risc_BufferFalling
AsyncSetClear   True
Percent 100
ActiveLowClockEnable    True
!
VhdlType        std_logic
VerilogType     wire
CORGROUP        $$clk_risc_BufferRisingFalling
SystemCType     sc_logic
Percent 100
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
!
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
CLOCK   clk_risc
LowVoltageThreshold     0
PERIODE 1
LSB     0
DUTY    50
MSB     31
OFFSETE 4.5
SignalActionType        0
INITIAL HIGH
isFallingEdgeSensitive  False
MAXUNCERTRISE   0
isRisingEdgeSensitive   True
MAXUNCERTFALL   0
DrawAnalog      0
MINUNCERTRISE   0
BooleanEquation
MINUNCERTFALL   0
NegTolerance    0
JRISEE  0
PosTolerance    0
JFALLE  0
UserSpecifiedSizeRatio  1
GRID    1       1       0        2       2       16711680        0        0
VerilogCode
ENDGRID -1
VHDLCode
DIRECTION       input
VhdlMapping     DefaultVhdlMapping
MASTERCLOCK     None
PROPS!
Clock   Unclocked
E0      X       1750    1750            1       0        DR      0
EdgeLevel       neg
E1      V       4750    4750    0x0     1       0        DR      0
Set     Not Used
E2      V       5750    5750    0x4     1       0        DR      0
Clear   Not Used
!
ClockEnable     Not Used
ActiveLowSetClear       True
SIGNAL  dbg_op_i
AsyncSetClear   True
DIRECTION       input
ActiveLowClockEnable    True
RADIX   hex
VhdlType        std_logic
GRID    0        1       0        1       0        16711680        0        0
VerilogType     wire
ENDGRID -1
SystemCType     sc_logic
Clock   Unclocked
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
EdgeLevel       neg
StateEquation   Hex(Inc(0,2,5))
Set     Not Used
HighVoltageThreshold    5
Clear   Not Used
LowVoltageThreshold     0
ClockEnable     Not Used
MSB     0
ActiveLowSetClear       True
LSB     0
AsyncSetClear   True
isFallingEdgeSensitive  False
ActiveLowClockEnable    True
isRisingEdgeSensitive   True
VhdlType        std_logic
DrawAnalog      0
VerilogType     wire
BooleanEquation
SystemCType     sc_logic
NegTolerance    0
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
PosTolerance    0
StateEquation   Hex(Inc(0,2,5))
UserSpecifiedSizeRatio  1
HighVoltageThreshold    5
VerilogCode
LowVoltageThreshold     0
VHDLCode
SignalActionType        0
PROPS!
MSB     3
E5      1       7000    7000            1       0        DR      0
LSB     0
E6      0        7500    7500            1       0        DR      0
isFallingEdgeSensitive  False
E7      1       8000    8000            1       0        DR      0
isRisingEdgeSensitive   False
E9      1       9000    9000            1       0        DR      0
DrawAnalog      0
!
BooleanEquation
NegTolerance    0
SIGNAL  rst
PosTolerance    0
DIRECTION       input
UserSpecifiedSizeRatio  1
RADIX   hex
VerilogCode
GRID    0        1       0        1       0        16711680        0        0
VHDLCode
ENDGRID -1
PROPS!
Clock   Unclocked
E0      V       5750    5750    READ PC 0x0     1       0        DR      0
EdgeLevel       neg
!
Set     Not Used
Clear   Not Used
PARM    Trs
ClockEnable     Not Used
MIN     NULL
ActiveLowSetClear       True
MAX     NULL
AsyncSetClear   True
COMMENT Reset Setup Time
ActiveLowClockEnable    True
NameRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont Trs}
VhdlType        std_logic
MinRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont}
VerilogType     wire
MaxRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont}
SystemCType     sc_logic
CommentRTF      {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont Reset Setup Time}
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
CLOCKNAME       Unclocked
StateEquation   Hex(Inc(0,2,5))
CLOCKEDGE       neg
HighVoltageThreshold    5
IsApplyInput    False
LowVoltageThreshold     0
PROPS!
SignalActionType        0
!
MSB     0
LSB     0
PARM    Trh
isFallingEdgeSensitive  False
MIN     NULL
isRisingEdgeSensitive   False
MAX     NULL
DrawAnalog      0
COMMENT Reset Hold Time
BooleanEquation
NameRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont Trh}
NegTolerance    0
MinRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont}
PosTolerance    0
MaxRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont}
UserSpecifiedSizeRatio  1
CommentRTF      {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont Reset Hold Time}
VerilogCode
CLOCKNAME       Unclocked
VHDLCode
CLOCKEDGE       neg
PROPS!
IsApplyInput    False
E0      0        1750    1750            1       0        DR      0
PROPS!
E1      1       3750    3750            1       0        DR      0
!
E2      0        5750    5750            1       0        DR      0
!
SETUP   Trs
FROM    clk_risc        E9      S0
SIGNAL  dbg_dat_o
TO      rst     E1      S1
DIRECTION       output
OUTARROWS       0
RADIX   hex
USERPLACED      0
GRID    0        1       0        1       0        16711680        0        0
DISPLAYAS       6
ENDGRID -1
CUSTDISPSTRING  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
Clock
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
EdgeLevel       neg
EnableHdlCodeGeneration False
Set     Not Used
OrderIndex      1
Clear   Not Used
PROPS!
ClockEnable     Not Used
!
ActiveLowSetClear       True
AsyncSetClear   True
HOLD    Trh
ActiveLowClockEnable    True
FROM    clk_risc        E7      S0
VhdlType        std_logic
TO      rst     E1      S1
VerilogType     wire
OUTARROWS       0
SystemCType     sc_logic
USERPLACED      0
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
DISPLAYAS       6
StateEquation   Hex(Inc(0,2,5))
CUSTDISPSTRING  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
HighVoltageThreshold    5
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
LowVoltageThreshold     0
EnableHdlCodeGeneration False
LSB     0
OrderIndex      2
MSB     31
PROPS!
SignalActionType        0
!
isFallingEdgeSensitive  False
isRisingEdgeSensitive   True
MARKER  MARK0
DrawAnalog      0
ATTACH  rst     NULL    S1
BooleanEquation
TIME    2750.000000
NegTolerance    0
RELATIVETIME    0.000000
PosTolerance    0
DISPLAYAS       5
UserSpecifiedSizeRatio  1
MARKERTYPE      Timebreak(Curved)
VerilogCode
WHILERETURN
VHDLCode
REPEATNUMBER
VhdlMapping     DefaultVhdlMapping
SNAPTO  0
PROPS!
COMPRESSTIME    0.000000
E0      X       1750    1750            1       0        DR      0
COMMENT
E1      V       4750    4750    0x0     1       0        DR      0
!
E2      V       5750    5750    0x4     1       0        DR      0
!
P&l   1Q
&" WMFC YyxjP&l EMFys     XVISIODrawing
 %RL Arial%Tl!y
SIGNAL  dbg_op_i
@
DIRECTION       input
@!yLXSET 0--)%Tl!
RADIX   hex
@
GRID    0        1       0        1       0        16711680        0        0
@!LXSET 1--)%RL Arial^0`>j8p2bP<pj8X rif design, Arial contains more humast characteristics than many of its predecessors and as such ie %T`b        6
ENDGRID -1

Clock   Unclocked
@
EdgeLevel       neg
@b        LT...haRL Arialhich helps to give the face a less mechanical appece.  Arial is an extremely versatile family of typefaces which can be used with equal success for text setting in reports, prentations, magazines etc, and for display use in newspapers, adw.%T`=      
S

Set     Not Used
@
Clear   Not Used
@= 
LTSETIC--)RL Arialts use by you is covered under the terms of a liceagreement. You have obtained this typeface software either directly from Monotype or together with software distributed by onef Monotypes licensees.
ClockEnable     Not Used
ActiveLowSetClear       True
This software is a valuable asset od %TTJ
     

AsyncSetClear   True
@
ActiveLowClockEnable    True
@J
LPIe RL Arialdistribute this software.
VhdlType        std_logic
VerilogType     wire
If you have any questconcerning your rights you should review the license agreement you received with the software or contact Monotype for a copy othe license agreement.
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
Monotype can be contacted at:
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
USA7 %T
LowVoltageThreshold     0
J
x

SignalActionType        0
@
MSB     3
@
LSB     0
J
isFallingEdgeSensitive  False
L`TLB_SETS-1&%%V09
:

::
%(RL Arial2. All Rights ReservedAriRegularMonotype:Arial Regular:Version 2.76 (Microsoft)ArialVerson 2.76ArialMTArial Trademark o%(RL Arial & TM Off. and elsewhere.notype TypographyMonotype Type Drawing Office - Robin Nicholas,Patricia Saunders 1982Contempors%(RL Arialacteristics than many of s predecessors and as such is more in tune with the mood of thelast decades of the twentieth ca%(RL Arialuller than in most industal style sans serif faces.  Terminal strokes are cut on the diaonal which helps to give the fac%(RL Arialversatile family of typefes which can be used with equal success for text setting in reprts, presentations, magazines ea%(RL Arialromotions.http://www.monop* !#0%`')<)***:*,r-P.../133344555&5666(6866707@8*8:8J8Z9f::;
isRisingEdgeSensitive   False
%(RL ArialL0MMLNpNNNNOPQQR*RSSTTTWXlXY"Z@ZZZ[[[[[\]]^B^_`Vaabbcde&fRfgXghizjkkm mooo%(RL ArialH:x2
DrawAnalog      0
NvBv>~h(^<`pBp2~H%(%
(%RL Arialz$bzB jt<
BooleanEquation
Hæ(ƆưǒǼBl˖@j͔;<fΐBм(R|Ҧ%Tl[{
NegTolerance    0
@
PosTolerance    0
@[LXVPN 0--0%Tl{
UserSpecifiedSizeRatio  1
@
VerilogCode
@LXVPN 1--0%RL Arial J
VHDLCode
B
Vn~>NdJZn~H  !"l"#$2%&z&'"'2'(((*++-<-L//113:3J4:4J55%T`    7
PROPS!

E0      V       5750    5750    READ PC 0x0     1       0        DR      0
@
!
@        LT...RL Arial[[^0`zcehgjbl2mnn@nPnnnnno(oRoboroooppp p0p@pPpzppppqqBqlqqqrr>rrrss:sdssstt6t`ttt%(%T`,
Md

@
MARKER  MARK0
@,
LTVPN!!$Th


ATTACH  rst     NULL    S1
@
TIME    2750.000000
@h
LdITLB_SETS-1!!!!&%%V0j        MkL L     kkL%(%RL ArialB
RELATIVETIME    0.000000
PZ&L~f"v&N4f@n(^0`>j8p%T~b
DISPLAYAS       5
@
MARKERTYPE      Timebreak(Curved)
@LpEFFECTIVE ADDRESS a-))-0(---000---&%&" WMFC 9y%V0F6        
G
5 
5     GG
%(RL Arialpearance.  Arial is an extremely versatile family ypefaces which can be used with equal success for text setting in reports, presentations, magazines etc, and for display use inewspapers, advertising and promotions.http://www.monotype.comww%(RL Arial
WHILERETURN
This typeface is the property of Monotype Typogr and its use by you is covered under the terms of a li6"BbJr&P|>h*n%(RL Arialhpvxp4>.^"RBrT      
REPEATNUMBER
0
SNAPTO  0
`
COMPRESSTIME    0.000000

COMMENT

!
Dt%(RL Arial4d4d* !#0%`')<)***:*,r-P.../133344555&565F66(686707@8*8:8J8Z9f::;
;@;p;;<%(RL ArialNNNOPQQR*RRSSTTWXlXY"Z@ZZZ[[[[[\]]^B^_`Vaabbccde&fRfghizjkkm mooopRpbprpp%(RL Arialx2

NvBv>~h(^<`pB2~HL%(RL Arial*hz$bzB jt<
Q<=KuyTiming DiagramTiming.Document.19qTiming Diagram
Hæ(ƆưǒǼBl@j͔;<fΐBм%(%
(%RL Arial&PPV
FMicrosoft Visio DrawingVISIO 6.0 ShapesVisio.Drawing.69qTiming Diagram Editor v7.1g - Output File
@Bz(R|$Nx JtFpBl^t~  J%Tl]o
@
PROJECT
@]oLXPPN 0--0%Tl] 
BaseTimeUnit    1
@
DisplayTimeUnit 2
@]LXPPN 1--0%%T`    ,
TextGridX       250.000000

TextGridY       6
@
EdgeGridX       250.000000
@        LT...RL Arialnnnnno(oRoborooopp p0p@pPpzppppqqBqlqqqrr>rhrrrss:sdssstt6t`ttuu2u\uuuvv.vXvvvww*%TI

ImportStartTime 0.000000
@
ImportEndTime   281474976710656.000000
@LlPPN ITLB_SETS-2--0)%-%--)-%TO


TimePerPixel    6.497175
@
Visible DELAYS  SETUPS  HOLDS   SAMPLES TEXT    HIDDENATTACHMENTS       CRITICALPATHS   GRIDLINES       UNCERTAINTY
@O
LlPPN ITLB_SETS-1--0)%-%--)-%%
(&%%V0        M     LL          L%(%
(%
(&%%V0MLLL%(%
(&
ColWidths       144,216,288,423,488

ScrollPos       0.000000,0.000009,0.000000

DefDelayRule    1

NoEventOverlap  NO

SigLabelFontHeight      10

LabelHeight     12

LoadLibsToMem   1
UseFullPathNames        1
LibPath
EntireTime      YES
PrintTimeSpecified      NO

FromTime        0
ToTime  5.75

AllSignals      YES

CurrSelSigs     NO

PrintTo 2

PrintFileName   C:\DOCS\reset.wmf

PreviewInterchange      YES

PreviewTIFF5    NO

UseMargins      NO

PrintTimeLine   NO

PrintBorderBox  YES

PrintSigNames   YES

PrintSigNamesOnEachPage YES

AddPreviewToEPS NO

PreviewRes      150

MarginLR        1.25

MifImageWidth   6.00

MarginTB        Auto

Header  %d %t;%f;%p

Footer
ScaleHorz       100
!
ScaleVert       100
"
ScaleHPage      1
#
PrintImage      DIAGRAM
$
DefaultTimingModel      minmax
%
DefaultClock    Unclocked
&
DefaultEdgeLevel        neg
'
DefaultSet      Not Used
(
DefaultClear    Not Used
)
DefaultClockEnable      Not Used
*
DefaultClockToOutLH     0
+
DefaultClockToOutHL     0
,
DefaultSetup    0
-
DefaultHold     0
.
DefaultRegStartupState  unknown
/
DefaultPodSize  8
0
DefaultActiveLowSetClear        True
1
DefaultAsyncSetClear    True
2
DefaultActiveLowClockEnable     True
3
SigLabelFontHeight      10
4
PROPS!
5
!
6
7
STYLE
8
DefaultFont     USER    {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
9
DrawWndFont     DEFAULT
DrawWndColor    DEFAULT
<
GridWndFont     DEFAULT
=
GridWndColor    DEFAULT
>
LabelWndFont    USER    {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
?
LabelWndColor   DEFAULT
@
ParamDispPref   0
A
ParamWndCellDisplay     0
B
CustDispString  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
C
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
D
MarkerDispPref  4
E
MarkerCustDispString    %n v=%mv,%Mv d=%md %t
F
MarkerCustomDisplayStringRTF    {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
G
SignalColor     2
H
LabelOffset     4
I
BusDisplay      0
J
WaveFormWidth   0.500000
K
WaveFormColor   0
L
InputWaveFormColor      16711680
M
SlantedEdges    1
N
SlantAngle      75
O
RightJustifySigNames    1
P
AutosplitEnabled        1
Q
AutosplitChar   _
R
DynamSizedSignals       1
S
!
T
U
DIAGRAMTESTBENCHSETTINGS
V
FilesBeforeDiagramModel
W
FilesInsideDiagramModelDeclarationSection
X
AbortHdlCodeEnabled     1
Y
DelayHdlCodeEnabled     1
Z
SampleHdlCodeEnabled    1
[
MarkerHdlCodeEnabled    1
\
VerboseSamples  0
]
VerboseDelays   0
^
VerboseFileInput        0
_
VerboseSequenceVerification     0
`
IncludeDelayTime        1
a
ExecuteFromTopLevel     1
b
TimeOutInDiagramLengths 0
d
DefaultCycleClock       Unclocked
e
DefaultCycleEdge        neg
f
!
g
h
MACROS
i
!
j
k
CORGROUP        $$CLK_I_BufferRising
l
Percent 100
m
!
n
o
CORGROUP        $$CLK_I_BufferFalling
p
Percent 100
q
!
r
s
CORGROUP        $$CLK_I_BufferRisingFalling
t
Percent 100
u
!
v
w
CORGROUP        $$CLK_I_BufferRising
x
Percent 100
y
!
z
{
CORGROUP        $$CLK_I_BufferFalling
|
Percent 100
}
!
~

CORGROUP        $$CLK_I_BufferRisingFalling
Percent 100
%%W,C$L--%(&%%W,Z
Y
Y
%(&%%W,CK
!
BLB
%(%%V0%%%%RL Arial%Txk
CORGROUP        $$CLK_I_BufferRising
@
Percent 100
@kL\TLB SET)%---)Tl
!
@
@LXINDEX00-+&%W$
CORGROUP        $$CLK_I_BufferFalling
a
Percent 100

!
X
%(%%V,N       =
CORGROUP        $$CLK_I_BufferRisingFalling
N       
Percent 100
N=
!
N     &%%V0
%(%%TdX
@
CORGROUP        $$CLK_I_BufferRising
@XLTCOMP047-&%W$qh%(%%V,}^^}^^&%%W$
$q
h%(%%V,^BB^^B^&%%V0%(%
(%%T`'q
Percent 100
@
!
@'LTINV0-&%W$Wi@``7%(%%V,9..`9..RL
CORGROUP        $$CLK_I_BufferFalling
 Arial%(%
(%%Tl8#
Percent 100
@
!
@LXHIT 00)%%
(RL Arial%TX
@
CORGROUP        $$CLK_I_BufferRisingFalling
@LP31%%RL Arial&" WMFC yp
Percent 100
      
!
%T`
@
CORGROUP        $$CLK_I_BufferRising
@LTlogRL Arial()*+,-/0123456789:;<=?@ABCDE%TT
Percent 100

!
@
@LP2, RL Arialessors and as such is more in tune with the mood oe last decades of the twentieth century.  The overall treatment of curves is softer and fuller than in most industrial style ss serif faces.  Terminal strokes are cut on the diagonal whichha%(%T    
CORGROUP        $$CLK_I_BufferFalling
@
Percent 100
@Lh(ITLB_SETS)+13!!!!%
(RL Arialtname/ms_welcome.htmlNOTIFICATION OF LICENSE AGREE
!
This typeface is the property of Monotype Typography and its use by you is covered under the terms of a license agreement.ou have obtained this typeface software either directly from Mdi%TXI
CORGROUP        $$CLK_I_BufferRisingFalling
@
Percent 100
@ILP13%%%TT
!
@
@LP0it%RL Arialte this software.
CORGROUP        $$CLK_I_BufferRising
Percent 100
If you have any question concng your rights you should review the license agreement you received with the software or contact Monotype for a copy of the linse agreement.
!
Monotype can be contacted at:
CORGROUP        $$CLK_I_BufferFalling
Percent 100
USA - (847)
!
%Tl
@
CORGROUP        $$CLK_I_BufferRisingFalling
@LXWAY 0nO98.&%W${%(%%V,%RL
Percent 100
!
 ArialialRegularMonotype:Arial gular:Version 2.76 (Microsoft)ArialVersion 2.76ArialMTArial Trdemark of The Monotype Corporatd%TP
@
CORGROUP        $$CLK_RISC_BufferRising
@     L`ITLB MISSr)%-7--Tl
Percent 100
@
!
@l     L`EXCEPTIONe-+0--)40%
(%
(RL Arialy of its predecessors ands such is more in tune with the mood of the last decades of thetwentieth century.  The overallv%TX

@
CORGROUP        $$CLK_RISC_BufferFalling
@LP12%%&%W$%(%%V,&%%W$%(&%%W$

%(&%%W$%(%%V9 
Percent 100

!
     &%%W${%(%%V,%
(%
(%RL
CORGROUP        $$CLK_RISC_BufferRisingFalling
 Arial
Percent 100
`
!


CORGROUP        $$CLK_RISC_BufferRising
DtD.@xB^,\&V44d* !#0%`%Tj
Percent 100
@
!
@jLdPADDR[31:13]--000%%%%&%W(CGL>%(&%%W$53>*%(%%V,!     !!       !RL ArialzzT{{|||}}~~:x2
NvBv>~h^<`pB%(%%T~T
CORGROUP        $$CLK_RISC_BufferFalling
@
Percent 100
@~LdPAGE OFFSET--4-4))--)TF1
!
@
@FLdPADDR[12:0]--000%%%%
(RL Arial0Z,V(R|&PPV
CORGROUP        $$CLK_RISC_BufferRisingFalling
@BzR|$Nx Jt%(RL Arialn~>NdJZn~H  !"l"#$2%&z&'"'2'((()*++-<-L//13:3J4:4J5577 8`8p88:::(%(%
(RL ArialWdWtWWY2Z[[^0`zcehgl2mnn@nPn`nnnnno(oRoboroooppp p0p@pPpzppppqqBqqqrr>rhrrrss:sdsss%T`
Percent 100
P
!

@
CORGROUP        $$CLK_I_BufferRising
@
Percent 100
LTlogRL Arial}~~B~l~~~(\xzJ.(Fn(^`Tjbr**<(:L^p%TTQ
!
b

CORGROUP        $$CLK_I_BufferFalling
@
Percent 100
@Q
!
LP2RL Arial~f"v&N4f@n(^
&WMFCy0`>j8p2bP<pj8X m%Tc

CORGROUP        $$CLK_I_BufferRisingFalling
@
Percent 100
@c
!
Lh(ITLB_SETS)+12!!!!&%W$      %(%%V0zb
zb
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zz%RL Arialpvxp4>.^"RBrT 

CORGROUP        $$CLK_RISC_BufferRising
0
Percent 100
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!

DtD.@%TY
.
CORGROUP        $$CLK_RISC_BufferFalling
@
Percent 100
@LlD & A attributes0--%%%%"&%%V0`
!
fa
eea
CORGROUP        $$CLK_RISC_BufferRisingFalling
a
Percent 100
e%(%
(%RL ArialQR*RRSSTTTWXlXY"ZZZ[[[[[\]]^B^_`Vaabbccde&fRfgXghizjkkmooopRpbprpprrrsstpu^%T
!
]
@
CORGROUP        $$CLK_I_BufferRising
@
Percent 100

!
L`PAGE FAULT--4-)-0%)&%W$0    B      9    9%(%%V, a
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9     `     &%%W$0  9     %(%
(%%V0mMmMMmmM%RL Arial(R|ҦP\׊ך&l8޾^0Z,V(R|&PPV
Percent 100
@Bz%Txv.
!
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CORGROUP        $$CLK_I_BufferRisingFalling
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Percent 100
@4LP]&%W$               %(%%V, a
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     a
          &%%W$                %(%
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(%%V0} }      }}RL Arialtt6t`tttuu2u\uuuvvXvvvww*wTw~wwwx&xPxzxxxy"yLyvzzZzz{${N{x{{{| |t|||}}F}p}}}~~B~l~~%(%RL Arialr**<(:L^p06 `.xHRdrf,`B%TpB 
CORGROUP        $$CLK_RISC_BufferRising
@
Percent 100
@BLXACCESS-00---Tdg        
!
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@
Percent 100
@z
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L`ATTRIBUTES-))0-0)--&%W$\e%(%%V,ffRL
!
 Arial#XX>C',f(QArialArial%(%RL
CORGROUP        $$CLK_I_BufferRising
Percent 100
 ArialE-ChQ ArialArialCCMT316eafa793t%T
2
!
@
@     L`DMMU PAGEX0770--4-TlQL$
CORGROUP        $$CLK_I_BufferFalling
@
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@QLLXFAULT)-0%)T?
!
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.-C Arial???????-2
!
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TLB_SETS-1--$:

::
-C Arial2. All Rights ReservedAri-C Arial & TM Off. and elsewhere.-C Arialacteristics than many of -C Arialuller than in most indust-C Arialversatile family of typef-2 Arialromotions.http://www.mono-2 Arial?A?A?A?A?A?A?A?A?A?A?A?A?-2 Arial?A?A?A?A?A?A?A?A?A?A?A?A?-     "System cpxρ/--C Arial?A?A?A?A?A?A?A?A?A?A?A?A?-2
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Percent 100
C Arial?A?A?A?A?A?A?A?A?A?A?A?A?-
!
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---$%%-C Arial-2
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'INV0--%``7---$.`9..C
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2
!
31%%2 Arial-2
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!
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!
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!
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!
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~PAGE OFFSET--4-4))--)2
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DIRECTION       input
MASTERCLOCK     None
Clock   Unclocked
EdgeLevel       neg
Set     Not Used
Clear   Not Used
ClockEnable     Not Used
ActiveLowSetClear       True
AsyncSetClear   True
ActiveLowClockEnable    True
VhdlType        std_logic
VerilogType     wire
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
LowVoltageThreshold     0
MSB     0
LSB     0
isFallingEdgeSensitive  False
isRisingEdgeSensitive   True
DrawAnalog      0
BooleanEquation
NegTolerance    0
PosTolerance    0
UserSpecifiedSizeRatio  1
VerilogCode
VHDLCode
PROPS!
E5      1       2500    2500            1       0        DR      0
E6      0        3000    3000            1       0        DR      0
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E7      0        3500    3500            1       0        DR      0
E9      1       4500    4500            1       0        DR      0
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SIGNAL  rst
DIRECTION       input
RADIX   hex
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
Clock   Unclocked
EdgeLevel       neg
Set     Not Used
Clear   Not Used
ClockEnable     Not Used
ActiveLowSetClear       True
AsyncSetClear   True
ActiveLowClockEnable    True
VhdlType        std_logic
VerilogType     wire
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
LowVoltageThreshold     0
SignalActionType        0
MSB     0
LSB     0
isFallingEdgeSensitive  False
isRisingEdgeSensitive   False
DrawAnalog      0
BooleanEquation
NegTolerance    0
PosTolerance    0
UserSpecifiedSizeRatio  1
VerilogCode
VHDLCode
PROPS!
E0      0        1750    1750            1       0        DR      0
E1      1       3750    3750            1       0        DR      0
E2      0        5750    5750            1       0        DR      0
!
SIGNAL  dbg_dat_o
DIRECTION       output
RADIX   hex
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
Clock
EdgeLevel       neg
Set     Not Used
Clear   Not Used
ClockEnable     Not Used
ActiveLowSetClear       True
AsyncSetClear   True
ActiveLowClockEnable    True
VhdlType        std_logic
VerilogType     wire
SystemCType     sc_logic
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
StateEquation   Hex(Inc(0,2,5))
HighVoltageThreshold    5
LowVoltageThreshold     0
LSB     0
MSB     31
SignalActionType        0
isFallingEdgeSensitive  False
isRisingEdgeSensitive   True
DrawAnalog      0
BooleanEquation
NegTolerance    0
PosTolerance    0
UserSpecifiedSizeRatio  1
VerilogCode
VHDLCode
VhdlMapping     DefaultVhdlMapping
PROPS!
E0      X       1750    1750            1       0        DR      0
E1      V       4750    4750    0x0     1       0        DR      0
E2      V       5750    5750    0x4     1       0        DR      0
!
SIGNAL  dbg_op_i
DIRECTION       input
RADIX   hex
GRID    0        1       0        1       0        16711680        0        0
ENDGRID -1
Clock   Unclocked
EdgeLevel       neg
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Set     Not Used
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Clear   Not Used
ClockEnable     Not Used
PROJECT
ActiveLowSetClear       True
BaseTimeUnit    1
AsyncSetClear   True
DisplayTimeUnit 2
ActiveLowClockEnable    True
TextGridX       625.000000
VhdlType        std_logic
TextGridY       6
VerilogType     wire
EdgeGridX       625.000000
SystemCType     sc_logic
ImportStartTime 0.000000
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
ImportEndTime   281474976710656.000000
StateEquation   Hex(Inc(0,2,5))
TimePerPixel    17.543860
HighVoltageThreshold    5
Visible DELAYS  SETUPS  HOLDS   SAMPLES TEXT    HIDDENATTACHMENTS       CRITICALPATHS   GRIDLINES       UNCERTAINTY
LowVoltageThreshold     0
ColWidths       144,216,288,423,488
SignalActionType        0
ScrollPos       0.000000,0.000000,0.000000
MSB     3
DefDelayRule    1
LSB     0
NoEventOverlap  NO
isFallingEdgeSensitive  False
SigLabelFontHeight      8
isRisingEdgeSensitive   False
LabelHeight     10
DrawAnalog      0
LoadLibsToMem   1
BooleanEquation
UseFullPathNames        1
NegTolerance    0
LibPath
PosTolerance    0
EntireTime      YES
UserSpecifiedSizeRatio  1
PrintTimeSpecified      NO
VerilogCode
FromTime        0
VHDLCode
ToTime  15.625
PROPS!
AllSignals      YES
E0      V       5750    5750    READ PC 0x0     1       0        DR      0
CurrSelSigs     NO
!
PrintTo 2
PrintFileName   C:\DOCS\wb_writesingle.wmf
PARM    Trs
PreviewInterchange      YES
MIN     NULL
PreviewTIFF5    NO
MAX     NULL
UseMargins      NO
COMMENT Reset Setup Time
PrintTimeLine   NO
NameRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont Trs}
PrintBorderBox  YES
MinRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont}
PrintSigNames   YES
MaxRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont}
PrintSigNamesOnEachPage YES
CommentRTF      {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont Reset Setup Time}
AddPreviewToEPS NO
CLOCKNAME       Unclocked
PreviewRes      150
CLOCKEDGE       neg
MarginLR        1
IsApplyInput    False
MifImageWidth   6.00
PROPS!
MarginTB        Auto
!
Header  %d %t;%f;%p
Footer
PARM    Trh
ScaleHorz       100
MIN     NULL
ScaleVert       100
MAX     NULL
ScaleHPage      1
COMMENT Reset Hold Time
PrintImage      DIAGRAM
NameRTF {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont Trh}
DefaultTimingModel      minmax
MinRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont}
DefaultClock    Unclocked
MaxRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont}
DefaultEdgeLevel        neg
CommentRTF      {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont Reset Hold Time}
DefaultSet      Not Used
CLOCKNAME       Unclocked
DefaultClear    Not Used
CLOCKEDGE       neg
DefaultClockEnable      Not Used
IsApplyInput    False
DefaultClockToOutLH     0
PROPS!
DefaultClockToOutHL     0
!
DefaultSetup    0
DefaultHold     0
SETUP   Trs
DefaultRegStartupState  unknown
FROM    clk_risc        E9      S0
DefaultPodSize  8
TO      rst     E1      S1
DefaultActiveLowSetClear        True
OUTARROWS       0
DefaultAsyncSetClear    True
USERPLACED      0
DefaultActiveLowClockEnable     True
DISPLAYAS       6
SigLabelFontHeight      10
CUSTDISPSTRING  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
PROPS!
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
!
EnableHdlCodeGeneration False
OrderIndex      1
STYLE
PROPS!
DefaultFont     USER    {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
!
DrawWndFont     DEFAULT
DrawWndColor    DEFAULT
HOLD    Trh
GridWndFont     DEFAULT
FROM    clk_risc        E7      S0
GridWndColor    DEFAULT
TO      rst     E1      S1
LabelWndFont    USER    {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
OUTARROWS       0
LabelWndColor   DEFAULT
USERPLACED      0
ParamDispPref   0
DISPLAYAS       6
ParamWndCellDisplay     0
CUSTDISPSTRING  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
CustDispString  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
EnableHdlCodeGeneration False
MarkerDispPref  4
OrderIndex      2
MarkerCustDispString    %n v=%mv,%Mv d=%md %t
PROPS!
MarkerCustomDisplayStringRTF    {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
!
SignalColor     2
LabelOffset     2
MARKER  MARK0
BusDisplay      0
ATTACH  rst     NULL    S1
WaveFormWidth   0.500000
TIME    2750.000000
WaveFormColor   0
RELATIVETIME    0.000000
InputWaveFormColor      16711680
DISPLAYAS       5
SlantedEdges    1
MARKERTYPE      Timebreak(Curved)
SlantAngle      75
WHILERETURN
RightJustifySigNames    1
REPEATNUMBER
AutosplitEnabled        1
SNAPTO  0
AutosplitChar   _
COMPRESSTIME    0.000000
DynamSizedSignals       1
COMMENT
!
!
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0
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SampleHdlCodeEnabled    1
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VerboseSequenceVerification     0
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IncludeDelayTime        1
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ExecuteFromTopLevel     1
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DefaultCycleClock       Unclocked
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CORGROUP        $$CLK_RISC_BufferRisingFalling
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Percent 100
@s1
LTSET--)RL Arial%T6r
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!
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CORGROUP        $$CLK_I_BufferRising
PZ&L%(RL Arial0`>j8p2bP<pj8X rif design, Arial contains more humanistharacteristics than many of its predecessors and as such is most%(RL Arialr and fuller than in most industrial style sans sefaces.  Terminal strokes are cut on the diagonal which helps to give the face a less mechanical appearance.  Arial is an extrely versatile family of typefaces which can be used with equal s,%(%RL Arialwww.monotype.com/html/mtname/ms_arial.htmlhttp://wonotype.com/html/mtname/ms_welcome.htmlNOTIFICATION OF LICENSE AGREEMENT
Percent 100
!
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@
CORGROUP        $$CLK_I_BufferFalling
@oLXTAG 0pe)-4%Tl 
Percent 100
@
!
@LXTAG 1 y)-4%RL Arialishing use. You may not copy or distribute this sore.
CORGROUP        $$CLK_I_BufferRisingFalling
If you have any question concerning your rights you should review the license agreement you received with the software  contact Monotype for a copy of the license agreement.
Percent 100
!
Mono (%T`5       m,

CORGROUP        $$CLK_RISC_BufferRising
@
Percent 100
@5        LT...peRL Arialypeface  The Monotype Cooration plc. Data  The Monotype Corporation plc/Type SolutionsInc. 1990-1992. All Rights Reseo%T`I

!
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CORGROUP        $$CLK_RISC_BufferFalling
@
Percent 100
@O
     L`IC_SETS-1 0%--)-%&%%V0
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CORGROUP        $$CLK_RISC_BufferRisingFalling
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Percent 100
@
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%(RL Arial appearance.  Arial is anxtremely versatile family of typefaces which can be used with eual success for text seBb%(RL Arial bHdB((hpvxp4>.^"RBr%(RL ArialB^,\&V4d4d* !#0%`')<)***,r-P.../133344555&%(%RL ArialEFGHIKKFK~KKL
L0MNpNNNNOPQQR*RRSSTTTWXlXY"Z@ZZZ[[[[[\]^B^_`Vaabbccde&fRf%Tpo`
CORGROUP        $$CLK_I_BufferRising
@
Percent 100
@oLXWord 0B%%%Tp`     
!
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@LXWord 1B%%%%T`        ,
CORGROUP        $$CLK_I_BufferFalling

Percent 100
@&" WMFC E
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Percent 100
@LhWord IC_SETS-2B%%0%--)-%TO


!
@
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LHLH
!

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CORGROUP        $$CLK_RISC_BufferRisingFalling
@d7
Percent 100
7[%(%%V,Q^^Q7Q^Q%%V0ccc&%%666#6'+6/367;6?C6GK6OS6W[6_c6gk6os6w{666666666666666666666#6'+6/367;6?C6GK6OS6W[6_c6gk6os6w{666666666666666666666#6'+6/367;6?C6GK6OS6W[6_c6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6c{cw6csco6ckcg6ccc_6c[cW6cScO6cKcG6cCc?6c;c76c3c/6c+c'6c#c6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6c{cw6csco6ckcg6ccc_6c[cW6cScO6cKcG6cCc?6c;c76c3c/6c+c'6c#c6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6cc6c6`\6XT6PL6HD6@<68460,6($6 66666666666666666666|6xt6pl6hd6`\6XT6PL6HD6@<68460,6($6 6666666666&" WMFC %6666666666|6xt6pl6hd6`\6XT6PL6HD6@<68460,6($6 666666666666        
666!%6)-61569=6AE6IM6QU6Y]6ae6im6qu6y}666666666666666666 
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666%(%RL Arial%Td
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@
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%(&%%W$
!


CORGROUP        $$CLK_I_BufferFalling

Percent 100
%(%%V,       =
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CORGROUP        $$CLK_I_BufferRisingFalling
     &%%V0CDDD%(%RL ArialArialArialCCMSTT315b3b3a84t Arial`c
Percent 100
:y      
!

 !"#$%&'()*+,-./01234569:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_abcdefghijklmnopqrstuvwxyz{|}~MS%Td1X
@
CORGROUP        $$CLK_RISC_BufferRising
@1XLTCOMP047-&%W$qh%(%%V,o^^o^^&%%W$H
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Percent 100
!
 Arial?COMSTT315b3b3a84t#XX>C',f(QArial%TlnL
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@LXHIT 00)%%
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Percent 100
@
!
@LP31%%%
(RL Arial#XX<KC+C(Q%(RL Ariald4d* #0%`')<)***:*,r-P.../133344555&565F66(6866707@8:8J8Z9f::;
;@;p;;<=R>(? %(RL ArialQR*RRSSTTTWXlXY"ZZZ[[[[[\]]^B^_`Vaabbccde&fRfgXghizjkkmooopRpbprpprrrsstpu^%T`:}
CORGROUP        $$CLK_RISC_BufferRisingFalling
@
Percent 100
@:LTlogRL Arial<`pBp2~HL4d(.f(2 <H*h%TT~
!
@
@~LP2RL ArialBм(R|ҦP\ך&l8>޾^0Z,V&" WMFC (R|&PPV
CORGROUP        $$CLK_I_BufferRising
@%T     
Percent 100
@
!
@Ld(IC_SETS)+4$!!!%
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@
CORGROUP        $$CLK_I_BufferFalling
@LP4%RL Arial7 8`8p88:::(:8;<=>ABCDDEFHXHhIJLLLLMNNNOOPPRRRRRSU>VjWtWWY2Z[[^0`zcehgjbl2m%TTh
Percent 100
@
!
@hLP3%RL Arialu2u\uuuvv.vXvvvww*w~wwwx&xPxzxxxy"yLyvzzZzz{${N{x{{{| |J|t|||}}F}}}~~B~l~~~(\xzJ.%TT
@
CORGROUP        $$CLK_I_BufferRisingFalling
@LP0%RL      Arial6 `.xHRdrf,`B
Percent 100
PZ&L~f"v&N%      Tl
!
@
@LXWAY 0O98.&
CORGROUP        $$CLK_RISC_BufferRising
%
Percent 100
%V0G*MHL)L)HHL%(
!
%
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(%
(%RL Arialserif faces.  Terminal strokes are cut on the diag which helps to give the face a less mechanical appearance.  Arial is an extremely versatile family of typefaces which can be ed with equal success for text setting in reports, presentatio u%TT"
@
CORGROUP        $$CLK_RISC_BufferFalling
@LP2ht%%
(%
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Percent 100
@
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(%%V0
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g%RL Arial versatile family of typefaces which can be used wequal success for text setting in reports, presentations, magazines etc, and for display use in newspapers, advertising and protions.http://www.monotype.com/html/mtname/ms_arial.htmlhttp:/el%TN

CORGROUP        $$CLK_RISC_BufferRisingFalling
@
Percent 100
@NLdWORD SELECT bB400--%-0)&%W$
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!
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Percent 100
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@
!
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PERIODE 2.5
DUTY    50

OFFSETE 0
@
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MAXUNCERTRISE   0
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MAXUNCERTFALL   0
MINUNCERTRISE   0

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@
JRISEE  0
@
JFALLE  0
LP2RL Arial%(      %T
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ENDGRID -1
@
DIRECTION       internal
@
MASTERCLOCK     None
Ld(IC_SETS)+3$!!!F.-C Arial???????-2
Clock   Unclocked
QWSET 0--)%2
EdgeLevel       neg
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Set     Not Used
       ...C Arial???-2
Clear   Not Used
1
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ClockEnable     Not Used
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ActiveLowSetClear       True
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AsyncSetClear   True
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ActiveLowClockEnable    True
       5...C Arialypeface  The Monotype Co-  2
VhdlType        std_logic
TAG)-42
VerilogType     wire
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    IC_SETS-10%--)-%-
SystemCType     sc_logic
-$L
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
L
StateEquation   Hex(Inc(0,2,5))
L-
HighVoltageThreshold    5
       "System΁cčρ -
LowVoltageThreshold     0
-
MSB     0
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LSB     0
--!2
isFallingEdgeSensitive  False
EFFECTIVE ADDRESS-))-0(---000-----$}
k       
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isRisingEdgeSensitive   False
oWord 0B%%%2
DrawAnalog      0
Word 1B%%%-2
BooleanEquation
       ...C Arial?A?A?A?A?A?A?A?A?A?A?A?A?-2
NegTolerance    0
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PosTolerance    0
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Word IC_SETS-1B%%0%--)-%-
UserSpecifiedSizeRatio  1
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PROPS!
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DUTY    50
---%

---%7
OFFSETE 0
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2
INITIAL LOW
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MAXUNCERTRISE   0
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     --$DDD--C Arial?????????-
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 Arial?????u???????t-        2
DIRECTION       input
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MASTERCLOCK     None
-
Clock   Unclocked
C Arial? ???????-
EdgeLevel       neg
2
Set     Not Used
31%%-
Clear   Not Used
! Arial-2 Arial?A?A?A?A?A?A?A?A?A?A?A?A?-2 Arial?A?A?A?A?A?A?A?A?A?A?A?A?-2
ClockEnable     Not Used
:log! Arial?A?A?A?A?A?A?A?A?A?A?A?A?-      2
ActiveLowSetClear       True
~22 Arial?A?A?A?A?A?A?A?A?A?A?A?A?-2
AsyncSetClear   True
(IC_SETS)+4$!!!-
ActiveLowClockEnable    True
 -       2
VhdlType        std_logic
4%C Arial?????????????????????????-             2
VerilogType     wire
h3%C Arial??????????????????????w??-    2
SystemCType     sc_logic
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2
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
WAY 0O98.--$HL)L)HHL--
StateEquation   Hex(Inc(0,2,5))
-
HighVoltageThreshold    5
-
LowVoltageThreshold     0
-C Arial????????????????????????-       2
MSB     0
2%-
LSB     0
-
isFallingEdgeSensitive  False
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isRisingEdgeSensitive   True
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DrawAnalog      0
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NegTolerance    0
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SIGNAL  dwb_ADR_O
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HighVoltageThreshold    5

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LowVoltageThreshold     0
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isRisingEdgeSensitive   False
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UserSpecifiedSizeRatio  1
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HighVoltageThreshold    5
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EdgeLevel       neg
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Clear   Not Used
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ClockEnable     Not Used
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ActiveLowSetClear       True
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AsyncSetClear   True
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ActiveLowClockEnable    True
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VhdlType        std_logic
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VerilogType     wire
SystemCType     sc_logic
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TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
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StateEquation   Hex(Inc(0,2,5))
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HighVoltageThreshold    5
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LowVoltageThreshold     0
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MSB     0
LSB     0
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isFallingEdgeSensitive  False
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PROJECT
 
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DisplayTimeUnit 2
 
TextGridX       250.000000
 
TextGridY       6
 
EdgeGridX       250.000000
 
ImportStartTime 0.000000
 
ImportEndTime   281474976710656.000000
 
TimePerPixel    6.497175
 
Visible DELAYS  SETUPS  HOLDS   SAMPLES TEXT    HIDDENATTACHMENTS       CRITICALPATHS   GRIDLINES       UNCERTAINTY
 
ColWidths       144,216,288,423,488
 
ScrollPos       0.000000,0.000000,0.000000
 
DefDelayRule    1
 
NoEventOverlap  NO
 
SigLabelFontHeight      10
 
LabelHeight     12
 
LoadLibsToMem   1
 
UseFullPathNames        1
 
LibPath
 
EntireTime      YES
 
PrintTimeSpecified      NO
 
FromTime        0
 
ToTime  5.75
 
AllSignals      YES
 
CurrSelSigs     NO
 
PrintTo 2
 
PrintFileName   C:\DOCS\reset_gated.wmf
 
PreviewInterchange      YES
 
PreviewTIFF5    NO
 
UseMargins      NO
 
PrintTimeLine   NO
 
PrintBorderBox  YES
 
PrintSigNames   YES
 
PrintSigNamesOnEachPage YES
 
AddPreviewToEPS NO
 
PreviewRes      150
 
MarginLR        1.25
 
MifImageWidth   6.00
 
MarginTB        Auto
 
Header  %d %t;%f;%p
 
Footer
 
ScaleHorz       100
 
ScaleVert       100
 
ScaleHPage      1
 
PrintImage      DIAGRAM
 
DefaultTimingModel      minmax
 
DefaultClock    Unclocked
 
DefaultEdgeLevel        neg
 
DefaultSet      Not Used
 
DefaultClear    Not Used
 
DefaultClockEnable      Not Used
 
DefaultClockToOutLH     0
 
DefaultClockToOutHL     0
 
DefaultSetup    0
 
DefaultHold     0
 
DefaultRegStartupState  unknown
 
DefaultPodSize  8
 
DefaultActiveLowSetClear        True
 
DefaultAsyncSetClear    True
 
DefaultActiveLowClockEnable     True
 
SigLabelFontHeight      10
 
PROPS!
 
!
 
 
STYLE
 
DefaultFont     USER    {-17,0,0,0,400,0,0,0,1,0,0,0,0,Arial,0}
 
DrawWndFont     DEFAULT
 
DrawWndColor    DEFAULT
 
GridWndFont     DEFAULT
 
GridWndColor    DEFAULT
 
LabelWndFont    USER    {-13,0,0,0,400,0,0,0,0,3,2,1,34,Arial,0}
 
LabelWndColor   DEFAULT
 
ParamDispPref   0
 
ParamWndCellDisplay     0
 
CustDispString  %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c
 
CustomDisplayStringRTF  {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont %n v=%mv,%Mv f=%mf,%Mf m=%mm,%Mm d=%md,%Md %c}
 
MarkerDispPref  4
 
MarkerCustDispString    %n v=%mv,%Mv d=%md %t
 
MarkerCustomDisplayStringRTF    {\rtf1\ansi{\fonttbl{\f0 \fswiss Arial;}{\f1 \fswiss MS Sans Serif;}}\sectd\marglsxn1800\margrsxn1800\margtsxn1440\margbsxn1440\headery1440\footery1440\sbkpage\pgncont\f1 %n v=%mv,%Mv d=%md %t }
 
SignalColor     2
 
LabelOffset     4
 
BusDisplay      0
 
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WaveFormColor   0
 
InputWaveFormColor      16711680
 
SlantedEdges    1
 
SlantAngle      75
 
RightJustifySigNames    1
 
AutosplitEnabled        1
 
AutosplitChar   _
 
DynamSizedSignals       1
 
!
 
 
DIAGRAMTESTBENCHSETTINGS
 
FilesBeforeDiagramModel
 
FilesInsideDiagramModelDeclarationSection
 
AbortHdlCodeEnabled     1
 
DelayHdlCodeEnabled     1
 
SampleHdlCodeEnabled    1
 
MarkerHdlCodeEnabled    1
 
VerboseSamples  0
 
VerboseDelays   0
 
VerboseFileInput        0
 
VerboseSequenceVerification     0
 
IncludeDelayTime        1
 
ExecuteFromTopLevel     1
 
TimeOutInDiagramLengths 0
 
DefaultCycleClock       Unclocked
 
DefaultCycleEdge        neg
 
!
 
 
MACROS
 
!
 
 
CORGROUP        $$CLK_I_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RI9

SC_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$clk_risc_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$clk_risc_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$clk_risc_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$clk_risc_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$clk_risc_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$clk_risc_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$clk_risc_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$clk_risc_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$clk_risc_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$clk_risc_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$clk_risc_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$clk_risc_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$clk_risc_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$clk_risc_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$clk_risc_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$clk_risc_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$clk_risc_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$clk_risc_BufferRisingFalling
 
Percent 100
 
!
 
 
CLOCK   clk_risc
 
PERIODE 1
 
DUTY    50
 
OFFSETE 4.5
 
INITIAL HIGH
 
MAXUNCERTRISE   0
 
MAXUNCERTFALL   0
 
MINUNCERTRISE   0
 
MINUNCERTFALL   0
 
JRISEE  0
 
JFALLE  0
 
GRID    1       1       0        2       2       16711680        0        0
 
ENDGRID -1
 
DIRECTION       input
 
MASTERCLOCK     None
 
Clock   Unclocked
 
EdgeLevel       neg
 
Set     Not Used
 
Clear   Not Used
 
ClockEnable     Not Used
 
ActiveLowSetClear       True
 
AsyncSetClear   True
 
ActiveLowClockEnable    True
 
VhdlType        std_logic
 
VerilogType     wire
 
SystemCType     sc_logic
 
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
 
StateEquation   Hex(Inc(0,2,5))
 
HighVoltageThreshold    5
 
LowVoltageThreshold     0
 
MSB     0
 
LSB     0
 
isFallingEdgeSensitive  False
 
isRisingEdgeSensitive   True
 
DrawAnalog      0
 
BooleanEquation
 
NegTolerance    0
 
PosTolerance    0
 
UserSpecifiedSizeRatio  1
 
VerilogCode
 
VHDLCode
 
PROPS!
 
E5      1       7000    7000            1       0        DR      0
 
E6      0        7500    7500            1       0        DR      0
 
E7      1       8000    8000            1       0        DR      0
 
E9      1       9000    9000            1       0        DR      0
 
!
 
 
SIGNAL  rst
 
DIRECTION       input
 
RADIX   hex
 
GRID    0        1       0        1       0        16711680        0        0
 
ENDGRID -1
 
Clock   Unclocked
 
EdgeLevel       neg
 
Set     Not Used
 
Clear   Not Used
 
ClockEnable     Not Used
 
ActiveLowSetClear       True
 
AsyncSetClear   True
 
ActiveLowClockEnable    True
 
VhdlType        std_logic
 
VerilogType     wire
 
SystemCType     sc_logic
 
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
 
StateEquation   Hex(Inc(0,2,5))
 
HighVoltageThreshold    5
 
LowVoltageThreshold     0
 
SignalActionType        0
 
MSB     0
 
LSB     0
 
isFallingEdgeSensitive  False
 
isRisingEdgeSensitive   False
 
DrawAnalog      0
 
BooleanEquation
 
NegTolerance    0
 
PosTolerance    0
 
UserSpecifiedSizeRatio  1
 
VerilogCode
 
VHDLCode
 
PROPS!
 
E0      0        1750    1750            1       0        DR      0
 
E1      1       3750    3750            1       0        DR      0
 
E2      0        5750    5750            1       0        DR      0
 
!
 
 
SIGNAL  dbg_dat_o
 
DIRECTION       output
 
RADIX   hex
 
GRID    0        1       0        1       0        16711680        0        0
 
ENDGRID -1
 
Clock
 
EdgeLevel       neg
 
Set     Not Used
 
Clear   Not Used
 
ClockEnable     Not Used
 
ActiveLowSetClear       True
 
AsyncSetClear   True
 
ActiveLowClockEnable    True
 
VhdlType        std_logic
 
VerilogType     wire
 
SystemCType     sc_logic
 
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
 
StateEquation   Hex(Inc(0,2,5))
 
HighVoltageThreshold    5
 
LowVoltageThreshold     0
 
LSB     0
 
MSB     31
 
SignalActionType        0
 
isFallingEdgeSensitive  False
 
isRisingEdgeSensitive   True
 
DrawAnalog      0
 
BooleanEquation
 
NegTolerance    0
 
PosTolerance    0
 
UserSpecifiedSizeRatio  1
 
VerilogCode
 
VHDLCode
 
VhdlMapping     DefaultVhdlMapping
 
PROPS!
 
E0      X       1750    1750            1       0        DR      0
 
E1      V       4750    4750    0x0     1       0        DR      0
 
E2      V       5750    5750    0x4     1       0        DR      0
 
!
 
 
SIGNAL  dbg_op_i
 
DIRECTION       input
 
RADIX   hex
 
GRID    0        1       0        1       0        16711680        0        0
 
ENDGRID -1
 
Clock   Unclocked
 
EdgeLevel       neg
 
Set     Not Used
 
Clear   Not Used
 
ClockEnable     Not Used
 
ActiveLowSetClear       True
 
AsyncSetClear   True
 
ActiveLowClockEnable    True
 
VhdlType        std_logic
 
VerilogType     wire
 
SystemCType     sc_logic
 
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
 
StateEquation   Hex(Inc(0,2,5))
 
HighVoltageThreshold    5
 
LowVoltageThreshold     0
 
SignalActionType        0
 
MSB     3
 
LSB     0
 
isFallingEdgeSensitive  False
 
isRisingEdgeSensitive   False
 
DrawAnalog      0
 
BooleanEquation
 
NegTolerance    0
 
PosTolerance    0
 
UserSpecifiedSizeRatio  1
 
VerilogCode
 
VHDLCode
 
PROPS!
 
E0      V       5750    5750    READ PC 0x0     1       0        DR      0
 
!
 
 
MARKER  MARK0
 
ATTACH  rst     NULL    S1
 
TIME    2750.000000
 
RELATIVETIME    0.000000
 
DISPLAYAS       5
 
MARKERTYPE      Timebreak(Curved)
 
WHILERETURN
 
REPEATNUMBER
 
SNAPTO  0
 
COMPRESSTIME    0.000000
 
COMMENT
 
!
 
 
Q&l     ^&" WMFC exQ&l EMFSXVISIODrawing
 
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PZ&L%(RL Arial0`>j8p2bP<pj8X rif design, Arial contains more humanistharacteristics than many of its predecessors and as such is most%(RL Arialr and fuller than in most industrial style sans sefaces.  Terminal strokes are cut on the diagonal which helps to give the face a less mechanical appearance.  Arial is an extrely versatile family of typefaces which can be used with equal s,%(%RL Arialwww.monotype.com/html/mtname/ms_arial.htmlhttp://wonotype.com/html/mtname/ms_welcome.htmlNOTIFICATION OF LICENSE AGREEMENT
 
 
This typeface is the property of Monotype Typograp and its use by you is covered under the terms of a license agpe%Tlo
 
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@LXTAG 1 y)-4%RL Arialishing use. You may not copy or distribute this sore.
 
 
If you have any question concerning your rights you should review the license agreement you received with the software  contact Monotype for a copy of the license agreement.
 
 
Mono (%T`5       m,
 

 
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@5        LT...peRL Arialypeface  The Monotype Cooration plc. Data  The Monotype Corporation plc/Type SolutionsInc. 1990-1992. All Rights Reseo%T`I

 
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%(RL Arial appearance.  Arial is anxtremely versatile family of typefaces which can be used with eual success for text seBb%(RL Arial bHdB((hpvxp4>.^"RBr%(RL ArialB^,\&V4d4d* !#0%`')<)***,r-P.../133344555&%(%RL ArialEFGHIKKFK~KKL
 
L0MNpNNNNOPQQR*RRSSTTTWXlXY"Z@ZZZ[[[[[\]^B^_`Vaabbccde&fRf%Tpo`
 
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LibPath
 
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PrintTo 2
 
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Footer
 
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CORGROUP        $$CLK_I_BufferRisingFalling
 
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CORGROUP        $$CLK_I_BufferRising
 
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!
 
 
CORGROUP        $$CLK_I_BufferFalling
 
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!
 
 
CORGROUP        $$CLK_I_BufferRisingFalling
 
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!
 
 
CORGROUP        $$CLK_I_BufferRising
 
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!
 
 
CORGROUP        $$CLK_I_BufferFalling
 
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!
 
 
CORGROUP        $$CLK_I_BufferRisingFalling
 
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!
 
 
CORGROUP        $$CLK_I_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_I_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$CLK_RISC_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$clk_risc_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$clk_risc_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$clk_risc_BufferRisingFalling
 
Percent 100
 
!
 
 
CORGROUP        $$clk_risc_BufferRising
 
Percent 100
 
!
 
 
CORGROUP        $$clk_risc_BufferFalling
 
Percent 100
 
!
 
 
CORGROUP        $$clk_risc_BufferRisingFalling
 
Percent 100
 
!
 
 
CLOCK   clk_risc
 
PERIODE 1
 
DUTY    50
 
OFFSETE 0
 
INITIAL LOW
 
MAXUNCERTRISE   0
 
MAXUNCERTFALL   0
 
MINUNCERTRISE   0
 
MINUNCERTFALL   0
 
JRISEE  0
 
JFALLE  0
 
GRID    1       1       1       2       2       16711680        0        0
 
ENDGRID -1
 
DIRECTION       input
 
MASTERCLOCK     None
 
Clock   Unclocked
 
EdgeLevel       neg
 
Set     Not Used
 
Clear   Not Used
 
ClockEnable     Not Used
 
ActiveLowSetClear       True
 
AsyncSetClear   True
 
ActiveLowClockEnable    True
 
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VerilogType     wire
 
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TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
 
StateEquation   Hex(Inc(0,2,5))
 
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LowVoltageThreshold     0
 
MSB     0
 
LSB     0
 
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DrawAnalog      0
 
BooleanEquation
 
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VerilogCode
 
VHDLCode
 
PROPS!
 
E5      1       2500    2500            1       0        DR      0
 
E6      0        3000    3000            1       0        DR      0
 
!
 
 
SIGNAL  dbg_adr_i
 
DIRECTION       input
 
RADIX   hex
 
GRID    0        1       0        1       0        16711680        0        0
 
ENDGRID -1
 
Clock   Unclocked
 
EdgeLevel       neg
 
Set     Not Used
 
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VerilogType     wire
 
SystemCType     sc_logic
 
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
 
StateEquation   Hex(Inc(0,2,5))
 
HighVoltageThreshold    5
 
LowVoltageThreshold     0
 
LSB     0
 
MSB     31
 
SignalActionType        0
 
isFallingEdgeSensitive  False
 
isRisingEdgeSensitive   False
 
DrawAnalog      0
 
BooleanEquation
 
NegTolerance    0
 
PosTolerance    0
 
UserSpecifiedSizeRatio  1
 
VerilogCode
 
VHDLCode
 
PROPS!
 
E0      X       750     750             1       0        DR      0
 
E1      V       1750    1750    A20     1       0        DR      0
 
E2      V       3750    3750    A100    1       0        DR      0
 
E3      X       5750    5750            1       0        DR      0
 
!
 
 
SIGNAL  dbg_dat_i
 
DIRECTION       input
 
RADIX   hex
 
GRID    0        1       0        1       0        16711680        0        0
 
ENDGRID -1
 
Clock
 
EdgeLevel       neg
 
Set     Not Used
 
Clear   Not Used
 
ClockEnable     Not Used
 
ActiveLowSetClear       True
 
AsyncSetClear   True
 
ActiveLowClockEnable    True
 
VhdlType        std_logic
 
VerilogType     wire
 
SystemCType     sc_logic
 
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
 
StateEquation   Hex(Inc(0,2,5))
 
HighVoltageThreshold    5
 
LowVoltageThreshold     0
 
LSB     0
 
MSB     31
 
SignalActionType        0
 
isFallingEdgeSensitive  False
 
isRisingEdgeSensitive   False
 
DrawAnalog      0
 
BooleanEquation
 
NegTolerance    0
 
PosTolerance    0
 
UserSpecifiedSizeRatio  1
 
VerilogCode
 
VHDLCode
 
VhdlMapping     DefaultVhdlMapping
 
PROPS!
 
E0      X       750     750             1       0        DR      0
 
E1      V       1750    1750    D20     1       0        DR      0
 
E2      X       5750    5750            1       0        DR      0
 
!
 
 
SIGNAL  dbg_dat_o
 
DIRECTION       output
 
RADIX   hex
 
GRID    0        1       0        1       0        16711680        0        0
 
ENDGRID -1
 
Clock
 
EdgeLevel       neg
 
Set     Not Used
 
Clear   Not Used
 
ClockEnable     Not Used
 
ActiveLowSetClear       True
 
AsyncSetClear   True
 
ActiveLowClockEnable    True
 
VhdlType        std_logic
 
VerilogType     wire
 
SystemCType     sc_logic
 
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
 
StateEquation   Hex(Inc(0,2,5))
 
HighVoltageThreshold    5
 
LowVoltageThreshold     0
 
LSB     0
 
MSB     31
 
SignalActionType        0
 
isFallingEdgeSensitive  False
 
isRisingEdgeSensitive   True
 
DrawAnalog      0
 
BooleanEquation
 
NegTolerance    0
 
PosTolerance    0
 
UserSpecifiedSizeRatio  1
 
VerilogCode
 
VHDLCode
 
VhdlMapping     DefaultVhdlMapping
 
PROPS!
 
E0      V       -1      -1              1       0        DR      0
 
E1      V       750     750     PC      1       0        DR      0
 
E2      X       2750    2750            1       0        DR      0
 
E3      V       3750    3750    D100    1       0        DR      0
 
E4      V       4750    4750    L/S EA  1       0        DR      0
 
E5      V       5750    5750    LOAD DATA       1       0        DR      0
 
!
 
 
SIGNAL  dbg_op_i
 
DIRECTION       input
 
RADIX   hex
 
GRID    0        1       0        1       0        16711680        0        0
 
ENDGRID -1
 
Clock   Unclocked
 
EdgeLevel       neg
 
Set     Not Used
 
Clear   Not Used
 
ClockEnable     Not Used
 
ActiveLowSetClear       True
 
AsyncSetClear   True
 
ActiveLowClockEnable    True
 
VhdlType        std_logic
 
VerilogType     wire
 
SystemCType     sc_logic
 
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
 
StateEquation   Hex(Inc(0,2,5))
 
HighVoltageThreshold    5
 
LowVoltageThreshold     0
 
SignalActionType        0
 
MSB     3
 
LSB     0
 
isFallingEdgeSensitive  False
 
isRisingEdgeSensitive   False
 
DrawAnalog      0
 
BooleanEquation
 
NegTolerance    0
 
PosTolerance    0
 
UserSpecifiedSizeRatio  1
 
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VHDLCode
 
PROPS!
 
E0      V       750     750     READ PC 0x0     1       0        DR      0
 
E1      V       1750    1750    WRITE SPR 0x5   1       0        DR      0
 
E2      V       3750    3750    READ SPR == 0x4 1       0        DR      0
 
E3      V       4750    4750    READ LSEA 0x1   1       0        DR      0
 
E4      V       5750    5750    READ LDAT 0x2   1       0        DR      0
 
!
 
 
SIGNAL  dbg_stall_i
 
DIRECTION       input
 
RADIX   hex
 
GRID    0        1       0        1       0        16711680        0        0
 
ENDGRID -1
 
Clock   Unclocked
 
EdgeLevel       neg
 
Set     Not Used
 
Clear   Not Used
 
ClockEnable     Not Used
 
ActiveLowSetClear       True
 
AsyncSetClear   True
 
ActiveLowClockEnable    True
 
VhdlType        std_logic
 
VerilogType     wire
 
SystemCType     sc_logic
 
TemporalEquation        8ns=Z (5=1 5=0)*5 9=H 9=L 5=V 5=X
 
StateEquation   Hex(Inc(0,2,5))
 
HighVoltageThreshold    5
 
LowVoltageThreshold     0
 
SignalActionType        0
 
MSB     0
 
LSB     0
 
isFallingEdgeSensitive  False
 
isRisingEdgeSensitive   False
 
DrawAnalog      0
 
BooleanEquation
 
NegTolerance    0
 
PosTolerance    0
 
UserSpecifiedSizeRatio  1
 
VerilogCode
 
VHDLCode
 
PROPS!
 
E0      0        5750    5750            1       0        DR      0
 
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