//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Generic Double-Port Synchronous RAM ////
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//// Generic Double-Port Synchronous RAM ////
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//// ////
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//// ////
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//// This file is part of memory library available from ////
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//// This file is part of memory library available from ////
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//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
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//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// This block is a wrapper with common double-port ////
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//// This block is a wrapper with common double-port ////
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//// synchronous memory interface for different ////
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//// synchronous memory interface for different ////
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//// types of ASIC and FPGA RAMs. Beside universal memory ////
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//// types of ASIC and FPGA RAMs. Beside universal memory ////
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//// interface it also provides behavioral model of generic ////
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//// interface it also provides behavioral model of generic ////
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//// double-port synchronous RAM. ////
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//// double-port synchronous RAM. ////
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//// It should be used in all OPENCORES designs that want to be ////
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//// It should be used in all OPENCORES designs that want to be ////
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//// portable accross different target technologies and ////
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//// portable accross different target technologies and ////
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//// independent of target memory. ////
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//// independent of target memory. ////
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//// ////
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//// ////
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//// Supported ASIC RAMs are: ////
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//// Supported ASIC RAMs are: ////
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//// ////
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//// ////
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//// Supported FPGA RAMs are: ////
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//// Supported FPGA RAMs are: ////
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//// - Xilinx Virtex RAMB16 ////
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//// - Xilinx Virtex RAMB16 ////
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//// - Xilinx Virtex RAMB4 ////
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//// - Xilinx Virtex RAMB4 ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - add additional RAMs ////
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//// - add additional RAMs ////
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//// - xilinx rams need external tri-state logic ////
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//// - xilinx rams need external tri-state logic ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Nir Mor, nirm@opencores.org ////
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//// - Nir Mor, nirm@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2005 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2005 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: or1200_dpram_256x32.v,v $
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// $Log: or1200_dpram_256x32.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// New
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// New
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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module or1200_dpram_256x32(
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module or1200_dpram_256x32(
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// Generic synchronous double-port RAM interface
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// Generic synchronous double-port RAM interface
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clk_a, rst_a, ce_a, oe_a, addr_a, do_a,
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clk_a, rst_a, ce_a, oe_a, addr_a, do_a,
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clk_b, rst_b, ce_b, we_b, addr_b, di_b
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clk_b, rst_b, ce_b, we_b, addr_b, di_b
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);
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);
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//
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//
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// Default address and data buses width
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// Default address and data buses width
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//
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//
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parameter aw = 8;
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parameter aw = 8;
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parameter dw = 32;
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parameter dw = 32;
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//
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//
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// Generic synchronous double-port RAM interface
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// Generic synchronous double-port RAM interface
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//
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//
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input clk_a; // Clock
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input clk_a; // Clock
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input rst_a; // Reset
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input rst_a; // Reset
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input ce_a; // Chip enable input
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input ce_a; // Chip enable input
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input oe_a; // Output enable input
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input oe_a; // Output enable input
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input [aw-1:0] addr_a; // address bus inputs
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input [aw-1:0] addr_a; // address bus inputs
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output [dw-1:0] do_a; // output data bus
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output [dw-1:0] do_a; // output data bus
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input clk_b; // Clock
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input clk_b; // Clock
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input rst_b; // Reset
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input rst_b; // Reset
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input ce_b; // Chip enable input
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input ce_b; // Chip enable input
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input we_b; // Write enable input
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input we_b; // Write enable input
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input [aw-1:0] addr_b; // address bus inputs
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input [aw-1:0] addr_b; // address bus inputs
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input [dw-1:0] di_b; // input data bus
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input [dw-1:0] di_b; // input data bus
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`ifdef OR1200_XILINX_RAMB4
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`ifdef OR1200_XILINX_RAMB4
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//
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//
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// Instantiation of FPGA memory:
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// Instantiation of FPGA memory:
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//
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//
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// Virtex/Spartan2
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// Virtex/Spartan2
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//
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//
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//
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//
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// Block 0
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// Block 0
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//
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//
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RAMB4_S16_S16 ramb4_s16_0(
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RAMB4_S16_S16 ramb4_s16_0(
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.CLKA(clk_a),
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.CLKA(clk_a),
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.RSTA(rst_a),
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.RSTA(rst_a),
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.ADDRA(addr_a),
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.ADDRA(addr_a),
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.DIA(16'h0000),
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.DIA(16'h0000),
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.ENA(ce_a),
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.ENA(ce_a),
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.WEA(1'b0),
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.WEA(1'b0),
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.DOA(do_a[15:0]),
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.DOA(do_a[15:0]),
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.CLKB(clk_b),
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.CLKB(clk_b),
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.RSTB(rst_b),
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.RSTB(rst_b),
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.ADDRB(addr_b),
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.ADDRB(addr_b),
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.DIB(di_b[15:0]),
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.DIB(di_b[15:0]),
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.ENB(ce_b),
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.ENB(ce_b),
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.WEB(we_b),
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.WEB(we_b),
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.DOB()
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.DOB()
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);
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);
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//
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//
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// Block 1
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// Block 1
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//
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//
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RAMB4_S16_S16 ramb4_s16_1(
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RAMB4_S16_S16 ramb4_s16_1(
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.CLKA(clk_a),
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.CLKA(clk_a),
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.RSTA(rst_a),
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.RSTA(rst_a),
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.ADDRA(addr_a),
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.ADDRA(addr_a),
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.DIA(16'h0000),
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.DIA(16'h0000),
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.ENA(ce_a),
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.ENA(ce_a),
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.WEA(1'b0),
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.WEA(1'b0),
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.DOA(do_a[31:16]),
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.DOA(do_a[31:16]),
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.CLKB(clk_b),
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.CLKB(clk_b),
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.RSTB(rst_b),
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.RSTB(rst_b),
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.ADDRB(addr_b),
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.ADDRB(addr_b),
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.DIB(di_b[31:16]),
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.DIB(di_b[31:16]),
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.ENB(ce_b),
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.ENB(ce_b),
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.WEB(we_b),
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.WEB(we_b),
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.DOB()
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.DOB()
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);
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);
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`else
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`else
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`ifdef OR1200_XILINX_RAMB16
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`ifdef OR1200_XILINX_RAMB16
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//
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//
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// Instantiation of FPGA memory:
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// Instantiation of FPGA memory:
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//
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//
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// Virtex4/Spartan3E
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// Virtex4/Spartan3E
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//
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//
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// Added By Nir Mor
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// Added By Nir Mor
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//
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//
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RAMB16_S36_S36 ramb16_s36_s36(
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RAMB16_S36_S36 ramb16_s36_s36(
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.CLKA(clk_a),
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.CLKA(clk_a),
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.SSRA(rst_a),
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.SSRA(rst_a),
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.ADDRA({1'b0, addr_a}),
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.ADDRA({1'b0, addr_a}),
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.DIA(32'h00000000),
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.DIA(32'h00000000),
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.DIPA(4'h0),
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.DIPA(4'h0),
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.ENA(ce_a),
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.ENA(ce_a),
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.WEA(1'b0),
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.WEA(1'b0),
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.DOA(do_a),
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.DOA(do_a),
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.DOPA(),
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.DOPA(),
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.CLKB(clk_b),
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.CLKB(clk_b),
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.SSRB(rst_b),
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.SSRB(rst_b),
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.ADDRB({1'b0, addr_b}),
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.ADDRB({1'b0, addr_b}),
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.DIB(di_b),
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.DIB(di_b),
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.DIPB(4'h0),
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.DIPB(4'h0),
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.ENB(ce_b),
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.ENB(ce_b),
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.WEB(we_b),
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.WEB(we_b),
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.DOB(),
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.DOB(),
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.DOPB()
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.DOPB()
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);
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);
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`else
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`else
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//
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//
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// Generic double-port synchronous RAM model
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// Generic double-port synchronous RAM model
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//
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//
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//
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//
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// Generic RAM's registers and wires
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// Generic RAM's registers and wires
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//
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//
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reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
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reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
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reg [aw-1:0] addr_a_reg; // RAM address registered
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reg [aw-1:0] addr_a_reg; // RAM address registered
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//
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//
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// Data output drivers
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// Data output drivers
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//
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//
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assign do_a = (oe_a) ? mem[addr_a_reg] : {dw{1'b0}};
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assign do_a = (oe_a) ? mem[addr_a_reg] : {dw{1'b0}};
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//
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//
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// RAM read
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// RAM read
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//
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//
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always @(posedge clk_a or posedge rst_a)
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always @(posedge clk_a or posedge rst_a)
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if (rst_a)
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if (rst_a)
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addr_a_reg <= #1 {aw{1'b0}};
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addr_a_reg <= {aw{1'b0}};
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else if (ce_a)
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else if (ce_a)
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addr_a_reg <= #1 addr_a;
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addr_a_reg <= addr_a;
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//
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//
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// RAM write
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// RAM write
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//
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//
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always @(posedge clk_b)
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always @(posedge clk_b)
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if (ce_b && we_b)
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if (ce_b && we_b)
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mem[addr_b] <= #1 di_b;
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mem[addr_b] <= di_b;
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`endif // !OR1200_XILINX_RAMB16
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`endif // !OR1200_XILINX_RAMB16
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`endif // !OR1200_XILINX_RAMB4
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`endif // !OR1200_XILINX_RAMB4
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endmodule
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endmodule
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