//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's Exception logic ////
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//// OR1200's Exception logic ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Handles all OR1K exceptions inside CPU block. ////
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//// Handles all OR1K exceptions inside CPU block. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - make it smaller and faster ////
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//// - make it smaller and faster ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: or1200_except.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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|
// Major update:
|
|
// Structure reordered and bugs fixed.
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//
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// Revision 1.17 2004/06/08 18:17:36 lampret
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|
// Non-functional changes. Coding style fixes.
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//
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// Revision 1.16 2004/04/05 08:29:57 lampret
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// Revision 1.16 2004/04/05 08:29:57 lampret
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// Merged branch_qmem into main tree.
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// Merged branch_qmem into main tree.
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//
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//
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// Revision 1.15.4.1 2004/02/11 01:40:11 lampret
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// Revision 1.15.4.1 2004/02/11 01:40:11 lampret
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// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
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// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
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//
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//
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// Revision 1.15 2003/04/20 22:23:57 lampret
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// Revision 1.15 2003/04/20 22:23:57 lampret
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// No functional change. Only added customization for exception vectors.
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// No functional change. Only added customization for exception vectors.
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//
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//
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// Revision 1.14 2002/09/03 22:28:21 lampret
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// Revision 1.14 2002/09/03 22:28:21 lampret
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// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
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// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
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//
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//
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// Revision 1.13 2002/08/28 01:44:25 lampret
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// Revision 1.13 2002/08/28 01:44:25 lampret
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// Removed some commented RTL. Fixed SR/ESR flag bug.
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// Removed some commented RTL. Fixed SR/ESR flag bug.
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//
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//
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// Revision 1.12 2002/08/22 02:16:45 lampret
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// Revision 1.12 2002/08/22 02:16:45 lampret
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// Fixed IMMU bug.
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// Fixed IMMU bug.
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//
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//
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// Revision 1.11 2002/08/18 19:54:28 lampret
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// Revision 1.11 2002/08/18 19:54:28 lampret
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// Added store buffer.
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// Added store buffer.
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//
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//
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// Revision 1.10 2002/07/14 22:17:17 lampret
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// Revision 1.10 2002/07/14 22:17:17 lampret
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// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
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// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
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//
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//
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// Revision 1.9 2002/02/11 04:33:17 lampret
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// Revision 1.9 2002/02/11 04:33:17 lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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//
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// Revision 1.8 2002/01/28 01:16:00 lampret
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// Revision 1.8 2002/01/28 01:16:00 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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//
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// Revision 1.7 2002/01/23 07:52:36 lampret
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// Revision 1.7 2002/01/23 07:52:36 lampret
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// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.
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// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.
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//
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//
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// Revision 1.6 2002/01/18 14:21:43 lampret
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// Revision 1.6 2002/01/18 14:21:43 lampret
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// Fixed 'the NPC single-step fix'.
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// Fixed 'the NPC single-step fix'.
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//
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//
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// Revision 1.5 2002/01/18 07:56:00 lampret
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// Revision 1.5 2002/01/18 07:56:00 lampret
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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//
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//
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// Revision 1.4 2002/01/14 21:11:50 lampret
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// Revision 1.4 2002/01/14 21:11:50 lampret
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// Changed alignment exception EPCR. Not tested yet.
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// Changed alignment exception EPCR. Not tested yet.
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//
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//
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// Revision 1.3 2002/01/14 19:09:57 lampret
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// Revision 1.3 2002/01/14 19:09:57 lampret
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// Fixed order of syscall and range exceptions.
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// Fixed order of syscall and range exceptions.
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//
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//
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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//
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// Revision 1.15 2001/11/27 23:13:11 lampret
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// Revision 1.15 2001/11/27 23:13:11 lampret
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// Fixed except_stop width and fixed EX PC for 1400444f no-ops.
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// Fixed except_stop width and fixed EX PC for 1400444f no-ops.
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//
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//
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// Revision 1.14 2001/11/23 08:38:51 lampret
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// Revision 1.14 2001/11/23 08:38:51 lampret
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// Changed DSR/DRR behavior and exception detection.
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// Changed DSR/DRR behavior and exception detection.
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//
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//
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// Revision 1.13 2001/11/20 18:46:15 simons
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// Revision 1.13 2001/11/20 18:46:15 simons
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// Break point bug fixed
|
// Break point bug fixed
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//
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//
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// Revision 1.12 2001/11/18 09:58:28 lampret
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// Revision 1.12 2001/11/18 09:58:28 lampret
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// Fixed some l.trap typos.
|
// Fixed some l.trap typos.
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//
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//
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// Revision 1.11 2001/11/18 08:36:28 lampret
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// Revision 1.11 2001/11/18 08:36:28 lampret
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// For GDB changed single stepping and disabled trap exception.
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// For GDB changed single stepping and disabled trap exception.
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//
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//
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// Revision 1.10 2001/11/13 10:02:21 lampret
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// Revision 1.10 2001/11/13 10:02:21 lampret
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// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
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// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
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//
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//
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// Revision 1.9 2001/11/10 03:43:57 lampret
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// Revision 1.9 2001/11/10 03:43:57 lampret
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// Fixed exceptions.
|
// Fixed exceptions.
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//
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//
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// Revision 1.8 2001/10/21 17:57:16 lampret
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// Revision 1.8 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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//
|
// Revision 1.7 2001/10/14 13:12:09 lampret
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// Revision 1.7 2001/10/14 13:12:09 lampret
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// MP3 version.
|
// MP3 version.
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//
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//
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// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
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// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
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// no message
|
// no message
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//
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//
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// Revision 1.2 2001/08/09 13:39:33 lampret
|
// Revision 1.2 2001/08/09 13:39:33 lampret
|
// Major clean-up.
|
// Major clean-up.
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//
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//
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Development version of RTL. Libraries are missing.
|
// Development version of RTL. Libraries are missing.
|
//
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//
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//
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//
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|
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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|
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`define OR1200_EXCEPTFSM_WIDTH 3
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`define OR1200_EXCEPTFSM_WIDTH 3
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`define OR1200_EXCEPTFSM_IDLE `OR1200_EXCEPTFSM_WIDTH'd0
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`define OR1200_EXCEPTFSM_IDLE `OR1200_EXCEPTFSM_WIDTH'd0
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`define OR1200_EXCEPTFSM_FLU1 `OR1200_EXCEPTFSM_WIDTH'd1
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`define OR1200_EXCEPTFSM_FLU1 `OR1200_EXCEPTFSM_WIDTH'd1
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`define OR1200_EXCEPTFSM_FLU2 `OR1200_EXCEPTFSM_WIDTH'd2
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`define OR1200_EXCEPTFSM_FLU2 `OR1200_EXCEPTFSM_WIDTH'd2
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`define OR1200_EXCEPTFSM_FLU3 `OR1200_EXCEPTFSM_WIDTH'd3
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`define OR1200_EXCEPTFSM_FLU3 `OR1200_EXCEPTFSM_WIDTH'd3
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`define OR1200_EXCEPTFSM_FLU4 `OR1200_EXCEPTFSM_WIDTH'd4
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`define OR1200_EXCEPTFSM_FLU4 `OR1200_EXCEPTFSM_WIDTH'd4
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`define OR1200_EXCEPTFSM_FLU5 `OR1200_EXCEPTFSM_WIDTH'd5
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`define OR1200_EXCEPTFSM_FLU5 `OR1200_EXCEPTFSM_WIDTH'd5
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|
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//
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//
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// Exception recognition and sequencing
|
// Exception recognition and sequencing
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//
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//
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|
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module or1200_except(
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module or1200_except(
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// Clock and reset
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// Clock and reset
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clk, rst,
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clk, rst,
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|
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// Internal i/f
|
// Internal i/f
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sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss, sig_dmmufault,
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sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss, sig_dmmufault,
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sig_int, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault, sig_tick,
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sig_int, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault, sig_tick,
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branch_taken, genpc_freeze, id_freeze, ex_freeze, wb_freeze, if_stall,
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ex_branch_taken, genpc_freeze, id_freeze, ex_freeze, wb_freeze, if_stall,
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if_pc, id_pc, lr_sav, flushpipe, extend_flush, except_type, except_start,
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if_pc, id_pc, ex_pc, wb_pc, id_flushpipe, ex_flushpipe, extend_flush, except_flushpipe, except_type, except_start,
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except_started, except_stop, ex_void,
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except_started, except_stop, except_trig, ex_void, abort_mvspr, branch_op,
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spr_dat_ppc, spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
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spr_dat_ppc, spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
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du_dmr1, du_hwbkpt, du_hwbkpt_ls_r,
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esr, sr_we, to_sr, sr, lsu_addr, abort_ex, icpu_ack_i, icpu_err_i, dcpu_ack_i, dcpu_err_i
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esr, sr_we, to_sr, sr, lsu_addr, abort_ex, icpu_ack_i, icpu_err_i, dcpu_ack_i, dcpu_err_i
|
|
|
|
|
);
|
);
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|
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//
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//
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// I/O
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// I/O
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//
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//
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input clk;
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input clk;
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input rst;
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input rst;
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input sig_ibuserr;
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input sig_ibuserr;
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input sig_dbuserr;
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input sig_dbuserr;
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input sig_illegal;
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input sig_illegal;
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input sig_align;
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input sig_align;
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input sig_range;
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input sig_range;
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input sig_dtlbmiss;
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input sig_dtlbmiss;
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input sig_dmmufault;
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input sig_dmmufault;
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input sig_int;
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input sig_int;
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input sig_syscall;
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input sig_syscall;
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input sig_trap;
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input sig_trap;
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input sig_itlbmiss;
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input sig_itlbmiss;
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input sig_immufault;
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input sig_immufault;
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input sig_tick;
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input sig_tick;
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input branch_taken;
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input ex_branch_taken;
|
input genpc_freeze;
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input genpc_freeze;
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input id_freeze;
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input id_freeze;
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input ex_freeze;
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input ex_freeze;
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input wb_freeze;
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input wb_freeze;
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input if_stall;
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input if_stall;
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input [31:0] if_pc;
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input [31:0] if_pc;
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output [31:0] id_pc;
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output [31:0] id_pc;
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output [31:2] lr_sav;
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output [31:0] ex_pc;
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|
output [31:0] wb_pc;
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input [31:0] datain;
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input [31:0] datain;
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input [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
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input [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
|
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input [24:0] du_dmr1;
|
|
input du_hwbkpt;
|
|
input du_hwbkpt_ls_r;
|
input epcr_we;
|
input epcr_we;
|
input eear_we;
|
input eear_we;
|
input esr_we;
|
input esr_we;
|
input pc_we;
|
input pc_we;
|
output [31:0] epcr;
|
output [31:0] epcr;
|
output [31:0] eear;
|
output [31:0] eear;
|
output [`OR1200_SR_WIDTH-1:0] esr;
|
output [`OR1200_SR_WIDTH-1:0] esr;
|
input [`OR1200_SR_WIDTH-1:0] to_sr;
|
input [`OR1200_SR_WIDTH-1:0] to_sr;
|
input sr_we;
|
input sr_we;
|
input [`OR1200_SR_WIDTH-1:0] sr;
|
input [`OR1200_SR_WIDTH-1:0] sr;
|
input [31:0] lsu_addr;
|
input [31:0] lsu_addr;
|
output flushpipe;
|
input id_flushpipe;
|
|
input ex_flushpipe;
|
|
output except_flushpipe;
|
output extend_flush;
|
output extend_flush;
|
output [`OR1200_EXCEPT_WIDTH-1:0] except_type;
|
output [`OR1200_EXCEPT_WIDTH-1:0] except_type;
|
output except_start;
|
output except_start;
|
output except_started;
|
output except_started;
|
output [12:0] except_stop;
|
output [12:0] except_stop;
|
|
output [12:0] except_trig;
|
input ex_void;
|
input ex_void;
|
|
input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
|
output [31:0] spr_dat_ppc;
|
output [31:0] spr_dat_ppc;
|
output [31:0] spr_dat_npc;
|
output [31:0] spr_dat_npc;
|
output abort_ex;
|
output abort_ex;
|
|
output abort_mvspr;
|
input icpu_ack_i;
|
input icpu_ack_i;
|
input icpu_err_i;
|
input icpu_err_i;
|
input dcpu_ack_i;
|
input dcpu_ack_i;
|
input dcpu_err_i;
|
input dcpu_err_i;
|
|
|
//
|
//
|
// Internal regs and wires
|
// Internal regs and wires
|
//
|
//
|
reg [`OR1200_EXCEPT_WIDTH-1:0] except_type;
|
reg [`OR1200_EXCEPT_WIDTH-1:0] except_type;
|
reg [31:0] id_pc;
|
reg [31:0] id_pc;
|
|
reg id_pc_val;
|
reg [31:0] ex_pc;
|
reg [31:0] ex_pc;
|
|
reg ex_pc_val;
|
reg [31:0] wb_pc;
|
reg [31:0] wb_pc;
|
|
reg [31:0] dl_pc;
|
reg [31:0] epcr;
|
reg [31:0] epcr;
|
reg [31:0] eear;
|
reg [31:0] eear;
|
reg [`OR1200_SR_WIDTH-1:0] esr;
|
reg [`OR1200_SR_WIDTH-1:0] esr;
|
reg [2:0] id_exceptflags;
|
reg [2:0] id_exceptflags;
|
reg [2:0] ex_exceptflags;
|
reg [2:0] ex_exceptflags;
|
reg [`OR1200_EXCEPTFSM_WIDTH-1:0] state;
|
reg [`OR1200_EXCEPTFSM_WIDTH-1:0] state;
|
reg extend_flush;
|
reg extend_flush;
|
reg extend_flush_last;
|
reg extend_flush_last;
|
reg ex_dslot;
|
reg ex_dslot;
|
reg delayed1_ex_dslot;
|
reg delayed1_ex_dslot;
|
reg delayed2_ex_dslot;
|
reg delayed2_ex_dslot;
|
wire except_started;
|
wire except_started;
|
wire [12:0] except_trig;
|
|
wire except_flushpipe;
|
|
reg [2:0] delayed_iee;
|
reg [2:0] delayed_iee;
|
reg [2:0] delayed_tee;
|
reg [2:0] delayed_tee;
|
wire int_pending;
|
wire int_pending;
|
wire tick_pending;
|
wire tick_pending;
|
|
reg trace_trap ;
|
|
reg ex_freeze_prev;
|
|
reg sr_ted_prev;
|
|
reg dsr_te_prev;
|
|
reg dmr1_st_prev ;
|
|
reg dmr1_bt_prev ;
|
|
wire dsr_te = ex_freeze_prev ? dsr_te_prev : du_dsr[`OR1200_DU_DSR_TE];
|
|
wire sr_ted = ex_freeze_prev ? sr_ted_prev : sr[`OR1200_SR_TED];
|
|
wire dmr1_st = ex_freeze_prev ? dmr1_st_prev: du_dmr1[`OR1200_DU_DMR1_ST] ;
|
|
wire dmr1_bt = ex_freeze_prev ? dmr1_bt_prev: du_dmr1[`OR1200_DU_DMR1_BT] ;
|
|
|
//
|
//
|
// Simple combinatorial logic
|
// Simple combinatorial logic
|
//
|
//
|
assign except_started = extend_flush & except_start;
|
assign except_started = extend_flush & except_start;
|
assign lr_sav = ex_pc[31:2];
|
assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
|
|
assign int_pending = sig_int & (sr[`OR1200_SR_IEE] | (sr_we & to_sr[`OR1200_SR_IEE])) & id_pc_val & delayed_iee[2] & ~ex_freeze & ~ex_branch_taken & ~ex_dslot & ~(sr_we & ~to_sr[`OR1200_SR_IEE]);
|
|
assign tick_pending = sig_tick & (sr[`OR1200_SR_TEE] | (sr_we & to_sr[`OR1200_SR_TEE])) & id_pc_val & delayed_tee[2] & ~ex_freeze & ~ex_branch_taken & ~ex_dslot & ~(sr_we & ~to_sr[`OR1200_SR_TEE]);
|
|
assign abort_ex = sig_dbuserr | sig_dmmufault | sig_dtlbmiss | sig_align | sig_illegal | ((du_hwbkpt | trace_trap) & ex_pc_val & !sr_ted & !dsr_te); // Abort write into RF by load & other instructions
|
|
assign abort_mvspr = sig_illegal | ((du_hwbkpt | trace_trap) & ex_pc_val & !sr_ted & !dsr_te) ; // abort spr read/writes
|
assign spr_dat_ppc = wb_pc;
|
assign spr_dat_ppc = wb_pc;
|
assign spr_dat_npc = ex_void ? id_pc : ex_pc;
|
assign spr_dat_npc = ex_void ? id_pc : ex_pc;
|
assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
|
|
assign int_pending = sig_int & sr[`OR1200_SR_IEE] & delayed_iee[2] & ~ex_freeze & ~branch_taken & ~ex_dslot & ~sr_we;
|
|
assign tick_pending = sig_tick & sr[`OR1200_SR_TEE] & ~ex_freeze & ~branch_taken & ~ex_dslot & ~sr_we;
|
|
assign abort_ex = sig_dbuserr | sig_dmmufault | sig_dtlbmiss | sig_align | sig_illegal; // Abort write into RF by load & other instructions
|
|
|
|
//
|
//
|
// Order defines exception detection priority
|
// Order defines exception detection priority
|
//
|
//
|
assign except_trig = {
|
assign except_trig = {
|
tick_pending & ~du_dsr[`OR1200_DU_DSR_TTE],
|
tick_pending & ~du_dsr[`OR1200_DU_DSR_TTE],
|
int_pending & ~du_dsr[`OR1200_DU_DSR_IE],
|
int_pending & ~du_dsr[`OR1200_DU_DSR_IE],
|
ex_exceptflags[1] & ~du_dsr[`OR1200_DU_DSR_IME],
|
ex_exceptflags[1] & ~du_dsr[`OR1200_DU_DSR_IME],
|
ex_exceptflags[0] & ~du_dsr[`OR1200_DU_DSR_IPFE],
|
ex_exceptflags[0] & ~du_dsr[`OR1200_DU_DSR_IPFE],
|
ex_exceptflags[2] & ~du_dsr[`OR1200_DU_DSR_BUSEE],
|
ex_exceptflags[2] & ~du_dsr[`OR1200_DU_DSR_BUSEE],
|
sig_illegal & ~du_dsr[`OR1200_DU_DSR_IIE],
|
sig_illegal & ~du_dsr[`OR1200_DU_DSR_IIE],
|
sig_align & ~du_dsr[`OR1200_DU_DSR_AE],
|
sig_align & ~du_dsr[`OR1200_DU_DSR_AE],
|
sig_dtlbmiss & ~du_dsr[`OR1200_DU_DSR_DME],
|
sig_dtlbmiss & ~du_dsr[`OR1200_DU_DSR_DME],
|
sig_dmmufault & ~du_dsr[`OR1200_DU_DSR_DPFE],
|
sig_dmmufault & ~du_dsr[`OR1200_DU_DSR_DPFE],
|
sig_dbuserr & ~du_dsr[`OR1200_DU_DSR_BUSEE],
|
sig_dbuserr & ~du_dsr[`OR1200_DU_DSR_BUSEE],
|
sig_range & ~du_dsr[`OR1200_DU_DSR_RE],
|
sig_range & ~du_dsr[`OR1200_DU_DSR_RE],
|
sig_trap & ~du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
|
sig_trap & ~du_dsr[`OR1200_DU_DSR_TE],
|
sig_syscall & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
|
sig_syscall & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
|
};
|
};
|
|
wire trace_cond = !ex_freeze && !ex_void && (1'b0
|
|
`ifdef OR1200_DU_DMR1_ST
|
|
|| dmr1_st
|
|
`endif
|
|
`ifdef OR1200_DU_DMR1_BT
|
|
|| ((branch_op != `OR1200_BRANCHOP_NOP) && (branch_op != `OR1200_BRANCHOP_RFE) && dmr1_bt)
|
|
`endif
|
|
);
|
|
|
assign except_stop = {
|
assign except_stop = {
|
tick_pending & du_dsr[`OR1200_DU_DSR_TTE],
|
tick_pending & du_dsr[`OR1200_DU_DSR_TTE],
|
int_pending & du_dsr[`OR1200_DU_DSR_IE],
|
int_pending & du_dsr[`OR1200_DU_DSR_IE],
|
ex_exceptflags[1] & du_dsr[`OR1200_DU_DSR_IME],
|
ex_exceptflags[1] & du_dsr[`OR1200_DU_DSR_IME],
|
ex_exceptflags[0] & du_dsr[`OR1200_DU_DSR_IPFE],
|
ex_exceptflags[0] & du_dsr[`OR1200_DU_DSR_IPFE],
|
ex_exceptflags[2] & du_dsr[`OR1200_DU_DSR_BUSEE],
|
ex_exceptflags[2] & du_dsr[`OR1200_DU_DSR_BUSEE],
|
sig_illegal & du_dsr[`OR1200_DU_DSR_IIE],
|
sig_illegal & du_dsr[`OR1200_DU_DSR_IIE],
|
sig_align & du_dsr[`OR1200_DU_DSR_AE],
|
sig_align & du_dsr[`OR1200_DU_DSR_AE],
|
sig_dtlbmiss & du_dsr[`OR1200_DU_DSR_DME],
|
sig_dtlbmiss & du_dsr[`OR1200_DU_DSR_DME],
|
sig_dmmufault & du_dsr[`OR1200_DU_DSR_DPFE],
|
sig_dmmufault & du_dsr[`OR1200_DU_DSR_DPFE],
|
sig_dbuserr & du_dsr[`OR1200_DU_DSR_BUSEE],
|
sig_dbuserr & du_dsr[`OR1200_DU_DSR_BUSEE],
|
sig_range & du_dsr[`OR1200_DU_DSR_RE],
|
sig_range & du_dsr[`OR1200_DU_DSR_RE],
|
sig_trap & du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
|
sig_trap & du_dsr[`OR1200_DU_DSR_TE],
|
sig_syscall & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
|
sig_syscall & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
|
};
|
};
|
|
|
|
always @(posedge clk or posedge rst) begin
|
|
if (rst) begin
|
|
trace_trap <= #1 1'b0 ;
|
|
end
|
|
else if (!(trace_trap && !ex_pc_val)) begin
|
|
trace_trap <= #1 trace_cond & !dsr_te & !sr_ted ;
|
|
end
|
|
end
|
|
|
|
always @(posedge clk or posedge rst) begin
|
|
if (rst) begin
|
|
ex_freeze_prev <= #1 1'b0 ;
|
|
sr_ted_prev <= #1 1'b0 ;
|
|
dsr_te_prev <= #1 1'b0 ;
|
|
dmr1_st_prev <= #1 1'b0 ;
|
|
dmr1_bt_prev <= #1 1'b0 ;
|
|
end
|
|
else begin
|
|
ex_freeze_prev <= #1 ex_freeze ;
|
|
if (!ex_freeze_prev || ex_void) begin
|
|
sr_ted_prev <= #1 sr [`OR1200_SR_TED ] ;
|
|
dsr_te_prev <= #1 du_dsr [`OR1200_DU_DSR_TE ] ;
|
|
dmr1_st_prev <= #1 du_dmr1[`OR1200_DU_DMR1_ST] ;
|
|
dmr1_bt_prev <= #1 du_dmr1[`OR1200_DU_DMR1_BT] ;
|
|
end
|
|
end
|
|
end
|
|
|
//
|
//
|
// PC and Exception flags pipelines
|
// PC and Exception flags pipelines
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst) begin
|
if (rst) begin
|
id_pc <= #1 32'd0;
|
id_pc <= #1 32'd0;
|
|
id_pc_val <= #1 1'b0 ;
|
id_exceptflags <= #1 3'b000;
|
id_exceptflags <= #1 3'b000;
|
end
|
end
|
else if (flushpipe) begin
|
else if (id_flushpipe) begin
|
id_pc <= #1 32'h0000_0000;
|
id_pc_val <= #1 1'b0 ;
|
id_exceptflags <= #1 3'b000;
|
id_exceptflags <= #1 3'b000;
|
end
|
end
|
else if (!id_freeze) begin
|
else if (!id_freeze) begin
|
id_pc <= #1 if_pc;
|
id_pc <= #1 if_pc;
|
|
id_pc_val <= #1 1'b1 ;
|
id_exceptflags <= #1 { sig_ibuserr, sig_itlbmiss, sig_immufault };
|
id_exceptflags <= #1 { sig_ibuserr, sig_itlbmiss, sig_immufault };
|
end
|
end
|
end
|
end
|
|
|
//
|
//
|
// delayed_iee
|
// delayed_iee
|
//
|
//
|
// SR[IEE] should not enable interrupts right away
|
// SR[IEE] should not enable interrupts right away
|
// when it is restored with l.rfe. Instead delayed_iee
|
// when it is restored with l.rfe. Instead delayed_iee
|
// together with SR[IEE] enables interrupts once
|
// together with SR[IEE] enables interrupts once
|
// pipeline is again ready.
|
// pipeline is again ready.
|
//
|
//
|
always @(posedge rst or posedge clk)
|
always @(posedge rst or posedge clk)
|
if (rst)
|
if (rst)
|
delayed_iee <= #1 3'b000;
|
delayed_iee <= #1 3'b000;
|
else if (!sr[`OR1200_SR_IEE])
|
else if (!sr[`OR1200_SR_IEE])
|
delayed_iee <= #1 3'b000;
|
delayed_iee <= #1 3'b000;
|
else
|
else
|
delayed_iee <= #1 {delayed_iee[1:0], 1'b1};
|
delayed_iee <= #1 {delayed_iee[1:0], 1'b1};
|
|
|
//
|
//
|
// delayed_tee
|
// delayed_tee
|
//
|
//
|
// SR[TEE] should not enable tick exceptions right away
|
// SR[TEE] should not enable tick exceptions right away
|
// when it is restored with l.rfe. Instead delayed_tee
|
// when it is restored with l.rfe. Instead delayed_tee
|
// together with SR[TEE] enables tick exceptions once
|
// together with SR[TEE] enables tick exceptions once
|
// pipeline is again ready.
|
// pipeline is again ready.
|
//
|
//
|
always @(posedge rst or posedge clk)
|
always @(posedge rst or posedge clk)
|
if (rst)
|
if (rst)
|
delayed_tee <= #1 3'b000;
|
delayed_tee <= #1 3'b000;
|
else if (!sr[`OR1200_SR_TEE])
|
else if (!sr[`OR1200_SR_TEE])
|
delayed_tee <= #1 3'b000;
|
delayed_tee <= #1 3'b000;
|
else
|
else
|
delayed_tee <= #1 {delayed_tee[1:0], 1'b1};
|
delayed_tee <= #1 {delayed_tee[1:0], 1'b1};
|
|
|
//
|
//
|
// PC and Exception flags pipelines
|
// PC and Exception flags pipelines
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst) begin
|
if (rst) begin
|
ex_dslot <= #1 1'b0;
|
ex_dslot <= #1 1'b0;
|
ex_pc <= #1 32'd0;
|
ex_pc <= #1 32'd0;
|
|
ex_pc_val <= #1 1'b0 ;
|
ex_exceptflags <= #1 3'b000;
|
ex_exceptflags <= #1 3'b000;
|
delayed1_ex_dslot <= #1 1'b0;
|
delayed1_ex_dslot <= #1 1'b0;
|
delayed2_ex_dslot <= #1 1'b0;
|
delayed2_ex_dslot <= #1 1'b0;
|
end
|
end
|
else if (flushpipe) begin
|
else if (ex_flushpipe) begin
|
ex_dslot <= #1 1'b0;
|
ex_dslot <= #1 1'b0;
|
ex_pc <= #1 32'h0000_0000;
|
ex_pc_val <= #1 1'b0 ;
|
ex_exceptflags <= #1 3'b000;
|
ex_exceptflags <= #1 3'b000;
|
delayed1_ex_dslot <= #1 1'b0;
|
delayed1_ex_dslot <= #1 1'b0;
|
delayed2_ex_dslot <= #1 1'b0;
|
delayed2_ex_dslot <= #1 1'b0;
|
end
|
end
|
else if (!ex_freeze & id_freeze) begin
|
else if (!ex_freeze & id_freeze) begin
|
ex_dslot <= #1 1'b0;
|
ex_dslot <= #1 1'b0;
|
ex_pc <= #1 id_pc;
|
ex_pc <= #1 id_pc;
|
|
ex_pc_val <= #1 id_pc_val ;
|
ex_exceptflags <= #1 3'b000;
|
ex_exceptflags <= #1 3'b000;
|
delayed1_ex_dslot <= #1 ex_dslot;
|
delayed1_ex_dslot <= #1 ex_dslot;
|
delayed2_ex_dslot <= #1 delayed1_ex_dslot;
|
delayed2_ex_dslot <= #1 delayed1_ex_dslot;
|
end
|
end
|
else if (!ex_freeze) begin
|
else if (!ex_freeze) begin
|
ex_dslot <= #1 branch_taken;
|
ex_dslot <= #1 ex_branch_taken;
|
ex_pc <= #1 id_pc;
|
ex_pc <= #1 id_pc;
|
|
ex_pc_val <= #1 id_pc_val ;
|
ex_exceptflags <= #1 id_exceptflags;
|
ex_exceptflags <= #1 id_exceptflags;
|
delayed1_ex_dslot <= #1 ex_dslot;
|
delayed1_ex_dslot <= #1 ex_dslot;
|
delayed2_ex_dslot <= #1 delayed1_ex_dslot;
|
delayed2_ex_dslot <= #1 delayed1_ex_dslot;
|
end
|
end
|
end
|
end
|
|
|
//
|
//
|
// PC and Exception flags pipelines
|
// PC and Exception flags pipelines
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst) begin
|
if (rst) begin
|
wb_pc <= #1 32'd0;
|
wb_pc <= #1 32'd0;
|
|
dl_pc <= #1 32'd0;
|
end
|
end
|
else if (!wb_freeze) begin
|
else if (!wb_freeze) begin
|
wb_pc <= #1 ex_pc;
|
wb_pc <= #1 ex_pc;
|
|
dl_pc <= #1 wb_pc;
|
end
|
end
|
end
|
end
|
|
|
//
|
//
|
// Flush pipeline
|
|
//
|
|
assign flushpipe = except_flushpipe | pc_we | extend_flush;
|
|
|
|
//
|
|
// We have started execution of exception handler:
|
// We have started execution of exception handler:
|
// 1. Asserted for 3 clock cycles
|
// 1. Asserted for 3 clock cycles
|
// 2. Don't execute any instruction that is still in pipeline and is not part of exception handler
|
// 2. Don't execute any instruction that is still in pipeline and is not part of exception handler
|
//
|
//
|
assign except_flushpipe = |except_trig & ~|state;
|
assign except_flushpipe = |except_trig & ~|state;
|
|
|
//
|
//
|
// Exception FSM that sequences execution of exception handler
|
// Exception FSM that sequences execution of exception handler
|
//
|
//
|
// except_type signals which exception handler we start fetching in:
|
// except_type signals which exception handler we start fetching in:
|
// 1. Asserted in next clock cycle after exception is recognized
|
// 1. Asserted in next clock cycle after exception is recognized
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst) begin
|
if (rst) begin
|
state <= #1 `OR1200_EXCEPTFSM_IDLE;
|
state <= #1 `OR1200_EXCEPTFSM_IDLE;
|
except_type <= #1 `OR1200_EXCEPT_NONE;
|
except_type <= #1 `OR1200_EXCEPT_NONE;
|
extend_flush <= #1 1'b0;
|
extend_flush <= #1 1'b0;
|
epcr <= #1 32'b0;
|
epcr <= #1 32'b0;
|
eear <= #1 32'b0;
|
eear <= #1 32'b0;
|
esr <= #1 {1'b1, {`OR1200_SR_WIDTH-2{1'b0}}, 1'b1};
|
esr <= #1 {2'h1, {`OR1200_SR_WIDTH-3{1'b0}}, 1'b1};
|
extend_flush_last <= #1 1'b0;
|
extend_flush_last <= #1 1'b0;
|
end
|
end
|
else begin
|
else begin
|
`ifdef OR1200_CASE_DEFAULT
|
`ifdef OR1200_CASE_DEFAULT
|
case (state) // synopsys parallel_case
|
case (state) // synopsys parallel_case
|
`else
|
`else
|
case (state) // synopsys full_case parallel_case
|
case (state) // synopsys full_case parallel_case
|
`endif
|
`endif
|
`OR1200_EXCEPTFSM_IDLE:
|
`OR1200_EXCEPTFSM_IDLE:
|
if (except_flushpipe) begin
|
if (except_flushpipe) begin
|
state <= #1 `OR1200_EXCEPTFSM_FLU1;
|
state <= #1 `OR1200_EXCEPTFSM_FLU1;
|
extend_flush <= #1 1'b1;
|
extend_flush <= #1 1'b1;
|
esr <= #1 sr_we ? to_sr : sr;
|
esr <= #1 sr_we ? to_sr : sr;
|
casex (except_trig)
|
casex (except_trig)
|
`ifdef OR1200_EXCEPT_TICK
|
`ifdef OR1200_EXCEPT_TICK
|
13'b1_xxxx_xxxx_xxxx: begin
|
13'b1_xxxx_xxxx_xxxx: begin
|
except_type <= #1 `OR1200_EXCEPT_TICK;
|
except_type <= #1 `OR1200_EXCEPT_TICK;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
epcr <= #1 id_pc;
|
|
//epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_INT
|
`ifdef OR1200_EXCEPT_INT
|
13'b0_1xxx_xxxx_xxxx: begin
|
13'b0_1xxx_xxxx_xxxx: begin
|
except_type <= #1 `OR1200_EXCEPT_INT;
|
except_type <= #1 `OR1200_EXCEPT_INT;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
epcr <= #1 id_pc;
|
|
//epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_ITLBMISS
|
`ifdef OR1200_EXCEPT_ITLBMISS
|
13'b0_01xx_xxxx_xxxx: begin
|
13'b0_01xx_xxxx_xxxx: begin
|
except_type <= #1 `OR1200_EXCEPT_ITLBMISS;
|
except_type <= #1 `OR1200_EXCEPT_ITLBMISS;
|
//
|
|
// itlb miss exception and active ex_dslot caused wb_pc to put into eear instead of +4 address of ex_pc (or id_pc since it was equal to ex_pc?)
|
|
// eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
|
// mmu-icdc-O2 ex_pc only OK when no ex_dslot eear <= #1 ex_dslot ? ex_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
|
// mmu-icdc-O2 ex_pc only OK when no ex_dslot epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
|
eear <= #1 ex_dslot ? ex_pc : ex_pc;
|
eear <= #1 ex_dslot ? ex_pc : ex_pc;
|
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
|
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
|
// eear <= #1 ex_dslot ? ex_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
|
// epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_IPF
|
`ifdef OR1200_EXCEPT_IPF
|
13'b0_001x_xxxx_xxxx: begin
|
13'b0_001x_xxxx_xxxx: begin
|
except_type <= #1 `OR1200_EXCEPT_IPF;
|
except_type <= #1 `OR1200_EXCEPT_IPF;
|
//
|
|
// ipf exception and active ex_dslot caused wb_pc to put into eear instead of +4 address of ex_pc (or id_pc since it was equal to ex_pc?)
|
|
// eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
|
eear <= #1 ex_dslot ? ex_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
eear <= #1 ex_dslot ? ex_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_BUSERR
|
`ifdef OR1200_EXCEPT_BUSERR
|
13'b0_0001_xxxx_xxxx: begin
|
13'b0_0001_xxxx_xxxx: begin
|
except_type <= #1 `OR1200_EXCEPT_BUSERR;
|
except_type <= #1 `OR1200_EXCEPT_BUSERR;
|
eear <= #1 ex_dslot ? wb_pc : ex_pc;
|
eear <= #1 ex_dslot ? wb_pc : ex_pc;
|
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
|
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_ILLEGAL
|
`ifdef OR1200_EXCEPT_ILLEGAL
|
13'b0_0000_1xxx_xxxx: begin
|
13'b0_0000_1xxx_xxxx: begin
|
except_type <= #1 `OR1200_EXCEPT_ILLEGAL;
|
except_type <= #1 `OR1200_EXCEPT_ILLEGAL;
|
eear <= #1 ex_pc;
|
eear <= #1 ex_pc;
|
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
|
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_ALIGN
|
`ifdef OR1200_EXCEPT_ALIGN
|
13'b0_0000_01xx_xxxx: begin
|
13'b0_0000_01xx_xxxx: begin
|
except_type <= #1 `OR1200_EXCEPT_ALIGN;
|
except_type <= #1 `OR1200_EXCEPT_ALIGN;
|
eear <= #1 lsu_addr;
|
eear <= #1 lsu_addr;
|
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
|
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_DTLBMISS
|
`ifdef OR1200_EXCEPT_DTLBMISS
|
13'b0_0000_001x_xxxx: begin
|
13'b0_0000_001x_xxxx: begin
|
except_type <= #1 `OR1200_EXCEPT_DTLBMISS;
|
except_type <= #1 `OR1200_EXCEPT_DTLBMISS;
|
eear <= #1 lsu_addr;
|
eear <= #1 lsu_addr;
|
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? dl_pc : ex_pc;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_DPF
|
`ifdef OR1200_EXCEPT_DPF
|
13'b0_0000_0001_xxxx: begin
|
13'b0_0000_0001_xxxx: begin
|
except_type <= #1 `OR1200_EXCEPT_DPF;
|
except_type <= #1 `OR1200_EXCEPT_DPF;
|
eear <= #1 lsu_addr;
|
eear <= #1 lsu_addr;
|
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? dl_pc : ex_pc;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_BUSERR
|
`ifdef OR1200_EXCEPT_BUSERR
|
13'b0_0000_0000_1xxx: begin // Data Bus Error
|
13'b0_0000_0000_1xxx: begin // Data Bus Error
|
except_type <= #1 `OR1200_EXCEPT_BUSERR;
|
except_type <= #1 `OR1200_EXCEPT_BUSERR;
|
eear <= #1 lsu_addr;
|
eear <= #1 lsu_addr;
|
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? dl_pc : ex_pc;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_RANGE
|
`ifdef OR1200_EXCEPT_RANGE
|
13'b0_0000_0000_01xx: begin
|
13'b0_0000_0000_01xx: begin
|
except_type <= #1 `OR1200_EXCEPT_RANGE;
|
except_type <= #1 `OR1200_EXCEPT_RANGE;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_TRAP 13'b0_0000_0000_001x: begin
|
`ifdef OR1200_EXCEPT_TRAP 13'b0_0000_0000_001x: begin
|
except_type <= #1 `OR1200_EXCEPT_TRAP;
|
except_type <= #1 `OR1200_EXCEPT_TRAP;
|
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : ex_pc;
|
end
|
end
|
`endif
|
`endif
|
`ifdef OR1200_EXCEPT_SYSCALL
|
`ifdef OR1200_EXCEPT_SYSCALL
|
13'b0_0000_0000_0001: begin
|
13'b0_0000_0000_0001: begin
|
except_type <= #1 `OR1200_EXCEPT_SYSCALL;
|
except_type <= #1 `OR1200_EXCEPT_SYSCALL;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
end
|
end
|
`endif
|
`endif
|
default:
|
default:
|
except_type <= #1 `OR1200_EXCEPT_NONE;
|
except_type <= #1 `OR1200_EXCEPT_NONE;
|
endcase
|
endcase
|
end
|
end
|
else if (pc_we) begin
|
else if (pc_we) begin
|
state <= #1 `OR1200_EXCEPTFSM_FLU1;
|
state <= #1 `OR1200_EXCEPTFSM_FLU1;
|
extend_flush <= #1 1'b1;
|
extend_flush <= #1 1'b1;
|
end
|
end
|
else begin
|
else begin
|
if (epcr_we)
|
if (epcr_we)
|
epcr <= #1 datain;
|
epcr <= #1 datain;
|
if (eear_we)
|
if (eear_we)
|
eear <= #1 datain;
|
eear <= #1 datain;
|
if (esr_we)
|
if (esr_we)
|
esr <= #1 {1'b1, datain[`OR1200_SR_WIDTH-2:0]};
|
esr <= #1 {datain[`OR1200_SR_WIDTH-1], 1'b1, datain[`OR1200_SR_WIDTH-3:0]};
|
end
|
end
|
`OR1200_EXCEPTFSM_FLU1:
|
`OR1200_EXCEPTFSM_FLU1:
|
if (icpu_ack_i | icpu_err_i | genpc_freeze)
|
if (icpu_ack_i | icpu_err_i | genpc_freeze)
|
state <= #1 `OR1200_EXCEPTFSM_FLU2;
|
state <= #1 `OR1200_EXCEPTFSM_FLU2;
|
`OR1200_EXCEPTFSM_FLU2:
|
`OR1200_EXCEPTFSM_FLU2:
|
`ifdef OR1200_EXCEPT_TRAP
|
`ifdef OR1200_EXCEPT_TRAP
|
if (except_type == `OR1200_EXCEPT_TRAP) begin
|
if (except_type == `OR1200_EXCEPT_TRAP) begin
|
state <= #1 `OR1200_EXCEPTFSM_IDLE;
|
state <= #1 `OR1200_EXCEPTFSM_IDLE;
|
extend_flush <= #1 1'b0;
|
extend_flush <= #1 1'b0;
|
extend_flush_last <= #1 1'b0;
|
extend_flush_last <= #1 1'b0;
|
except_type <= #1 `OR1200_EXCEPT_NONE;
|
except_type <= #1 `OR1200_EXCEPT_NONE;
|
end
|
end
|
else
|
else
|
`endif
|
`endif
|
state <= #1 `OR1200_EXCEPTFSM_FLU3;
|
state <= #1 `OR1200_EXCEPTFSM_FLU3;
|
`OR1200_EXCEPTFSM_FLU3:
|
`OR1200_EXCEPTFSM_FLU3:
|
begin
|
begin
|
state <= #1 `OR1200_EXCEPTFSM_FLU4;
|
state <= #1 `OR1200_EXCEPTFSM_FLU4;
|
end
|
end
|
`OR1200_EXCEPTFSM_FLU4: begin
|
`OR1200_EXCEPTFSM_FLU4: begin
|
state <= #1 `OR1200_EXCEPTFSM_FLU5;
|
state <= #1 `OR1200_EXCEPTFSM_FLU5;
|
extend_flush <= #1 1'b0;
|
extend_flush <= #1 1'b0;
|
extend_flush_last <= #1 1'b0; // damjan
|
extend_flush_last <= #1 1'b0; // damjan
|
end
|
end
|
`ifdef OR1200_CASE_DEFAULT
|
`ifdef OR1200_CASE_DEFAULT
|
default: begin
|
default: begin
|
`else
|
`else
|
`OR1200_EXCEPTFSM_FLU5: begin
|
`OR1200_EXCEPTFSM_FLU5: begin
|
`endif
|
`endif
|
if (!if_stall && !id_freeze) begin
|
if (!if_stall && !id_freeze) begin
|
state <= #1 `OR1200_EXCEPTFSM_IDLE;
|
state <= #1 `OR1200_EXCEPTFSM_IDLE;
|
except_type <= #1 `OR1200_EXCEPT_NONE;
|
except_type <= #1 `OR1200_EXCEPT_NONE;
|
extend_flush_last <= #1 1'b0;
|
extend_flush_last <= #1 1'b0;
|
end
|
end
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
