//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's FPU Wrapper ////
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//// OR1200's FPU Wrapper ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://opencores.org/project,or1k ////
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//// http://opencores.org/project,or1k ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Wrapper for floating point unit. ////
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//// Wrapper for floating point unit. ////
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//// Interface based on MULT/MAC unit. ////
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//// Interface based on MULT/MAC unit. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - remainder instruction implementation ////
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//// - remainder instruction implementation ////
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//// - registering in/around compare unit ////
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//// - registering in/around compare unit ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Julius Baxter, julius@opencores.org ////
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//// - Julius Baxter, julius@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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module or1200_fpu(
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module or1200_fpu(
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// Clock and reset
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// Clock and reset
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clk, rst,
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clk, rst,
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// FPU interface
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// FPU interface
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ex_freeze, a, b, fpu_op, result,
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ex_freeze, a, b, fpu_op, result,
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// Flag controls
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// Flag controls
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flagforw, flag_we,
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flagforw, flag_we,
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// Exception signal
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// Exception signal
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sig_fp, except_started,
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sig_fp, except_started,
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// SPR interface
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// SPR interface
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fpcsr_we, fpcsr,
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fpcsr_we, fpcsr,
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
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);
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);
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parameter width = `OR1200_OPERAND_WIDTH;
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parameter width = `OR1200_OPERAND_WIDTH;
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//
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//
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// I/O
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// I/O
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//
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//
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//
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//
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// Clock and reset
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// Clock and reset
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//
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//
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input clk;
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input clk;
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input rst;
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input rst;
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//
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//
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// FPU interface
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// FPU interface
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//
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//
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input ex_freeze;
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input ex_freeze;
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input [width-1:0] a;
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input [width-1:0] a;
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input [width-1:0] b;
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input [width-1:0] b;
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input [`OR1200_FPUOP_WIDTH-1:0] fpu_op;
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input [`OR1200_FPUOP_WIDTH-1:0] fpu_op;
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output [width-1:0] result;
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output [width-1:0] result;
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//
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//
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// Flag signals
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// Flag signals
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//
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//
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output flagforw;
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output flagforw;
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output flag_we;
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output flag_we;
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//
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//
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// FPCSR interface
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// FPCSR interface
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//
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//
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input fpcsr_we;
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input fpcsr_we;
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output [`OR1200_FPCSR_WIDTH-1:0] fpcsr;
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output [`OR1200_FPCSR_WIDTH-1:0] fpcsr;
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//
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//
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// Exception signal
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// Exception signal
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//
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//
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output sig_fp;
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output sig_fp;
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input except_started;
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input except_started;
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//
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//
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// SPR interface
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// SPR interface
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//
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//
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input spr_cs;
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input spr_cs;
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input spr_write;
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input spr_write;
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input [31:0] spr_addr;
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input [31:0] spr_addr;
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input [31:0] spr_dat_i;
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input [31:0] spr_dat_i;
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output [31:0] spr_dat_o;
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output [31:0] spr_dat_o;
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`ifndef OR1200_FPU_IMPLEMENTED
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// No FPU needed
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assign result = 0;
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assign flagforw = 0;
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assign flag_we = 0;
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assign sig_fp = 0;
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assign spr_dat_o = 0;
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`else
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//
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//
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// Internals
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// Internals
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//
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//
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reg [2:0] fpu_op_count;
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reg [2:0] fpu_op_count;
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reg [`OR1200_FPUOP_WIDTH:0] fpu_op_r;
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reg [`OR1200_FPUOP_WIDTH:0] fpu_op_r;
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reg [`OR1200_FPCSR_WIDTH-1:0] fpcsr_r;
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reg [`OR1200_FPCSR_WIDTH-1:0] fpcsr_r;
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reg fpu_latch_operand;
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reg fpu_latch_operand;
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wire fpu_check_op;
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wire fpu_check_op;
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wire fpu_latch_op;
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wire fpu_latch_op;
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wire inf, snan, qnan, ine, overflow,
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wire inf, snan, qnan, ine, overflow,
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underflow, zero, div_by_zero;
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underflow, zero, div_by_zero;
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wire fpu_op_is_comp, fpu_op_r_is_comp;
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wire fpu_op_is_comp, fpu_op_r_is_comp;
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wire altb, blta, aeqb, cmp_inf, cmp_zero,
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wire altb, blta, aeqb, cmp_inf, cmp_zero,
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unordered ;
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unordered ;
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reg flag;
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reg flag;
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assign fpcsr = fpcsr_r;
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assign fpcsr = fpcsr_r;
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assign sig_fp = fpcsr_r[`OR1200_FPCSR_FPEE]
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assign sig_fp = fpcsr_r[`OR1200_FPCSR_FPEE]
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& (|fpcsr_r[`OR1200_FPCSR_WIDTH-1:`OR1200_FPCSR_OVF]);
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& (|fpcsr_r[`OR1200_FPCSR_WIDTH-1:`OR1200_FPCSR_OVF]);
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// Generate signals to latch fpu_op from decode instruction, then latch
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// Generate signals to latch fpu_op from decode instruction, then latch
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// operands when they appear during execute stage
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// operands when they appear during execute stage
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assign fpu_check_op = (!ex_freeze & fpu_op[`OR1200_FPUOP_WIDTH-1]);
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assign fpu_check_op = (!ex_freeze & fpu_op[`OR1200_FPUOP_WIDTH-1]);
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assign fpu_op_is_comp = fpu_op[3];
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assign fpu_op_is_comp = fpu_op[3];
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assign fpu_op_r_is_comp = fpu_op_r[3];
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assign fpu_op_r_is_comp = fpu_op_r[3];
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assign fpu_latch_op = fpu_check_op & !fpu_op_is_comp;
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assign fpu_latch_op = fpu_check_op & !fpu_op_is_comp;
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always @(posedge clk)
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always @(posedge clk)
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fpu_latch_operand <= fpu_check_op & !fpu_op_is_comp;
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fpu_latch_operand <= fpu_check_op & !fpu_op_is_comp;
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// Register fpu_op on comparisons, clear otherwise, remove top bit
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// Register fpu_op on comparisons, clear otherwise, remove top bit
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always @(posedge clk)
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always @(posedge clk)
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fpu_op_r <= (fpu_check_op & fpu_op_is_comp) ?
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fpu_op_r <= (fpu_check_op & fpu_op_is_comp) ?
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{1'b0,fpu_op[`OR1200_FPUOP_WIDTH-2:0]} : !ex_freeze ?
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{1'b0,fpu_op[`OR1200_FPUOP_WIDTH-2:0]} : !ex_freeze ?
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0 : fpu_op_r;
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0 : fpu_op_r;
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//
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//
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// Counter for each FPU operation
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// Counter for each FPU operation
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// Loaded at start, counts down
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// Loaded at start, counts down
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//
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//
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always @(posedge clk or posedge rst) begin
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always @(posedge clk or posedge rst) begin
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if (rst)
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if (rst)
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fpu_op_count <= 0;
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fpu_op_count <= 0;
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else
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else
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if (|fpu_op_count)
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if (|fpu_op_count)
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fpu_op_count <= fpu_op_count - 1;
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fpu_op_count <= fpu_op_count - 1;
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else if(fpu_check_op)
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else if(fpu_check_op)
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fpu_op_count <= 5;
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fpu_op_count <= 5;
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end
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end
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//
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//
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// FPCSR register
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// FPCSR register
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//
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//
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always @(posedge clk or posedge rst) begin
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always @(posedge clk or posedge rst) begin
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if (rst)
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if (rst)
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fpcsr_r <= 0;
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fpcsr_r <= 0;
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else
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else
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begin
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begin
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if (fpcsr_we)
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if (fpcsr_we)
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fpcsr_r <= b[`OR1200_FPCSR_WIDTH-1:0];
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fpcsr_r <= b[`OR1200_FPCSR_WIDTH-1:0];
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else if (fpu_op_count == 1)
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else if (fpu_op_count == 1)
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begin
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begin
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fpcsr_r[`OR1200_FPCSR_OVF] <= overflow;
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fpcsr_r[`OR1200_FPCSR_OVF] <= overflow;
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fpcsr_r[`OR1200_FPCSR_UNF] <= underflow;
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fpcsr_r[`OR1200_FPCSR_UNF] <= underflow;
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fpcsr_r[`OR1200_FPCSR_SNF] <= snan;
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fpcsr_r[`OR1200_FPCSR_SNF] <= snan;
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fpcsr_r[`OR1200_FPCSR_QNF] <= qnan;
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fpcsr_r[`OR1200_FPCSR_QNF] <= qnan;
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fpcsr_r[`OR1200_FPCSR_ZF] <= zero |
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fpcsr_r[`OR1200_FPCSR_ZF] <= zero |
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(cmp_zero & fpu_op_r_is_comp);
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(cmp_zero & fpu_op_r_is_comp);
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fpcsr_r[`OR1200_FPCSR_IXF] <= ine;
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fpcsr_r[`OR1200_FPCSR_IXF] <= ine;
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fpcsr_r[`OR1200_FPCSR_IVF] <= 0; // Not used by this FPU
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fpcsr_r[`OR1200_FPCSR_IVF] <= 0; // Not used by this FPU
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fpcsr_r[`OR1200_FPCSR_INF] <= inf |
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fpcsr_r[`OR1200_FPCSR_INF] <= inf |
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(cmp_inf & fpu_op_r_is_comp);
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(cmp_inf & fpu_op_r_is_comp);
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fpcsr_r[`OR1200_FPCSR_DZF] <= div_by_zero;
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fpcsr_r[`OR1200_FPCSR_DZF] <= div_by_zero;
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end // if (fpu_op_count == 1)
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end // if (fpu_op_count == 1)
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if (except_started)
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if (except_started)
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fpcsr_r[`OR1200_FPCSR_FPEE] <= 0;
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fpcsr_r[`OR1200_FPCSR_FPEE] <= 0;
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end // else: !if(rst)
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end // else: !if(rst)
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end // always @ (posedge clk or posedge rst)
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end // always @ (posedge clk or posedge rst)
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//
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//
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// Comparison flag generation
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// Comparison flag generation
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//
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//
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always@(posedge clk)
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always@(posedge clk)
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begin
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begin
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if (fpu_op_r_is_comp)
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if (fpu_op_r_is_comp)
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begin
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begin
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case(fpu_op_r)
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case(fpu_op_r)
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`OR1200_FPCOP_SFEQ: begin
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`OR1200_FPCOP_SFEQ: begin
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flag <= aeqb;
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flag <= aeqb;
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end
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end
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`OR1200_FPCOP_SFNE: begin
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`OR1200_FPCOP_SFNE: begin
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flag <= !aeqb;
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flag <= !aeqb;
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end
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end
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`OR1200_FPCOP_SFGT: begin
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`OR1200_FPCOP_SFGT: begin
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flag <= blta & !aeqb;
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flag <= blta & !aeqb;
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end
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end
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`OR1200_FPCOP_SFGE: begin
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`OR1200_FPCOP_SFGE: begin
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flag <= blta | aeqb;
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flag <= blta | aeqb;
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end
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end
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`OR1200_FPCOP_SFLT: begin
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`OR1200_FPCOP_SFLT: begin
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flag <= altb & !aeqb;
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flag <= altb & !aeqb;
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end
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end
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`OR1200_FPCOP_SFLE: begin
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`OR1200_FPCOP_SFLE: begin
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flag <= altb | aeqb;
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flag <= altb | aeqb;
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end
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end
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default: begin
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default: begin
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flag <= 0;
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flag <= 0;
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end
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end
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endcase // case (fpu_op_r)
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endcase // case (fpu_op_r)
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end // if (fpu_op_r_is_comp)
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end // if (fpu_op_r_is_comp)
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else
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else
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flag <= 0;
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flag <= 0;
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end // always@ (posedge clk)
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end // always@ (posedge clk)
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assign flagforw = flag;
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assign flagforw = flag;
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|
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// Determine here where we do the write, ie how much we pipeline the
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// Determine here where we do the write, ie how much we pipeline the
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// comparison
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// comparison
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assign flag_we = fpu_op_r_is_comp & (fpu_op_count == 2);
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assign flag_we = fpu_op_r_is_comp & (fpu_op_count == 2);
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|
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// FP arithmetic module
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// FP arithmetic module
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fpu fpu0
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fpu fpu0
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(
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(
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.clk(clk),
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.clk(clk),
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.rmode(fpcsr_r[`OR1200_FPCSR_RM]),
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.rmode(fpcsr_r[`OR1200_FPCSR_RM]),
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.fpu_op(fpu_op[2:0]),
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.fpu_op(fpu_op[2:0]),
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.opa(a),
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.opa(a),
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.opb(b),
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.opb(b),
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.out(result),
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.out(result),
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.latch_operand(fpu_latch_operand),
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.latch_operand(fpu_latch_operand),
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.latch_op(fpu_latch_op),
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.latch_op(fpu_latch_op),
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.inf(inf),
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.inf(inf),
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.snan(snan),
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.snan(snan),
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.qnan(qnan),
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.qnan(qnan),
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.ine(ine),
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.ine(ine),
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.overflow(overflow),
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.overflow(overflow),
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.underflow(underflow),
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.underflow(underflow),
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.zero(zero),
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.zero(zero),
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.div_by_zero(div_by_zero)
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.div_by_zero(div_by_zero)
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);
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);
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|
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// FP comparator
|
// FP comparator
|
fcmp fcmp0
|
fcmp fcmp0
|
(
|
(
|
.opa(a),
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.opa(a),
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.opb(b),
|
.opb(b),
|
.unordered(unordered),
|
.unordered(unordered),
|
// I am convinced the comparison logic is wrong way around in this
|
// I am convinced the comparison logic is wrong way around in this
|
// module, simplest to swap them on output -- julius
|
// module, simplest to swap them on output -- julius
|
|
|
.altb(blta),
|
.altb(blta),
|
.blta(altb),
|
.blta(altb),
|
.aeqb(aeqb),
|
.aeqb(aeqb),
|
.inf(cmp_inf),
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.inf(cmp_inf),
|
.zero(cmp_zero));
|
.zero(cmp_zero));
|
|
|
|
`endif // !`ifndef OR1200_FPU_IMPLEMENTED
|
|
|
endmodule // or1200_fpu
|
endmodule // or1200_fpu
|
|
|
