//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// or1200_fpu_post_norm_mul ////
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//// or1200_fpu_post_norm_mul ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://opencores.org/project,or1k ////
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//// http://opencores.org/project,or1k ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// post-normalization entity for the multiplication unit ////
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//// post-normalization entity for the multiplication unit ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Original design (FPU100) - ////
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//// - Original design (FPU100) - ////
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//// Jidan Al-eryani, jidan@gmx.net ////
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//// Jidan Al-eryani, jidan@gmx.net ////
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//// - Conv. to Verilog and inclusion in OR1200 - ////
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//// - Conv. to Verilog and inclusion in OR1200 - ////
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//// Julius Baxter, julius@opencores.org ////
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//// Julius Baxter, julius@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2006, 2010
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// Copyright (C) 2006, 2010
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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//
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//
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// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
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// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
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// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
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// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
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// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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// POSSIBILITY OF SUCH DAMAGE.
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//
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//
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module or1200_fpu_post_norm_mul(
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module or1200_fpu_post_norm_mul(
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clk_i,
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clk_i,
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opa_i,
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opa_i,
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opb_i,
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opb_i,
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exp_10_i,
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exp_10_i,
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fract_48_i,
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fract_48_i,
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sign_i,
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sign_i,
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rmode_i,
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rmode_i,
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output_o,
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output_o,
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ine_o
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ine_o
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);
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);
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parameter FP_WIDTH = 32;
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parameter FP_WIDTH = 32;
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parameter MUL_SERIAL = 0; // 0 for parallel multiplier, 1 for serial
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parameter MUL_SERIAL = 0; // 0 for parallel multiplier, 1 for serial
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parameter MUL_COUNT = 11; //11 for parallel multiplier, 34 for serial
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parameter MUL_COUNT = 11; //11 for parallel multiplier, 34 for serial
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parameter FRAC_WIDTH = 23;
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parameter FRAC_WIDTH = 23;
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parameter EXP_WIDTH = 8;
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parameter EXP_WIDTH = 8;
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parameter ZERO_VECTOR = 31'd0;
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parameter ZERO_VECTOR = 31'd0;
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parameter INF = 31'b1111111100000000000000000000000;
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parameter INF = 31'b1111111100000000000000000000000;
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parameter QNAN = 31'b1111111110000000000000000000000;
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parameter QNAN = 31'b1111111110000000000000000000000;
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parameter SNAN = 31'b1111111100000000000000000000001;
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parameter SNAN = 31'b1111111100000000000000000000001;
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input clk_i;
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input clk_i;
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input [FP_WIDTH-1:0] opa_i;
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input [FP_WIDTH-1:0] opa_i;
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input [FP_WIDTH-1:0] opb_i;
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input [FP_WIDTH-1:0] opb_i;
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input [EXP_WIDTH+1:0] exp_10_i;
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input [EXP_WIDTH+1:0] exp_10_i;
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input [2*FRAC_WIDTH+1:0] fract_48_i;
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input [2*FRAC_WIDTH+1:0] fract_48_i;
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input sign_i;
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input sign_i;
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input [1:0] rmode_i;
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input [1:0] rmode_i;
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output reg [FP_WIDTH-1:0] output_o;
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output reg [FP_WIDTH-1:0] output_o;
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output reg ine_o;
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output reg ine_o;
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reg [EXP_WIDTH-1:0] s_expa;
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reg [EXP_WIDTH-1:0] s_expa;
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reg [EXP_WIDTH-1:0] s_expb;
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reg [EXP_WIDTH-1:0] s_expb;
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reg [EXP_WIDTH+1:0] s_exp_10_i;
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reg [EXP_WIDTH+1:0] s_exp_10_i;
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reg [2*FRAC_WIDTH+1:0] s_fract_48_i;
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reg [2*FRAC_WIDTH+1:0] s_fract_48_i;
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reg s_sign_i;
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reg s_sign_i;
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wire [FP_WIDTH-1:0] s_output_o;
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wire [FP_WIDTH-1:0] s_output_o;
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wire s_ine_o;
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wire s_ine_o;
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wire s_overflow;
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wire s_overflow;
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reg [FP_WIDTH-1:0] s_opa_i;
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reg [FP_WIDTH-1:0] s_opa_i;
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reg [FP_WIDTH-1:0] s_opb_i;
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reg [FP_WIDTH-1:0] s_opb_i;
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reg [1:0] s_rmode_i;
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reg [1:0] s_rmode_i;
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reg [5:0] s_zeros;
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reg [5:0] s_zeros;
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wire s_carry;
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wire s_carry;
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reg [5:0] s_shr2;
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reg [5:0] s_shr2;
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reg [5:0] s_shl2;
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reg [5:0] s_shl2;
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reg [8:0] s_expo1;
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reg [8:0] s_expo1;
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wire [8:0] s_expo2b;
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wire [8:0] s_expo2b;
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wire [9:0] s_exp_10a;
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wire [9:0] s_exp_10a;
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wire [9:0] s_exp_10b;
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wire [9:0] s_exp_10b;
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reg [47:0] s_frac2a;
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reg [47:0] s_frac2a;
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wire s_sticky, s_guard, s_round;
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wire s_sticky, s_guard, s_round;
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wire s_roundup;
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wire s_roundup;
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reg [24:0] s_frac_rnd;
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reg [24:0] s_frac_rnd;
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wire [24:0] s_frac3;
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wire [24:0] s_frac3;
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wire s_shr3;
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wire s_shr3;
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reg [5:0] s_r_zeros;
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reg [5:0] s_r_zeros;
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wire s_lost;
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wire s_lost;
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wire s_op_0;
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wire s_op_0;
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wire [8:0] s_expo3;
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wire [8:0] s_expo3;
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wire s_infa, s_infb;
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wire s_infa, s_infb;
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wire s_nan_in, s_nan_op, s_nan_a, s_nan_b;
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wire s_nan_in, s_nan_op, s_nan_a, s_nan_b;
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// Input Register
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// Input Register
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always @(posedge clk_i)
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always @(posedge clk_i)
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begin
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begin
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s_opa_i <= opa_i;
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s_opa_i <= opa_i;
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s_opb_i <= opb_i;
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s_opb_i <= opb_i;
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s_expa <= opa_i[30:23];
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s_expa <= opa_i[30:23];
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s_expb <= opb_i[30:23];
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s_expb <= opb_i[30:23];
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s_exp_10_i <= exp_10_i;
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s_exp_10_i <= exp_10_i;
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s_fract_48_i <= fract_48_i;
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s_fract_48_i <= fract_48_i;
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s_sign_i <= sign_i;
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s_sign_i <= sign_i;
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s_rmode_i <= rmode_i;
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s_rmode_i <= rmode_i;
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end
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end
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// Output register
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// Output register
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always @(posedge clk_i)
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always @(posedge clk_i)
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begin
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begin
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output_o <= s_output_o;
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output_o <= s_output_o;
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ine_o <= s_ine_o;
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ine_o <= s_ine_o;
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end
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end
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//*** Stage 1 ****
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//*** Stage 1 ****
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// figure out the exponent and howmuch the fraction has to be shiftd
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// figure out the exponent and howmuch the fraction has to be shiftd
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// right/left
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// right/left
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assign s_carry = s_fract_48_i[47];
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assign s_carry = s_fract_48_i[47];
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always @(posedge clk_i)
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always @(posedge clk_i)
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if (!s_fract_48_i[47])
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if (!s_fract_48_i[47])
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casex(s_fract_48_i[46:1]) // synopsys full_case parallel_case
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casez(s_fract_48_i[46:1]) // synopsys full_case parallel_case
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46'b1?????????????????????????????????????????????: s_zeros <= 0;
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46'b1?????????????????????????????????????????????: s_zeros <= 0;
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46'b01????????????????????????????????????????????: s_zeros <= 1;
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46'b01????????????????????????????????????????????: s_zeros <= 1;
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46'b001???????????????????????????????????????????: s_zeros <= 2;
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46'b001???????????????????????????????????????????: s_zeros <= 2;
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46'b0001??????????????????????????????????????????: s_zeros <= 3;
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46'b0001??????????????????????????????????????????: s_zeros <= 3;
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46'b00001?????????????????????????????????????????: s_zeros <= 4;
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46'b00001?????????????????????????????????????????: s_zeros <= 4;
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46'b000001????????????????????????????????????????: s_zeros <= 5;
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46'b000001????????????????????????????????????????: s_zeros <= 5;
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46'b0000001???????????????????????????????????????: s_zeros <= 6;
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46'b0000001???????????????????????????????????????: s_zeros <= 6;
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46'b00000001??????????????????????????????????????: s_zeros <= 7;
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46'b00000001??????????????????????????????????????: s_zeros <= 7;
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46'b000000001?????????????????????????????????????: s_zeros <= 8;
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46'b000000001?????????????????????????????????????: s_zeros <= 8;
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46'b0000000001????????????????????????????????????: s_zeros <= 9;
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46'b0000000001????????????????????????????????????: s_zeros <= 9;
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46'b00000000001???????????????????????????????????: s_zeros <= 10;
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46'b00000000001???????????????????????????????????: s_zeros <= 10;
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46'b000000000001??????????????????????????????????: s_zeros <= 11;
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46'b000000000001??????????????????????????????????: s_zeros <= 11;
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46'b0000000000001?????????????????????????????????: s_zeros <= 12;
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46'b0000000000001?????????????????????????????????: s_zeros <= 12;
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46'b00000000000001????????????????????????????????: s_zeros <= 13;
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46'b00000000000001????????????????????????????????: s_zeros <= 13;
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46'b000000000000001???????????????????????????????: s_zeros <= 14;
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46'b000000000000001???????????????????????????????: s_zeros <= 14;
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46'b0000000000000001??????????????????????????????: s_zeros <= 15;
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46'b0000000000000001??????????????????????????????: s_zeros <= 15;
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46'b00000000000000001?????????????????????????????: s_zeros <= 16;
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46'b00000000000000001?????????????????????????????: s_zeros <= 16;
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46'b000000000000000001????????????????????????????: s_zeros <= 17;
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46'b000000000000000001????????????????????????????: s_zeros <= 17;
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46'b0000000000000000001???????????????????????????: s_zeros <= 18;
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46'b0000000000000000001???????????????????????????: s_zeros <= 18;
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46'b00000000000000000001??????????????????????????: s_zeros <= 19;
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46'b00000000000000000001??????????????????????????: s_zeros <= 19;
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46'b000000000000000000001?????????????????????????: s_zeros <= 20;
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46'b000000000000000000001?????????????????????????: s_zeros <= 20;
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46'b0000000000000000000001????????????????????????: s_zeros <= 21;
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46'b0000000000000000000001????????????????????????: s_zeros <= 21;
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46'b00000000000000000000001???????????????????????: s_zeros <= 22;
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46'b00000000000000000000001???????????????????????: s_zeros <= 22;
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46'b000000000000000000000001??????????????????????: s_zeros <= 23;
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46'b000000000000000000000001??????????????????????: s_zeros <= 23;
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46'b0000000000000000000000001?????????????????????: s_zeros <= 24;
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46'b0000000000000000000000001?????????????????????: s_zeros <= 24;
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46'b00000000000000000000000001????????????????????: s_zeros <= 25;
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46'b00000000000000000000000001????????????????????: s_zeros <= 25;
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46'b000000000000000000000000001???????????????????: s_zeros <= 26;
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46'b000000000000000000000000001???????????????????: s_zeros <= 26;
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46'b0000000000000000000000000001??????????????????: s_zeros <= 27;
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46'b0000000000000000000000000001??????????????????: s_zeros <= 27;
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46'b00000000000000000000000000001?????????????????: s_zeros <= 28;
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46'b00000000000000000000000000001?????????????????: s_zeros <= 28;
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46'b000000000000000000000000000001????????????????: s_zeros <= 29;
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46'b000000000000000000000000000001????????????????: s_zeros <= 29;
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46'b0000000000000000000000000000001???????????????: s_zeros <= 30;
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46'b0000000000000000000000000000001???????????????: s_zeros <= 30;
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46'b00000000000000000000000000000001??????????????: s_zeros <= 31;
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46'b00000000000000000000000000000001??????????????: s_zeros <= 31;
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46'b000000000000000000000000000000001?????????????: s_zeros <= 32;
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46'b000000000000000000000000000000001?????????????: s_zeros <= 32;
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46'b0000000000000000000000000000000001????????????: s_zeros <= 33;
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46'b0000000000000000000000000000000001????????????: s_zeros <= 33;
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46'b00000000000000000000000000000000001???????????: s_zeros <= 34;
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46'b00000000000000000000000000000000001???????????: s_zeros <= 34;
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46'b000000000000000000000000000000000001??????????: s_zeros <= 35;
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46'b000000000000000000000000000000000001??????????: s_zeros <= 35;
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46'b0000000000000000000000000000000000001?????????: s_zeros <= 36;
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46'b0000000000000000000000000000000000001?????????: s_zeros <= 36;
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46'b00000000000000000000000000000000000001????????: s_zeros <= 37;
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46'b00000000000000000000000000000000000001????????: s_zeros <= 37;
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46'b000000000000000000000000000000000000001???????: s_zeros <= 38;
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46'b000000000000000000000000000000000000001???????: s_zeros <= 38;
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46'b0000000000000000000000000000000000000001??????: s_zeros <= 39;
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46'b0000000000000000000000000000000000000001??????: s_zeros <= 39;
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46'b00000000000000000000000000000000000000001?????: s_zeros <= 40;
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46'b00000000000000000000000000000000000000001?????: s_zeros <= 40;
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46'b000000000000000000000000000000000000000001????: s_zeros <= 41;
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46'b000000000000000000000000000000000000000001????: s_zeros <= 41;
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46'b0000000000000000000000000000000000000000001???: s_zeros <= 42;
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46'b0000000000000000000000000000000000000000001???: s_zeros <= 42;
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46'b00000000000000000000000000000000000000000001??: s_zeros <= 43;
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46'b00000000000000000000000000000000000000000001??: s_zeros <= 43;
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46'b000000000000000000000000000000000000000000001?: s_zeros <= 44;
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46'b000000000000000000000000000000000000000000001?: s_zeros <= 44;
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46'b0000000000000000000000000000000000000000000001: s_zeros <= 45;
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46'b0000000000000000000000000000000000000000000001: s_zeros <= 45;
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46'b0000000000000000000000000000000000000000000000: s_zeros <= 46;
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46'b0000000000000000000000000000000000000000000000: s_zeros <= 46;
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endcase // casex (s_fract_48_i[46:1])
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endcase // casex (s_fract_48_i[46:1])
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else
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else
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s_zeros <= 0;
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s_zeros <= 0;
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always @(posedge clk_i)
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always @(posedge clk_i)
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casex(s_fract_48_i) // synopsys full_case parallel_case
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casez(s_fract_48_i) // synopsys full_case parallel_case
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48'b???????????????????????????????????????????????1: s_r_zeros <= 0;
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48'b???????????????????????????????????????????????1: s_r_zeros <= 0;
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48'b??????????????????????????????????????????????10: s_r_zeros <= 1;
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48'b??????????????????????????????????????????????10: s_r_zeros <= 1;
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48'b?????????????????????????????????????????????100: s_r_zeros <= 2;
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48'b?????????????????????????????????????????????100: s_r_zeros <= 2;
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48'b????????????????????????????????????????????1000: s_r_zeros <= 3;
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48'b????????????????????????????????????????????1000: s_r_zeros <= 3;
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48'b???????????????????????????????????????????10000: s_r_zeros <= 4;
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48'b???????????????????????????????????????????10000: s_r_zeros <= 4;
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48'b??????????????????????????????????????????100000: s_r_zeros <= 5;
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48'b??????????????????????????????????????????100000: s_r_zeros <= 5;
|
48'b?????????????????????????????????????????1000000: s_r_zeros <= 6;
|
48'b?????????????????????????????????????????1000000: s_r_zeros <= 6;
|
48'b????????????????????????????????????????10000000: s_r_zeros <= 7;
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48'b????????????????????????????????????????10000000: s_r_zeros <= 7;
|
48'b???????????????????????????????????????100000000: s_r_zeros <= 8;
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48'b???????????????????????????????????????100000000: s_r_zeros <= 8;
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48'b??????????????????????????????????????1000000000: s_r_zeros <= 9;
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48'b??????????????????????????????????????1000000000: s_r_zeros <= 9;
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48'b?????????????????????????????????????10000000000: s_r_zeros <= 10;
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48'b?????????????????????????????????????10000000000: s_r_zeros <= 10;
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48'b????????????????????????????????????100000000000: s_r_zeros <= 11;
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48'b????????????????????????????????????100000000000: s_r_zeros <= 11;
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48'b???????????????????????????????????1000000000000: s_r_zeros <= 12;
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48'b???????????????????????????????????1000000000000: s_r_zeros <= 12;
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48'b??????????????????????????????????10000000000000: s_r_zeros <= 13;
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48'b??????????????????????????????????10000000000000: s_r_zeros <= 13;
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48'b?????????????????????????????????100000000000000: s_r_zeros <= 14;
|
48'b?????????????????????????????????100000000000000: s_r_zeros <= 14;
|
48'b????????????????????????????????1000000000000000: s_r_zeros <= 15;
|
48'b????????????????????????????????1000000000000000: s_r_zeros <= 15;
|
48'b???????????????????????????????10000000000000000: s_r_zeros <= 16;
|
48'b???????????????????????????????10000000000000000: s_r_zeros <= 16;
|
48'b??????????????????????????????100000000000000000: s_r_zeros <= 17;
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48'b??????????????????????????????100000000000000000: s_r_zeros <= 17;
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48'b?????????????????????????????1000000000000000000: s_r_zeros <= 18;
|
48'b?????????????????????????????1000000000000000000: s_r_zeros <= 18;
|
48'b????????????????????????????10000000000000000000: s_r_zeros <= 19;
|
48'b????????????????????????????10000000000000000000: s_r_zeros <= 19;
|
48'b???????????????????????????100000000000000000000: s_r_zeros <= 20;
|
48'b???????????????????????????100000000000000000000: s_r_zeros <= 20;
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48'b??????????????????????????1000000000000000000000: s_r_zeros <= 21;
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48'b??????????????????????????1000000000000000000000: s_r_zeros <= 21;
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48'b?????????????????????????10000000000000000000000: s_r_zeros <= 22;
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48'b?????????????????????????10000000000000000000000: s_r_zeros <= 22;
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48'b????????????????????????100000000000000000000000: s_r_zeros <= 23;
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48'b????????????????????????100000000000000000000000: s_r_zeros <= 23;
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48'b???????????????????????1000000000000000000000000: s_r_zeros <= 24;
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48'b???????????????????????1000000000000000000000000: s_r_zeros <= 24;
|
48'b??????????????????????10000000000000000000000000: s_r_zeros <= 25;
|
48'b??????????????????????10000000000000000000000000: s_r_zeros <= 25;
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48'b?????????????????????100000000000000000000000000: s_r_zeros <= 26;
|
48'b?????????????????????100000000000000000000000000: s_r_zeros <= 26;
|
48'b????????????????????1000000000000000000000000000: s_r_zeros <= 27;
|
48'b????????????????????1000000000000000000000000000: s_r_zeros <= 27;
|
48'b???????????????????10000000000000000000000000000: s_r_zeros <= 28;
|
48'b???????????????????10000000000000000000000000000: s_r_zeros <= 28;
|
48'b??????????????????100000000000000000000000000000: s_r_zeros <= 29;
|
48'b??????????????????100000000000000000000000000000: s_r_zeros <= 29;
|
48'b?????????????????1000000000000000000000000000000: s_r_zeros <= 30;
|
48'b?????????????????1000000000000000000000000000000: s_r_zeros <= 30;
|
48'b????????????????10000000000000000000000000000000: s_r_zeros <= 31;
|
48'b????????????????10000000000000000000000000000000: s_r_zeros <= 31;
|
48'b???????????????100000000000000000000000000000000: s_r_zeros <= 32;
|
48'b???????????????100000000000000000000000000000000: s_r_zeros <= 32;
|
48'b??????????????1000000000000000000000000000000000: s_r_zeros <= 33;
|
48'b??????????????1000000000000000000000000000000000: s_r_zeros <= 33;
|
48'b?????????????10000000000000000000000000000000000: s_r_zeros <= 34;
|
48'b?????????????10000000000000000000000000000000000: s_r_zeros <= 34;
|
48'b????????????100000000000000000000000000000000000: s_r_zeros <= 35;
|
48'b????????????100000000000000000000000000000000000: s_r_zeros <= 35;
|
48'b???????????1000000000000000000000000000000000000: s_r_zeros <= 36;
|
48'b???????????1000000000000000000000000000000000000: s_r_zeros <= 36;
|
48'b??????????10000000000000000000000000000000000000: s_r_zeros <= 37;
|
48'b??????????10000000000000000000000000000000000000: s_r_zeros <= 37;
|
48'b?????????100000000000000000000000000000000000000: s_r_zeros <= 38;
|
48'b?????????100000000000000000000000000000000000000: s_r_zeros <= 38;
|
48'b????????1000000000000000000000000000000000000000: s_r_zeros <= 39;
|
48'b????????1000000000000000000000000000000000000000: s_r_zeros <= 39;
|
48'b???????10000000000000000000000000000000000000000: s_r_zeros <= 40;
|
48'b???????10000000000000000000000000000000000000000: s_r_zeros <= 40;
|
48'b??????100000000000000000000000000000000000000000: s_r_zeros <= 41;
|
48'b??????100000000000000000000000000000000000000000: s_r_zeros <= 41;
|
48'b?????1000000000000000000000000000000000000000000: s_r_zeros <= 42;
|
48'b?????1000000000000000000000000000000000000000000: s_r_zeros <= 42;
|
48'b????10000000000000000000000000000000000000000000: s_r_zeros <= 43;
|
48'b????10000000000000000000000000000000000000000000: s_r_zeros <= 43;
|
48'b???100000000000000000000000000000000000000000000: s_r_zeros <= 44;
|
48'b???100000000000000000000000000000000000000000000: s_r_zeros <= 44;
|
48'b??1000000000000000000000000000000000000000000000: s_r_zeros <= 45;
|
48'b??1000000000000000000000000000000000000000000000: s_r_zeros <= 45;
|
48'b?10000000000000000000000000000000000000000000000: s_r_zeros <= 46;
|
48'b?10000000000000000000000000000000000000000000000: s_r_zeros <= 46;
|
48'b100000000000000000000000000000000000000000000000: s_r_zeros <= 47;
|
48'b100000000000000000000000000000000000000000000000: s_r_zeros <= 47;
|
48'b000000000000000000000000000000000000000000000000: s_r_zeros <= 48;
|
48'b000000000000000000000000000000000000000000000000: s_r_zeros <= 48;
|
endcase // casex (s_fract_48_i)
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endcase // casex (s_fract_48_i)
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assign s_exp_10a = s_exp_10_i + {9'd0,s_carry};
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assign s_exp_10a = s_exp_10_i + {9'd0,s_carry};
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assign s_exp_10b = s_exp_10a - {4'd0,s_zeros};
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assign s_exp_10b = s_exp_10a - {4'd0,s_zeros};
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|
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wire [9:0] v_shr1;
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wire [9:0] v_shr1;
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wire [9:0] v_shl1;
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wire [9:0] v_shl1;
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|
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assign v_shr1 = (s_exp_10a[9] | !(|s_exp_10a)) ?
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assign v_shr1 = (s_exp_10a[9] | !(|s_exp_10a)) ?
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10'd1 - s_exp_10a + {9'd0,s_carry} :
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10'd1 - s_exp_10a + {9'd0,s_carry} :
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(s_exp_10b[9] | !(|s_exp_10b)) ?
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(s_exp_10b[9] | !(|s_exp_10b)) ?
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0 :
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0 :
|
s_exp_10b[8] ?
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s_exp_10b[8] ?
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0 : {9'd0,s_carry};
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0 : {9'd0,s_carry};
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|
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assign v_shl1 = (s_exp_10a[9] | !(|s_exp_10a)) ?
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assign v_shl1 = (s_exp_10a[9] | !(|s_exp_10a)) ?
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0 :
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0 :
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(s_exp_10b[9] | !(|s_exp_10b)) ?
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(s_exp_10b[9] | !(|s_exp_10b)) ?
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{4'd0,s_zeros} - s_exp_10a :
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{4'd0,s_zeros} - s_exp_10a :
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s_exp_10b[8] ?
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s_exp_10b[8] ?
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0 : {4'd0,s_zeros};
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0 : {4'd0,s_zeros};
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|
|
|
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always @(posedge clk_i)
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always @(posedge clk_i)
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begin
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begin
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if ((s_exp_10a[9] | !(|s_exp_10a)))
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if ((s_exp_10a[9] | !(|s_exp_10a)))
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s_expo1 <= 9'd1;
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s_expo1 <= 9'd1;
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else if (s_exp_10b[9] | !(|s_exp_10b))
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else if (s_exp_10b[9] | !(|s_exp_10b))
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s_expo1 <= 1'd1;
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s_expo1 <= 9'd1;
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else if (s_exp_10b[8])
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else if (s_exp_10b[8])
|
s_expo1 <= 9'b011111111;
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s_expo1 <= 9'b011111111;
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else
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else
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s_expo1 <= s_exp_10b[8:0];
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s_expo1 <= s_exp_10b[8:0];
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|
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if (v_shr1[6])
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if (v_shr1[6])
|
s_shr2 <= {6{1'b1}};
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s_shr2 <= {6{1'b1}};
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else
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else
|
s_shr2 <= v_shr1[5:0];
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s_shr2 <= v_shr1[5:0];
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|
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s_shl2 <= v_shl1[5:0];
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s_shl2 <= v_shl1[5:0];
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end // always @ (posedge clk_i)
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end // always @ (posedge clk_i)
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|
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// *** Stage 2 ***
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// *** Stage 2 ***
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// Shifting the fraction and rounding
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// Shifting the fraction and rounding
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|
|
|
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// shift the fraction
|
// shift the fraction
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always @(posedge clk_i)
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always @(posedge clk_i)
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if (|s_shr2)
|
if (|s_shr2)
|
s_frac2a <= s_fract_48_i >> s_shr2;
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s_frac2a <= s_fract_48_i >> s_shr2;
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else
|
else
|
s_frac2a <= s_fract_48_i << s_shl2;
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s_frac2a <= s_fract_48_i << s_shl2;
|
|
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assign s_expo2b = s_frac2a[46] ? s_expo1 : s_expo1 - 9'd1;
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assign s_expo2b = s_frac2a[46] ? s_expo1 : s_expo1 - 9'd1;
|
|
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// signals if precision was last during the right-shift above
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// signals if precision was last during the right-shift above
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assign s_lost = (s_shr2 + {5'd0,s_shr3}) > s_r_zeros;
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assign s_lost = (s_shr2 + {5'd0,s_shr3}) > s_r_zeros;
|
|
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// ***Stage 3***
|
// ***Stage 3***
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// Rounding
|
// Rounding
|
|
|
// 23
|
// 23
|
// |
|
// |
|
// xx00000000000000000000000grsxxxxxxxxxxxxxxxxxxxx
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// xx00000000000000000000000grsxxxxxxxxxxxxxxxxxxxx
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// guard bit: s_frac2a[23] (LSB of output)
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// guard bit: s_frac2a[23] (LSB of output)
|
// round bit: s_frac2a[22]
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// round bit: s_frac2a[22]
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assign s_guard = s_frac2a[22];
|
assign s_guard = s_frac2a[22];
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assign s_round = s_frac2a[21];
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assign s_round = s_frac2a[21];
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assign s_sticky = (|s_frac2a[20:0]) | s_lost;
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assign s_sticky = (|s_frac2a[20:0]) | s_lost;
|
|
|
assign s_roundup = s_rmode_i==2'b00 ? // round to nearest even
|
assign s_roundup = s_rmode_i==2'b00 ? // round to nearest even
|
s_guard & ((s_round | s_sticky) | s_frac2a[23]) :
|
s_guard & ((s_round | s_sticky) | s_frac2a[23]) :
|
s_rmode_i==2'b10 ? // round up
|
s_rmode_i==2'b10 ? // round up
|
(s_guard | s_round | s_sticky) & !s_sign_i :
|
(s_guard | s_round | s_sticky) & !s_sign_i :
|
s_rmode_i==2'b11 ? // round down
|
s_rmode_i==2'b11 ? // round down
|
(s_guard | s_round | s_sticky) & s_sign_i :
|
(s_guard | s_round | s_sticky) & s_sign_i :
|
0; // round to zero(truncate = no rounding)
|
0; // round to zero(truncate = no rounding)
|
|
|
|
|
always @(posedge clk_i)
|
always @(posedge clk_i)
|
if (s_roundup)
|
if (s_roundup)
|
s_frac_rnd <= s_frac2a[47:23] + 1;
|
s_frac_rnd <= s_frac2a[47:23] + 1;
|
else
|
else
|
s_frac_rnd <= s_frac2a[47:23];
|
s_frac_rnd <= s_frac2a[47:23];
|
|
|
assign s_shr3 = s_frac_rnd[24];
|
assign s_shr3 = s_frac_rnd[24];
|
|
|
|
|
assign s_expo3 = (s_shr3 & (s_expo2b!=9'b011111111)) ?
|
assign s_expo3 = (s_shr3 & (s_expo2b!=9'b011111111)) ?
|
s_expo2b + 1 : s_expo2b;
|
s_expo2b + 1 : s_expo2b;
|
|
|
assign s_frac3 = (s_shr3 & (s_expo2b!=9'b011111111)) ?
|
assign s_frac3 = (s_shr3 & (s_expo2b!=9'b011111111)) ?
|
{1'b0,s_frac_rnd[24:1]} : s_frac_rnd;
|
{1'b0,s_frac_rnd[24:1]} : s_frac_rnd;
|
|
|
//-***Stage 4****
|
//-***Stage 4****
|
// Output
|
// Output
|
|
|
assign s_op_0 = !((|s_opa_i[30:0]) & (|s_opb_i[30:0]));
|
assign s_op_0 = !((|s_opa_i[30:0]) & (|s_opb_i[30:0]));
|
|
|
assign s_infa = &s_expa;
|
assign s_infa = &s_expa;
|
|
|
assign s_infb = &s_expb;
|
assign s_infb = &s_expb;
|
|
|
assign s_nan_a = s_infa & (|s_opa_i[22:0]);
|
assign s_nan_a = s_infa & (|s_opa_i[22:0]);
|
|
|
assign s_nan_b = s_infb & (|s_opb_i[22:0]);
|
assign s_nan_b = s_infb & (|s_opb_i[22:0]);
|
|
|
assign s_nan_in = s_nan_a | s_nan_b;
|
assign s_nan_in = s_nan_a | s_nan_b;
|
|
|
assign s_nan_op = (s_infa | s_infb) & s_op_0; // 0 * inf = nan
|
assign s_nan_op = (s_infa | s_infb) & s_op_0; // 0 * inf = nan
|
|
|
assign s_overflow = (s_expo3==9'b011111111) & !(s_infa | s_infb);
|
assign s_overflow = (s_expo3==9'b011111111) & !(s_infa | s_infb);
|
|
|
assign s_ine_o = !s_op_0 & (s_lost | (|s_frac2a[22:0]) | s_overflow);
|
assign s_ine_o = !s_op_0 & (s_lost | (|s_frac2a[22:0]) | s_overflow);
|
|
|
assign s_output_o = (s_nan_in | s_nan_op) ?
|
assign s_output_o = (s_nan_in | s_nan_op) ?
|
{s_sign_i,QNAN} :
|
{s_sign_i,QNAN} :
|
(s_infa | s_infb) | s_overflow ?
|
(s_infa | s_infb) | s_overflow ?
|
{s_sign_i,INF} :
|
{s_sign_i,INF} :
|
s_r_zeros==48 ?
|
s_r_zeros==48 ?
|
{s_sign_i,ZERO_VECTOR} :
|
{s_sign_i,ZERO_VECTOR} :
|
{s_sign_i,s_expo3[7:0],s_frac3[22:0]};
|
{s_sign_i,s_expo3[7:0],s_frac3[22:0]};
|
|
|
endmodule // or1200_fpu_post_norm_mul
|
endmodule // or1200_fpu_post_norm_mul
|
|
|
|
|
