//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// or1200_fpu_pre_norm_addsub ////
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//// or1200_fpu_pre_norm_addsub ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://opencores.org/project,or1k ////
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//// http://opencores.org/project,or1k ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// pre-normalization entity for the addition/subtraction unit ////
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//// pre-normalization entity for the addition/subtraction unit ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Original design (FPU100) - ////
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//// - Original design (FPU100) - ////
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//// Jidan Al-eryani, jidan@gmx.net ////
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//// Jidan Al-eryani, jidan@gmx.net ////
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//// - Conv. to Verilog and inclusion in OR1200 - ////
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//// - Conv. to Verilog and inclusion in OR1200 - ////
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//// Julius Baxter, julius@opencores.org ////
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//// Julius Baxter, julius@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2006, 2010
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// Copyright (C) 2006, 2010
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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//
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//
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// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
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// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
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// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
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// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
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// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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// POSSIBILITY OF SUCH DAMAGE.
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//
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//
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module or1200_fpu_pre_norm_addsub (
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module or1200_fpu_pre_norm_addsub (
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clk_i,
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clk_i,
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opa_i,
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opa_i,
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opb_i,
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opb_i,
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fracta_28_o,
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fracta_28_o,
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fractb_28_o,
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fractb_28_o,
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exp_o
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exp_o
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);
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);
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parameter FP_WIDTH = 32;
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parameter FP_WIDTH = 32;
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parameter MUL_SERIAL = 0; // 0 for parallel multiplier, 1 for serial
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parameter MUL_SERIAL = 0; // 0 for parallel multiplier, 1 for serial
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parameter MUL_COUNT = 11; //11 for parallel multiplier, 34 for serial
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parameter MUL_COUNT = 11; //11 for parallel multiplier, 34 for serial
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parameter FRAC_WIDTH = 23;
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parameter FRAC_WIDTH = 23;
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parameter EXP_WIDTH = 8;
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parameter EXP_WIDTH = 8;
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parameter ZERO_VECTOR = 31'd0;
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parameter ZERO_VECTOR = 31'd0;
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parameter INF = 31'b1111111100000000000000000000000;
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parameter INF = 31'b1111111100000000000000000000000;
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parameter QNAN = 31'b1111111110000000000000000000000;
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parameter QNAN = 31'b1111111110000000000000000000000;
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parameter SNAN = 31'b1111111100000000000000000000001;
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parameter SNAN = 31'b1111111100000000000000000000001;
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input clk_i;
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input clk_i;
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input [FP_WIDTH-1:0] opa_i;
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input [FP_WIDTH-1:0] opa_i;
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input [FP_WIDTH-1:0] opb_i;
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input [FP_WIDTH-1:0] opb_i;
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// carry(1) & hidden(1) & fraction(23) & guard(1) & round(1) & sticky(1)
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// carry(1) & hidden(1) & fraction(23) & guard(1) & round(1) & sticky(1)
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output reg [FRAC_WIDTH+4:0] fracta_28_o;
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output reg [FRAC_WIDTH+4:0] fracta_28_o;
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output reg [FRAC_WIDTH+4:0] fractb_28_o;
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output reg [FRAC_WIDTH+4:0] fractb_28_o;
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output reg [EXP_WIDTH-1:0] exp_o;
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output reg [EXP_WIDTH-1:0] exp_o;
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reg [EXP_WIDTH-1 : 0] s_exp_o ;
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reg [EXP_WIDTH-1 : 0] s_exp_o ;
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wire [FRAC_WIDTH+4 : 0] s_fracta_28_o, s_fractb_28_o ;
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wire [FRAC_WIDTH+4 : 0] s_fracta_28_o, s_fractb_28_o ;
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wire [EXP_WIDTH-1 : 0] s_expa;
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wire [EXP_WIDTH-1 : 0] s_expa;
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wire [EXP_WIDTH-1 : 0] s_expb ;
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wire [EXP_WIDTH-1 : 0] s_expb ;
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wire [FRAC_WIDTH-1 : 0] s_fracta;
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wire [FRAC_WIDTH-1 : 0] s_fracta;
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wire [FRAC_WIDTH-1 : 0] s_fractb ;
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wire [FRAC_WIDTH-1 : 0] s_fractb ;
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wire [FRAC_WIDTH+4 : 0] s_fracta_28;
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wire [FRAC_WIDTH+4 : 0] s_fracta_28;
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wire [FRAC_WIDTH+4 : 0] s_fractb_28 ;
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wire [FRAC_WIDTH+4 : 0] s_fractb_28 ;
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wire [FRAC_WIDTH+4 : 0] s_fract_sm_28;
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wire [FRAC_WIDTH+4 : 0] s_fract_sm_28;
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wire [FRAC_WIDTH+4 : 0] s_fract_shr_28 ;
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wire [FRAC_WIDTH+4 : 0] s_fract_shr_28 ;
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reg [EXP_WIDTH-1 : 0] s_exp_diff ;
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reg [EXP_WIDTH-1 : 0] s_exp_diff ;
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reg [5 : 0] s_rzeros ;
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reg [5 : 0] s_rzeros ;
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wire s_expa_eq_expb;
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wire s_expa_eq_expb;
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wire s_expa_gt_expb;
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wire s_expa_gt_expb;
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wire s_fracta_1;
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wire s_fracta_1;
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wire s_fractb_1;
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wire s_fractb_1;
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wire s_op_dn,s_opa_dn, s_opb_dn;
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wire s_op_dn,s_opa_dn, s_opb_dn;
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wire [1 : 0] s_mux_diff ;
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wire [1 : 0] s_mux_diff ;
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wire s_mux_exp;
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wire s_mux_exp;
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wire s_sticky;
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wire s_sticky;
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assign s_expa = opa_i[30:23];
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assign s_expa = opa_i[30:23];
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assign s_expb = opb_i[30:23];
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assign s_expb = opb_i[30:23];
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assign s_fracta = opa_i[22:0];
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assign s_fracta = opa_i[22:0];
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assign s_fractb = opb_i[22:0];
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assign s_fractb = opb_i[22:0];
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always @(posedge clk_i)
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always @(posedge clk_i)
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begin
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begin
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exp_o <= s_exp_o;
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exp_o <= s_exp_o;
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fracta_28_o <= s_fracta_28_o;
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fracta_28_o <= s_fracta_28_o;
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fractb_28_o <= s_fractb_28_o;
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fractb_28_o <= s_fractb_28_o;
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end
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end
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assign s_expa_eq_expb = (s_expa == s_expb);
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assign s_expa_eq_expb = (s_expa == s_expb);
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assign s_expa_gt_expb = (s_expa > s_expb);
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assign s_expa_gt_expb = (s_expa > s_expb);
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// '1' if fraction is not zero
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// '1' if fraction is not zero
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assign s_fracta_1 = |s_fracta;
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assign s_fracta_1 = |s_fracta;
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assign s_fractb_1 = |s_fractb;
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assign s_fractb_1 = |s_fractb;
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// opa or Opb is denormalized
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// opa or Opb is denormalized
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assign s_opa_dn = !(|s_expa);
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assign s_opa_dn = !(|s_expa);
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assign s_opb_dn = !(|s_expb);
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assign s_opb_dn = !(|s_expb);
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assign s_op_dn = s_opa_dn | s_opb_dn;
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assign s_op_dn = s_opa_dn | s_opb_dn;
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// Output larger exponent
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// Output larger exponent
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assign s_mux_exp = s_expa_gt_expb;
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assign s_mux_exp = s_expa_gt_expb;
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always @(posedge clk_i)
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always @(posedge clk_i)
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s_exp_o <= s_mux_exp ? s_expa : s_expb;
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s_exp_o <= s_mux_exp ? s_expa : s_expb;
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// convert to an easy to handle floating-point format
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// convert to an easy to handle floating-point format
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assign s_fracta_28 = s_opa_dn ?
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assign s_fracta_28 = s_opa_dn ?
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{2'b00, s_fracta, 3'b000} : {2'b01, s_fracta, 3'b000};
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{2'b00, s_fracta, 3'b000} : {2'b01, s_fracta, 3'b000};
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assign s_fractb_28 = s_opb_dn ?
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assign s_fractb_28 = s_opb_dn ?
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{2'b00, s_fractb, 3'b000} : {2'b01, s_fractb, 3'b000};
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{2'b00, s_fractb, 3'b000} : {2'b01, s_fractb, 3'b000};
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assign s_mux_diff = {s_expa_gt_expb, s_opa_dn ^ s_opb_dn};
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assign s_mux_diff = {s_expa_gt_expb, s_opa_dn ^ s_opb_dn};
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// calculate howmany postions the fraction will be shifted
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// calculate howmany postions the fraction will be shifted
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always @(posedge clk_i)
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always @(posedge clk_i)
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begin
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begin
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case(s_mux_diff)
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case(s_mux_diff)
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2'b00: s_exp_diff <= s_expb - s_expa;
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2'b00: s_exp_diff <= s_expb - s_expa;
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2'b01: s_exp_diff <= s_expb - (s_expa + 8'd1);
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2'b01: s_exp_diff <= s_expb - (s_expa + 8'd1);
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2'b10: s_exp_diff <= s_expa - s_expb;
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2'b10: s_exp_diff <= s_expa - s_expb;
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2'b11: s_exp_diff <= s_expa - (s_expb + 8'd1);
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2'b11: s_exp_diff <= s_expa - (s_expb + 8'd1);
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endcase
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endcase
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end
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end
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assign s_fract_sm_28 = s_expa_gt_expb ? s_fractb_28 : s_fracta_28;
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assign s_fract_sm_28 = s_expa_gt_expb ? s_fractb_28 : s_fracta_28;
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// shift-right the fraction if necessary
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// shift-right the fraction if necessary
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assign s_fract_shr_28 = s_fract_sm_28 >> s_exp_diff;
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assign s_fract_shr_28 = s_fract_sm_28 >> s_exp_diff;
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// count the zeros from right to check if result is inexact
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// count the zeros from right to check if result is inexact
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always @(s_fract_sm_28)
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always @(s_fract_sm_28)
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casex(s_fract_sm_28) // synopsys full_case parallel_case
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casez(s_fract_sm_28) // synopsys full_case parallel_case
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28'b???????????????????????????1: s_rzeros <= 0;
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28'b???????????????????????????1: s_rzeros = 0;
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28'b??????????????????????????10: s_rzeros <= 1;
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28'b??????????????????????????10: s_rzeros = 1;
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28'b?????????????????????????100: s_rzeros <= 2;
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28'b?????????????????????????100: s_rzeros = 2;
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28'b????????????????????????1000: s_rzeros <= 3;
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28'b????????????????????????1000: s_rzeros = 3;
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28'b???????????????????????10000: s_rzeros <= 4;
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28'b???????????????????????10000: s_rzeros = 4;
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28'b??????????????????????100000: s_rzeros <= 5;
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28'b??????????????????????100000: s_rzeros = 5;
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28'b?????????????????????1000000: s_rzeros <= 6;
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28'b?????????????????????1000000: s_rzeros = 6;
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28'b????????????????????10000000: s_rzeros <= 7;
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28'b????????????????????10000000: s_rzeros = 7;
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28'b???????????????????100000000: s_rzeros <= 8;
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28'b???????????????????100000000: s_rzeros = 8;
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28'b??????????????????1000000000: s_rzeros <= 9;
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28'b??????????????????1000000000: s_rzeros = 9;
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28'b?????????????????10000000000: s_rzeros <= 10;
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28'b?????????????????10000000000: s_rzeros = 10;
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28'b????????????????100000000000: s_rzeros <= 11;
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28'b????????????????100000000000: s_rzeros = 11;
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28'b???????????????1000000000000: s_rzeros <= 12;
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28'b???????????????1000000000000: s_rzeros = 12;
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28'b??????????????10000000000000: s_rzeros <= 13;
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28'b??????????????10000000000000: s_rzeros = 13;
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28'b?????????????100000000000000: s_rzeros <= 14;
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28'b?????????????100000000000000: s_rzeros = 14;
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28'b????????????1000000000000000: s_rzeros <= 15;
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28'b????????????1000000000000000: s_rzeros = 15;
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28'b???????????10000000000000000: s_rzeros <= 16;
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28'b???????????10000000000000000: s_rzeros = 16;
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28'b??????????100000000000000000: s_rzeros <= 17;
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28'b??????????100000000000000000: s_rzeros = 17;
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28'b?????????1000000000000000000: s_rzeros <= 18;
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28'b?????????1000000000000000000: s_rzeros = 18;
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28'b????????10000000000000000000: s_rzeros <= 19;
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28'b????????10000000000000000000: s_rzeros = 19;
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28'b???????100000000000000000000: s_rzeros <= 20;
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28'b???????100000000000000000000: s_rzeros = 20;
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28'b??????1000000000000000000000: s_rzeros <= 21;
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28'b??????1000000000000000000000: s_rzeros = 21;
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28'b?????10000000000000000000000: s_rzeros <= 22;
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28'b?????10000000000000000000000: s_rzeros = 22;
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28'b????100000000000000000000000: s_rzeros <= 23;
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28'b????100000000000000000000000: s_rzeros = 23;
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28'b???1000000000000000000000000: s_rzeros <= 24;
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28'b???1000000000000000000000000: s_rzeros = 24;
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28'b??10000000000000000000000000: s_rzeros <= 25;
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28'b??10000000000000000000000000: s_rzeros = 25;
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28'b?100000000000000000000000000: s_rzeros <= 26;
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28'b?100000000000000000000000000: s_rzeros = 26;
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28'b1000000000000000000000000000: s_rzeros <= 27;
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28'b1000000000000000000000000000: s_rzeros = 27;
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28'b0000000000000000000000000000: s_rzeros <= 28;
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28'b0000000000000000000000000000: s_rzeros = 28;
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endcase // casex (s_fract_sm_28)
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endcase // casex (s_fract_sm_28)
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assign s_sticky = (s_exp_diff > s_rzeros) & (|s_fract_sm_28);
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assign s_sticky = (s_exp_diff > {2'b00,s_rzeros}) & (|s_fract_sm_28);
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assign s_fracta_28_o = s_expa_gt_expb ?
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assign s_fracta_28_o = s_expa_gt_expb ?
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s_fracta_28 :
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s_fracta_28 :
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{s_fract_shr_28[27:1],(s_sticky|s_fract_shr_28[0])};
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{s_fract_shr_28[27:1],(s_sticky|s_fract_shr_28[0])};
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assign s_fractb_28_o = s_expa_gt_expb ?
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assign s_fractb_28_o = s_expa_gt_expb ?
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{s_fract_shr_28[27:1],(s_sticky|s_fract_shr_28[0])} :
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{s_fract_shr_28[27:1],(s_sticky|s_fract_shr_28[0])} :
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s_fractb_28;
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s_fractb_28;
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endmodule // or1200_fpu_pre_norm_addsub
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endmodule // or1200_fpu_pre_norm_addsub
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