//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's instruction fetch ////
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//// OR1200's instruction fetch ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/project,or1k ////
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//// http://www.opencores.org/project,or1k ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// PC, instruction fetch, interface to IC. ////
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//// PC, instruction fetch, interface to IC. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - make it smaller and faster ////
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//// - make it smaller and faster ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// $Log: or1200_if.v,v $
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// $Log: or1200_if.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Major update:
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// Major update:
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// Structure reordered and bugs fixed.
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// Structure reordered and bugs fixed.
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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module or1200_if(
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module or1200_if(
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// Clock and reset
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// Clock and reset
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clk, rst,
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clk, rst,
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// External i/f to IC
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// External i/f to IC
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icpu_dat_i, icpu_ack_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
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icpu_dat_i, icpu_ack_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
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// Internal i/f
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// Internal i/f
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if_freeze, if_insn, if_pc, if_flushpipe, saving_if_insn,
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if_freeze, if_insn, if_pc, if_flushpipe, saving_if_insn,
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if_stall, no_more_dslot, genpc_refetch, rfe,
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if_stall, no_more_dslot, genpc_refetch, rfe,
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except_itlbmiss, except_immufault, except_ibuserr
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except_itlbmiss, except_immufault, except_ibuserr
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);
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);
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//
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//
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// I/O
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// I/O
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//
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//
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//
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//
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// Clock and reset
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// Clock and reset
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//
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//
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input clk;
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input clk;
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input rst;
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input rst;
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//
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//
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// External i/f to IC
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// External i/f to IC
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//
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//
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input [31:0] icpu_dat_i;
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input [31:0] icpu_dat_i;
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input icpu_ack_i;
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input icpu_ack_i;
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input icpu_err_i;
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input icpu_err_i;
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input [31:0] icpu_adr_i;
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input [31:0] icpu_adr_i;
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input [3:0] icpu_tag_i;
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input [3:0] icpu_tag_i;
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//
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//
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// Internal i/f
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// Internal i/f
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//
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//
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input if_freeze;
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input if_freeze;
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output [31:0] if_insn;
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output [31:0] if_insn;
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output [31:0] if_pc;
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output [31:0] if_pc;
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input if_flushpipe;
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input if_flushpipe;
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output saving_if_insn;
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output saving_if_insn;
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output if_stall;
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output if_stall;
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input no_more_dslot;
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input no_more_dslot;
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output genpc_refetch;
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output genpc_refetch;
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input rfe;
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input rfe;
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output except_itlbmiss;
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output except_itlbmiss;
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output except_immufault;
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output except_immufault;
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output except_ibuserr;
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output except_ibuserr;
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//
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//
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// Internal wires and regs
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// Internal wires and regs
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//
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//
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wire save_insn;
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wire save_insn;
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wire if_bypass;
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wire if_bypass;
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reg if_bypass_reg;
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reg if_bypass_reg;
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reg [31:0] insn_saved;
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reg [31:0] insn_saved;
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reg [31:0] addr_saved;
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reg [31:0] addr_saved;
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reg [2:0] err_saved;
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reg [2:0] err_saved;
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reg saved;
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reg saved;
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assign save_insn = (icpu_ack_i | icpu_err_i) & if_freeze & !saved;
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assign save_insn = (icpu_ack_i | icpu_err_i) & if_freeze & !saved;
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assign saving_if_insn = !if_flushpipe & save_insn;
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assign saving_if_insn = !if_flushpipe & save_insn;
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//
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//
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// IF bypass
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// IF bypass
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//
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//
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assign if_bypass = icpu_adr_i[0] ? 1'b0 : if_bypass_reg | if_flushpipe;
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assign if_bypass = icpu_adr_i[0] ? 1'b0 : if_bypass_reg | if_flushpipe;
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always @(posedge clk or posedge rst)
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always @(posedge clk or `OR1200_RST_EVENT rst)
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if (rst)
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if (rst == `OR1200_RST_VALUE)
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if_bypass_reg <= 1'b0;
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if_bypass_reg <= 1'b0;
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else
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else
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if_bypass_reg <= if_bypass;
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if_bypass_reg <= if_bypass;
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//
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//
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// IF stage insn
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// IF stage insn
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//
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//
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assign if_insn = no_more_dslot | rfe | if_bypass ? {`OR1200_OR32_NOP, 26'h041_0000} : saved ? insn_saved : icpu_ack_i ? icpu_dat_i : {`OR1200_OR32_NOP, 26'h061_0000};
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assign if_insn = no_more_dslot | rfe | if_bypass ? {`OR1200_OR32_NOP, 26'h041_0000} : saved ? insn_saved : icpu_ack_i ? icpu_dat_i : {`OR1200_OR32_NOP, 26'h061_0000};
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assign if_pc = saved ? addr_saved : {icpu_adr_i[31:2], 2'h0};
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assign if_pc = saved ? addr_saved : {icpu_adr_i[31:2], 2'h0};
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assign if_stall = !icpu_err_i & !icpu_ack_i & !saved;
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assign if_stall = !icpu_err_i & !icpu_ack_i & !saved;
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assign genpc_refetch = saved & icpu_ack_i;
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assign genpc_refetch = saved & icpu_ack_i;
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assign except_itlbmiss = no_more_dslot ? 1'b0 : saved ? err_saved[0] : icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE);
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assign except_itlbmiss = no_more_dslot ? 1'b0 : saved ? err_saved[0] : icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE);
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assign except_immufault = no_more_dslot ? 1'b0 : saved ? err_saved[1] : icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE);
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assign except_immufault = no_more_dslot ? 1'b0 : saved ? err_saved[1] : icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE);
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assign except_ibuserr = no_more_dslot ? 1'b0 : saved ? err_saved[2] : icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE);
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assign except_ibuserr = no_more_dslot ? 1'b0 : saved ? err_saved[2] : icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE);
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//
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//
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// Flag for saved insn/address
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// Flag for saved insn/address
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or `OR1200_RST_EVENT rst)
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if (rst)
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if (rst == `OR1200_RST_VALUE)
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saved <= 1'b0;
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saved <= 1'b0;
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else if (if_flushpipe)
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else if (if_flushpipe)
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saved <= 1'b0;
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saved <= 1'b0;
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else if (save_insn)
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else if (save_insn)
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saved <= 1'b1;
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saved <= 1'b1;
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else if (!if_freeze)
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else if (!if_freeze)
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saved <= 1'b0;
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saved <= 1'b0;
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//
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//
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// Store fetched instruction
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// Store fetched instruction
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or `OR1200_RST_EVENT rst)
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if (rst)
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if (rst == `OR1200_RST_VALUE)
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insn_saved <= {`OR1200_OR32_NOP, 26'h041_0000};
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insn_saved <= {`OR1200_OR32_NOP, 26'h041_0000};
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else if (if_flushpipe)
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else if (if_flushpipe)
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insn_saved <= {`OR1200_OR32_NOP, 26'h041_0000};
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insn_saved <= {`OR1200_OR32_NOP, 26'h041_0000};
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else if (save_insn)
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else if (save_insn)
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insn_saved <= icpu_err_i ? {`OR1200_OR32_NOP, 26'h041_0000} : icpu_dat_i;
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insn_saved <= icpu_err_i ? {`OR1200_OR32_NOP, 26'h041_0000} : icpu_dat_i;
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else if (!if_freeze)
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else if (!if_freeze)
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insn_saved <= {`OR1200_OR32_NOP, 26'h041_0000};
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insn_saved <= {`OR1200_OR32_NOP, 26'h041_0000};
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//
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//
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// Store fetched instruction's address
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// Store fetched instruction's address
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or `OR1200_RST_EVENT rst)
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if (rst)
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if (rst == `OR1200_RST_VALUE)
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addr_saved <= 32'h00000000;
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addr_saved <= 32'h00000000;
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else if (if_flushpipe)
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else if (if_flushpipe)
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addr_saved <= 32'h00000000;
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addr_saved <= 32'h00000000;
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else if (save_insn)
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else if (save_insn)
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addr_saved <= {icpu_adr_i[31:2], 2'b00};
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addr_saved <= {icpu_adr_i[31:2], 2'b00};
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else if (!if_freeze)
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else if (!if_freeze)
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addr_saved <= {icpu_adr_i[31:2], 2'b00};
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addr_saved <= {icpu_adr_i[31:2], 2'b00};
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//
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//
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// Store fetched instruction's error tags
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// Store fetched instruction's error tags
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or `OR1200_RST_EVENT rst)
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if (rst)
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if (rst == `OR1200_RST_VALUE)
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err_saved <= 3'b000;
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err_saved <= 3'b000;
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else if (if_flushpipe)
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else if (if_flushpipe)
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err_saved <= 3'b000;
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err_saved <= 3'b000;
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else if (save_insn) begin
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else if (save_insn) begin
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err_saved[0] <= icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE);
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err_saved[0] <= icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE);
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err_saved[1] <= icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE);
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err_saved[1] <= icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE);
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err_saved[2] <= icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE);
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err_saved[2] <= icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE);
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end
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end
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else if (!if_freeze)
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else if (!if_freeze)
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err_saved <= 3'b000;
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err_saved <= 3'b000;
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endmodule
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endmodule
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