//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// OR1200's register file read operands mux ////
|
//// OR1200's register file read operands mux ////
|
//// ////
|
//// ////
|
//// This file is part of the OpenRISC 1200 project ////
|
//// This file is part of the OpenRISC 1200 project ////
|
//// http://www.opencores.org/project,or1k ////
|
//// http://www.opencores.org/project,or1k ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// Mux for two register file read operands. ////
|
//// Mux for two register file read operands. ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - make it smaller and faster ////
|
//// - make it smaller and faster ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Damjan Lampret, lampret@opencores.org ////
|
//// - Damjan Lampret, lampret@opencores.org ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// $Log: or1200_operandmuxes.v,v $
|
// $Log: or1200_operandmuxes.v,v $
|
// Revision 2.0 2010/06/30 11:00:00 ORSoC
|
// Revision 2.0 2010/06/30 11:00:00 ORSoC
|
// Minor update:
|
// Minor update:
|
// Bugs fixed.
|
// Bugs fixed.
|
|
|
// synopsys translate_off
|
// synopsys translate_off
|
`include "timescale.v"
|
`include "timescale.v"
|
// synopsys translate_on
|
// synopsys translate_on
|
`include "or1200_defines.v"
|
`include "or1200_defines.v"
|
|
|
module or1200_operandmuxes(
|
module or1200_operandmuxes(
|
// Clock and reset
|
// Clock and reset
|
clk, rst,
|
clk, rst,
|
|
|
// Internal i/f
|
// Internal i/f
|
id_freeze, ex_freeze, rf_dataa, rf_datab, ex_forw, wb_forw,
|
id_freeze, ex_freeze, rf_dataa, rf_datab, ex_forw, wb_forw,
|
simm, sel_a, sel_b, operand_a, operand_b, muxed_a, muxed_b
|
simm, sel_a, sel_b, operand_a, operand_b, muxed_a, muxed_b
|
);
|
);
|
|
|
parameter width = `OR1200_OPERAND_WIDTH;
|
parameter width = `OR1200_OPERAND_WIDTH;
|
|
|
//
|
//
|
// I/O
|
// I/O
|
//
|
//
|
input clk;
|
input clk;
|
input rst;
|
input rst;
|
input id_freeze;
|
input id_freeze;
|
input ex_freeze;
|
input ex_freeze;
|
input [width-1:0] rf_dataa;
|
input [width-1:0] rf_dataa;
|
input [width-1:0] rf_datab;
|
input [width-1:0] rf_datab;
|
input [width-1:0] ex_forw;
|
input [width-1:0] ex_forw;
|
input [width-1:0] wb_forw;
|
input [width-1:0] wb_forw;
|
input [width-1:0] simm;
|
input [width-1:0] simm;
|
input [`OR1200_SEL_WIDTH-1:0] sel_a;
|
input [`OR1200_SEL_WIDTH-1:0] sel_a;
|
input [`OR1200_SEL_WIDTH-1:0] sel_b;
|
input [`OR1200_SEL_WIDTH-1:0] sel_b;
|
output [width-1:0] operand_a;
|
output [width-1:0] operand_a;
|
output [width-1:0] operand_b;
|
output [width-1:0] operand_b;
|
output [width-1:0] muxed_a;
|
output [width-1:0] muxed_a;
|
output [width-1:0] muxed_b;
|
output [width-1:0] muxed_b;
|
|
|
//
|
//
|
// Internal wires and regs
|
// Internal wires and regs
|
//
|
//
|
reg [width-1:0] operand_a;
|
reg [width-1:0] operand_a;
|
reg [width-1:0] operand_b;
|
reg [width-1:0] operand_b;
|
reg [width-1:0] muxed_a;
|
reg [width-1:0] muxed_a;
|
reg [width-1:0] muxed_b;
|
reg [width-1:0] muxed_b;
|
reg saved_a;
|
reg saved_a;
|
reg saved_b;
|
reg saved_b;
|
|
|
//
|
//
|
// Operand A register
|
// Operand A register
|
//
|
//
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
if (rst == `OR1200_RST_VALUE) begin
|
if (rst == `OR1200_RST_VALUE) begin
|
operand_a <= 32'd0;
|
operand_a <= 32'd0;
|
saved_a <= 1'b0;
|
saved_a <= 1'b0;
|
end else if (!ex_freeze && id_freeze && !saved_a) begin
|
end else if (!ex_freeze && id_freeze && !saved_a) begin
|
operand_a <= muxed_a;
|
operand_a <= muxed_a;
|
saved_a <= 1'b1;
|
saved_a <= 1'b1;
|
end else if (!ex_freeze && !saved_a) begin
|
end else if (!ex_freeze && !saved_a) begin
|
operand_a <= muxed_a;
|
operand_a <= muxed_a;
|
end else if (!ex_freeze && !id_freeze)
|
end else if (!ex_freeze && !id_freeze)
|
saved_a <= 1'b0;
|
saved_a <= 1'b0;
|
end
|
end
|
|
|
//
|
//
|
// Operand B register
|
// Operand B register
|
//
|
//
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
always @(posedge clk or `OR1200_RST_EVENT rst) begin
|
if (rst == `OR1200_RST_VALUE) begin
|
if (rst == `OR1200_RST_VALUE) begin
|
operand_b <= 32'd0;
|
operand_b <= 32'd0;
|
saved_b <= 1'b0;
|
saved_b <= 1'b0;
|
end else if (!ex_freeze && id_freeze && !saved_b) begin
|
end else if (!ex_freeze && id_freeze && !saved_b) begin
|
operand_b <= muxed_b;
|
operand_b <= muxed_b;
|
saved_b <= 1'b1;
|
saved_b <= 1'b1;
|
end else if (!ex_freeze && !saved_b) begin
|
end else if (!ex_freeze && !saved_b) begin
|
operand_b <= muxed_b;
|
operand_b <= muxed_b;
|
end else if (!ex_freeze && !id_freeze)
|
end else if (!ex_freeze && !id_freeze)
|
saved_b <= 1'b0;
|
saved_b <= 1'b0;
|
end
|
end
|
|
|
//
|
//
|
// Forwarding logic for operand A register
|
// Forwarding logic for operand A register
|
//
|
//
|
always @(ex_forw or wb_forw or rf_dataa or sel_a) begin
|
always @(ex_forw or wb_forw or rf_dataa or sel_a) begin
|
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
|
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
|
casex (sel_a) // synopsys parallel_case infer_mux
|
casez (sel_a) // synopsys parallel_case infer_mux
|
`else
|
`else
|
casex (sel_a) // synopsys parallel_case
|
casez (sel_a) // synopsys parallel_case
|
`endif
|
`endif
|
`OR1200_SEL_EX_FORW:
|
`OR1200_SEL_EX_FORW:
|
muxed_a = ex_forw;
|
muxed_a = ex_forw;
|
`OR1200_SEL_WB_FORW:
|
`OR1200_SEL_WB_FORW:
|
muxed_a = wb_forw;
|
muxed_a = wb_forw;
|
default:
|
default:
|
muxed_a = rf_dataa;
|
muxed_a = rf_dataa;
|
endcase
|
endcase
|
end
|
end
|
|
|
//
|
//
|
// Forwarding logic for operand B register
|
// Forwarding logic for operand B register
|
//
|
//
|
always @(simm or ex_forw or wb_forw or rf_datab or sel_b) begin
|
always @(simm or ex_forw or wb_forw or rf_datab or sel_b) begin
|
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
|
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
|
casex (sel_b) // synopsys parallel_case infer_mux
|
casez (sel_b) // synopsys parallel_case infer_mux
|
`else
|
`else
|
casex (sel_b) // synopsys parallel_case
|
casez (sel_b) // synopsys parallel_case
|
`endif
|
`endif
|
`OR1200_SEL_IMM:
|
`OR1200_SEL_IMM:
|
muxed_b = simm;
|
muxed_b = simm;
|
`OR1200_SEL_EX_FORW:
|
`OR1200_SEL_EX_FORW:
|
muxed_b = ex_forw;
|
muxed_b = ex_forw;
|
`OR1200_SEL_WB_FORW:
|
`OR1200_SEL_WB_FORW:
|
muxed_b = wb_forw;
|
muxed_b = wb_forw;
|
default:
|
default:
|
muxed_b = rf_datab;
|
muxed_b = rf_datab;
|
endcase
|
endcase
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
