OpenCores

Rev 10	Rev 141
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//// ////`	`//// ////`
`//// OR1200's Programmable Interrupt Controller ////`	`//// OR1200's Programmable Interrupt Controller ////`
`//// ////`	`//// ////`
`//// This file is part of the OpenRISC 1200 project ////`	`//// This file is part of the OpenRISC 1200 project ////`
`//// http://www.opencores.org/cores/or1k/ ////`	`//// http://www.opencores.org/cores/or1k/ ////`
`//// ////`	`//// ////`
`//// Description ////`	`//// Description ////`
`//// PIC according to OR1K architectural specification. ////`	`//// PIC according to OR1K architectural specification. ////`
`//// ////`	`//// ////`
`//// To Do: ////`	`//// To Do: ////`
`//// None ////`	`//// None ////`
`//// ////`	`//// ////`
`//// Author(s): ////`	`//// Author(s): ////`
`//// - Damjan Lampret, lampret@opencores.org ////`	`//// - Damjan Lampret, lampret@opencores.org ////`
`//// ////`	`//// ////`
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//// ////`	`//// ////`
`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`	`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
`//// ////`	`//// ////`
`//// This source file may be used and distributed without ////`	`//// This source file may be used and distributed without ////`
`//// restriction provided that this copyright statement is not ////`	`//// restriction provided that this copyright statement is not ////`
`//// removed from the file and that any derivative work contains ////`	`//// removed from the file and that any derivative work contains ////`
`//// the original copyright notice and the associated disclaimer. ////`	`//// the original copyright notice and the associated disclaimer. ////`
`//// ////`	`//// ////`
`//// This source file is free software; you can redistribute it ////`	`//// This source file is free software; you can redistribute it ////`
`//// and/or modify it under the terms of the GNU Lesser General ////`	`//// and/or modify it under the terms of the GNU Lesser General ////`
`//// Public License as published by the Free Software Foundation; ////`	`//// Public License as published by the Free Software Foundation; ////`
`//// either version 2.1 of the License, or (at your option) any ////`	`//// either version 2.1 of the License, or (at your option) any ////`
`//// later version. ////`	`//// later version. ////`
`//// ////`	`//// ////`
`//// This source is distributed in the hope that it will be ////`	`//// This source is distributed in the hope that it will be ////`
`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`	`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`	`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
`//// PURPOSE. See the GNU Lesser General Public License for more ////`	`//// PURPOSE. See the GNU Lesser General Public License for more ////`
`//// details. ////`	`//// details. ////`
`//// ////`	`//// ////`
`//// You should have received a copy of the GNU Lesser General ////`	`//// You should have received a copy of the GNU Lesser General ////`
`//// Public License along with this source; if not, download it ////`	`//// Public License along with this source; if not, download it ////`
`//// from http://www.opencores.org/lgpl.shtml ////`	`//// from http://www.opencores.org/lgpl.shtml ////`
`//// ////`	`//// ////`
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: or1200_pic.v,v $`
	`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
	`// No update`
	`//`
	`// Revision 1.4 2004/06/08 18:17:36 lampret`
	`// Non-functional changes. Coding style fixes.`
	`//`
`// Revision 1.3 2002/03/29 15:16:56 lampret`	`// Revision 1.3 2002/03/29 15:16:56 lampret`
`// Some of the warnings fixed.`	`// Some of the warnings fixed.`
`//`	`//`
`// Revision 1.2 2002/01/18 07:56:00 lampret`	`// Revision 1.2 2002/01/18 07:56:00 lampret`
`// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.`	`// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.`
`//`	`//`
`// Revision 1.1 2002/01/03 08:16:15 lampret`	`// Revision 1.1 2002/01/03 08:16:15 lampret`
`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`	`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
`//`	`//`
`// Revision 1.8 2001/10/21 17:57:16 lampret`	`// Revision 1.8 2001/10/21 17:57:16 lampret`
`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`	`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
`//`	`//`
`// Revision 1.7 2001/10/14 13:12:10 lampret`	`// Revision 1.7 2001/10/14 13:12:10 lampret`
`// MP3 version.`	`// MP3 version.`
`//`	`//`
`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`	`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
`// no message`	`// no message`
`//`	`//`
`// Revision 1.2 2001/08/09 13:39:33 lampret`	`// Revision 1.2 2001/08/09 13:39:33 lampret`
`// Major clean-up.`	`// Major clean-up.`
`//`	`//`
`// Revision 1.1 2001/07/20 00:46:21 lampret`	`// Revision 1.1 2001/07/20 00:46:21 lampret`
`// Development version of RTL. Libraries are missing.`	`// Development version of RTL. Libraries are missing.`
`//`	`//`
`//`	`//`

`// synopsys translate_off`	`// synopsys translate_off`
`include "timescale.v"	`include "timescale.v"
`// synopsys translate_on`	`// synopsys translate_on`
`include "or1200_defines.v"	`include "or1200_defines.v"

`module or1200_pic(`	`module or1200_pic(`
`// RISC Internal Interface`	`// RISC Internal Interface`
`clk, rst, spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,`	`clk, rst, spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,`
`pic_wakeup, intr,`	`pic_wakeup, intr,`

`// PIC Interface`	`// PIC Interface`
`pic_int`	`pic_int`
`);`	`);`

`//`	`//`
`// RISC Internal Interface`	`// RISC Internal Interface`
`//`	`//`
`input clk; // Clock`	`input clk; // Clock`
`input rst; // Reset`	`input rst; // Reset`
`input spr_cs; // SPR CS`	`input spr_cs; // SPR CS`
`input spr_write; // SPR Write`	`input spr_write; // SPR Write`
`input [31:0] spr_addr; // SPR Address`	`input [31:0] spr_addr; // SPR Address`
`input [31:0] spr_dat_i; // SPR Write Data`	`input [31:0] spr_dat_i; // SPR Write Data`
`output [31:0] spr_dat_o; // SPR Read Data`	`output [31:0] spr_dat_o; // SPR Read Data`
`output pic_wakeup; // Wakeup to the PM`	`output pic_wakeup; // Wakeup to the PM`
`output intr; // interrupt`	`output intr; // interrupt`
`// exception request`	`// exception request`

`//`	`//`
`// PIC Interface`	`// PIC Interface`
`//`	`//`
input [`OR1200_PIC_INTS-1:0] pic_int;// Interrupt inputs	input [`OR1200_PIC_INTS-1:0] pic_int;// Interrupt inputs

`ifdef OR1200_PIC_IMPLEMENTED	`ifdef OR1200_PIC_IMPLEMENTED

`//`	`//`
`// PIC Mask Register bits (or no register)`	`// PIC Mask Register bits (or no register)`
`//`	`//`
`ifdef OR1200_PIC_PICMR	`ifdef OR1200_PIC_PICMR
reg [`OR1200_PIC_INTS-1:2] picmr; // PICMR bits	reg [`OR1200_PIC_INTS-1:2] picmr; // PICMR bits
`else	`else
wire [`OR1200_PIC_INTS-1:2] picmr; // No PICMR register	wire [`OR1200_PIC_INTS-1:2] picmr; // No PICMR register
`endif	`endif

`//`	`//`
`// PIC Status Register bits (or no register)`	`// PIC Status Register bits (or no register)`
`//`	`//`
`ifdef OR1200_PIC_PICSR	`ifdef OR1200_PIC_PICSR
reg [`OR1200_PIC_INTS-1:0] picsr; // PICSR bits	reg [`OR1200_PIC_INTS-1:0] picsr; // PICSR bits
`else	`else
wire [`OR1200_PIC_INTS-1:0] picsr; // No PICSR register	wire [`OR1200_PIC_INTS-1:0] picsr; // No PICSR register
`endif	`endif

`//`	`//`
`// Internal wires & regs`	`// Internal wires & regs`
`//`	`//`
`wire picmr_sel; // PICMR select`	`wire picmr_sel; // PICMR select`
`wire picsr_sel; // PICSR select`	`wire picsr_sel; // PICSR select`
wire [`OR1200_PIC_INTS-1:0] um_ints;// Unmasked interrupts	wire [`OR1200_PIC_INTS-1:0] um_ints;// Unmasked interrupts
`reg [31:0] spr_dat_o; // SPR data out`	`reg [31:0] spr_dat_o; // SPR data out`

`//`	`//`
`// PIC registers address decoder`	`// PIC registers address decoder`
`//`	`//`
assign picmr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICMR)) ? 1'b1 : 1'b0;	assign picmr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICMR)) ? 1'b1 : 1'b0;
assign picsr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICSR)) ? 1'b1 : 1'b0;	assign picsr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICSR)) ? 1'b1 : 1'b0;

`//`	`//`
`// Write to PICMR`	`// Write to PICMR`
`//`	`//`
`ifdef OR1200_PIC_PICMR	`ifdef OR1200_PIC_PICMR
`always @(posedge clk or posedge rst)`	`always @(posedge clk or posedge rst)`
`if (rst)`	`if (rst)`
picmr <= {1'b1, {`OR1200_PIC_INTS-3{1'b0}}};	picmr <= {1'b1, {`OR1200_PIC_INTS-3{1'b0}}};
`else if (picmr_sel && spr_write) begin`	`else if (picmr_sel && spr_write) begin`
picmr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:2];	picmr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:2];
`end`	`end`
`else	`else
assign picmr = (`OR1200_PIC_INTS)'b1;	assign picmr = (`OR1200_PIC_INTS)'b1;
`endif	`endif

`//`	`//`
`// Write to PICSR, both CPU and external ints`	`// Write to PICSR, both CPU and external ints`
`//`	`//`
`ifdef OR1200_PIC_PICSR	`ifdef OR1200_PIC_PICSR
`always @(posedge clk or posedge rst)`	`always @(posedge clk or posedge rst)`
`if (rst)`	`if (rst)`
picsr <= {`OR1200_PIC_INTS{1'b0}};	picsr <= {`OR1200_PIC_INTS{1'b0}};
`else if (picsr_sel && spr_write) begin`	`else if (picsr_sel && spr_write) begin`
picsr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:0] \| um_ints;	picsr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:0] \| um_ints;
`end else`	`end else`
`picsr <= #1 picsr \| um_ints;`	`picsr <= #1 picsr \| um_ints;`
`else	`else
`assign picsr = pic_int;`	`assign picsr = pic_int;`
`endif	`endif

`//`	`//`
`// Read PIC registers`	`// Read PIC registers`
`//`	`//`
`always @(spr_addr or picmr or picsr)`	`always @(spr_addr or picmr or picsr)`
case (spr_addr[`OR1200_PICOFS_BITS]) // synopsys parallel_case	case (spr_addr[`OR1200_PICOFS_BITS]) // synopsys parallel_case
`ifdef OR1200_PIC_READREGS	`ifdef OR1200_PIC_READREGS
`OR1200_PIC_OFS_PICMR: begin	`OR1200_PIC_OFS_PICMR: begin
spr_dat_o[`OR1200_PIC_INTS-1:0] = {picmr, 2'b0};	spr_dat_o[`OR1200_PIC_INTS-1:0] = {picmr, 2'b0};
`ifdef OR1200_PIC_UNUSED_ZERO	`ifdef OR1200_PIC_UNUSED_ZERO
spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};	spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
`endif	`endif
`end`	`end`
`endif	`endif
`default: begin`	`default: begin`
spr_dat_o[`OR1200_PIC_INTS-1:0] = picsr;	spr_dat_o[`OR1200_PIC_INTS-1:0] = picsr;
`ifdef OR1200_PIC_UNUSED_ZERO	`ifdef OR1200_PIC_UNUSED_ZERO
spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};	spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
`endif	`endif
`end`	`end`
`endcase`	`endcase`

`//`	`//`
`// Unmasked interrupts`	`// Unmasked interrupts`
`//`	`//`
`assign um_ints = pic_int & {picmr, 2'b11};`	`assign um_ints = pic_int & {picmr, 2'b11};`

`//`	`//`
`// Generate intr`	`// Generate intr`
`//`	`//`
`assign intr = \|um_ints;`	`assign intr = \|um_ints;`

`//`	`//`
`// Assert pic_wakeup when intr is asserted`	`// Assert pic_wakeup when intr is asserted`
`//`	`//`
`assign pic_wakeup = intr;`	`assign pic_wakeup = intr;`

`else	`else

`//`	`//`
`// When PIC is not implemented, drive all outputs as would when PIC is disabled`	`// When PIC is not implemented, drive all outputs as would when PIC is disabled`
`//`	`//`
`assign intr = pic_int[1] \| pic_int[0];`	`assign intr = pic_int[1] \| pic_int[0];`
`assign pic_wakeup= intr;`	`assign pic_wakeup= intr;`

`//`	`//`
`// Read PIC registers`	`// Read PIC registers`
`//`	`//`
`ifdef OR1200_PIC_READREGS	`ifdef OR1200_PIC_READREGS
assign spr_dat_o[`OR1200_PIC_INTS-1:0] = `OR1200_PIC_INTS'b0;	assign spr_dat_o[`OR1200_PIC_INTS-1:0] = `OR1200_PIC_INTS'b0;
`ifdef OR1200_PIC_UNUSED_ZERO	`ifdef OR1200_PIC_UNUSED_ZERO
assign spr_dat_o[31:`OR1200_PIC_INTS] = 32-`OR1200_PIC_INTS'b0;	assign spr_dat_o[31:`OR1200_PIC_INTS] = 32-`OR1200_PIC_INTS'b0;
`endif	`endif
`endif	`endif

`endif	`endif

`endmodule`	`endmodule`

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

////                                                              ////

////                                                              ////

////  OR1200's Programmable Interrupt Controller                  ////

////  OR1200's Programmable Interrupt Controller                  ////

////                                                              ////

////                                                              ////

////  This file is part of the OpenRISC 1200 project              ////

////  This file is part of the OpenRISC 1200 project              ////

////  http://www.opencores.org/cores/or1k/                        ////

////  http://www.opencores.org/cores/or1k/                        ////

////                                                              ////

////                                                              ////

////  Description                                                 ////

////  Description                                                 ////

////  PIC according to OR1K architectural specification.          ////

////  PIC according to OR1K architectural specification.          ////

////                                                              ////

////                                                              ////

////  To Do:                                                      ////

////  To Do:                                                      ////

////   None                                                       ////

////   None                                                       ////

////                                                              ////

////                                                              ////

////  Author(s):                                                  ////

////  Author(s):                                                  ////

////      - Damjan Lampret, lampret@opencores.org                 ////

////      - Damjan Lampret, lampret@opencores.org                 ////

////                                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

////                                                              ////

////                                                              ////

//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////

//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////

////                                                              ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

//// later version.                                               ////

////                                                              ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

//// details.                                                     ////

////                                                              ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

//

//

// CVS Revision History

// CVS Revision History

//

//

// $Log: not supported by cvs2svn $

// $Log: or1200_pic.v,v $

// Revision 2.0  2010/06/30 11:00:00  ORSoC

// No update

//

// Revision 1.4  2004/06/08 18:17:36  lampret

// Non-functional changes. Coding style fixes.

//

// Revision 1.3  2002/03/29 15:16:56  lampret

// Revision 1.3  2002/03/29 15:16:56  lampret

// Some of the warnings fixed.

// Some of the warnings fixed.

//

//

// Revision 1.2  2002/01/18 07:56:00  lampret

// Revision 1.2  2002/01/18 07:56:00  lampret

// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.

// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.

//

//

// Revision 1.1  2002/01/03 08:16:15  lampret

// Revision 1.1  2002/01/03 08:16:15  lampret

// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.

// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.

//

//

// Revision 1.8  2001/10/21 17:57:16  lampret

// Revision 1.8  2001/10/21 17:57:16  lampret

// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.

// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.

//

//

// Revision 1.7  2001/10/14 13:12:10  lampret

// Revision 1.7  2001/10/14 13:12:10  lampret

// MP3 version.

// MP3 version.

//

//

// Revision 1.1.1.1  2001/10/06 10:18:36  igorm

// Revision 1.1.1.1  2001/10/06 10:18:36  igorm

// no message

// no message

//

//

// Revision 1.2  2001/08/09 13:39:33  lampret

// Revision 1.2  2001/08/09 13:39:33  lampret

// Major clean-up.

// Major clean-up.

//

//

// Revision 1.1  2001/07/20 00:46:21  lampret

// Revision 1.1  2001/07/20 00:46:21  lampret

// Development version of RTL. Libraries are missing.

// Development version of RTL. Libraries are missing.

//

//

//

//

// synopsys translate_off

// synopsys translate_off

`include "timescale.v"

`include "timescale.v"

// synopsys translate_on

// synopsys translate_on

`include "or1200_defines.v"

`include "or1200_defines.v"

module or1200_pic(

module or1200_pic(

        // RISC Internal Interface

        // RISC Internal Interface

        clk, rst, spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,

        clk, rst, spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,

        pic_wakeup, intr,

        pic_wakeup, intr,

        // PIC Interface

        // PIC Interface

        pic_int

        pic_int

);

);

//

//

// RISC Internal Interface

// RISC Internal Interface

//

//

input           clk;            // Clock

input           clk;            // Clock

input           rst;            // Reset

input           rst;            // Reset

input           spr_cs;         // SPR CS

input           spr_cs;         // SPR CS

input           spr_write;      // SPR Write

input           spr_write;      // SPR Write

input   [31:0]   spr_addr;       // SPR Address

input   [31:0]   spr_addr;       // SPR Address

input   [31:0]   spr_dat_i;      // SPR Write Data

input   [31:0]   spr_dat_i;      // SPR Write Data

output  [31:0]   spr_dat_o;      // SPR Read Data

output  [31:0]   spr_dat_o;      // SPR Read Data

output          pic_wakeup;     // Wakeup to the PM

output          pic_wakeup;     // Wakeup to the PM

output          intr;           // interrupt

output          intr;           // interrupt

                                // exception request

                                // exception request

//

//

// PIC Interface

// PIC Interface

//

//

input   [`OR1200_PIC_INTS-1:0]   pic_int;// Interrupt inputs

input   [`OR1200_PIC_INTS-1:0]   pic_int;// Interrupt inputs

`ifdef OR1200_PIC_IMPLEMENTED

`ifdef OR1200_PIC_IMPLEMENTED

//

//

// PIC Mask Register bits (or no register)

// PIC Mask Register bits (or no register)

//

//

`ifdef OR1200_PIC_PICMR

`ifdef OR1200_PIC_PICMR

reg     [`OR1200_PIC_INTS-1:2]  picmr;  // PICMR bits

reg     [`OR1200_PIC_INTS-1:2]  picmr;  // PICMR bits

`else

`else

wire    [`OR1200_PIC_INTS-1:2]  picmr;  // No PICMR register

wire    [`OR1200_PIC_INTS-1:2]  picmr;  // No PICMR register

`endif

`endif

//

//

// PIC Status Register bits (or no register)

// PIC Status Register bits (or no register)

//

//

`ifdef OR1200_PIC_PICSR

`ifdef OR1200_PIC_PICSR

reg     [`OR1200_PIC_INTS-1:0]   picsr;  // PICSR bits

reg     [`OR1200_PIC_INTS-1:0]   picsr;  // PICSR bits

`else

`else

wire    [`OR1200_PIC_INTS-1:0]   picsr;  // No PICSR register

wire    [`OR1200_PIC_INTS-1:0]   picsr;  // No PICSR register

`endif

`endif

//

//

// Internal wires & regs

// Internal wires & regs

//

//

wire            picmr_sel;      // PICMR select

wire            picmr_sel;      // PICMR select

wire            picsr_sel;      // PICSR select

wire            picsr_sel;      // PICSR select

wire    [`OR1200_PIC_INTS-1:0] um_ints;// Unmasked interrupts

wire    [`OR1200_PIC_INTS-1:0] um_ints;// Unmasked interrupts

reg     [31:0]   spr_dat_o;      // SPR data out

reg     [31:0]   spr_dat_o;      // SPR data out

//

//

// PIC registers address decoder

// PIC registers address decoder

//

//

assign picmr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICMR)) ? 1'b1 : 1'b0;

assign picmr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICMR)) ? 1'b1 : 1'b0;

assign picsr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICSR)) ? 1'b1 : 1'b0;

assign picsr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICSR)) ? 1'b1 : 1'b0;

//

//

// Write to PICMR

// Write to PICMR

//

//

`ifdef OR1200_PIC_PICMR

`ifdef OR1200_PIC_PICMR

always @(posedge clk or posedge rst)

always @(posedge clk or posedge rst)

        if (rst)

        if (rst)

                picmr <= {1'b1, {`OR1200_PIC_INTS-3{1'b0}}};

                picmr <= {1'b1, {`OR1200_PIC_INTS-3{1'b0}}};

        else if (picmr_sel && spr_write) begin

        else if (picmr_sel && spr_write) begin

                picmr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:2];

                picmr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:2];

end

end

`else

`else

assign picmr = (`OR1200_PIC_INTS)'b1;

assign picmr = (`OR1200_PIC_INTS)'b1;

`endif

`endif

//

//

// Write to PICSR, both CPU and external ints

// Write to PICSR, both CPU and external ints

//

//

`ifdef OR1200_PIC_PICSR

`ifdef OR1200_PIC_PICSR

always @(posedge clk or posedge rst)

always @(posedge clk or posedge rst)

        if (rst)

        if (rst)

                picsr <= {`OR1200_PIC_INTS{1'b0}};

                picsr <= {`OR1200_PIC_INTS{1'b0}};

        else if (picsr_sel && spr_write) begin

        else if (picsr_sel && spr_write) begin

                picsr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:0] | um_ints;

                picsr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:0] | um_ints;

        end else

        end else

                picsr <= #1 picsr | um_ints;

                picsr <= #1 picsr | um_ints;

`else

`else

assign picsr = pic_int;

assign picsr = pic_int;

`endif

`endif

//

//

// Read PIC registers

// Read PIC registers

//

//

always @(spr_addr or picmr or picsr)

always @(spr_addr or picmr or picsr)

        case (spr_addr[`OR1200_PICOFS_BITS])    // synopsys parallel_case

        case (spr_addr[`OR1200_PICOFS_BITS])    // synopsys parallel_case

`ifdef OR1200_PIC_READREGS

`ifdef OR1200_PIC_READREGS

                `OR1200_PIC_OFS_PICMR: begin

                `OR1200_PIC_OFS_PICMR: begin

                                        spr_dat_o[`OR1200_PIC_INTS-1:0] = {picmr, 2'b0};

                                        spr_dat_o[`OR1200_PIC_INTS-1:0] = {picmr, 2'b0};

`ifdef OR1200_PIC_UNUSED_ZERO

`ifdef OR1200_PIC_UNUSED_ZERO

                                        spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};

                                        spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};

`endif

`endif

end

end

`endif

`endif

                default: begin

                default: begin

                                spr_dat_o[`OR1200_PIC_INTS-1:0] = picsr;

                                spr_dat_o[`OR1200_PIC_INTS-1:0] = picsr;

`ifdef OR1200_PIC_UNUSED_ZERO

`ifdef OR1200_PIC_UNUSED_ZERO

                                spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};

                                spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};

`endif

`endif

end

end

        endcase

        endcase

//

//

// Unmasked interrupts

// Unmasked interrupts

//

//

assign um_ints = pic_int & {picmr, 2'b11};

assign um_ints = pic_int & {picmr, 2'b11};

//

//

// Generate intr

// Generate intr

//

//

assign intr = |um_ints;

assign intr = |um_ints;

//

//

// Assert pic_wakeup when intr is asserted

// Assert pic_wakeup when intr is asserted

//

//

assign pic_wakeup = intr;

assign pic_wakeup = intr;

`else

`else

//

//

// When PIC is not implemented, drive all outputs as would when PIC is disabled

// When PIC is not implemented, drive all outputs as would when PIC is disabled

//

//

assign intr = pic_int[1] | pic_int[0];

assign intr = pic_int[1] | pic_int[0];

assign pic_wakeup= intr;

assign pic_wakeup= intr;

//

//

// Read PIC registers

// Read PIC registers

//

//

`ifdef OR1200_PIC_READREGS

`ifdef OR1200_PIC_READREGS

assign spr_dat_o[`OR1200_PIC_INTS-1:0] = `OR1200_PIC_INTS'b0;

assign spr_dat_o[`OR1200_PIC_INTS-1:0] = `OR1200_PIC_INTS'b0;

`ifdef OR1200_PIC_UNUSED_ZERO

`ifdef OR1200_PIC_UNUSED_ZERO

assign spr_dat_o[31:`OR1200_PIC_INTS] = 32-`OR1200_PIC_INTS'b0;

assign spr_dat_o[31:`OR1200_PIC_INTS] = 32-`OR1200_PIC_INTS'b0;

`endif

`endif

`endif

`endif

`endif

`endif

endmodule

endmodule

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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_pic.v] - Diff between revs 10 and 141