//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's register file inside CPU ////
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//// OR1200's register file inside CPU ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/project,or1k ////
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//// http://www.opencores.org/project,or1k ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Instantiation of register file memories ////
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//// Instantiation of register file memories ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - make it smaller and faster ////
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//// - make it smaller and faster ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// $Log: or1200_rf.v,v $
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// $Log: or1200_rf.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Minor update:
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// Minor update:
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// Bugs fixed, coding style changed.
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// Bugs fixed, coding style changed.
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//
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//
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|
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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|
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module or1200_rf(
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module or1200_rf(
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// Clock and reset
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// Clock and reset
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clk, rst,
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clk, rst,
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|
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// Write i/f
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// Write i/f
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cy_we_i, cy_we_o, supv, wb_freeze, addrw, dataw, we, flushpipe,
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cy_we_i, cy_we_o, supv, wb_freeze, addrw, dataw, we, flushpipe,
|
|
|
// Read i/f
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// Read i/f
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id_freeze, addra, addrb, dataa, datab, rda, rdb,
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id_freeze, addra, addrb, dataa, datab, rda, rdb,
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|
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// Debug
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// Debug
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o, du_read
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o, du_read
|
);
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);
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|
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
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parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
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|
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//
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//
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// I/O
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// I/O
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//
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//
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|
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//
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//
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// Clock and reset
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// Clock and reset
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//
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//
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input clk;
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input clk;
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input rst;
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input rst;
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|
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//
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//
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// Write i/f
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// Write i/f
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//
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//
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input cy_we_i;
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input cy_we_i;
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output cy_we_o;
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output cy_we_o;
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input supv;
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input supv;
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input wb_freeze;
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input wb_freeze;
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input [aw-1:0] addrw;
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input [aw-1:0] addrw;
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input [dw-1:0] dataw;
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input [dw-1:0] dataw;
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input we;
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input we;
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input flushpipe;
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input flushpipe;
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|
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//
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//
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// Read i/f
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// Read i/f
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//
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//
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input id_freeze;
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input id_freeze;
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input [aw-1:0] addra;
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input [aw-1:0] addra;
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input [aw-1:0] addrb;
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input [aw-1:0] addrb;
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output [dw-1:0] dataa;
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output [dw-1:0] dataa;
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output [dw-1:0] datab;
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output [dw-1:0] datab;
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input rda;
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input rda;
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input rdb;
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input rdb;
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|
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//
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//
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// SPR access for debugging purposes
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// SPR access for debugging purposes
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//
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//
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input spr_cs;
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input spr_cs;
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input spr_write;
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input spr_write;
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input [31:0] spr_addr;
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input [31:0] spr_addr;
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input [31:0] spr_dat_i;
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input [31:0] spr_dat_i;
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output [31:0] spr_dat_o;
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output [31:0] spr_dat_o;
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input du_read;
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input du_read;
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|
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//
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//
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// Internal wires and regs
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// Internal wires and regs
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//
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//
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wire [dw-1:0] from_rfa;
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wire [dw-1:0] from_rfa;
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wire [dw-1:0] from_rfb;
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wire [dw-1:0] from_rfb;
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wire [aw-1:0] rf_addra;
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wire [aw-1:0] rf_addra;
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wire [aw-1:0] rf_addrw;
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wire [aw-1:0] rf_addrw;
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wire [dw-1:0] rf_dataw;
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wire [dw-1:0] rf_dataw;
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wire rf_we;
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wire rf_we;
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wire spr_valid;
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wire spr_valid;
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wire rf_ena;
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wire rf_ena;
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wire rf_enb;
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wire rf_enb;
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reg rf_we_allow;
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reg rf_we_allow;
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|
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// Logic to restore output on RFA after debug unit has read out via SPR if.
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// Logic to restore output on RFA after debug unit has read out via SPR if.
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// Problem was that the incorrect output would be on RFA after debug unit
|
// Problem was that the incorrect output would be on RFA after debug unit
|
// had read out - this is bad if that output is relied upon by execute
|
// had read out - this is bad if that output is relied upon by execute
|
// stage for next instruction. We simply save the last address for rf A and
|
// stage for next instruction. We simply save the last address for rf A and
|
// and re-read it whenever the SPR select goes low, so we must remember
|
// and re-read it whenever the SPR select goes low, so we must remember
|
// the last address and generate a signal for falling edge of SPR cs.
|
// the last address and generate a signal for falling edge of SPR cs.
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// -- Julius
|
// -- Julius
|
|
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// Detect falling edge of SPR select
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// Detect falling edge of SPR select
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reg spr_du_cs;
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reg spr_du_cs;
|
wire spr_cs_fe;
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wire spr_cs_fe;
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// Track RF A's address each time it's enabled
|
// Track RF A's address each time it's enabled
|
reg [aw-1:0] addra_last;
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reg [aw-1:0] addra_last;
|
|
|
|
|
always @(posedge clk)
|
always @(posedge clk)
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if (rf_ena & !(spr_cs_fe | (du_read & spr_cs)))
|
if (rf_ena & !(spr_cs_fe | (du_read & spr_cs)))
|
addra_last <= addra;
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addra_last <= addra;
|
|
|
always @(posedge clk)
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always @(posedge clk)
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spr_du_cs <= spr_cs & du_read;
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spr_du_cs <= spr_cs & du_read;
|
|
|
assign spr_cs_fe = spr_du_cs & !(spr_cs & du_read);
|
assign spr_cs_fe = spr_du_cs & !(spr_cs & du_read);
|
|
|
|
|
//
|
//
|
// SPR access is valid when spr_cs is asserted and
|
// SPR access is valid when spr_cs is asserted and
|
// SPR address matches GPR addresses
|
// SPR address matches GPR addresses
|
//
|
//
|
assign spr_valid = spr_cs & (spr_addr[10:5] == `OR1200_SPR_RF);
|
assign spr_valid = spr_cs & (spr_addr[10:5] == `OR1200_SPR_RF);
|
|
|
//
|
//
|
// SPR data output is always from RF A
|
// SPR data output is always from RF A
|
//
|
//
|
assign spr_dat_o = from_rfa;
|
assign spr_dat_o = from_rfa;
|
|
|
//
|
//
|
// Operand A comes from RF or from saved A register
|
// Operand A comes from RF or from saved A register
|
//
|
//
|
assign dataa = from_rfa;
|
assign dataa = from_rfa;
|
|
|
//
|
//
|
// Operand B comes from RF or from saved B register
|
// Operand B comes from RF or from saved B register
|
//
|
//
|
assign datab = from_rfb;
|
assign datab = from_rfb;
|
|
|
//
|
//
|
// RF A read address is either from SPRS or normal from CPU control
|
// RF A read address is either from SPRS or normal from CPU control
|
//
|
//
|
assign rf_addra = (spr_valid & !spr_write) ? spr_addr[4:0] :
|
assign rf_addra = (spr_valid & !spr_write) ? spr_addr[4:0] :
|
spr_cs_fe ? addra_last : addra;
|
spr_cs_fe ? addra_last : addra;
|
|
|
//
|
//
|
// RF write address is either from SPRS or normal from CPU control
|
// RF write address is either from SPRS or normal from CPU control
|
//
|
//
|
assign rf_addrw = (spr_valid & spr_write) ? spr_addr[4:0] : addrw;
|
assign rf_addrw = (spr_valid & spr_write) ? spr_addr[4:0] : addrw;
|
|
|
//
|
//
|
// RF write data is either from SPRS or normal from CPU datapath
|
// RF write data is either from SPRS or normal from CPU datapath
|
//
|
//
|
assign rf_dataw = (spr_valid & spr_write) ? spr_dat_i : dataw;
|
assign rf_dataw = (spr_valid & spr_write) ? spr_dat_i : dataw;
|
|
|
//
|
//
|
// RF write enable is either from SPRS or normal from CPU control
|
// RF write enable is either from SPRS or normal from CPU control
|
//
|
//
|
always @(`OR1200_RST_EVENT rst or posedge clk)
|
always @(`OR1200_RST_EVENT rst or posedge clk)
|
if (rst == `OR1200_RST_VALUE)
|
if (rst == `OR1200_RST_VALUE)
|
rf_we_allow <= 1'b1;
|
rf_we_allow <= 1'b1;
|
else if (~wb_freeze)
|
else if (~wb_freeze)
|
rf_we_allow <= ~flushpipe;
|
rf_we_allow <= ~flushpipe;
|
|
|
//assign rf_we = ((spr_valid & spr_write) | (we & ~wb_freeze)) & rf_we_allow & (supv | (|rf_addrw));
|
|
assign rf_we = ((spr_valid & spr_write) | (we & ~wb_freeze)) & rf_we_allow;
|
assign rf_we = ((spr_valid & spr_write) | (we & ~wb_freeze)) & rf_we_allow;
|
//assign cy_we_o = cy_we_i && rf_we;
|
|
assign cy_we_o = cy_we_i && ~wb_freeze && rf_we_allow;
|
|
|
|
|
assign cy_we_o = cy_we_i && ~wb_freeze && rf_we_allow;
|
|
|
//
|
//
|
// CS RF A asserted when instruction reads operand A and ID stage
|
// CS RF A asserted when instruction reads operand A and ID stage
|
// is not stalled
|
// is not stalled
|
//
|
//
|
//assign rf_ena = rda & ~id_freeze | spr_valid; // probably works with fixed binutils
|
assign rf_ena = (rda & ~id_freeze) | (spr_valid & !spr_write) | spr_cs_fe;
|
assign rf_ena = (rda & ~id_freeze) | (spr_valid & !spr_write) | spr_cs_fe; // probably works with fixed binutils
|
|
// assign rf_ena = 1'b1; // does not work with single-stepping
|
|
//assign rf_ena = ~id_freeze | spr_valid; // works with broken binutils
|
|
|
|
//
|
//
|
// CS RF B asserted when instruction reads operand B and ID stage
|
// CS RF B asserted when instruction reads operand B and ID stage
|
// is not stalled
|
// is not stalled
|
//
|
//
|
//assign rf_enb = rdb & ~id_freeze | spr_valid;
|
|
assign rf_enb = rdb & ~id_freeze;
|
assign rf_enb = rdb & ~id_freeze;
|
// assign rf_enb = 1'b1;
|
|
//assign rf_enb = ~id_freeze | spr_valid; // works with broken binutils
|
|
|
|
`ifdef OR1200_RFRAM_TWOPORT
|
`ifdef OR1200_RFRAM_TWOPORT
|
|
|
//
|
//
|
// Instantiation of register file two-port RAM A
|
// Instantiation of register file two-port RAM A
|
//
|
//
|
or1200_tpram_32x32 rf_a(
|
or1200_tpram_32x32 rf_a(
|
// Port A
|
// Port A
|
.clk_a(clk),
|
.clk_a(clk),
|
.rst_a(rst),
|
.rst_a(rst),
|
.ce_a(rf_ena),
|
.ce_a(rf_ena),
|
.we_a(1'b0),
|
.we_a(1'b0),
|
.oe_a(1'b1),
|
.oe_a(1'b1),
|
.addr_a(rf_addra),
|
.addr_a(rf_addra),
|
.di_a(32'h0000_0000),
|
.di_a(32'h0000_0000),
|
.do_a(from_rfa),
|
.do_a(from_rfa),
|
|
|
// Port B
|
// Port B
|
.clk_b(clk),
|
.clk_b(clk),
|
.rst_b(rst),
|
.rst_b(rst),
|
.ce_b(rf_we),
|
.ce_b(rf_we),
|
.we_b(rf_we),
|
.we_b(rf_we),
|
.oe_b(1'b0),
|
.oe_b(1'b0),
|
.addr_b(rf_addrw),
|
.addr_b(rf_addrw),
|
.di_b(rf_dataw),
|
.di_b(rf_dataw),
|
.do_b()
|
.do_b()
|
);
|
);
|
|
|
//
|
//
|
// Instantiation of register file two-port RAM B
|
// Instantiation of register file two-port RAM B
|
//
|
//
|
or1200_tpram_32x32 rf_b(
|
or1200_tpram_32x32 rf_b(
|
// Port A
|
// Port A
|
.clk_a(clk),
|
.clk_a(clk),
|
.rst_a(rst),
|
.rst_a(rst),
|
.ce_a(rf_enb),
|
.ce_a(rf_enb),
|
.we_a(1'b0),
|
.we_a(1'b0),
|
.oe_a(1'b1),
|
.oe_a(1'b1),
|
.addr_a(addrb),
|
.addr_a(addrb),
|
.di_a(32'h0000_0000),
|
.di_a(32'h0000_0000),
|
.do_a(from_rfb),
|
.do_a(from_rfb),
|
|
|
// Port B
|
// Port B
|
.clk_b(clk),
|
.clk_b(clk),
|
.rst_b(rst),
|
.rst_b(rst),
|
.ce_b(rf_we),
|
.ce_b(rf_we),
|
.we_b(rf_we),
|
.we_b(rf_we),
|
.oe_b(1'b0),
|
.oe_b(1'b0),
|
.addr_b(rf_addrw),
|
.addr_b(rf_addrw),
|
.di_b(rf_dataw),
|
.di_b(rf_dataw),
|
.do_b()
|
.do_b()
|
);
|
);
|
|
|
`else
|
`else
|
|
|
`ifdef OR1200_RFRAM_DUALPORT
|
`ifdef OR1200_RFRAM_DUALPORT
|
|
|
//
|
//
|
// Instantiation of register file two-port RAM A
|
// Instantiation of register file two-port RAM A
|
//
|
//
|
or1200_dpram #
|
or1200_dpram #
|
(
|
(
|
.aw(5),
|
.aw(5),
|
.dw(32)
|
.dw(32)
|
)
|
)
|
rf_a
|
rf_a
|
(
|
(
|
// Port A
|
// Port A
|
.clk_a(clk),
|
.clk_a(clk),
|
.ce_a(rf_ena),
|
.ce_a(rf_ena),
|
.addr_a(rf_addra),
|
.addr_a(rf_addra),
|
.do_a(from_rfa),
|
.do_a(from_rfa),
|
|
|
// Port B
|
// Port B
|
.clk_b(clk),
|
.clk_b(clk),
|
.ce_b(rf_we),
|
.ce_b(rf_we),
|
.we_b(rf_we),
|
.we_b(rf_we),
|
.addr_b(rf_addrw),
|
.addr_b(rf_addrw),
|
.di_b(rf_dataw)
|
.di_b(rf_dataw)
|
);
|
);
|
|
|
//
|
//
|
// Instantiation of register file two-port RAM B
|
// Instantiation of register file two-port RAM B
|
//
|
//
|
or1200_dpram #
|
or1200_dpram #
|
(
|
(
|
.aw(5),
|
.aw(5),
|
.dw(32)
|
.dw(32)
|
)
|
)
|
rf_b
|
rf_b
|
(
|
(
|
// Port A
|
// Port A
|
.clk_a(clk),
|
.clk_a(clk),
|
.ce_a(rf_enb),
|
.ce_a(rf_enb),
|
.addr_a(addrb),
|
.addr_a(addrb),
|
.do_a(from_rfb),
|
.do_a(from_rfb),
|
|
|
// Port B
|
// Port B
|
.clk_b(clk),
|
.clk_b(clk),
|
.ce_b(rf_we),
|
.ce_b(rf_we),
|
.we_b(rf_we),
|
.we_b(rf_we),
|
.addr_b(rf_addrw),
|
.addr_b(rf_addrw),
|
.di_b(rf_dataw)
|
.di_b(rf_dataw)
|
);
|
);
|
|
|
`else
|
`else
|
|
|
`ifdef OR1200_RFRAM_GENERIC
|
`ifdef OR1200_RFRAM_GENERIC
|
|
|
//
|
//
|
// Instantiation of generic (flip-flop based) register file
|
// Instantiation of generic (flip-flop based) register file
|
//
|
//
|
or1200_rfram_generic rf_a(
|
or1200_rfram_generic rf_a(
|
// Clock and reset
|
// Clock and reset
|
.clk(clk),
|
.clk(clk),
|
.rst(rst),
|
.rst(rst),
|
|
|
// Port A
|
// Port A
|
.ce_a(rf_ena),
|
.ce_a(rf_ena),
|
.addr_a(rf_addra),
|
.addr_a(rf_addra),
|
.do_a(from_rfa),
|
.do_a(from_rfa),
|
|
|
// Port B
|
// Port B
|
.ce_b(rf_enb),
|
.ce_b(rf_enb),
|
.addr_b(addrb),
|
.addr_b(addrb),
|
.do_b(from_rfb),
|
.do_b(from_rfb),
|
|
|
// Port W
|
// Port W
|
.ce_w(rf_we),
|
.ce_w(rf_we),
|
.we_w(rf_we),
|
.we_w(rf_we),
|
.addr_w(rf_addrw),
|
.addr_w(rf_addrw),
|
.di_w(rf_dataw)
|
.di_w(rf_dataw)
|
);
|
);
|
|
|
`else
|
`else
|
|
|
//
|
//
|
// RFRAM type not specified
|
// RFRAM type not specified
|
//
|
//
|
initial begin
|
initial begin
|
$display("Define RFRAM type.");
|
$display("Define RFRAM type.");
|
$finish;
|
$finish;
|
end
|
end
|
|
|
`endif
|
`endif
|
`endif
|
`endif
|
`endif
|
`endif
|
|
|
endmodule
|
endmodule
|
|
|
