OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_128x32.v] - Diff between revs 258 and 358

Go to most recent revision | Only display areas with differences | Details | Blame | View Log

Rev 258 Rev 358
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Generic Single-Port Synchronous RAM                         ////
////  Generic Single-Port Synchronous RAM                         ////
////                                                              ////
////                                                              ////
////  This file is part of memory library available from          ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////  independent of target memory.                               ////
////                                                              ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  Supported ASIC RAMs are:                                    ////
////                                                              ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB16                                      ////
////  - Xilinx Virtex RAMB16                                      ////
////  - Xilinx Virtex RAMB4                                       ////
////  - Xilinx Virtex RAMB4                                       ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   - add support for other RAM's                              ////
////   - add support for other RAM's                              ////
////   - xilinx rams need external tri-state logic                ////
////   - xilinx rams need external tri-state logic                ////
////   - fix avant! two-port ram                                  ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs                                      ////
////   - add additional RAMs                                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: or1200_spram_128x32.v,v $
// $Log: or1200_spram_128x32.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Minor update: 
// Minor update: 
// Coding style changed.
// Coding style changed.
//
//
// Revision 1.3  2005/10/19 11:37:56  jcastillo
// Revision 1.3  2005/10/19 11:37:56  jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
//
// Revision 1.2  2004/06/08 18:15:32  lampret
// Revision 1.2  2004/06/08 18:15:32  lampret
// Changed behavior of the simulation generic models
// Changed behavior of the simulation generic models
//
//
// Revision 1.1  2004/04/08 11:00:46  simont
// Revision 1.1  2004/04/08 11:00:46  simont
// Add support for 512B instruction cache.
// Add support for 512B instruction cache.
//
//
//
//
//
//
 
 
// synopsys translate_off
// synopsys translate_off
`include "timescale.v"
`include "timescale.v"
// synopsys translate_on
// synopsys translate_on
`include "or1200_defines.v"
`include "or1200_defines.v"
 
 
module or1200_spram_128x32(
module or1200_spram_128x32(
`ifdef OR1200_BIST
`ifdef OR1200_BIST
        // RAM BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
`endif
        // Generic synchronous single-port RAM interface
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, doq
        clk, rst, ce, we, oe, addr, di, doq
);
);
 
 
//
//
// Default address and data buses width
// Default address and data buses width
//
//
parameter aw = 7;
parameter aw = 7;
parameter dw = 32;
parameter dw = 32;
 
 
`ifdef OR1200_BIST
`ifdef OR1200_BIST
//
//
// RAM BIST
// RAM BIST
//
//
input mbist_si_i;
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
output mbist_so_o;
`endif
`endif
 
 
//
//
// Generic synchronous single-port RAM interface
// Generic synchronous single-port RAM interface
//
//
input                   clk;    // Clock
input                   clk;    // Clock
input                   rst;    // Reset
input                   rst;    // Reset
input                   ce;     // Chip enable input
input                   ce;     // Chip enable input
input                   we;     // Write enable input
input                   we;     // Write enable input
input                   oe;     // Output enable input
input                   oe;     // Output enable input
input   [aw-1:0] addr;   // address bus inputs
input   [aw-1:0] addr;   // address bus inputs
input   [dw-1:0] di;     // input data bus
input   [dw-1:0] di;     // input data bus
output  [dw-1:0] doq;    // output data bus
output  [dw-1:0] doq;    // output data bus
 
 
//
//
// Internal wires and registers
// Internal wires and registers
//
//
 
 
`ifdef OR1200_ARTISAN_SSP
`ifdef OR1200_ARTISAN_SSP
`else
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`else
`ifdef OR1200_BIST
`ifdef OR1200_BIST
`endif
`endif
`endif
`endif
`endif
`endif
 
 
`ifdef OR1200_ARTISAN_SSP
`ifdef OR1200_ARTISAN_SSP
 
 
//
//
// Instantiation of ASIC memory:
// Instantiation of ASIC memory:
//
//
// Artisan Synchronous Single-Port RAM (ra1sh)
// Artisan Synchronous Single-Port RAM (ra1sh)
//
//
`ifdef UNUSED
`ifdef UNUSED
`else
`else
`ifdef OR1200_BIST
`ifdef OR1200_BIST
`else
`else
`endif
`endif
`endif
`endif
`ifdef OR1200_BIST
`ifdef OR1200_BIST
`endif
`endif
`else
`else
 
 
`ifdef OR1200_AVANT_ATP
`ifdef OR1200_AVANT_ATP
 
 
//
//
// Instantiation of ASIC memory:
// Instantiation of ASIC memory:
//
//
// Avant! Asynchronous Two-Port RAM
// Avant! Asynchronous Two-Port RAM
//
//
 
 
`else
`else
 
 
`ifdef OR1200_VIRAGE_SSP
`ifdef OR1200_VIRAGE_SSP
 
 
//
//
// Instantiation of ASIC memory:
// Instantiation of ASIC memory:
//
//
// Virage Synchronous 1-port R/W RAM
// Virage Synchronous 1-port R/W RAM
//
//
 
 
`else
`else
 
 
`ifdef OR1200_VIRTUALSILICON_SSP
`ifdef OR1200_VIRTUALSILICON_SSP
 
 
//
//
// Instantiation of ASIC memory:
// Instantiation of ASIC memory:
//
//
// Virtual Silicon Single-Port Synchronous SRAM
// Virtual Silicon Single-Port Synchronous SRAM
//
//
`ifdef UNUSED
`ifdef UNUSED
`else
`else
`ifdef OR1200_BIST
`ifdef OR1200_BIST
`else
`else
`endif
`endif
`endif
`endif
`ifdef OR1200_BIST
`ifdef OR1200_BIST
        // RAM BIST
        // RAM BIST
`endif
`endif
 
 
`else
`else
 
 
`ifdef OR1200_XILINX_RAMB4
`ifdef OR1200_XILINX_RAMB4
 
 
//
//
// Instantiation of FPGA memory:
// Instantiation of FPGA memory:
//
//
// Virtex/Spartan2
// Virtex/Spartan2
//
//
 
 
//
//
// Block 0
// Block 0
//
//
RAMB4_S16 ramb4_s16_0(
RAMB4_S16 ramb4_s16_0(
        .CLK(clk),
        .CLK(clk),
        .RST(1'b0),
        .RST(1'b0),
        .ADDR({1'b0, addr}),
        .ADDR({1'b0, addr}),
        .DI(di[15:0]),
        .DI(di[15:0]),
        .EN(ce),
        .EN(ce),
        .WE(we),
        .WE(we),
        .DO(doq[15:0])
        .DO(doq[15:0])
);
);
 
 
//
//
// Block 1
// Block 1
//
//
RAMB4_S16 ramb4_s16_1(
RAMB4_S16 ramb4_s16_1(
        .CLK(clk),
        .CLK(clk),
        .RST(1'b0),
        .RST(1'b0),
        .ADDR({1'b0, addr}),
        .ADDR({1'b0, addr}),
        .DI(di[31:16]),
        .DI(di[31:16]),
        .EN(ce),
        .EN(ce),
        .WE(we),
        .WE(we),
        .DO(doq[31:16])
        .DO(doq[31:16])
);
);
 
 
`else
`else
 
 
`ifdef OR1200_XILINX_RAMB16
`ifdef OR1200_XILINX_RAMB16
 
 
//
//
// Instantiation of FPGA memory:
// Instantiation of FPGA memory:
//
//
// Virtex4/Spartan3E
// Virtex4/Spartan3E
//
//
// Added By Nir Mor
// Added By Nir Mor
//
//
 
 
RAMB16_S36 ramb16_s36(
RAMB16_S36 ramb16_s36(
        .CLK(clk),
        .CLK(clk),
        .SSR(1'b0),
        .SSR(1'b0),
        .ADDR({2'b00, addr}),
        .ADDR({2'b00, addr}),
        .DI(di),
        .DI(di),
        .DIP(4'h0),
        .DIP(4'h0),
        .EN(ce),
        .EN(ce),
        .WE(we),
        .WE(we),
        .DO(doq),
        .DO(doq),
        .DOP()
        .DOP()
);
);
 
 
`else
`else
 
 
//
//
// Generic single-port synchronous RAM model
// Generic single-port synchronous RAM model
//
//
 
 
//
//
// Generic RAM's registers and wires
// Generic RAM's registers and wires
//
//
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
reg     [aw-1:0] addr_reg;               // RAM address register
reg     [aw-1:0] addr_reg;               // RAM address register
 
 
//
//
// Data output drivers
// Data output drivers
//
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
 
 
//
//
// RAM address register
// RAM address register
//
//
always @(posedge clk or posedge rst)
always @(posedge clk or `OR1200_RST_EVENT rst)
        if (rst)
        if (rst == `OR1200_RST_VALUE)
                addr_reg <=  {aw{1'b0}};
                addr_reg <=  {aw{1'b0}};
        else if (ce)
        else if (ce)
                addr_reg <=  addr;
                addr_reg <=  addr;
 
 
//
//
// RAM write
// RAM write
//
//
always @(posedge clk)
always @(posedge clk)
        if (ce && we)
        if (ce && we)
                mem[addr] <=  di;
                mem[addr] <=  di;
 
 
`endif  // !OR1200_XILINX_RAMB16
`endif  // !OR1200_XILINX_RAMB16
`endif  // !OR1200_XILINX_RAMB4
`endif  // !OR1200_XILINX_RAMB4
`endif  // !OR1200_VIRTUALSILICON_SSP
`endif  // !OR1200_VIRTUALSILICON_SSP
`endif  // !OR1200_VIRAGE_SSP
`endif  // !OR1200_VIRAGE_SSP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SSP
`endif  // !OR1200_ARTISAN_SSP
 
 
endmodule
endmodule
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.