OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_32_bw.v] - Diff between revs 142 and 258

Go to most recent revision | Only display areas with differences | Details | Blame | View Log

Rev 142 Rev 258
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Generic Single-Port Synchronous RAM 32-bit Byte-Write       ////
////  Generic Single-Port Synchronous RAM 32-bit Byte-Write       ////
////                                                              ////
////                                                              ////
////  This file is part of memory library available from          ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////  independent of target memory.                               ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Tadej Markovic, tadej.markovic@gmail.com              ////
////      - Tadej Markovic, tadej.markovic@gmail.com              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: or1200_dpram_32x32.v,v $
// $Log: or1200_dpram_32x32.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// New 
// New 
//
//
 
 
// synopsys translate_off
// synopsys translate_off
`include "timescale.v"
`include "timescale.v"
// synopsys translate_on
// synopsys translate_on
`include "or1200_defines.v"
`include "or1200_defines.v"
 
 
module or1200_spram_32_bw
module or1200_spram_32_bw
  (
  (
`ifdef OR1200_BIST
`ifdef OR1200_BIST
   // RAM BIST
   // RAM BIST
   mbist_si_i, mbist_so_o, mbist_ctrl_i,
   mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
`endif
   // Generic synchronous single-port RAM interface
   // Generic synchronous single-port RAM interface
   clk, ce, we, addr, di, doq
   clk, ce, we, addr, di, doq
   );
   );
 
 
   //
   //
   // Default address and data buses width
   // Default address and data buses width
   //
   //
   parameter aw = 10;
   parameter aw = 10;
   parameter dw = 32;
   parameter dw = 32;
 
 
`ifdef OR1200_BIST
`ifdef OR1200_BIST
   //
   //
   // RAM BIST
   // RAM BIST
   //
   //
   input mbist_si_i;
   input mbist_si_i;
   input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
   input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
   output                                 mbist_so_o;
   output                                 mbist_so_o;
`endif
`endif
 
 
   //
   //
   // Generic synchronous single-port RAM interface
   // Generic synchronous single-port RAM interface
   //
   //
   input                                  clk;  // Clock
   input                                  clk;  // Clock
   input                                  ce;   // Chip enable input
   input                                  ce;   // Chip enable input
   input [3:0]                             we;   // Write enable input
   input [3:0]                             we;   // Write enable input
   input [aw-1:0]                          addr; // address bus inputs
   input [aw-1:0]                          addr; // address bus inputs
   input [dw-1:0]                          di;   // input data bus
   input [dw-1:0]                          di;   // input data bus
   output [dw-1:0]                         doq;  // output data bus
   output [dw-1:0]                         doq;  // output data bus
 
 
   //
   //
   // Internal wires and registers
   // Internal wires and registers
   //
   //
 
 
   //
   //
   // Generic single-port synchronous RAM model
   // Generic single-port synchronous RAM model
   //
   //
 
 
   //
   //
   // Generic RAM's registers and wires
   // Generic RAM's registers and wires
   //
   //
`ifdef OR1200_ACTEL
`ifdef OR1200_GENERIC
   reg [7:0]                               mem0 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
   reg [7:0]                               mem0 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
   reg [7:0]                               mem1 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
   reg [7:0]                               mem1 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
   reg [7:0]                               mem2 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
   reg [7:0]                               mem2 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
   reg [7:0]                               mem3 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
   reg [7:0]                               mem3 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
`else
`else
   reg [7:0]                               mem0 [(1<<aw)-1:0];
   reg [7:0]                               mem0 [(1<<aw)-1:0];
   reg [7:0]                               mem1 [(1<<aw)-1:0];
   reg [7:0]                               mem1 [(1<<aw)-1:0];
   reg [7:0]                               mem2 [(1<<aw)-1:0];
   reg [7:0]                               mem2 [(1<<aw)-1:0];
   reg [7:0]                               mem3 [(1<<aw)-1:0];
   reg [7:0]                               mem3 [(1<<aw)-1:0];
`endif
`endif
   reg [aw-1:0]                    addr_reg;             // RAM address register
   reg [aw-1:0]                    addr_reg;             // RAM address register
 
 
   //
   //
   // Data output drivers
   // Data output drivers
   //
   //
   assign doq = {mem0[addr_reg], mem1[addr_reg], mem2[addr_reg], mem3[addr_reg]};
   assign doq = {mem0[addr_reg], mem1[addr_reg], mem2[addr_reg], mem3[addr_reg]};
 
 
   //
   //
   // RAM read address register
   // RAM read address register
   //
   //
   always @(posedge clk)
   always @(posedge clk)
     if (ce)
     if (ce)
       addr_reg <= #1 addr;
       addr_reg <=  addr;
 
 
   //
   //
   // RAM write
   // RAM write - big endian selection
   //
   //
   always @(posedge clk)
   always @(posedge clk)
     if (ce) begin
     if (ce) begin
       if (we[0])
 
         mem0[addr] <= #1 di[31:24];
 
       if (we[1])
 
         mem1[addr] <= #1 di[23:16];
 
       if (we[2])
 
         mem2[addr] <= #1 di[15:08];
 
       if (we[3])
       if (we[3])
         mem3[addr] <= #1 di[07:00];
         mem0[addr] <=  di[31:24];
 
       if (we[2])
 
         mem1[addr] <=  di[23:16];
 
       if (we[1])
 
         mem2[addr] <=  di[15:08];
 
       if (we[0])
 
         mem3[addr] <=  di[07:00];
     end
     end
 
 
endmodule // or1200_spram
endmodule // or1200_spram
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.