//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Generic Single-Port Synchronous RAM 32-bit Byte-Write ////
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//// Generic Single-Port Synchronous RAM 32-bit Byte-Write ////
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//// ////
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//// ////
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//// This file is part of memory library available from ////
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//// This file is part of memory library available from ////
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//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
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//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// This block is a wrapper with common single-port ////
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//// This block is a wrapper with common single-port ////
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//// synchronous memory interface for different ////
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//// synchronous memory interface for different ////
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//// types of ASIC and FPGA RAMs. Beside universal memory ////
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//// types of ASIC and FPGA RAMs. Beside universal memory ////
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//// interface it also provides behavioral model of generic ////
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//// interface it also provides behavioral model of generic ////
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//// single-port synchronous RAM. ////
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//// single-port synchronous RAM. ////
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//// It should be used in all OPENCORES designs that want to be ////
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//// It should be used in all OPENCORES designs that want to be ////
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//// portable accross different target technologies and ////
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//// portable accross different target technologies and ////
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//// independent of target memory. ////
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//// independent of target memory. ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Michael Unneback, unneback@opencores.org ////
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//// - Michael Unneback, unneback@opencores.org ////
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//// - Tadej Markovic, tadej.markovic@gmail.com ////
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//// - Tadej Markovic, tadej.markovic@gmail.com ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: or1200_dpram_32x32.v,v $
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// $Log: or1200_dpram_32x32.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// New
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// New
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//
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//
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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module or1200_spram_32_bw
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module or1200_spram_32_bw
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(
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(
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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// RAM BIST
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// RAM BIST
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mbist_si_i, mbist_so_o, mbist_ctrl_i,
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mbist_si_i, mbist_so_o, mbist_ctrl_i,
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`endif
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`endif
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// Generic synchronous single-port RAM interface
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// Generic synchronous single-port RAM interface
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clk, ce, we, addr, di, doq
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clk, ce, we, addr, di, doq
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);
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);
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//
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//
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// Default address and data buses width
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// Default address and data buses width
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//
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//
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parameter aw = 10;
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parameter aw = 10;
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parameter dw = 32;
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parameter dw = 32;
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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//
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//
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// RAM BIST
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// RAM BIST
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//
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//
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input mbist_si_i;
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input mbist_si_i;
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input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
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input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
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output mbist_so_o;
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output mbist_so_o;
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`endif
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`endif
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//
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//
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// Generic synchronous single-port RAM interface
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// Generic synchronous single-port RAM interface
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//
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//
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input clk; // Clock
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input clk; // Clock
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input ce; // Chip enable input
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input ce; // Chip enable input
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input [3:0] we; // Write enable input
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input [3:0] we; // Write enable input
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input [aw-1:0] addr; // address bus inputs
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input [aw-1:0] addr; // address bus inputs
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input [dw-1:0] di; // input data bus
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input [dw-1:0] di; // input data bus
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output [dw-1:0] doq; // output data bus
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output [dw-1:0] doq; // output data bus
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//
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//
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// Internal wires and registers
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// Internal wires and registers
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//
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//
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//
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//
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// Generic single-port synchronous RAM model
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// Generic single-port synchronous RAM model
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//
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//
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//
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//
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// Generic RAM's registers and wires
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// Generic RAM's registers and wires
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//
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//
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`ifdef OR1200_ACTEL
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`ifdef OR1200_GENERIC
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reg [7:0] mem0 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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reg [7:0] mem0 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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reg [7:0] mem1 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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reg [7:0] mem1 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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reg [7:0] mem2 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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reg [7:0] mem2 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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reg [7:0] mem3 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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reg [7:0] mem3 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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`else
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`else
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reg [7:0] mem0 [(1<<aw)-1:0];
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reg [7:0] mem0 [(1<<aw)-1:0];
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reg [7:0] mem1 [(1<<aw)-1:0];
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reg [7:0] mem1 [(1<<aw)-1:0];
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reg [7:0] mem2 [(1<<aw)-1:0];
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reg [7:0] mem2 [(1<<aw)-1:0];
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reg [7:0] mem3 [(1<<aw)-1:0];
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reg [7:0] mem3 [(1<<aw)-1:0];
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`endif
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`endif
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reg [aw-1:0] addr_reg; // RAM address register
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reg [aw-1:0] addr_reg; // RAM address register
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//
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//
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// Data output drivers
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// Data output drivers
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//
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//
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assign doq = {mem0[addr_reg], mem1[addr_reg], mem2[addr_reg], mem3[addr_reg]};
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assign doq = {mem0[addr_reg], mem1[addr_reg], mem2[addr_reg], mem3[addr_reg]};
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//
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//
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// RAM read address register
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// RAM read address register
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//
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//
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always @(posedge clk)
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always @(posedge clk)
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if (ce)
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if (ce)
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addr_reg <= #1 addr;
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addr_reg <= addr;
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//
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//
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// RAM write
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// RAM write - big endian selection
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//
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//
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always @(posedge clk)
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always @(posedge clk)
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if (ce) begin
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if (ce) begin
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if (we[0])
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mem0[addr] <= #1 di[31:24];
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if (we[1])
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mem1[addr] <= #1 di[23:16];
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if (we[2])
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mem2[addr] <= #1 di[15:08];
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if (we[3])
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if (we[3])
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mem3[addr] <= #1 di[07:00];
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mem0[addr] <= di[31:24];
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if (we[2])
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mem1[addr] <= di[23:16];
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if (we[1])
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mem2[addr] <= di[15:08];
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if (we[0])
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mem3[addr] <= di[07:00];
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end
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end
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endmodule // or1200_spram
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endmodule // or1200_spram
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