/* icache-model.c -- instruction cache simulation
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/* icache-model.c -- instruction cache simulation
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 2008 Embecosm Limited
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Copyright (C) 2008 Embecosm Limited
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify it
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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more details.
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You should have received a copy of the GNU General Public License along
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You should have received a copy of the GNU General Public License along
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* This program is commented throughout in a fashion suitable for processing
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/* This program is commented throughout in a fashion suitable for processing
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with Doxygen. */
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with Doxygen. */
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/* Cache functions.
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/* Cache functions.
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At the moment this functions only simulate functionality of instruction
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At the moment this functions only simulate functionality of instruction
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caches and do not influence on fetche/decode/execute stages and timings.
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caches and do not influence on fetche/decode/execute stages and timings.
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They are here only to verify performance of various cache configurations.
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They are here only to verify performance of various cache configurations.
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*/
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*/
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/* Autoconf and/or portability configuration */
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/* Autoconf and/or portability configuration */
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#include "config.h"
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#include "config.h"
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#include "port.h"
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#include "port.h"
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/* System includes */
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/* System includes */
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#include <stdlib.h>
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#include <stdlib.h>
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/* Package includes */
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/* Package includes */
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#include "icache-model.h"
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#include "icache-model.h"
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#include "execute.h"
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#include "execute.h"
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#include "spr-defs.h"
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#include "spr-defs.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "misc.h"
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#include "misc.h"
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#include "stats.h"
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#include "stats.h"
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#include "sim-cmd.h"
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#include "sim-cmd.h"
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#define MAX_IC_SETS 1024
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#define MAX_IC_SETS 1024
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#define MAX_IC_WAYS 32
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#define MAX_IC_WAYS 32
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#define MIN_IC_BLOCK_SIZE 16
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#define MIN_IC_BLOCK_SIZE 16
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#define MAX_IC_BLOCK_SIZE 32
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#define MAX_IC_BLOCK_SIZE 32
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struct ic *ic_state = NULL;
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struct ic *ic_state = NULL;
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static void
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static void
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ic_info (void *dat)
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ic_info (void *dat)
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{
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{
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struct ic *ic = dat;
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struct ic *ic = dat;
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if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_ICP))
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if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_ICP))
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{
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{
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PRINTF ("ICache not implemented. Set UPR[ICP].\n");
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PRINTF ("ICache not implemented. Set UPR[ICP].\n");
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return;
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return;
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}
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}
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PRINTF ("Instruction cache %dKB: ",
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PRINTF ("Instruction cache %dKB: ",
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ic->nsets * ic->blocksize * ic->nways / 1024);
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ic->nsets * ic->blocksize * ic->nways / 1024);
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PRINTF ("%d ways, %d sets, block size %d bytes\n", ic->nways, ic->nsets,
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PRINTF ("%d ways, %d sets, block size %d bytes\n", ic->nways, ic->nsets,
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ic->blocksize);
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ic->blocksize);
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}
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}
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/* First check if instruction is already in the cache and if it is:
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/* First check if instruction is already in the cache and if it is:
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- increment IC read hit stats,
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- increment IC read hit stats,
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- set 'lru' at this way to ic->ustates - 1 and
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- set 'lru' at this way to ic->ustates - 1 and
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decrement 'lru' of other ways unless they have reached 0,
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decrement 'lru' of other ways unless they have reached 0,
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- read insn from the cache line
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- read insn from the cache line
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and if not:
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and if not:
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- increment IC read miss stats
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- increment IC read miss stats
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- find lru way and entry and replace old tag with tag of the 'fetchaddr'
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- find lru way and entry and replace old tag with tag of the 'fetchaddr'
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- set 'lru' with ic->ustates - 1 and decrement 'lru' of other
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- set 'lru' with ic->ustates - 1 and decrement 'lru' of other
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ways unless they have reached 0
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ways unless they have reached 0
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- refill cache line
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- refill cache line
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*/
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*/
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uint32_t
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uint32_t
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ic_simulate_fetch (oraddr_t fetchaddr, oraddr_t virt_addr)
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ic_simulate_fetch (oraddr_t fetchaddr, oraddr_t virt_addr)
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{
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{
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oraddr_t set;
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oraddr_t set;
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oraddr_t way;
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oraddr_t way;
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oraddr_t lru_way;
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oraddr_t lru_way;
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oraddr_t tagaddr;
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oraddr_t tagaddr;
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uint32_t tmp;
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uint32_t tmp;
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oraddr_t reload_addr;
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oraddr_t reload_addr;
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oraddr_t reload_end;
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oraddr_t reload_end;
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unsigned int minlru;
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unsigned int minlru;
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struct ic *ic = ic_state;
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struct ic *ic = ic_state;
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|
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/* ICache simulation enabled/disabled. */
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/* ICache simulation enabled/disabled. */
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if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_ICP) ||
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if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_ICP) ||
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!(cpu_state.sprs[SPR_SR] & SPR_SR_ICE) || insn_ci)
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!(cpu_state.sprs[SPR_SR] & SPR_SR_ICE) || insn_ci)
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{
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{
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tmp = evalsim_mem32 (fetchaddr, virt_addr);
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tmp = evalsim_mem32 (fetchaddr, virt_addr);
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if (cur_area && cur_area->log)
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if (cur_area && cur_area->log)
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fprintf (cur_area->log, "[%" PRIxADDR "] -> read %08" PRIx32 "\n",
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fprintf (cur_area->log, "[%" PRIxADDR "] -> read %08" PRIx32 "\n",
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fetchaddr, tmp);
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fetchaddr, tmp);
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return tmp;
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return tmp;
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}
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}
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/* Which set to check out? */
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/* Which set to check out? */
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set = (fetchaddr & ic->set_mask) >> ic->blocksize_log2;
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set = (fetchaddr & ic->set_mask) >> ic->blocksize_log2;
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tagaddr = fetchaddr & ic->tagaddr_mask;
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tagaddr = fetchaddr & ic->tagaddr_mask;
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|
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/* Scan all ways and try to find a matching way. */
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/* Scan all ways and try to find a matching way. */
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for (way = set; way < ic->last_way; way += ic->nsets)
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for (way = set; way < ic->last_way; way += ic->nsets)
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{
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{
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if (ic->tags[way] == tagaddr)
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if (ic->tags[way] == tagaddr)
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{
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{
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ic_stats.readhit++;
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ic_stats.readhit++;
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for (lru_way = set; lru_way < ic->last_way; lru_way += ic->nsets)
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for (lru_way = set; lru_way < ic->last_way; lru_way += ic->nsets)
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if (ic->lrus[lru_way] > ic->lrus[way])
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if (ic->lrus[lru_way] > ic->lrus[way])
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ic->lrus[lru_way]--;
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ic->lrus[lru_way]--;
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ic->lrus[way] = ic->ustates_reload;
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ic->lrus[way] = ic->ustates_reload;
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runtime.sim.mem_cycles += ic->hitdelay;
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runtime.sim.mem_cycles += ic->hitdelay;
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way <<= ic->blocksize_log2;
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way <<= ic->blocksize_log2;
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return *(uint32_t *) & ic->
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return *(uint32_t *) & ic->
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mem[way | (fetchaddr & ic->block_offset_mask)];
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mem[way | (fetchaddr & ic->block_offset_mask)];
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}
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}
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}
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}
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minlru = ic->ustates_reload;
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minlru = ic->ustates_reload;
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way = set;
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way = set;
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ic_stats.readmiss++;
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ic_stats.readmiss++;
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for (lru_way = set; lru_way < ic->last_way; lru_way += ic->nsets)
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for (lru_way = set; lru_way < ic->last_way; lru_way += ic->nsets)
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{
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{
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if (ic->lrus[lru_way] < minlru)
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if (ic->lrus[lru_way] < minlru)
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{
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{
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way = lru_way;
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way = lru_way;
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minlru = ic->lrus[lru_way];
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minlru = ic->lrus[lru_way];
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}
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}
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}
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}
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ic->tags[way] = tagaddr;
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ic->tags[way] = tagaddr;
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for (lru_way = set; lru_way < ic->last_way; lru_way += ic->nsets)
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for (lru_way = set; lru_way < ic->last_way; lru_way += ic->nsets)
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if (ic->lrus[lru_way])
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if (ic->lrus[lru_way])
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ic->lrus[lru_way]--;
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ic->lrus[lru_way]--;
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ic->lrus[way] = ic->ustates_reload;
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ic->lrus[way] = ic->ustates_reload;
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reload_addr = fetchaddr & ic->block_offset_mask;
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reload_addr = fetchaddr & ic->block_offset_mask;
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reload_end = reload_addr + ic->blocksize;
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reload_end = reload_addr + ic->blocksize;
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fetchaddr &= ic->block_mask;
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fetchaddr &= ic->block_mask;
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way <<= ic->blocksize_log2;
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way <<= ic->blocksize_log2;
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for (; reload_addr < reload_end; reload_addr += 4)
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for (; reload_addr < reload_end; reload_addr += 4)
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{
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{
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tmp =
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tmp =
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*(uint32_t *) & ic->mem[way | (reload_addr & ic->block_offset_mask)] =
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*(uint32_t *) & ic->mem[way | (reload_addr & ic->block_offset_mask)] =
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/* FIXME: What is the virtual address meant to be? (ie. What happens if
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/* FIXME: What is the virtual address meant to be? (ie. What happens if
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* we read out of memory while refilling a cache line?) */
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* we read out of memory while refilling a cache line?) */
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evalsim_mem32 (fetchaddr | (reload_addr & ic->block_offset_mask), 0);
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evalsim_mem32 (fetchaddr | (reload_addr & ic->block_offset_mask), 0);
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if (!cur_area)
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if (!cur_area)
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{
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{
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ic->tags[way >> ic->blocksize_log2] = -1;
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ic->tags[way >> ic->blocksize_log2] = -1;
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ic->lrus[way >> ic->blocksize_log2] = 0;
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ic->lrus[way >> ic->blocksize_log2] = 0;
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return 0;
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return 0;
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}
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}
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else if (cur_area->log)
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else if (cur_area->log)
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fprintf (cur_area->log, "[%" PRIxADDR "] -> read %08" PRIx32 "\n",
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fprintf (cur_area->log, "[%" PRIxADDR "] -> read %08" PRIx32 "\n",
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fetchaddr, tmp);
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fetchaddr, tmp);
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}
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}
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runtime.sim.mem_cycles += ic->missdelay;
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runtime.sim.mem_cycles += ic->missdelay;
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return *(uint32_t *) & ic->mem[way | (reload_addr & ic->block_offset_mask)];
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return *(uint32_t *) & ic->mem[way | (reload_addr & ic->block_offset_mask)];
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}
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}
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/* First check if data is already in the cache and if it is:
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/* First check if data is already in the cache and if it is:
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- invalidate block if way isn't locked
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- invalidate block if way isn't locked
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otherwise don't do anything.
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otherwise don't do anything.
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*/
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*/
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void
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void
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ic_inv (oraddr_t dataaddr)
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ic_inv (oraddr_t dataaddr)
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{
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{
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oraddr_t set;
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oraddr_t set;
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oraddr_t way;
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oraddr_t way;
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oraddr_t tagaddr;
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oraddr_t tagaddr;
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struct ic *ic = ic_state;
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struct ic *ic = ic_state;
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|
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if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_ICP))
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if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_ICP))
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return;
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return;
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|
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/* Which set to check out? */
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/* Which set to check out? */
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set = (dataaddr & ic->set_mask) >> ic->blocksize_log2;
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set = (dataaddr & ic->set_mask) >> ic->blocksize_log2;
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|
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if (!(cpu_state.sprs[SPR_SR] & SPR_SR_ICE))
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if (!(cpu_state.sprs[SPR_SR] & SPR_SR_ICE))
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{
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{
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for (way = set; way < ic->last_way; way += ic->nsets)
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for (way = set; way < ic->last_way; way += ic->nsets)
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{
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{
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ic->tags[way] = -1;
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ic->tags[way] = -1;
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ic->lrus[way] = 0;
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ic->lrus[way] = 0;
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}
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}
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return;
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return;
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}
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}
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tagaddr = dataaddr & ic->tagaddr_mask;
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tagaddr = dataaddr & ic->tagaddr_mask;
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|
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/* Scan all ways and try to find a matching way. */
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/* Scan all ways and try to find a matching way. */
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for (way = set; way < ic->last_way; way += ic->nsets)
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for (way = set; way < ic->last_way; way += ic->nsets)
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{
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{
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if (ic->tags[way] == tagaddr)
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if (ic->tags[way] == tagaddr)
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{
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{
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ic->tags[way] = -1;
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ic->tags[way] = -1;
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ic->lrus[way] = 0;
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ic->lrus[way] = 0;
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}
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}
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}
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}
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}
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}
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/*-----------------------------------------------------[ IC configuration ]---*/
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/*-----------------------------------------------------[ IC configuration ]---*/
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|
|
|
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/*!Enable or disable the instruction cache
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/*!Enable or disable the instruction cache
|
|
|
Set the corresponding fields in the UPR
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Set the corresponding fields in the UPR
|
|
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@param[in] val The value to use
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@param[in] val The value to use
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@param[in] dat The config data structure */
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@param[in] dat The config data structure */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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static void
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static void
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ic_enabled (union param_val val,
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ic_enabled (union param_val val,
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void *dat)
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void *dat)
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{
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{
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struct ic *ic = dat;
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struct ic *ic = dat;
|
|
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ic->enabled = val.int_val;
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ic->enabled = val.int_val;
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|
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if (val.int_val)
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if (val.int_val)
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{
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{
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cpu_state.sprs[SPR_UPR] |= SPR_UPR_ICP;
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cpu_state.sprs[SPR_UPR] |= SPR_UPR_ICP;
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}
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}
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else
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else
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{
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{
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cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_ICP;
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cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_ICP;
|
}
|
}
|
} /* ic_enabled() */
|
} /* ic_enabled() */
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
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/*!Set the number of instruction cache sets
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/*!Set the number of instruction cache sets
|
|
|
Set the corresponding field in the UPR
|
Set the corresponding field in the UPR
|
|
|
@param[in] val The value to use
|
@param[in] val The value to use
|
@param[in] dat The config data structure */
|
@param[in] dat The config data structure */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
static void
|
static void
|
ic_nsets (union param_val val,
|
ic_nsets (union param_val val,
|
void *dat)
|
void *dat)
|
{
|
{
|
struct ic *ic = dat;
|
struct ic *ic = dat;
|
|
|
if (is_power2 (val.int_val) && (val.int_val <= MAX_IC_SETS))
|
if (is_power2 (val.int_val) && (val.int_val <= MAX_IC_SETS))
|
{
|
{
|
int set_bits = log2_int (val.int_val);
|
int set_bits = log2_int (val.int_val);
|
|
|
ic->nsets = val.int_val;
|
ic->nsets = val.int_val;
|
|
|
cpu_state.sprs[SPR_ICCFGR] &= ~SPR_ICCFGR_NCS;
|
cpu_state.sprs[SPR_ICCFGR] &= ~SPR_ICCFGR_NCS;
|
cpu_state.sprs[SPR_ICCFGR] |= set_bits << SPR_ICCFGR_NCS_OFF;
|
cpu_state.sprs[SPR_ICCFGR] |= set_bits << SPR_ICCFGR_NCS_OFF;
|
}
|
}
|
else
|
else
|
{
|
{
|
fprintf (stderr, "Warning: instruction cache nsets not a power of "
|
fprintf (stderr, "Warning: instruction cache nsets not a power of "
|
"2 <= %d: ignored\n", MAX_IC_SETS);
|
"2 <= %d: ignored\n", MAX_IC_SETS);
|
}
|
}
|
} /* ic_nsets() */
|
} /* ic_nsets() */
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/*!Set the number of instruction cache ways
|
/*!Set the number of instruction cache ways
|
|
|
Set the corresponding field in the UPR
|
Set the corresponding field in the UPR
|
|
|
@param[in] val The value to use
|
@param[in] val The value to use
|
@param[in] dat The config data structure */
|
@param[in] dat The config data structure */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
static void
|
static void
|
ic_nways (union param_val val,
|
ic_nways (union param_val val,
|
void *dat)
|
void *dat)
|
{
|
{
|
struct ic *ic = dat;
|
struct ic *ic = dat;
|
|
|
if (is_power2 (val.int_val) && (val.int_val <= MAX_IC_WAYS))
|
if (is_power2 (val.int_val) && (val.int_val <= MAX_IC_WAYS))
|
{
|
{
|
int way_bits = log2_int (val.int_val);
|
int way_bits = log2_int (val.int_val);
|
|
|
ic->nways = val.int_val;
|
ic->nways = val.int_val;
|
|
|
cpu_state.sprs[SPR_ICCFGR] &= ~SPR_ICCFGR_NCW;
|
cpu_state.sprs[SPR_ICCFGR] &= ~SPR_ICCFGR_NCW;
|
cpu_state.sprs[SPR_ICCFGR] |= way_bits << SPR_ICCFGR_NCW_OFF;
|
cpu_state.sprs[SPR_ICCFGR] |= way_bits << SPR_ICCFGR_NCW_OFF;
|
}
|
}
|
else
|
else
|
{
|
{
|
fprintf (stderr, "Warning: instruction cache nways not a power of "
|
fprintf (stderr, "Warning: instruction cache nways not a power of "
|
"2 <= %d: ignored\n", MAX_IC_WAYS);
|
"2 <= %d: ignored\n", MAX_IC_WAYS);
|
}
|
}
|
} /* ic_nways() */
|
} /* ic_nways() */
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/*!Set the instruction cache block size
|
/*!Set the instruction cache block size
|
|
|
Value must be either MIN_IC_BLOCK_SIZE or MAX_IC_BLOCK_SIZE. If not issue a
|
Value must be either MIN_IC_BLOCK_SIZE or MAX_IC_BLOCK_SIZE. If not issue a
|
warning and ignore. Set the relevant field in the data cache config register
|
warning and ignore. Set the relevant field in the data cache config register
|
|
|
@param[in] val The value to use
|
@param[in] val The value to use
|
@param[in] dat The config data structure */
|
@param[in] dat The config data structure */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
static void
|
static void
|
ic_blocksize (union param_val val,
|
ic_blocksize (union param_val val,
|
void *dat)
|
void *dat)
|
{
|
{
|
struct ic *ic = dat;
|
struct ic *ic = dat;
|
|
|
switch (val.int_val)
|
switch (val.int_val)
|
{
|
{
|
case MIN_IC_BLOCK_SIZE:
|
case MIN_IC_BLOCK_SIZE:
|
ic->blocksize = val.int_val;
|
ic->blocksize = val.int_val;
|
cpu_state.sprs[SPR_ICCFGR] &= ~SPR_ICCFGR_CBS;
|
cpu_state.sprs[SPR_ICCFGR] &= ~SPR_ICCFGR_CBS;
|
break;
|
break;
|
|
|
case MAX_IC_BLOCK_SIZE:
|
case MAX_IC_BLOCK_SIZE:
|
ic->blocksize = val.int_val;
|
ic->blocksize = val.int_val;
|
cpu_state.sprs[SPR_ICCFGR] |= SPR_ICCFGR_CBS;
|
cpu_state.sprs[SPR_ICCFGR] |= SPR_ICCFGR_CBS;
|
break;
|
break;
|
|
|
default:
|
default:
|
fprintf (stderr, "Warning: instruction cache block size not %d or %d: "
|
fprintf (stderr, "Warning: instruction cache block size not %d or %d: "
|
"ignored\n", MIN_IC_BLOCK_SIZE, MAX_IC_BLOCK_SIZE);
|
"ignored\n", MIN_IC_BLOCK_SIZE, MAX_IC_BLOCK_SIZE);
|
break;
|
break;
|
}
|
}
|
} /* ic_blocksize() */
|
} /* ic_blocksize() */
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/*!Set the number of instruction cache usage states
|
/*!Set the number of instruction cache usage states
|
|
|
Value must be 2, 3 or 4. If not issue a warning and ignore.
|
Value must be 2, 3 or 4. If not issue a warning and ignore.
|
|
|
@param[in] val The value to use
|
@param[in] val The value to use
|
@param[in] dat The config data structure */
|
@param[in] dat The config data structure */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
static void
|
static void
|
ic_ustates (union param_val val,
|
ic_ustates (union param_val val,
|
void *dat)
|
void *dat)
|
{
|
{
|
struct ic *ic = dat;
|
struct ic *ic = dat;
|
|
|
if ((val.int_val >= 2) && (val.int_val <= 4))
|
if ((val.int_val >= 2) && (val.int_val <= 4))
|
{
|
{
|
ic->ustates = val.int_val;
|
ic->ustates = val.int_val;
|
}
|
}
|
else
|
else
|
{
|
{
|
fprintf (stderr, "Warning number of instruction cache usage states "
|
fprintf (stderr, "Warning number of instruction cache usage states "
|
"must be 2, 3 or 4: ignored\n");
|
"must be 2, 3 or 4: ignored\n");
|
}
|
}
|
} /* ic_ustates() */
|
} /* ic_ustates() */
|
|
|
|
|
static void
|
static void
|
ic_hitdelay (union param_val val,
|
ic_hitdelay (union param_val val,
|
void *dat)
|
void *dat)
|
{
|
{
|
struct ic *ic = dat;
|
struct ic *ic = dat;
|
ic->hitdelay = val.int_val;
|
ic->hitdelay = val.int_val;
|
}
|
}
|
|
|
|
|
static void
|
static void
|
ic_missdelay (union param_val val,
|
ic_missdelay (union param_val val,
|
void *dat)
|
void *dat)
|
{
|
{
|
struct ic *ic = dat;
|
struct ic *ic = dat;
|
ic->missdelay = val.int_val;
|
ic->missdelay = val.int_val;
|
}
|
}
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/*!Initialize a new instruction cache configuration
|
/*!Initialize a new instruction cache configuration
|
|
|
ALL parameters are set explicitly to default values. Corresponding SPR
|
ALL parameters are set explicitly to default values. Corresponding SPR
|
flags are set as appropriate.
|
flags are set as appropriate.
|
|
|
@return The new memory configuration data structure */
|
@return The new memory configuration data structure */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
static void *
|
static void *
|
ic_start_sec ()
|
ic_start_sec ()
|
{
|
{
|
struct ic *ic;
|
struct ic *ic;
|
int set_bits;
|
int set_bits;
|
int way_bits;
|
int way_bits;
|
|
|
if (NULL == (ic = malloc (sizeof (struct ic))))
|
if (NULL == (ic = malloc (sizeof (struct ic))))
|
{
|
{
|
fprintf (stderr, "OOM\n");
|
fprintf (stderr, "OOM\n");
|
exit (1);
|
exit (1);
|
}
|
}
|
|
|
ic->enabled = 0;
|
ic->enabled = 0;
|
ic->nsets = 1;
|
ic->nsets = 1;
|
ic->nways = 1;
|
ic->nways = 1;
|
ic->blocksize = MIN_IC_BLOCK_SIZE;
|
ic->blocksize = MIN_IC_BLOCK_SIZE;
|
ic->ustates = 2;
|
ic->ustates = 2;
|
ic->hitdelay = 1;
|
ic->hitdelay = 1;
|
ic->missdelay = 1;
|
ic->missdelay = 1;
|
|
|
ic->mem = NULL; /* Internal configuration */
|
ic->mem = NULL; /* Internal configuration */
|
ic->lrus = NULL;
|
ic->lrus = NULL;
|
ic->tags = NULL;
|
ic->tags = NULL;
|
|
|
/* Set SPRs as appropriate */
|
/* Set SPRs as appropriate */
|
|
|
if (ic->enabled)
|
if (ic->enabled)
|
{
|
{
|
cpu_state.sprs[SPR_UPR] |= SPR_UPR_ICP;
|
cpu_state.sprs[SPR_UPR] |= SPR_UPR_ICP;
|
}
|
}
|
else
|
else
|
{
|
{
|
cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_ICP;
|
cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_ICP;
|
}
|
}
|
|
|
set_bits = log2_int (ic->nsets);
|
set_bits = log2_int (ic->nsets);
|
cpu_state.sprs[SPR_ICCFGR] &= ~SPR_ICCFGR_NCS;
|
cpu_state.sprs[SPR_ICCFGR] &= ~SPR_ICCFGR_NCS;
|
cpu_state.sprs[SPR_ICCFGR] |= set_bits << SPR_ICCFGR_NCS_OFF;
|
cpu_state.sprs[SPR_ICCFGR] |= set_bits << SPR_ICCFGR_NCS_OFF;
|
|
|
way_bits = log2_int (ic->nways);
|
way_bits = log2_int (ic->nways);
|
cpu_state.sprs[SPR_ICCFGR] &= ~SPR_ICCFGR_NCW;
|
cpu_state.sprs[SPR_ICCFGR] &= ~SPR_ICCFGR_NCW;
|
cpu_state.sprs[SPR_ICCFGR] |= way_bits << SPR_ICCFGR_NCW_OFF;
|
cpu_state.sprs[SPR_ICCFGR] |= way_bits << SPR_ICCFGR_NCW_OFF;
|
|
|
if (MIN_IC_BLOCK_SIZE == ic->blocksize)
|
if (MIN_IC_BLOCK_SIZE == ic->blocksize)
|
{
|
{
|
cpu_state.sprs[SPR_ICCFGR] &= ~SPR_ICCFGR_CBS;
|
cpu_state.sprs[SPR_ICCFGR] &= ~SPR_ICCFGR_CBS;
|
}
|
}
|
else
|
else
|
{
|
{
|
cpu_state.sprs[SPR_ICCFGR] |= SPR_ICCFGR_CBS;
|
cpu_state.sprs[SPR_ICCFGR] |= SPR_ICCFGR_CBS;
|
}
|
}
|
|
|
ic_state = ic;
|
ic_state = ic;
|
return ic;
|
return ic;
|
|
|
} /* ic_start_sec() */
|
} /* ic_start_sec() */
|
|
|
|
|
static void
|
static void
|
ic_end_sec (void *dat)
|
ic_end_sec (void *dat)
|
{
|
{
|
struct ic *ic = dat;
|
struct ic *ic = dat;
|
unsigned int size = ic->nways * ic->nsets * ic->blocksize;
|
unsigned int size = ic->nways * ic->nsets * ic->blocksize;
|
|
|
if (size)
|
if (size)
|
{
|
{
|
if (!(ic->mem = malloc (size)))
|
if (!(ic->mem = malloc (size)))
|
{
|
{
|
fprintf (stderr, "OOM\n");
|
fprintf (stderr, "OOM\n");
|
exit (1);
|
exit (1);
|
}
|
}
|
if (!
|
if (!
|
(ic->lrus = malloc (ic->nsets * ic->nways * sizeof (unsigned int))))
|
(ic->lrus = malloc (ic->nsets * ic->nways * sizeof (unsigned int))))
|
{
|
{
|
fprintf (stderr, "OOM\n");
|
fprintf (stderr, "OOM\n");
|
exit (1);
|
exit (1);
|
}
|
}
|
if (!(ic->tags = malloc (ic->nsets * ic->nways * sizeof (oraddr_t))))
|
if (!(ic->tags = malloc (ic->nsets * ic->nways * sizeof (oraddr_t))))
|
{
|
{
|
fprintf (stderr, "OOM\n");
|
fprintf (stderr, "OOM\n");
|
exit (1);
|
exit (1);
|
}
|
}
|
|
|
/* Clear the cache data. John Alfredo's fix for using 0 (which is a
|
/* Clear the cache data. John Alfredo's fix for using 0 (which is a
|
valid tag), so we now use -1 */
|
valid tag), so we now use -1 */
|
memset (ic->mem, 0, size);
|
memset (ic->mem, 0, size);
|
memset (ic->lrus, 0, ic->nsets * ic->nways * sizeof (unsigned int));
|
memset (ic->lrus, 0, ic->nsets * ic->nways * sizeof (unsigned int));
|
memset (ic->tags, -1, ic->nsets * ic->nways * sizeof (oraddr_t));
|
memset (ic->tags, -1, ic->nsets * ic->nways * sizeof (oraddr_t));
|
}
|
}
|
else
|
else
|
{
|
{
|
ic->enabled = 0;
|
ic->enabled = 0;
|
}
|
}
|
|
|
ic->blocksize_log2 = log2_int (ic->blocksize);
|
ic->blocksize_log2 = log2_int (ic->blocksize);
|
ic->set_mask = (ic->nsets - 1) << ic->blocksize_log2;
|
ic->set_mask = (ic->nsets - 1) << ic->blocksize_log2;
|
ic->tagaddr_mask = ~((ic->nsets * ic->blocksize) - 1);
|
ic->tagaddr_mask = ~((ic->nsets * ic->blocksize) - 1);
|
ic->last_way = ic->nsets * ic->nways;
|
ic->last_way = ic->nsets * ic->nways;
|
ic->block_offset_mask = ic->blocksize - 1;
|
ic->block_offset_mask = ic->blocksize - 1;
|
ic->block_mask = ~ic->block_offset_mask;
|
ic->block_mask = ~ic->block_offset_mask;
|
ic->ustates_reload = ic->ustates - 1;
|
ic->ustates_reload = ic->ustates - 1;
|
|
|
if (ic->enabled)
|
if (ic->enabled)
|
reg_sim_stat (ic_info, dat);
|
reg_sim_stat (ic_info, dat);
|
}
|
}
|
|
|
void
|
void
|
reg_ic_sec (void)
|
reg_ic_sec (void)
|
{
|
{
|
struct config_section *sec =
|
struct config_section *sec =
|
reg_config_sec ("ic", ic_start_sec, ic_end_sec);
|
reg_config_sec ("ic", ic_start_sec, ic_end_sec);
|
|
|
reg_config_param (sec, "enabled", paramt_int, ic_enabled);
|
reg_config_param (sec, "enabled", PARAMT_INT, ic_enabled);
|
reg_config_param (sec, "nsets", paramt_int, ic_nsets);
|
reg_config_param (sec, "nsets", PARAMT_INT, ic_nsets);
|
reg_config_param (sec, "nways", paramt_int, ic_nways);
|
reg_config_param (sec, "nways", PARAMT_INT, ic_nways);
|
reg_config_param (sec, "blocksize", paramt_int, ic_blocksize);
|
reg_config_param (sec, "blocksize", PARAMT_INT, ic_blocksize);
|
reg_config_param (sec, "ustates", paramt_int, ic_ustates);
|
reg_config_param (sec, "ustates", PARAMT_INT, ic_ustates);
|
reg_config_param (sec, "missdelay", paramt_int, ic_missdelay);
|
reg_config_param (sec, "missdelay", PARAMT_INT, ic_missdelay);
|
reg_config_param (sec, "hitdelay", paramt_int, ic_hitdelay);
|
reg_config_param (sec, "hitdelay" , PARAMT_INT, ic_hitdelay);
|
}
|
}
|
|
|
