/* spr_dump.c -- Dump given spr in human readable form
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/* spr_dump.c -- Dump given spr in human readable form
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Copyright (C) 2005 György `nog' Jeney, nog@sdf.lonestar.org
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Copyright (C) 2005 György `nog' Jeney, nog@sdf.lonestar.org
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Copyright (C) 2008 Embecosm Limited
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Copyright (C) 2008 Embecosm Limited
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify it
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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more details.
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You should have received a copy of the GNU General Public License along
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You should have received a copy of the GNU General Public License along
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* This program is commented throughout in a fashion suitable for processing
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/* This program is commented throughout in a fashion suitable for processing
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with Doxygen. */
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with Doxygen. */
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/* Autoconf and/or portability configuration */
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/* Autoconf and/or portability configuration */
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#include "config.h"
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#include "config.h"
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#include "port.h"
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#include "port.h"
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/* System includes */
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/* System includes */
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#include <stdio.h>
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#include <stdio.h>
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/* Package includes */
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/* Package includes */
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#include "arch.h"
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#include "arch.h"
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#include "spr-defs.h"
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#include "spr-defs.h"
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#include "debug.h"
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#include "debug.h"
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#include "misc.h"
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#include "misc.h"
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struct spr_bit_def {
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struct spr_bit_def {
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const char *name;
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const char *name;
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uorreg_t mask;
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uorreg_t mask;
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};
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};
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struct spr_def {
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struct spr_def {
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uint16_t from_spr;
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uint16_t from_spr;
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uint16_t to_spr;
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uint16_t to_spr;
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const char *name;
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const char *name;
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const struct spr_bit_def *bits;
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const struct spr_bit_def *bits;
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};
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};
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/* One value spr */
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/* One value spr */
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static const struct spr_bit_def spr_one_val[] = {
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static const struct spr_bit_def spr_one_val[] = {
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{ "", 0xffffffff },
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{ "", 0xffffffff },
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{ NULL, 0 } };
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{ NULL, 0 } };
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/*---------------------------------------------------------[ System group ]---*/
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/*---------------------------------------------------------[ System group ]---*/
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/* Supervisor register */
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/* Supervisor register */
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static const struct spr_bit_def spr_sr[] = {
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static const struct spr_bit_def spr_sr[] = {
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{ "SR_SM", SPR_SR_SM },
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{ "SR_SM", SPR_SR_SM },
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{ "SR_TEE", SPR_SR_TEE },
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{ "SR_TEE", SPR_SR_TEE },
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{ "SR_IEE", SPR_SR_IEE },
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{ "SR_IEE", SPR_SR_IEE },
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{ "SR_DCE", SPR_SR_DCE },
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{ "SR_DCE", SPR_SR_DCE },
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{ "SR_ICE", SPR_SR_ICE },
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{ "SR_ICE", SPR_SR_ICE },
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{ "SR_DME", SPR_SR_DME },
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{ "SR_DME", SPR_SR_DME },
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{ "SR_IME", SPR_SR_IME },
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{ "SR_IME", SPR_SR_IME },
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{ "SR_LEE", SPR_SR_IME },
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{ "SR_LEE", SPR_SR_IME },
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{ "SR_CE", SPR_SR_CE },
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{ "SR_CE", SPR_SR_CE },
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{ "SR_F", SPR_SR_F },
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{ "SR_F", SPR_SR_F },
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{ "SR_CY", SPR_SR_CY },
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{ "SR_CY", SPR_SR_CY },
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{ "SR_OV", SPR_SR_OV },
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{ "SR_OV", SPR_SR_OV },
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{ "SR_OVE", SPR_SR_OVE },
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{ "SR_OVE", SPR_SR_OVE },
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{ "SR_DSX", SPR_SR_DSX },
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{ "SR_DSX", SPR_SR_DSX },
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{ "SR_EPH", SPR_SR_EPH },
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{ "SR_EPH", SPR_SR_EPH },
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{ "SR_FO", SPR_SR_FO },
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{ "SR_FO", SPR_SR_FO },
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{ "SR_SUMRA", SPR_SR_SUMRA },
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{ "SR_SUMRA", SPR_SR_SUMRA },
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{ "SR_RES", SPR_SR_RES },
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{ "SR_RES", SPR_SR_RES },
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{ "SR_CID", SPR_SR_CID },
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{ "SR_CID", SPR_SR_CID },
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{ NULL, 0 } };
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{ NULL, 0 } };
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/* Version register */
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/* Version register */
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static const struct spr_bit_def spr_vr[] = {
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static const struct spr_bit_def spr_vr[] = {
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{ "VR_VER", SPR_VR_VER },
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{ "VR_VER", SPR_VR_VER },
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{ "VR_REV", SPR_VR_REV },
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{ "VR_REV", SPR_VR_REV },
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{ NULL, 0 } };
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{ NULL, 0 } };
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/* upr register */
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/* upr register */
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static const struct spr_bit_def spr_upr[] = {
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static const struct spr_bit_def spr_upr[] = {
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{ "UPR_UP", SPR_UPR_UP },
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{ "UPR_UP", SPR_UPR_UP },
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{ "UPR_DCP", SPR_UPR_DCP },
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{ "UPR_DCP", SPR_UPR_DCP },
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{ "UPR_ICP", SPR_UPR_ICP },
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{ "UPR_ICP", SPR_UPR_ICP },
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{ "UPR_DMP", SPR_UPR_DMP },
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{ "UPR_DMP", SPR_UPR_DMP },
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{ "UPR_IMP", SPR_UPR_IMP },
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{ "UPR_IMP", SPR_UPR_IMP },
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{ "UPR_MP", SPR_UPR_MP },
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{ "UPR_MP", SPR_UPR_MP },
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{ "UPR_DUP", SPR_UPR_DUP },
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{ "UPR_DUP", SPR_UPR_DUP },
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{ "UPR_PCUP", SPR_UPR_PCUP },
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{ "UPR_PCUP", SPR_UPR_PCUP },
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{ "UPR_PMP", SPR_UPR_PMP },
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{ "UPR_PMP", SPR_UPR_PMP },
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{ "UPR_PICP", SPR_UPR_PICP },
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{ "UPR_PICP", SPR_UPR_PICP },
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{ "UPR_TTP", SPR_UPR_TTP },
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{ "UPR_TTP", SPR_UPR_TTP },
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{ "UPR_RES", SPR_UPR_RES },
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{ "UPR_RES", SPR_UPR_RES },
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{ "UPR_CUP", SPR_UPR_CUP },
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{ "UPR_CUP", SPR_UPR_CUP },
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{ NULL, 0 } };
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{ NULL, 0 } };
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/* CPUCFGR register */
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/* CPUCFGR register */
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static const struct spr_bit_def spr_cpucfgr[] = {
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static const struct spr_bit_def spr_cpucfgr[] = {
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{ "CPUCFGR_OB32S", SPR_CPUCFGR_OB32S },
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{ "CPUCFGR_OB32S", SPR_CPUCFGR_OB32S },
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{ "CPUCFGR_OB64S", SPR_CPUCFGR_OB64S },
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{ "CPUCFGR_OB64S", SPR_CPUCFGR_OB64S },
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{ "CPUCFGR_OF32S", SPR_CPUCFGR_OF32S },
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{ "CPUCFGR_OF32S", SPR_CPUCFGR_OF32S },
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{ "CPUCFGR_OF64S", SPR_CPUCFGR_OF64S },
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{ "CPUCFGR_OF64S", SPR_CPUCFGR_OF64S },
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{ "CPUCFGR_OV64S", SPR_CPUCFGR_OV64S },
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{ "CPUCFGR_OV64S", SPR_CPUCFGR_OV64S },
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{ NULL, 0 } };
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{ NULL, 0 } };
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/* dmmucfgr register */
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/* dmmucfgr register */
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static const struct spr_bit_def spr_dmmucfgr[] = {
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static const struct spr_bit_def spr_dmmucfgr[] = {
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{ "DMMUCFGR_NTW", SPR_DMMUCFGR_NTW },
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{ "DMMUCFGR_NTW", SPR_DMMUCFGR_NTW },
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{ "DMMUCFGR_NTS", SPR_DMMUCFGR_NTS },
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{ "DMMUCFGR_NTS", SPR_DMMUCFGR_NTS },
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{ "DMMUCFGR_NAE", SPR_DMMUCFGR_NAE },
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{ "DMMUCFGR_NAE", SPR_DMMUCFGR_NAE },
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{ "DMMUCFGR_CRI", SPR_DMMUCFGR_CRI },
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{ "DMMUCFGR_CRI", SPR_DMMUCFGR_CRI },
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{ "DMMUCFGR_PRI", SPR_DMMUCFGR_PRI },
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{ "DMMUCFGR_PRI", SPR_DMMUCFGR_PRI },
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{ "DMMUCFGR_TEIRI", SPR_DMMUCFGR_TEIRI },
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{ "DMMUCFGR_TEIRI", SPR_DMMUCFGR_TEIRI },
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{ "DMMUCFGR_HTR", SPR_DMMUCFGR_HTR },
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{ "DMMUCFGR_HTR", SPR_DMMUCFGR_HTR },
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{ NULL, 0 } };
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{ NULL, 0 } };
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/* immucfgr register */
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/* immucfgr register */
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static const struct spr_bit_def spr_immucfgr[] = {
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static const struct spr_bit_def spr_immucfgr[] = {
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{ "IMMUCFGR_NTW", SPR_IMMUCFGR_NTW },
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{ "IMMUCFGR_NTW", SPR_IMMUCFGR_NTW },
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{ "IMMUCFGR_NTS", SPR_IMMUCFGR_NTS },
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{ "IMMUCFGR_NTS", SPR_IMMUCFGR_NTS },
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{ "IMMUCFGR_NAE", SPR_IMMUCFGR_NAE },
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{ "IMMUCFGR_NAE", SPR_IMMUCFGR_NAE },
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{ "IMMUCFGR_CRI", SPR_IMMUCFGR_CRI },
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{ "IMMUCFGR_CRI", SPR_IMMUCFGR_CRI },
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{ "IMMUCFGR_PRI", SPR_IMMUCFGR_PRI },
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{ "IMMUCFGR_PRI", SPR_IMMUCFGR_PRI },
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{ "IMMUCFGR_TEIRI", SPR_IMMUCFGR_TEIRI },
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{ "IMMUCFGR_TEIRI", SPR_IMMUCFGR_TEIRI },
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{ "IMMUCFGR_HTR", SPR_IMMUCFGR_HTR },
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{ "IMMUCFGR_HTR", SPR_IMMUCFGR_HTR },
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{ NULL, 0 } };
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{ NULL, 0 } };
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/* dccfgr register */
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/* dccfgr register */
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static const struct spr_bit_def spr_dccfgr[] = {
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static const struct spr_bit_def spr_dccfgr[] = {
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{ "DCCFGR_NCW", SPR_DCCFGR_NCW },
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{ "DCCFGR_NCW", SPR_DCCFGR_NCW },
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{ "DCCFGR_NCS", SPR_DCCFGR_NCS },
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{ "DCCFGR_NCS", SPR_DCCFGR_NCS },
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{ "DCCFGR_CBS", SPR_DCCFGR_CBS },
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{ "DCCFGR_CBS", SPR_DCCFGR_CBS },
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{ "DCCFGR_CWS", SPR_DCCFGR_CWS },
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{ "DCCFGR_CWS", SPR_DCCFGR_CWS },
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{ "DCCFGR_CCRI", SPR_DCCFGR_CCRI },
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{ "DCCFGR_CCRI", SPR_DCCFGR_CCRI },
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{ "DCCFGR_CBIRI", SPR_DCCFGR_CBIRI },
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{ "DCCFGR_CBIRI", SPR_DCCFGR_CBIRI },
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{ "DCCFGR_CBPRI", SPR_DCCFGR_CBPRI },
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{ "DCCFGR_CBPRI", SPR_DCCFGR_CBPRI },
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{ "DCCFGR_CBLRI", SPR_DCCFGR_CBLRI },
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{ "DCCFGR_CBLRI", SPR_DCCFGR_CBLRI },
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{ "DCCFGR_CBFRI", SPR_DCCFGR_CBFRI },
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{ "DCCFGR_CBFRI", SPR_DCCFGR_CBFRI },
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{ "DCCFGR_CBWBRI", SPR_DCCFGR_CBWBRI },
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{ "DCCFGR_CBWBRI", SPR_DCCFGR_CBWBRI },
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{ NULL, 0 } };
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{ NULL, 0 } };
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/* iccfgr register */
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/* iccfgr register */
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static const struct spr_bit_def spr_iccfgr[] = {
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static const struct spr_bit_def spr_iccfgr[] = {
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{ "ICCFGR_NCW", SPR_ICCFGR_NCW },
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{ "ICCFGR_NCW", SPR_ICCFGR_NCW },
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{ "ICCFGR_NCS", SPR_ICCFGR_NCS },
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{ "ICCFGR_NCS", SPR_ICCFGR_NCS },
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{ "ICCFGR_CBS", SPR_ICCFGR_CBS },
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{ "ICCFGR_CBS", SPR_ICCFGR_CBS },
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{ "ICCFGR_CCRI", SPR_ICCFGR_CCRI },
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{ "ICCFGR_CCRI", SPR_ICCFGR_CCRI },
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{ "ICCFGR_CBIRI", SPR_ICCFGR_CBIRI },
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{ "ICCFGR_CBIRI", SPR_ICCFGR_CBIRI },
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{ "ICCFGR_CBPRI", SPR_ICCFGR_CBPRI },
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{ "ICCFGR_CBPRI", SPR_ICCFGR_CBPRI },
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{ "ICCFGR_CBLRI", SPR_ICCFGR_CBLRI },
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{ "ICCFGR_CBLRI", SPR_ICCFGR_CBLRI },
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{ NULL, 0 } };
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{ NULL, 0 } };
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/* DCFGR register */
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/* DCFGR register */
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static const struct spr_bit_def spr_dcfgr[] = {
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static const struct spr_bit_def spr_dcfgr[] = {
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{ "DCFGR_NDP", SPR_DCFGR_NDP },
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{ "DCFGR_NDP", SPR_DCFGR_NDP },
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{ "DCFGR_WPCI", SPR_DCFGR_WPCI },
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{ "DCFGR_WPCI", SPR_DCFGR_WPCI },
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{ NULL, 0 } };
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{ NULL, 0 } };
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/* System group */
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/* System group */
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static const struct spr_def spr_sys_group[] = {
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static const struct spr_def spr_sys_group[] = {
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/* 000-000 */ { 0x000, 0x000, "SPR_VR", spr_vr },
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/* 000-000 */ { 0x000, 0x000, "SPR_VR", spr_vr },
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/* 001-001 */ { 0x001, 0x001, "SPR_UPR", spr_upr },
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/* 001-001 */ { 0x001, 0x001, "SPR_UPR", spr_upr },
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/* 002-002 */ { 0x002, 0x002, "SPR_CPUCFGR", spr_cpucfgr }, /* JPB */
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/* 002-002 */ { 0x002, 0x002, "SPR_CPUCFGR", spr_cpucfgr }, /* JPB */
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/* 003-003 */ { 0x003, 0x003, "SPR_DMMUCFGR", spr_dmmucfgr },
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/* 003-003 */ { 0x003, 0x003, "SPR_DMMUCFGR", spr_dmmucfgr },
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/* 004-004 */ { 0x004, 0x004, "SPR_IMMUCFGR", spr_immucfgr },
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/* 004-004 */ { 0x004, 0x004, "SPR_IMMUCFGR", spr_immucfgr },
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/* 005-005 */ { 0x005, 0x005, "SPR_DCCFGR", spr_dccfgr },
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/* 005-005 */ { 0x005, 0x005, "SPR_DCCFGR", spr_dccfgr },
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/* 006-006 */ { 0x006, 0x006, "SPR_ICCFGR", spr_iccfgr },
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/* 006-006 */ { 0x006, 0x006, "SPR_ICCFGR", spr_iccfgr },
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/* 007-007 */ { 0x007, 0x007, "SPR_DCFGR", spr_dcfgr }, /* JPB */
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/* 007-007 */ { 0x007, 0x007, "SPR_DCFGR", spr_dcfgr }, /* JPB */
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/* 010-010 */ { 0x010, 0x010, "SPR_NPC", spr_one_val },
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/* 010-010 */ { 0x010, 0x010, "SPR_NPC", spr_one_val },
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/* 011-011 */ { 0x011, 0x011, "SPR_SR", spr_sr },
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/* 011-011 */ { 0x011, 0x011, "SPR_SR", spr_sr },
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/* 012-012 */ { 0x012, 0x012, "SPR_PPC", spr_one_val },
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/* 012-012 */ { 0x012, 0x012, "SPR_PPC", spr_one_val },
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/* 020-02f */ { 0x020, 0x02f, "SPR_EPCR(%i)", spr_one_val },
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/* 020-02f */ { 0x020, 0x02f, "SPR_EPCR(%i)", spr_one_val },
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/* 030-03f */ { 0x030, 0x03f, "SPR_EEAR(%i)", spr_one_val },
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/* 030-03f */ { 0x030, 0x03f, "SPR_EEAR(%i)", spr_one_val },
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/* 040-04f */ { 0x040, 0x04f, "SPR_ESR(%i)", spr_sr },
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/* 040-04f */ { 0x040, 0x04f, "SPR_ESR(%i)", spr_sr },
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/* 400-41f */ { 0x400, 0x41f, "GPR(%i)", spr_one_val },
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/* 400-41f */ { 0x400, 0x41f, "GPR(%i)", spr_one_val },
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/* ------- */ { -1, -1, NULL, NULL } };
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/* ------- */ { -1, -1, NULL, NULL } };
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/*-----------------------------------------------------------[ DMMU group ]---*/
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/*-----------------------------------------------------------[ DMMU group ]---*/
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/* Data MMU conrtol reg */
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/* Data MMU conrtol reg */
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static const struct spr_bit_def spr_dmmucr[] = {
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static const struct spr_bit_def spr_dmmucr[] = {
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{ "DMMUCR_P2S", SPR_DMMUCR_P2S },
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{ "DMMUCR_P2S", SPR_DMMUCR_P2S },
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{ "DMMUCR_P1S", SPR_DMMUCR_P1S },
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{ "DMMUCR_P1S", SPR_DMMUCR_P1S },
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{ "DMMUCR_VADDR_WIDTH", SPR_DMMUCR_VADDR_WIDTH },
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{ "DMMUCR_VADDR_WIDTH", SPR_DMMUCR_VADDR_WIDTH },
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{ "DMMUCR_PADDR_WIDTH", SPR_DMMUCR_PADDR_WIDTH },
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{ "DMMUCR_PADDR_WIDTH", SPR_DMMUCR_PADDR_WIDTH },
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{ NULL, 0 } };
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{ NULL, 0 } };
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/* dtlbmr register */
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/* dtlbmr register */
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static const struct spr_bit_def spr_dtlbmr[] = {
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static const struct spr_bit_def spr_dtlbmr[] = {
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{ "DTLBMR_V", SPR_DTLBMR_V },
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{ "DTLBMR_V", SPR_DTLBMR_V },
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{ "DTLBMR_PL1", SPR_DTLBMR_PL1 },
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{ "DTLBMR_PL1", SPR_DTLBMR_PL1 },
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{ "DTLBMR_CID", SPR_DTLBMR_CID },
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{ "DTLBMR_CID", SPR_DTLBMR_CID },
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{ "DTLBMR_LRU", SPR_DTLBMR_LRU },
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{ "DTLBMR_LRU", SPR_DTLBMR_LRU },
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{ "DTLBMR_VPN", SPR_DTLBMR_VPN },
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{ "DTLBMR_VPN", SPR_DTLBMR_VPN },
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{ NULL, 0 } };
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{ NULL, 0 } };
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/* dtlbtr register */
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/* dtlbtr register */
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static const struct spr_bit_def spr_dtlbtr[] = {
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static const struct spr_bit_def spr_dtlbtr[] = {
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{ "DTLBTR_CC", SPR_DTLBTR_CC },
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{ "DTLBTR_CC", SPR_DTLBTR_CC },
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{ "DTLBTR_CI", SPR_DTLBTR_CI },
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{ "DTLBTR_CI", SPR_DTLBTR_CI },
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{ "DTLBTR_WBC", SPR_DTLBTR_WBC },
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{ "DTLBTR_WBC", SPR_DTLBTR_WBC },
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{ "DTLBTR_WOM", SPR_DTLBTR_WOM },
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{ "DTLBTR_WOM", SPR_DTLBTR_WOM },
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{ "DTLBTR_A", SPR_DTLBTR_A },
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{ "DTLBTR_A", SPR_DTLBTR_A },
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{ "DTLBTR_D", SPR_DTLBTR_D },
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{ "DTLBTR_D", SPR_DTLBTR_D },
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{ "DTLBTR_URE", SPR_DTLBTR_URE },
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{ "DTLBTR_URE", SPR_DTLBTR_URE },
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{ "DTLBTR_UWE", SPR_DTLBTR_UWE },
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{ "DTLBTR_UWE", SPR_DTLBTR_UWE },
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{ "DTLBTR_SRE", SPR_DTLBTR_SRE },
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{ "DTLBTR_SRE", SPR_DTLBTR_SRE },
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{ "DTLBTR_SWE", SPR_DTLBTR_SWE },
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{ "DTLBTR_SWE", SPR_DTLBTR_SWE },
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{ "DTLBTR_PPN", SPR_DTLBTR_PPN },
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{ "DTLBTR_PPN", SPR_DTLBTR_PPN },
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{ NULL, 0 } };
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{ NULL, 0 } };
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/* DMMU group */
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/* DMMU group */
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static const struct spr_def spr_dmmu_group[] = {
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static const struct spr_def spr_dmmu_group[] = {
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/* 000-000 */ { 0, 0, "SPR_DMMUCR", spr_dmmucr },
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/* 000-000 */ { 0, 0, "SPR_DMMUCR", spr_dmmucr },
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/* 200-27f */ { 0x200, 0x27f, "SPR_DTLBMR way 0 set %i", spr_dtlbmr },
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/* 200-27f */ { 0x200, 0x27f, "SPR_DTLBMR way 0 set %i", spr_dtlbmr },
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/* 280-2ff */ { 0x280, 0x2ff, "SPR_DTLBTR way 0 set %i", spr_dtlbtr },
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/* 280-2ff */ { 0x280, 0x2ff, "SPR_DTLBTR way 0 set %i", spr_dtlbtr },
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/* 300-37f */ { 0x300, 0x37f, "SPR_DTLBMR way 1 set %i", spr_dtlbmr },
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/* 300-37f */ { 0x300, 0x37f, "SPR_DTLBMR way 1 set %i", spr_dtlbmr },
|
/* 380-3ff */ { 0x380, 0x3ff, "SPR_DTLBTR way 1 set %i", spr_dtlbtr },
|
/* 380-3ff */ { 0x380, 0x3ff, "SPR_DTLBTR way 1 set %i", spr_dtlbtr },
|
/* 400-47f */ { 0x400, 0x47f, "SPR_DTLBMR way 2 set %i", spr_dtlbmr },
|
/* 400-47f */ { 0x400, 0x47f, "SPR_DTLBMR way 2 set %i", spr_dtlbmr },
|
/* 480-4ff */ { 0x480, 0x4ff, "SPR_DTLBTR way 2 set %i", spr_dtlbtr },
|
/* 480-4ff */ { 0x480, 0x4ff, "SPR_DTLBTR way 2 set %i", spr_dtlbtr },
|
/* 500-57f */ { 0x500, 0x57f, "SPR_DTLBMR way 3 set %i", spr_dtlbmr },
|
/* 500-57f */ { 0x500, 0x57f, "SPR_DTLBMR way 3 set %i", spr_dtlbmr },
|
/* 580-5ff */ { 0x580, 0x5ff, "SPR_DTLBTR way 3 set %i", spr_dtlbtr },
|
/* 580-5ff */ { 0x580, 0x5ff, "SPR_DTLBTR way 3 set %i", spr_dtlbtr },
|
/* ------- */ { -1, -1, NULL, NULL } };
|
/* ------- */ { -1, -1, NULL, NULL } };
|
|
|
/*-----------------------------------------------------------[ IMMU group ]---*/
|
/*-----------------------------------------------------------[ IMMU group ]---*/
|
/* Instruction MMU conrtol reg */
|
/* Instruction MMU conrtol reg */
|
static const struct spr_bit_def spr_immucr[] = {
|
static const struct spr_bit_def spr_immucr[] = {
|
{ "IMMUCR_P2S", SPR_IMMUCR_P2S },
|
{ "IMMUCR_P2S", SPR_IMMUCR_P2S },
|
{ "IMMUCR_P1S", SPR_IMMUCR_P1S },
|
{ "IMMUCR_P1S", SPR_IMMUCR_P1S },
|
{ "IMMUCR_VADDR_WIDTH", SPR_IMMUCR_VADDR_WIDTH },
|
{ "IMMUCR_VADDR_WIDTH", SPR_IMMUCR_VADDR_WIDTH },
|
{ "IMMUCR_PADDR_WIDTH", SPR_IMMUCR_PADDR_WIDTH },
|
{ "IMMUCR_PADDR_WIDTH", SPR_IMMUCR_PADDR_WIDTH },
|
{ NULL, 0 } };
|
{ NULL, 0 } };
|
|
|
/* itlbmr register */
|
/* itlbmr register */
|
static const struct spr_bit_def spr_itlbmr[] = {
|
static const struct spr_bit_def spr_itlbmr[] = {
|
{ "ITLBMR_V", SPR_ITLBMR_V },
|
{ "ITLBMR_V", SPR_ITLBMR_V },
|
{ "ITLBMR_PL1", SPR_ITLBMR_PL1 },
|
{ "ITLBMR_PL1", SPR_ITLBMR_PL1 },
|
{ "ITLBMR_CID", SPR_ITLBMR_CID },
|
{ "ITLBMR_CID", SPR_ITLBMR_CID },
|
{ "ITLBMR_LRU", SPR_ITLBMR_LRU },
|
{ "ITLBMR_LRU", SPR_ITLBMR_LRU },
|
{ "ITLBMR_VPN", SPR_ITLBMR_VPN },
|
{ "ITLBMR_VPN", SPR_ITLBMR_VPN },
|
{ NULL, 0 } };
|
{ NULL, 0 } };
|
|
|
/* itlbtr register */
|
/* itlbtr register */
|
static const struct spr_bit_def spr_itlbtr[] = {
|
static const struct spr_bit_def spr_itlbtr[] = {
|
{ "ITLBTR_CC", SPR_ITLBTR_CC },
|
{ "ITLBTR_CC", SPR_ITLBTR_CC },
|
{ "ITLBTR_CI", SPR_ITLBTR_CI },
|
{ "ITLBTR_CI", SPR_ITLBTR_CI },
|
{ "ITLBTR_WBC", SPR_ITLBTR_WBC },
|
{ "ITLBTR_WBC", SPR_ITLBTR_WBC },
|
{ "ITLBTR_WOM", SPR_ITLBTR_WOM },
|
{ "ITLBTR_WOM", SPR_ITLBTR_WOM },
|
{ "ITLBTR_A", SPR_ITLBTR_A },
|
{ "ITLBTR_A", SPR_ITLBTR_A },
|
{ "ITLBTR_D", SPR_ITLBTR_D },
|
{ "ITLBTR_D", SPR_ITLBTR_D },
|
{ "ITLBTR_URE", SPR_ITLBTR_SXE },
|
{ "ITLBTR_URE", SPR_ITLBTR_SXE },
|
{ "ITLBTR_UWE", SPR_ITLBTR_UXE },
|
{ "ITLBTR_UWE", SPR_ITLBTR_UXE },
|
{ "ITLBTR_PPN", SPR_ITLBTR_PPN },
|
{ "ITLBTR_PPN", SPR_ITLBTR_PPN },
|
{ NULL, 0 } };
|
{ NULL, 0 } };
|
|
|
/* IMMU group */
|
/* IMMU group */
|
static const struct spr_def spr_immu_group[] = {
|
static const struct spr_def spr_immu_group[] = {
|
/* 000-000 */ { 0, 0, "SPR_IMMUCR", spr_immucr },
|
/* 000-000 */ { 0, 0, "SPR_IMMUCR", spr_immucr },
|
/* 200-27f */ { 0x200, 0x27f, "SPR_ITLBMR way 0 set %i", spr_itlbmr },
|
/* 200-27f */ { 0x200, 0x27f, "SPR_ITLBMR way 0 set %i", spr_itlbmr },
|
/* 280-2ff */ { 0x280, 0x2ff, "SPR_ITLBTR way 0 set %i", spr_itlbtr },
|
/* 280-2ff */ { 0x280, 0x2ff, "SPR_ITLBTR way 0 set %i", spr_itlbtr },
|
/* 300-37f */ { 0x300, 0x37f, "SPR_ITLBMR way 1 set %i", spr_itlbmr },
|
/* 300-37f */ { 0x300, 0x37f, "SPR_ITLBMR way 1 set %i", spr_itlbmr },
|
/* 380-3ff */ { 0x380, 0x3ff, "SPR_ITLBTR way 1 set %i", spr_itlbtr },
|
/* 380-3ff */ { 0x380, 0x3ff, "SPR_ITLBTR way 1 set %i", spr_itlbtr },
|
/* 400-47f */ { 0x400, 0x47f, "SPR_ITLBMR way 2 set %i", spr_itlbmr },
|
/* 400-47f */ { 0x400, 0x47f, "SPR_ITLBMR way 2 set %i", spr_itlbmr },
|
/* 480-4ff */ { 0x480, 0x4ff, "SPR_ITLBTR way 2 set %i", spr_itlbtr },
|
/* 480-4ff */ { 0x480, 0x4ff, "SPR_ITLBTR way 2 set %i", spr_itlbtr },
|
/* 500-57f */ { 0x500, 0x57f, "SPR_ITLBMR way 3 set %i", spr_itlbmr },
|
/* 500-57f */ { 0x500, 0x57f, "SPR_ITLBMR way 3 set %i", spr_itlbmr },
|
/* 580-5ff */ { 0x580, 0x5ff, "SPR_ITLBTR way 3 set %i", spr_itlbtr },
|
/* 580-5ff */ { 0x580, 0x5ff, "SPR_ITLBTR way 3 set %i", spr_itlbtr },
|
/* ------- */ { -1, -1, NULL, NULL } };
|
/* ------- */ { -1, -1, NULL, NULL } };
|
|
|
/*-----------------------------------------------------[ Data cache group ]---*/
|
/*-----------------------------------------------------[ Data cache group ]---*/
|
static const struct spr_bit_def spr_dccr[] = {
|
static const struct spr_bit_def spr_dccr[] = {
|
{ "DCCR_EW", SPR_DCCR_EW },
|
{ "DCCR_EW", SPR_DCCR_EW },
|
{ NULL, 0 } };
|
{ NULL, 0 } };
|
|
|
static const struct spr_def spr_dc_group[] = {
|
static const struct spr_def spr_dc_group[] = {
|
/* 000-000 */ { 0x000, 0x000, "SPR_DCCR", spr_dccr },
|
/* 000-000 */ { 0x000, 0x000, "SPR_DCCR", spr_dccr },
|
/* 001-001 */ { 0x001, 0x001, "SPR_DCBPR", spr_one_val },
|
/* 001-001 */ { 0x001, 0x001, "SPR_DCBPR", spr_one_val },
|
/* 002-002 */ { 0x002, 0x002, "SPR_DCBFR", spr_one_val },
|
/* 002-002 */ { 0x002, 0x002, "SPR_DCBFR", spr_one_val },
|
/* 003-003 */ { 0x003, 0x003, "SPR_DCBIR", spr_one_val },
|
/* 003-003 */ { 0x003, 0x003, "SPR_DCBIR", spr_one_val },
|
/* 004-004 */ { 0x004, 0x004, "SPR_DCBWR", spr_one_val },
|
/* 004-004 */ { 0x004, 0x004, "SPR_DCBWR", spr_one_val },
|
/* 005-005 */ { 0x005, 0x005, "SPR_DCBLR", spr_one_val },
|
/* 005-005 */ { 0x005, 0x005, "SPR_DCBLR", spr_one_val },
|
/* 200-3ff */ { 0x200, 0x3ff, "SPR_DCR way 0 set %i", spr_one_val },
|
/* 200-3ff */ { 0x200, 0x3ff, "SPR_DCR way 0 set %i", spr_one_val },
|
/* 400-5ff */ { 0x400, 0x5ff, "SPR_DCR way 1 set %i", spr_one_val },
|
/* 400-5ff */ { 0x400, 0x5ff, "SPR_DCR way 1 set %i", spr_one_val },
|
/* 600-7ff */ { 0x600, 0x7ff, "SPR_DCR way 2 set %i", spr_one_val },
|
/* 600-7ff */ { 0x600, 0x7ff, "SPR_DCR way 2 set %i", spr_one_val },
|
/* 800-9ff */ { 0x800, 0x9ff, "SPR_DCR way 3 set %i", spr_one_val },
|
/* 800-9ff */ { 0x800, 0x9ff, "SPR_DCR way 3 set %i", spr_one_val },
|
/* ------- */ { -1, -1, NULL, NULL } };
|
/* ------- */ { -1, -1, NULL, NULL } };
|
|
|
/*----------------------------------------------[ Instruction cache group ]---*/
|
/*----------------------------------------------[ Instruction cache group ]---*/
|
static const struct spr_bit_def spr_iccr[] = {
|
static const struct spr_bit_def spr_iccr[] = {
|
{ "ICCR_EW", SPR_ICCR_EW },
|
{ "ICCR_EW", SPR_ICCR_EW },
|
{ NULL, 0 } };
|
{ NULL, 0 } };
|
|
|
static const struct spr_def spr_ic_group[] = {
|
static const struct spr_def spr_ic_group[] = {
|
/* 000-000 */ { 0x000, 0x000, "SPR_ICCR", spr_iccr },
|
/* 000-000 */ { 0x000, 0x000, "SPR_ICCR", spr_iccr },
|
/* 001-001 */ { 0x001, 0x001, "SPR_ICBPR", spr_one_val },
|
/* 001-001 */ { 0x001, 0x001, "SPR_ICBPR", spr_one_val },
|
/* 002-002 */ { 0x002, 0x002, "SPR_ICBFR", spr_one_val },
|
/* 002-002 */ { 0x002, 0x002, "SPR_ICBFR", spr_one_val },
|
/* 003-003 */ { 0x003, 0x003, "SPR_ICBIR", spr_one_val },
|
/* 003-003 */ { 0x003, 0x003, "SPR_ICBIR", spr_one_val },
|
/* 200-3ff */ { 0x200, 0x3ff, "SPR_ICR way 0 set %i", spr_one_val },
|
/* 200-3ff */ { 0x200, 0x3ff, "SPR_ICR way 0 set %i", spr_one_val },
|
/* 400-5ff */ { 0x400, 0x5ff, "SPR_ICR way 1 set %i", spr_one_val },
|
/* 400-5ff */ { 0x400, 0x5ff, "SPR_ICR way 1 set %i", spr_one_val },
|
/* 600-7ff */ { 0x600, 0x7ff, "SPR_ICR way 2 set %i", spr_one_val },
|
/* 600-7ff */ { 0x600, 0x7ff, "SPR_ICR way 2 set %i", spr_one_val },
|
/* 800-9ff */ { 0x800, 0x9ff, "SPR_ICR way 3 set %i", spr_one_val },
|
/* 800-9ff */ { 0x800, 0x9ff, "SPR_ICR way 3 set %i", spr_one_val },
|
/* ------- */ { -1, -1, NULL, NULL } };
|
/* ------- */ { -1, -1, NULL, NULL } };
|
|
|
/*------------------------------------------------------------[ MAC group ]---*/
|
/*------------------------------------------------------------[ MAC group ]---*/
|
static const struct spr_def spr_mac_group[] = {
|
static const struct spr_def spr_mac_group[] = {
|
/* 1-1 */ { 0x1, 0x1, "SPR_MACLO", spr_one_val },
|
/* 1-1 */ { 0x1, 0x1, "SPR_MACLO", spr_one_val },
|
/* 2-2 */ { 0x2, 0x2, "SPR_MACHI", spr_one_val },
|
/* 2-2 */ { 0x2, 0x2, "SPR_MACHI", spr_one_val },
|
/* ------- */ { -1, -1, NULL, NULL } };
|
/* ------- */ { -1, -1, NULL, NULL } };
|
|
|
/*----------------------------------------------------------[ Debug group ]---*/
|
/*----------------------------------------------------------[ Debug group ]---*/
|
/* dmr1 register */
|
/* dmr1 register */
|
static const struct spr_bit_def spr_dmr1[] = {
|
static const struct spr_bit_def spr_dmr1[] = {
|
{ "DMR1_CW0", SPR_DMR1_CW0 },
|
{ "DMR1_CW0", SPR_DMR1_CW0 },
|
{ "DMR1_CW1", SPR_DMR1_CW1 },
|
{ "DMR1_CW1", SPR_DMR1_CW1 },
|
{ "DMR1_CW2", SPR_DMR1_CW2 },
|
{ "DMR1_CW2", SPR_DMR1_CW2 },
|
{ "DMR1_CW3", SPR_DMR1_CW3 },
|
{ "DMR1_CW3", SPR_DMR1_CW3 },
|
{ "DMR1_CW4", SPR_DMR1_CW4 },
|
{ "DMR1_CW4", SPR_DMR1_CW4 },
|
{ "DMR1_CW5", SPR_DMR1_CW5 },
|
{ "DMR1_CW5", SPR_DMR1_CW5 },
|
{ "DMR1_CW6", SPR_DMR1_CW6 },
|
{ "DMR1_CW6", SPR_DMR1_CW6 },
|
{ "DMR1_CW7", SPR_DMR1_CW7 },
|
{ "DMR1_CW7", SPR_DMR1_CW7 },
|
{ "DMR1_CW8", SPR_DMR1_CW8 },
|
{ "DMR1_CW8", SPR_DMR1_CW8 },
|
{ "DMR1_CW9", SPR_DMR1_CW9 },
|
{ "DMR1_CW9", SPR_DMR1_CW9 },
|
{ "DMR1_RES1", SPR_DMR1_RES1 },
|
{ "DMR1_RES1", SPR_DMR1_RES1 },
|
{ "DMR1_ST", SPR_DMR1_ST },
|
{ "DMR1_ST", SPR_DMR1_ST },
|
{ "DMR1_BT", SPR_DMR1_BT },
|
{ "DMR1_BT", SPR_DMR1_BT },
|
{ "DMR1_RES2", SPR_DMR1_RES2 },
|
{ "DMR1_RES2", SPR_DMR1_RES2 },
|
{ NULL, 0 } };
|
{ NULL, 0 } };
|
|
|
/* dmr2 register */
|
/* dmr2 register */
|
static const struct spr_bit_def spr_dmr2[] = {
|
static const struct spr_bit_def spr_dmr2[] = {
|
{ "DMR2_WCE0", SPR_DMR2_WCE0 },
|
{ "DMR2_WCE0", SPR_DMR2_WCE0 },
|
{ "DMR2_WCE1", SPR_DMR2_WCE1 },
|
{ "DMR2_WCE1", SPR_DMR2_WCE1 },
|
{ "DMR2_AWTC", SPR_DMR2_AWTC },
|
{ "DMR2_AWTC", SPR_DMR2_AWTC },
|
{ "DMR2_WGB", SPR_DMR2_WGB },
|
{ "DMR2_WGB", SPR_DMR2_WGB },
|
{ "DMR2_WBS", SPR_DMR2_WBS }, /* JPB */
|
{ "DMR2_WBS", SPR_DMR2_WBS }, /* JPB */
|
{ NULL, 0 } };
|
{ NULL, 0 } };
|
|
|
/* dwcr register */
|
/* dwcr register */
|
static const struct spr_bit_def spr_dwcr[] = {
|
static const struct spr_bit_def spr_dwcr[] = {
|
{ "DWCR_COUNT", SPR_DWCR_COUNT },
|
{ "DWCR_COUNT", SPR_DWCR_COUNT },
|
{ "DWCR_MATCH", SPR_DWCR_MATCH },
|
{ "DWCR_MATCH", SPR_DWCR_MATCH },
|
{ NULL, 0 } };
|
{ NULL, 0 } };
|
|
|
/* dsr register */
|
/* dsr register */
|
static const struct spr_bit_def spr_dsr[] = {
|
static const struct spr_bit_def spr_dsr[] = {
|
{ "DSR_RSTE", SPR_DSR_RSTE },
|
{ "DSR_RSTE", SPR_DSR_RSTE },
|
{ "DSR_BUSE", SPR_DSR_BUSEE },
|
{ "DSR_BUSE", SPR_DSR_BUSEE },
|
{ "DSR_DPFE", SPR_DSR_DPFE },
|
{ "DSR_DPFE", SPR_DSR_DPFE },
|
{ "DSR_IPFE", SPR_DSR_IPFE },
|
{ "DSR_IPFE", SPR_DSR_IPFE },
|
{ "DSR_TTE", SPR_DSR_TTE },
|
{ "DSR_TTE", SPR_DSR_TTE },
|
{ "DSR_AE", SPR_DSR_AE },
|
{ "DSR_AE", SPR_DSR_AE },
|
{ "DSR_IIE", SPR_DSR_IIE },
|
{ "DSR_IIE", SPR_DSR_IIE },
|
{ "DSR_IE", SPR_DSR_IE },
|
{ "DSR_IE", SPR_DSR_IE },
|
{ "DSR_DME", SPR_DSR_DME },
|
{ "DSR_DME", SPR_DSR_DME },
|
{ "DSR_IME", SPR_DSR_IME },
|
{ "DSR_IME", SPR_DSR_IME },
|
{ "DSR_RE", SPR_DSR_RE },
|
{ "DSR_RE", SPR_DSR_RE },
|
{ "DSR_SCE", SPR_DSR_SCE },
|
{ "DSR_SCE", SPR_DSR_SCE },
|
{ "DSR_FPE", SPR_DSR_FPE },
|
{ "DSR_FPE", SPR_DSR_FPE },
|
{ "DSR_TE", SPR_DSR_TE },
|
{ "DSR_TE", SPR_DSR_TE },
|
{ NULL, 0 } };
|
{ NULL, 0 } };
|
|
|
/* drr register */
|
/* drr register */
|
static const struct spr_bit_def spr_drr[] = {
|
static const struct spr_bit_def spr_drr[] = {
|
{ "DRR_RSTE", SPR_DRR_RSTE },
|
{ "DRR_RSTE", SPR_DRR_RSTE },
|
{ "DRR_BUSE", SPR_DRR_BUSEE },
|
{ "DRR_BUSE", SPR_DRR_BUSEE },
|
{ "DRR_DPFE", SPR_DRR_DPFE },
|
{ "DRR_DPFE", SPR_DRR_DPFE },
|
{ "DRR_IPFE", SPR_DRR_IPFE },
|
{ "DRR_IPFE", SPR_DRR_IPFE },
|
{ "DRR_TTE", SPR_DRR_TTE },
|
{ "DRR_TTE", SPR_DRR_TTE },
|
{ "DRR_AE", SPR_DRR_AE },
|
{ "DRR_AE", SPR_DRR_AE },
|
{ "DRR_IIE", SPR_DRR_IIE },
|
{ "DRR_IIE", SPR_DRR_IIE },
|
{ "DRR_IE", SPR_DRR_IE },
|
{ "DRR_IE", SPR_DRR_IE },
|
{ "DRR_DME", SPR_DRR_DME },
|
{ "DRR_DME", SPR_DRR_DME },
|
{ "DRR_IME", SPR_DRR_IME },
|
{ "DRR_IME", SPR_DRR_IME },
|
{ "DRR_RE", SPR_DRR_RE },
|
{ "DRR_RE", SPR_DRR_RE },
|
{ "DRR_SCE", SPR_DRR_SCE },
|
{ "DRR_SCE", SPR_DRR_SCE },
|
{ "DRR_TE", SPR_DRR_TE },
|
{ "DRR_TE", SPR_DRR_TE },
|
{ NULL, 0 } };
|
{ NULL, 0 } };
|
|
|
/* Debug group */
|
/* Debug group */
|
static const struct spr_def spr_d_group[] = {
|
static const struct spr_def spr_d_group[] = {
|
#if 0
|
#if 0
|
/* 00-07 */ { 0x00, 0x07, "SPR_DVR(%i)", spr_dvr },
|
/* 00-07 */ { 0x00, 0x07, "SPR_DVR(%i)", spr_dvr },
|
/* 08-0f */ { 0x08, 0x0f, "SPR_DCR(%i)", spr_dcr },
|
/* 08-0f */ { 0x08, 0x0f, "SPR_DCR(%i)", spr_dcr },
|
#endif
|
#endif
|
/* 10-10 */ { 0x10, 0x10, "SPR_DMR1", spr_dmr1 },
|
/* 10-10 */ { 0x10, 0x10, "SPR_DMR1", spr_dmr1 },
|
/* 11-11 */ { 0x11, 0x11, "SPR_DMR2", spr_dmr2 },
|
/* 11-11 */ { 0x11, 0x11, "SPR_DMR2", spr_dmr2 },
|
/* 12-12 */ { 0x12, 0x12, "SPR_DWCR0", spr_dwcr },
|
/* 12-12 */ { 0x12, 0x12, "SPR_DWCR0", spr_dwcr },
|
/* 13-13 */ { 0x13, 0x13, "SPR_DWCR1", spr_dwcr },
|
/* 13-13 */ { 0x13, 0x13, "SPR_DWCR1", spr_dwcr },
|
/* 14-14 */ { 0x14, 0x14, "SPR_DSR", spr_dsr },
|
/* 14-14 */ { 0x14, 0x14, "SPR_DSR", spr_dsr },
|
/* 15-15 */ { 0x15, 0x15, "SPR_DRR", spr_drr },
|
/* 15-15 */ { 0x15, 0x15, "SPR_DRR", spr_drr },
|
/* ----- */ { -1, -1, NULL, NULL } };
|
/* ----- */ { -1, -1, NULL, NULL } };
|
|
|
/*-------------------------------------------[ Performance counters group ]---*/
|
/*-------------------------------------------[ Performance counters group ]---*/
|
static const struct spr_bit_def spr_pcmr[] = {
|
static const struct spr_bit_def spr_pcmr[] = {
|
{ "PCMR_CP", SPR_PCMR_CP },
|
{ "PCMR_CP", SPR_PCMR_CP },
|
{ "PCMR_UMRA", SPR_PCMR_UMRA },
|
{ "PCMR_UMRA", SPR_PCMR_UMRA },
|
{ "PCMR_CISM", SPR_PCMR_CISM },
|
{ "PCMR_CISM", SPR_PCMR_CISM },
|
{ "PCMR_CIUM", SPR_PCMR_CIUM },
|
{ "PCMR_CIUM", SPR_PCMR_CIUM },
|
{ "PCMR_LA", SPR_PCMR_LA },
|
{ "PCMR_LA", SPR_PCMR_LA },
|
{ "PCMR_SA", SPR_PCMR_SA },
|
{ "PCMR_SA", SPR_PCMR_SA },
|
{ "PCMR_IF", SPR_PCMR_IF },
|
{ "PCMR_IF", SPR_PCMR_IF },
|
{ "PCMR_DCM", SPR_PCMR_DCM },
|
{ "PCMR_DCM", SPR_PCMR_DCM },
|
{ "PCMR_ICM", SPR_PCMR_ICM },
|
{ "PCMR_ICM", SPR_PCMR_ICM },
|
{ "PCMR_IFS", SPR_PCMR_IFS },
|
{ "PCMR_IFS", SPR_PCMR_IFS },
|
{ "PCMR_LSUS", SPR_PCMR_LSUS },
|
{ "PCMR_LSUS", SPR_PCMR_LSUS },
|
{ "PCMR_BS", SPR_PCMR_BS },
|
{ "PCMR_BS", SPR_PCMR_BS },
|
{ "PCMR_DTLBM", SPR_PCMR_DTLBM },
|
{ "PCMR_DTLBM", SPR_PCMR_DTLBM },
|
{ "PCMR_ITLBM", SPR_PCMR_ITLBM },
|
{ "PCMR_ITLBM", SPR_PCMR_ITLBM },
|
{ "PCMR_DDS", SPR_PCMR_DDS },
|
{ "PCMR_DDS", SPR_PCMR_DDS },
|
{ "PCMR_WPE", SPR_PCMR_WPE },
|
{ "PCMR_WPE", SPR_PCMR_WPE },
|
{ NULL, 0 } };
|
{ NULL, 0 } };
|
|
|
static const struct spr_def spr_pc_group[] = {
|
static const struct spr_def spr_pc_group[] = {
|
/* 00-07 */ { 0x00, 0x07, "PCCR", spr_one_val },
|
/* 00-07 */ { 0x00, 0x07, "PCCR", spr_one_val },
|
/* 08-0f */ { 0x08, 0x0f, "PCMR", spr_pcmr },
|
/* 08-0f */ { 0x08, 0x0f, "PCMR", spr_pcmr },
|
/* ----- */ { -1, -1, NULL, NULL } };
|
/* ----- */ { -1, -1, NULL, NULL } };
|
|
|
/*------------------------------------------------[ Power managment group ]---*/
|
/*------------------------------------------------[ Power managment group ]---*/
|
static const struct spr_bit_def spr_pmr[] = {
|
static const struct spr_bit_def spr_pmr[] = {
|
{ "PMR_SDF", SPR_PMR_SDF },
|
{ "PMR_SDF", SPR_PMR_SDF },
|
{ "PMR_DME", SPR_PMR_DME },
|
{ "PMR_DME", SPR_PMR_DME },
|
{ "PMR_SME", SPR_PMR_SME },
|
{ "PMR_SME", SPR_PMR_SME },
|
{ "PMR_DCGE", SPR_PMR_DCGE },
|
{ "PMR_DCGE", SPR_PMR_DCGE },
|
{ "PMR_SUME", SPR_PMR_SUME },
|
{ "PMR_SUME", SPR_PMR_SUME },
|
{ NULL, 0 } };
|
{ NULL, 0 } };
|
|
|
static const struct spr_def spr_pm_group[] = {
|
static const struct spr_def spr_pm_group[] = {
|
/* 0-0 */ { 0x0, 0x0, "SPR_PMR", spr_pmr },
|
/* 0-0 */ { 0x0, 0x0, "SPR_PMR", spr_pmr },
|
/* --- */ { -1, -1, NULL, NULL } };
|
/* --- */ { -1, -1, NULL, NULL } };
|
|
|
/*------------------------------------------------------------[ PIC group ]---*/
|
/*------------------------------------------------------------[ PIC group ]---*/
|
/* picmr register */
|
/* picmr register */
|
static const struct spr_bit_def spr_picmr[] = {
|
static const struct spr_bit_def spr_picmr[] = {
|
{ "PICMR_IUM", SPR_PICMR_IUM },
|
{ "PICMR_IUM", SPR_PICMR_IUM },
|
{ NULL, 0 } };
|
{ NULL, 0 } };
|
|
|
static const struct spr_def spr_pic_group[] = {
|
static const struct spr_def spr_pic_group[] = {
|
/* 0-0 */ { 0, 0, "PICMR", spr_picmr },
|
/* 0-0 */ { 0, 0, "PICMR", spr_picmr },
|
/* 2-2 */ { 2, 2, "PICSR", spr_one_val },
|
/* 2-2 */ { 2, 2, "PICSR", spr_one_val },
|
/* --- */ { -1, -1, NULL, NULL } };
|
/* --- */ { -1, -1, NULL, NULL } };
|
|
|
/*-----------------------------------------------------[ Tick timer group ]---*/
|
/*-----------------------------------------------------[ Tick timer group ]---*/
|
static const struct spr_bit_def spr_ttmr[] = {
|
static const struct spr_bit_def spr_ttmr[] = {
|
{ "TTMR_PERIOD", SPR_TTMR_PERIOD },
|
{ "TTMR_TP", SPR_TTMR_TP },
|
{ "TTMR_IP", SPR_TTMR_IP },
|
{ "TTMR_IP", SPR_TTMR_IP },
|
{ "TTMR_IE", SPR_TTMR_IE },
|
{ "TTMR_IE", SPR_TTMR_IE },
|
{ "TTMR_M", SPR_TTMR_M },
|
{ "TTMR_M", SPR_TTMR_M },
|
{ NULL, 0 } };
|
{ NULL, 0 } };
|
|
|
static const struct spr_def spr_tt_group[] = {
|
static const struct spr_def spr_tt_group[] = {
|
/* 0-0 */ { 0, 0, "TTMR", spr_ttmr },
|
/* 0-0 */ { 0, 0, "TTMR", spr_ttmr },
|
/* 1-1 */ { 0, 0, "TTCR", spr_one_val },
|
/* 1-1 */ { 0, 0, "TTCR", spr_one_val },
|
/* --- */ { -1, -1, NULL, NULL } };
|
/* --- */ { -1, -1, NULL, NULL } };
|
|
|
/* Spr groups */
|
/* Spr groups */
|
static const struct spr_def *spr_groups[] = {
|
static const struct spr_def *spr_groups[] = {
|
/* 00 */ spr_sys_group,
|
/* 00 */ spr_sys_group,
|
/* 01 */ spr_dmmu_group,
|
/* 01 */ spr_dmmu_group,
|
/* 02 */ spr_immu_group,
|
/* 02 */ spr_immu_group,
|
/* 03 */ spr_dc_group,
|
/* 03 */ spr_dc_group,
|
/* 04 */ spr_ic_group,
|
/* 04 */ spr_ic_group,
|
/* 05 */ spr_mac_group,
|
/* 05 */ spr_mac_group,
|
/* 06 */ spr_d_group,
|
/* 06 */ spr_d_group,
|
/* 07 */ spr_pc_group,
|
/* 07 */ spr_pc_group,
|
/* 08 */ spr_pm_group,
|
/* 08 */ spr_pm_group,
|
/* 09 */ spr_pic_group,
|
/* 09 */ spr_pic_group,
|
/* 0a */ spr_tt_group };
|
/* 0a */ spr_tt_group };
|
|
|
/* Should be long enough for everything */
|
/* Should be long enough for everything */
|
static char ret_spr[1000];
|
static char ret_spr[1000];
|
|
|
/* Dumps the given spr in nice, human readable form */
|
/* Dumps the given spr in nice, human readable form */
|
char *dump_spr(uint16_t spr, uorreg_t spr_val)
|
char *dump_spr(uint16_t spr, uorreg_t spr_val)
|
{
|
{
|
const struct spr_def *spr_def;
|
const struct spr_def *spr_def;
|
uint16_t spr_in_group = spr & (MAX_SPRS_PER_GRP - 1);
|
uint16_t spr_in_group = spr & (MAX_SPRS_PER_GRP - 1);
|
uint16_t spr_group = spr >> MAX_SPRS_PER_GRP_BITS;
|
uint16_t spr_group = spr >> MAX_SPRS_PER_GRP_BITS;
|
const struct spr_bit_def *spr_bit_def;
|
const struct spr_bit_def *spr_bit_def;
|
|
|
int first_bit = 1;
|
int first_bit = 1;
|
int i;
|
int i;
|
uorreg_t tmp;
|
uorreg_t tmp;
|
|
|
spr_def = spr_groups[spr_group];
|
spr_def = spr_groups[spr_group];
|
|
|
/* Find the given spr */
|
/* Find the given spr */
|
for(; spr_def->from_spr != 0xffff; spr_def++) {
|
for(; spr_def->from_spr != 0xffff; spr_def++) {
|
if((spr_def->from_spr <= spr_in_group) && (spr_def->to_spr >= spr_in_group))
|
if((spr_def->from_spr <= spr_in_group) && (spr_def->to_spr >= spr_in_group))
|
break;
|
break;
|
}
|
}
|
|
|
if(spr_def->from_spr == 0xffff) {
|
if(spr_def->from_spr == 0xffff) {
|
sprintf(ret_spr, "Spr %"PRIx16", group %"PRIx16" = 0x%"PRIxREG"\n",
|
sprintf(ret_spr, "Spr %"PRIx16", group %"PRIx16" = 0x%"PRIxREG"\n",
|
spr_in_group, spr_group, spr_val);
|
spr_in_group, spr_group, spr_val);
|
return ret_spr;
|
return ret_spr;
|
}
|
}
|
|
|
/* Decode the spr bits and show them in a pretty format */
|
/* Decode the spr bits and show them in a pretty format */
|
if(spr_def->from_spr == spr_def->to_spr)
|
if(spr_def->from_spr == spr_def->to_spr)
|
sprintf(ret_spr, "%s", spr_def->name);
|
sprintf(ret_spr, "%s", spr_def->name);
|
else
|
else
|
sprintf(ret_spr, spr_def->name, spr_in_group - spr_def->from_spr);
|
sprintf(ret_spr, spr_def->name, spr_in_group - spr_def->from_spr);
|
strcat(ret_spr, " = ");
|
strcat(ret_spr, " = ");
|
|
|
/* First get all the single-bit bit fields and dump them */
|
/* First get all the single-bit bit fields and dump them */
|
for(spr_bit_def = spr_def->bits; spr_bit_def->name; spr_bit_def++) {
|
for(spr_bit_def = spr_def->bits; spr_bit_def->name; spr_bit_def++) {
|
if(!is_power2(spr_bit_def->mask))
|
if(!is_power2(spr_bit_def->mask))
|
continue;
|
continue;
|
|
|
if(!(spr_bit_def->mask & spr_val))
|
if(!(spr_bit_def->mask & spr_val))
|
continue;
|
continue;
|
|
|
if(!first_bit)
|
if(!first_bit)
|
strcat(ret_spr, " | ");
|
strcat(ret_spr, " | ");
|
else
|
else
|
first_bit = 0;
|
first_bit = 0;
|
strcat(ret_spr, spr_bit_def->name);
|
strcat(ret_spr, spr_bit_def->name);
|
}
|
}
|
|
|
/* Now dump all the multi-bit bit fields */
|
/* Now dump all the multi-bit bit fields */
|
for(spr_bit_def = spr_def->bits; spr_bit_def->name; spr_bit_def++) {
|
for(spr_bit_def = spr_def->bits; spr_bit_def->name; spr_bit_def++) {
|
if(is_power2(spr_bit_def->mask))
|
if(is_power2(spr_bit_def->mask))
|
continue;
|
continue;
|
if(!first_bit)
|
if(!first_bit)
|
strcat(ret_spr, " | ");
|
strcat(ret_spr, " | ");
|
else
|
else
|
first_bit = 0;
|
first_bit = 0;
|
for(tmp = spr_bit_def->mask, i = 0; !(tmp & 1); i++)
|
for(tmp = spr_bit_def->mask, i = 0; !(tmp & 1); i++)
|
tmp >>= 1;
|
tmp >>= 1;
|
|
|
sprintf(ret_spr, "%s%s = %" PRIxREG, ret_spr, spr_bit_def->name,
|
sprintf(ret_spr, "%s%s = %" PRIxREG, ret_spr, spr_bit_def->name,
|
(spr_val >> i) & tmp);
|
(spr_val >> i) & tmp);
|
}
|
}
|
return ret_spr;
|
return ret_spr;
|
}
|
}
|
|
|
|
|
