/* insnset.c -- Instruction specific functions.
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/* insnset.c -- Instruction specific functions.
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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2000-2002 Marko Mlinar, markom@opencores.org
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2000-2002 Marko Mlinar, markom@opencores.org
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Copyright (C) 2008 Embecosm Limited
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Copyright (C) 2008 Embecosm Limited
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Copyright (C) 2009 Jungsook yang, jungsook.yang@uci.edu
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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Contributor Julius Baxter julius@orsoc.se
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify it
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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more details.
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You should have received a copy of the GNU General Public License along
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You should have received a copy of the GNU General Public License along
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* This program is commented throughout in a fashion suitable for processing
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/* This program is commented throughout in a fashion suitable for processing
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with Doxygen. */
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with Doxygen. */
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INSTRUCTION (l_add) {
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INSTRUCTION (l_add) {
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orreg_t temp1, temp2, temp3;
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orreg_t temp1, temp2, temp3;
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int8_t temp4;
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int8_t temp4;
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temp2 = (orreg_t)PARAM2;
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temp2 = (orreg_t)PARAM2;
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temp3 = (orreg_t)PARAM1;
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temp3 = (orreg_t)PARAM1;
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temp1 = temp2 + temp3;
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temp1 = temp2 + temp3;
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SET_PARAM0(temp1);
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SET_PARAM0(temp1);
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SET_OV_FLAG_FN (temp1);
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SET_OV_FLAG_FN (temp1);
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if (ARITH_SET_FLAG) {
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if (ARITH_SET_FLAG) {
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if(!temp1)
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if(!temp1)
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cpu_state.sprs[SPR_SR] |= SPR_SR_F;
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cpu_state.sprs[SPR_SR] |= SPR_SR_F;
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else
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else
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cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
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cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
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}
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}
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if ((uorreg_t) temp1 < (uorreg_t) temp2)
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if ((uorreg_t) temp1 < (uorreg_t) temp2)
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cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
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cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
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else
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else
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cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
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cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
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temp4 = temp1;
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temp4 = temp1;
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if (temp4 == temp1)
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if (temp4 == temp1)
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or1k_mstats.byteadd++;
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or1k_mstats.byteadd++;
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}
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}
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INSTRUCTION (l_addc) {
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INSTRUCTION (l_addc) {
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orreg_t temp1, temp2, temp3;
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orreg_t temp1, temp2, temp3;
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int8_t temp4;
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int8_t temp4;
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temp2 = (orreg_t)PARAM2;
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temp2 = (orreg_t)PARAM2;
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temp3 = (orreg_t)PARAM1;
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temp3 = (orreg_t)PARAM1;
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temp1 = temp2 + temp3;
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temp1 = temp2 + temp3;
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if(cpu_state.sprs[SPR_SR] & SPR_SR_CY)
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if(cpu_state.sprs[SPR_SR] & SPR_SR_CY)
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temp1++;
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temp1++;
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SET_PARAM0(temp1);
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SET_PARAM0(temp1);
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SET_OV_FLAG_FN (temp1);
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SET_OV_FLAG_FN (temp1);
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if (ARITH_SET_FLAG) {
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if (ARITH_SET_FLAG) {
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if(!temp1)
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if(!temp1)
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cpu_state.sprs[SPR_SR] |= SPR_SR_F;
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cpu_state.sprs[SPR_SR] |= SPR_SR_F;
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else
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else
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cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
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cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
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}
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}
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if ((uorreg_t) temp1 < (uorreg_t) temp2)
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if ((uorreg_t) temp1 < (uorreg_t) temp2)
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cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
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cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
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else
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else
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cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
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cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
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temp4 = temp1;
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temp4 = temp1;
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if (temp4 == temp1)
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if (temp4 == temp1)
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or1k_mstats.byteadd++;
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or1k_mstats.byteadd++;
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}
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}
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INSTRUCTION (l_sw) {
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INSTRUCTION (l_sw) {
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int old_cyc = 0;
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int old_cyc = 0;
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if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
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if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
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set_mem32(PARAM0, PARAM1, &breakpoint);
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set_mem32(PARAM0, PARAM1, &breakpoint);
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if (config.cpu.sbuf_len) {
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if (config.cpu.sbuf_len) {
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int t = runtime.sim.mem_cycles;
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int t = runtime.sim.mem_cycles;
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runtime.sim.mem_cycles = old_cyc;
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runtime.sim.mem_cycles = old_cyc;
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sbuf_store (t - old_cyc);
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sbuf_store (t - old_cyc);
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}
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}
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}
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}
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INSTRUCTION (l_sb) {
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INSTRUCTION (l_sb) {
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int old_cyc = 0;
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int old_cyc = 0;
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if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
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if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
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set_mem8(PARAM0, PARAM1, &breakpoint);
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set_mem8(PARAM0, PARAM1, &breakpoint);
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if (config.cpu.sbuf_len) {
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if (config.cpu.sbuf_len) {
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int t = runtime.sim.mem_cycles;
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int t = runtime.sim.mem_cycles;
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runtime.sim.mem_cycles = old_cyc;
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runtime.sim.mem_cycles = old_cyc;
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sbuf_store (t- old_cyc);
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sbuf_store (t- old_cyc);
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}
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}
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}
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}
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INSTRUCTION (l_sh) {
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INSTRUCTION (l_sh) {
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int old_cyc = 0;
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int old_cyc = 0;
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if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
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if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
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set_mem16(PARAM0, PARAM1, &breakpoint);
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set_mem16(PARAM0, PARAM1, &breakpoint);
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if (config.cpu.sbuf_len) {
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if (config.cpu.sbuf_len) {
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int t = runtime.sim.mem_cycles;
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int t = runtime.sim.mem_cycles;
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runtime.sim.mem_cycles = old_cyc;
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runtime.sim.mem_cycles = old_cyc;
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sbuf_store (t - old_cyc);
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sbuf_store (t - old_cyc);
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}
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}
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}
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}
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INSTRUCTION (l_lwz) {
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INSTRUCTION (l_lwz) {
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uint32_t val;
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uint32_t val;
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if (config.cpu.sbuf_len) sbuf_load ();
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if (config.cpu.sbuf_len) sbuf_load ();
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val = eval_mem32(PARAM1, &breakpoint);
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val = eval_mem32(PARAM1, &breakpoint);
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/* If eval operand produced exception don't set anything. JPB changed to
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/* If eval operand produced exception don't set anything. JPB changed to
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trigger on breakpoint, as well as except_pending (seemed to be a bug). */
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trigger on breakpoint, as well as except_pending (seemed to be a bug). */
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if (!(except_pending || breakpoint))
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if (!(except_pending || breakpoint))
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SET_PARAM0(val);
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SET_PARAM0(val);
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}
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}
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INSTRUCTION (l_lbs) {
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INSTRUCTION (l_lbs) {
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int8_t val;
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int8_t val;
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if (config.cpu.sbuf_len) sbuf_load ();
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if (config.cpu.sbuf_len) sbuf_load ();
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val = eval_mem8(PARAM1, &breakpoint);
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val = eval_mem8(PARAM1, &breakpoint);
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/* If eval operand produced exception don't set anything. JPB changed to
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/* If eval operand produced exception don't set anything. JPB changed to
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trigger on breakpoint, as well as except_pending (seemed to be a bug). */
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trigger on breakpoint, as well as except_pending (seemed to be a bug). */
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if (!(except_pending || breakpoint))
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if (!(except_pending || breakpoint))
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SET_PARAM0(val);
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SET_PARAM0(val);
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}
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}
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INSTRUCTION (l_lbz) {
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INSTRUCTION (l_lbz) {
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uint8_t val;
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uint8_t val;
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if (config.cpu.sbuf_len) sbuf_load ();
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if (config.cpu.sbuf_len) sbuf_load ();
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val = eval_mem8(PARAM1, &breakpoint);
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val = eval_mem8(PARAM1, &breakpoint);
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/* If eval operand produced exception don't set anything. JPB changed to
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/* If eval operand produced exception don't set anything. JPB changed to
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trigger on breakpoint, as well as except_pending (seemed to be a bug). */
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trigger on breakpoint, as well as except_pending (seemed to be a bug). */
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if (!(except_pending || breakpoint))
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if (!(except_pending || breakpoint))
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SET_PARAM0(val);
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SET_PARAM0(val);
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}
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}
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INSTRUCTION (l_lhs) {
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INSTRUCTION (l_lhs) {
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int16_t val;
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int16_t val;
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if (config.cpu.sbuf_len) sbuf_load ();
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if (config.cpu.sbuf_len) sbuf_load ();
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val = eval_mem16(PARAM1, &breakpoint);
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val = eval_mem16(PARAM1, &breakpoint);
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/* If eval operand produced exception don't set anything. JPB changed to
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/* If eval operand produced exception don't set anything. JPB changed to
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trigger on breakpoint, as well as except_pending (seemed to be a bug). */
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trigger on breakpoint, as well as except_pending (seemed to be a bug). */
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if (!(except_pending || breakpoint))
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if (!(except_pending || breakpoint))
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SET_PARAM0(val);
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SET_PARAM0(val);
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}
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}
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INSTRUCTION (l_lhz) {
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INSTRUCTION (l_lhz) {
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uint16_t val;
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uint16_t val;
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if (config.cpu.sbuf_len) sbuf_load ();
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if (config.cpu.sbuf_len) sbuf_load ();
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val = eval_mem16(PARAM1, &breakpoint);
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val = eval_mem16(PARAM1, &breakpoint);
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/* If eval operand produced exception don't set anything. JPB changed to
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/* If eval operand produced exception don't set anything. JPB changed to
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trigger on breakpoint, as well as except_pending (seemed to be a bug). */
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trigger on breakpoint, as well as except_pending (seemed to be a bug). */
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if (!(except_pending || breakpoint))
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if (!(except_pending || breakpoint))
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SET_PARAM0(val);
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SET_PARAM0(val);
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}
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}
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INSTRUCTION (l_movhi) {
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INSTRUCTION (l_movhi) {
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SET_PARAM0(PARAM1 << 16);
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SET_PARAM0(PARAM1 << 16);
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}
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}
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INSTRUCTION (l_and) {
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INSTRUCTION (l_and) {
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uorreg_t temp1;
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uorreg_t temp1;
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temp1 = PARAM1 & PARAM2;
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temp1 = PARAM1 & PARAM2;
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SET_OV_FLAG_FN (temp1);
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SET_OV_FLAG_FN (temp1);
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SET_PARAM0(temp1);
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SET_PARAM0(temp1);
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if (ARITH_SET_FLAG) {
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if (ARITH_SET_FLAG) {
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if(!temp1)
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if(!temp1)
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cpu_state.sprs[SPR_SR] |= SPR_SR_F;
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cpu_state.sprs[SPR_SR] |= SPR_SR_F;
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else
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else
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cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
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cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
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}
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}
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}
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}
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INSTRUCTION (l_or) {
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INSTRUCTION (l_or) {
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uorreg_t temp1;
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uorreg_t temp1;
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temp1 = PARAM1 | PARAM2;
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temp1 = PARAM1 | PARAM2;
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SET_OV_FLAG_FN (temp1);
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SET_OV_FLAG_FN (temp1);
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SET_PARAM0(temp1);
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SET_PARAM0(temp1);
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}
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}
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INSTRUCTION (l_xor) {
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INSTRUCTION (l_xor) {
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uorreg_t temp1;
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uorreg_t temp1;
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temp1 = PARAM1 ^ PARAM2;
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temp1 = PARAM1 ^ PARAM2;
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SET_OV_FLAG_FN (temp1);
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SET_OV_FLAG_FN (temp1);
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SET_PARAM0(temp1);
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SET_PARAM0(temp1);
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}
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}
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INSTRUCTION (l_sub) {
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INSTRUCTION (l_sub) {
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orreg_t temp1;
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orreg_t temp1;
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temp1 = (orreg_t)PARAM1 - (orreg_t)PARAM2;
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temp1 = (orreg_t)PARAM1 - (orreg_t)PARAM2;
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SET_OV_FLAG_FN (temp1);
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SET_OV_FLAG_FN (temp1);
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SET_PARAM0(temp1);
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SET_PARAM0(temp1);
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}
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}
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/*int mcount = 0;*/
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/*int mcount = 0;*/
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INSTRUCTION (l_mul) {
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INSTRUCTION (l_mul) {
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orreg_t temp1;
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orreg_t temp1;
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temp1 = (orreg_t)PARAM1 * (orreg_t)PARAM2;
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temp1 = (orreg_t)PARAM1 * (orreg_t)PARAM2;
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SET_OV_FLAG_FN (temp1);
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SET_OV_FLAG_FN (temp1);
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SET_PARAM0(temp1);
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SET_PARAM0(temp1);
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/*if (!(mcount++ & 1023)) {
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/*if (!(mcount++ & 1023)) {
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PRINTF ("[%i]\n",mcount);
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PRINTF ("[%i]\n",mcount);
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}*/
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}*/
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}
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}
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INSTRUCTION (l_div) {
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INSTRUCTION (l_div) {
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orreg_t temp3, temp2, temp1;
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orreg_t temp3, temp2, temp1;
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temp3 = PARAM2;
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temp3 = PARAM2;
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temp2 = PARAM1;
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temp2 = PARAM1;
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if (temp3)
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if (temp3)
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temp1 = temp2 / temp3;
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temp1 = temp2 / temp3;
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else {
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else {
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except_handle(EXCEPT_ILLEGAL, cpu_state.pc);
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except_handle(EXCEPT_ILLEGAL, cpu_state.pc);
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return;
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return;
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}
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}
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SET_OV_FLAG_FN (temp1);
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SET_OV_FLAG_FN (temp1);
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SET_PARAM0(temp1);
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SET_PARAM0(temp1);
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}
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}
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INSTRUCTION (l_divu) {
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INSTRUCTION (l_divu) {
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uorreg_t temp3, temp2, temp1;
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uorreg_t temp3, temp2, temp1;
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temp3 = PARAM2;
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temp3 = PARAM2;
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temp2 = PARAM1;
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temp2 = PARAM1;
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if (temp3)
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if (temp3)
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temp1 = temp2 / temp3;
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temp1 = temp2 / temp3;
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else {
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else {
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except_handle(EXCEPT_ILLEGAL, cpu_state.pc);
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except_handle(EXCEPT_ILLEGAL, cpu_state.pc);
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return;
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return;
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}
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}
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SET_OV_FLAG_FN (temp1);
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SET_OV_FLAG_FN (temp1);
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SET_PARAM0(temp1);
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SET_PARAM0(temp1);
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/* runtime.sim.cycles += 16; */
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/* runtime.sim.cycles += 16; */
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}
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}
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INSTRUCTION (l_sll) {
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INSTRUCTION (l_sll) {
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uorreg_t temp1;
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uorreg_t temp1;
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temp1 = PARAM1 << PARAM2;
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temp1 = PARAM1 << PARAM2;
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SET_OV_FLAG_FN (temp1);
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SET_OV_FLAG_FN (temp1);
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SET_PARAM0(temp1);
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SET_PARAM0(temp1);
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/* runtime.sim.cycles += 2; */
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/* runtime.sim.cycles += 2; */
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}
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}
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INSTRUCTION (l_sra) {
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INSTRUCTION (l_sra) {
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orreg_t temp1;
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orreg_t temp1;
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temp1 = (orreg_t)PARAM1 >> PARAM2;
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temp1 = (orreg_t)PARAM1 >> PARAM2;
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SET_OV_FLAG_FN (temp1);
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SET_OV_FLAG_FN (temp1);
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SET_PARAM0(temp1);
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SET_PARAM0(temp1);
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/* runtime.sim.cycles += 2; */
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/* runtime.sim.cycles += 2; */
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}
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}
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INSTRUCTION (l_srl) {
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INSTRUCTION (l_srl) {
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uorreg_t temp1;
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uorreg_t temp1;
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temp1 = PARAM1 >> PARAM2;
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temp1 = PARAM1 >> PARAM2;
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SET_OV_FLAG_FN (temp1);
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SET_OV_FLAG_FN (temp1);
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SET_PARAM0(temp1);
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SET_PARAM0(temp1);
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/* runtime.sim.cycles += 2; */
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/* runtime.sim.cycles += 2; */
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}
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}
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INSTRUCTION (l_bf) {
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INSTRUCTION (l_bf) {
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if (config.bpb.enabled) {
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if (config.bpb.enabled) {
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int fwd = (PARAM0 >= cpu_state.pc) ? 1 : 0;
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int fwd = (PARAM0 >= cpu_state.pc) ? 1 : 0;
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or1k_mstats.bf[cpu_state.sprs[SPR_SR] & SPR_SR_F ? 1 : 0][fwd]++;
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or1k_mstats.bf[cpu_state.sprs[SPR_SR] & SPR_SR_F ? 1 : 0][fwd]++;
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bpb_update(current->insn_addr, cpu_state.sprs[SPR_SR] & SPR_SR_F ? 1 : 0);
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bpb_update(current->insn_addr, cpu_state.sprs[SPR_SR] & SPR_SR_F ? 1 : 0);
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}
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}
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if(cpu_state.sprs[SPR_SR] & SPR_SR_F) {
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if(cpu_state.sprs[SPR_SR] & SPR_SR_F) {
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cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
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cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
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btic_update(pcnext);
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btic_update(pcnext);
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next_delay_insn = 1;
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next_delay_insn = 1;
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} else {
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} else {
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btic_update(cpu_state.pc);
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btic_update(cpu_state.pc);
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}
|
}
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}
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}
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INSTRUCTION (l_bnf) {
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INSTRUCTION (l_bnf) {
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if (config.bpb.enabled) {
|
if (config.bpb.enabled) {
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int fwd = (PARAM0 >= cpu_state.pc) ? 1 : 0;
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int fwd = (PARAM0 >= cpu_state.pc) ? 1 : 0;
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or1k_mstats.bnf[cpu_state.sprs[SPR_SR] & SPR_SR_F ? 0 : 1][fwd]++;
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or1k_mstats.bnf[cpu_state.sprs[SPR_SR] & SPR_SR_F ? 0 : 1][fwd]++;
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bpb_update(current->insn_addr, cpu_state.sprs[SPR_SR] & SPR_SR_F ? 0 : 1);
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bpb_update(current->insn_addr, cpu_state.sprs[SPR_SR] & SPR_SR_F ? 0 : 1);
|
}
|
}
|
if (!(cpu_state.sprs[SPR_SR] & SPR_SR_F)) {
|
if (!(cpu_state.sprs[SPR_SR] & SPR_SR_F)) {
|
cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
|
cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
|
btic_update(pcnext);
|
btic_update(pcnext);
|
next_delay_insn = 1;
|
next_delay_insn = 1;
|
} else {
|
} else {
|
btic_update(cpu_state.pc);
|
btic_update(cpu_state.pc);
|
}
|
}
|
}
|
}
|
INSTRUCTION (l_j) {
|
INSTRUCTION (l_j) {
|
cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
|
cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
|
next_delay_insn = 1;
|
next_delay_insn = 1;
|
}
|
}
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INSTRUCTION (l_jal) {
|
INSTRUCTION (l_jal) {
|
cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
|
cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4;
|
|
|
setsim_reg(LINK_REGNO, cpu_state.pc + 8);
|
setsim_reg(LINK_REGNO, cpu_state.pc + 8);
|
next_delay_insn = 1;
|
next_delay_insn = 1;
|
if (config.sim.profile) {
|
if (config.sim.profile) {
|
struct label_entry *tmp;
|
struct label_entry *tmp;
|
if (verify_memoryarea(cpu_state.pc_delay) && (tmp = get_label (cpu_state.pc_delay)))
|
if (verify_memoryarea(cpu_state.pc_delay) && (tmp = get_label (cpu_state.pc_delay)))
|
fprintf (runtime.sim.fprof, "+%08llX %"PRIxADDR" %"PRIxADDR" %s\n",
|
fprintf (runtime.sim.fprof, "+%08llX %"PRIxADDR" %"PRIxADDR" %s\n",
|
runtime.sim.cycles, cpu_state.pc + 8, cpu_state.pc_delay,
|
runtime.sim.cycles, cpu_state.pc + 8, cpu_state.pc_delay,
|
tmp->name);
|
tmp->name);
|
else
|
else
|
fprintf (runtime.sim.fprof, "+%08llX %"PRIxADDR" %"PRIxADDR" @%"PRIxADDR"\n",
|
fprintf (runtime.sim.fprof, "+%08llX %"PRIxADDR" %"PRIxADDR" @%"PRIxADDR"\n",
|
runtime.sim.cycles, cpu_state.pc + 8, cpu_state.pc_delay,
|
runtime.sim.cycles, cpu_state.pc + 8, cpu_state.pc_delay,
|
cpu_state.pc_delay);
|
cpu_state.pc_delay);
|
}
|
}
|
}
|
}
|
INSTRUCTION (l_jalr) {
|
INSTRUCTION (l_jalr) {
|
cpu_state.pc_delay = PARAM0;
|
cpu_state.pc_delay = PARAM0;
|
setsim_reg(LINK_REGNO, cpu_state.pc + 8);
|
setsim_reg(LINK_REGNO, cpu_state.pc + 8);
|
next_delay_insn = 1;
|
next_delay_insn = 1;
|
}
|
}
|
INSTRUCTION (l_jr) {
|
INSTRUCTION (l_jr) {
|
cpu_state.pc_delay = PARAM0;
|
cpu_state.pc_delay = PARAM0;
|
next_delay_insn = 1;
|
next_delay_insn = 1;
|
if (config.sim.profile)
|
if (config.sim.profile)
|
fprintf (runtime.sim.fprof, "-%08llX %"PRIxADDR"\n", runtime.sim.cycles,
|
fprintf (runtime.sim.fprof, "-%08llX %"PRIxADDR"\n", runtime.sim.cycles,
|
cpu_state.pc_delay);
|
cpu_state.pc_delay);
|
}
|
}
|
INSTRUCTION (l_rfe) {
|
INSTRUCTION (l_rfe) {
|
pcnext = cpu_state.sprs[SPR_EPCR_BASE];
|
pcnext = cpu_state.sprs[SPR_EPCR_BASE];
|
mtspr(SPR_SR, cpu_state.sprs[SPR_ESR_BASE]);
|
mtspr(SPR_SR, cpu_state.sprs[SPR_ESR_BASE]);
|
}
|
}
|
INSTRUCTION (l_nop) {
|
INSTRUCTION (l_nop) {
|
uint32_t k = PARAM0;
|
uint32_t k = PARAM0;
|
switch (k) {
|
switch (k) {
|
case NOP_NOP:
|
case NOP_NOP:
|
break;
|
break;
|
case NOP_EXIT:
|
case NOP_EXIT:
|
PRINTF("exit(%"PRIdREG")\n", evalsim_reg (3));
|
PRINTF("exit(%"PRIdREG")\n", evalsim_reg (3));
|
fprintf(stderr, "@reset : cycles %lld, insn #%lld\n",
|
fprintf(stderr, "@reset : cycles %lld, insn #%lld\n",
|
runtime.sim.reset_cycles, runtime.cpu.reset_instructions);
|
runtime.sim.reset_cycles, runtime.cpu.reset_instructions);
|
fprintf(stderr, "@exit : cycles %lld, insn #%lld\n", runtime.sim.cycles,
|
fprintf(stderr, "@exit : cycles %lld, insn #%lld\n", runtime.sim.cycles,
|
runtime.cpu.instructions);
|
runtime.cpu.instructions);
|
fprintf(stderr, " diff : cycles %lld, insn #%lld\n",
|
fprintf(stderr, " diff : cycles %lld, insn #%lld\n",
|
runtime.sim.cycles - runtime.sim.reset_cycles,
|
runtime.sim.cycles - runtime.sim.reset_cycles,
|
runtime.cpu.instructions - runtime.cpu.reset_instructions);
|
runtime.cpu.instructions - runtime.cpu.reset_instructions);
|
if (config.debug.gdb_enabled)
|
if (config.debug.gdb_enabled)
|
set_stall_state (1);
|
set_stall_state (1);
|
else
|
else
|
sim_done();
|
sim_done();
|
break;
|
break;
|
case NOP_CNT_RESET:
|
case NOP_CNT_RESET:
|
PRINTF("****************** counters reset ******************\n");
|
PRINTF("****************** counters reset ******************\n");
|
PRINTF("cycles %lld, insn #%lld\n", runtime.sim.cycles, runtime.cpu.instructions);
|
PRINTF("cycles %lld, insn #%lld\n", runtime.sim.cycles, runtime.cpu.instructions);
|
PRINTF("****************** counters reset ******************\n");
|
PRINTF("****************** counters reset ******************\n");
|
runtime.sim.reset_cycles = runtime.sim.cycles;
|
runtime.sim.reset_cycles = runtime.sim.cycles;
|
runtime.cpu.reset_instructions = runtime.cpu.instructions;
|
runtime.cpu.reset_instructions = runtime.cpu.instructions;
|
break;
|
break;
|
case NOP_PUTC: /*JPB */
|
case NOP_PUTC: /*JPB */
|
printf( "%c", (char)(evalsim_reg( 3 ) & 0xff));
|
printf( "%c", (char)(evalsim_reg( 3 ) & 0xff));
|
fflush( stdout );
|
fflush( stdout );
|
break;
|
break;
|
case NOP_GET_TICKS:
|
case NOP_GET_TICKS:
|
cpu_state.reg[11] = runtime.sim.cycles & 0xffffffff;
|
cpu_state.reg[11] = runtime.sim.cycles & 0xffffffff;
|
cpu_state.reg[12] = runtime.sim.cycles >> 32;
|
cpu_state.reg[12] = runtime.sim.cycles >> 32;
|
break;
|
break;
|
case NOP_GET_PS:
|
case NOP_GET_PS:
|
cpu_state.reg[11] = config.sim.clkcycle_ps;
|
cpu_state.reg[11] = config.sim.clkcycle_ps;
|
break;
|
break;
|
case NOP_REPORT:
|
case NOP_REPORT:
|
PRINTF("report(0x%"PRIxREG");\n", evalsim_reg(3));
|
PRINTF("report(0x%"PRIxREG");\n", evalsim_reg(3));
|
default:
|
default:
|
if (k >= NOP_REPORT_FIRST && k <= NOP_REPORT_LAST)
|
if (k >= NOP_REPORT_FIRST && k <= NOP_REPORT_LAST)
|
PRINTF("report %" PRIdREG " (0x%"PRIxREG");\n", k - NOP_REPORT_FIRST,
|
PRINTF("report %" PRIdREG " (0x%"PRIxREG");\n", k - NOP_REPORT_FIRST,
|
evalsim_reg(3));
|
evalsim_reg(3));
|
break;
|
break;
|
}
|
}
|
}
|
}
|
INSTRUCTION (l_sfeq) {
|
INSTRUCTION (l_sfeq) {
|
if(PARAM0 == PARAM1)
|
if(PARAM0 == PARAM1)
|
cpu_state.sprs[SPR_SR] |= SPR_SR_F;
|
cpu_state.sprs[SPR_SR] |= SPR_SR_F;
|
else
|
else
|
cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
|
cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
|
}
|
}
|
INSTRUCTION (l_sfne) {
|
INSTRUCTION (l_sfne) {
|
if(PARAM0 != PARAM1)
|
if(PARAM0 != PARAM1)
|
cpu_state.sprs[SPR_SR] |= SPR_SR_F;
|
cpu_state.sprs[SPR_SR] |= SPR_SR_F;
|
else
|
else
|
cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
|
cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
|
}
|
}
|
INSTRUCTION (l_sfgts) {
|
INSTRUCTION (l_sfgts) {
|
if((orreg_t)PARAM0 > (orreg_t)PARAM1)
|
if((orreg_t)PARAM0 > (orreg_t)PARAM1)
|
cpu_state.sprs[SPR_SR] |= SPR_SR_F;
|
cpu_state.sprs[SPR_SR] |= SPR_SR_F;
|
else
|
else
|
cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
|
cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
|
}
|
}
|
INSTRUCTION (l_sfges) {
|
INSTRUCTION (l_sfges) {
|
if((orreg_t)PARAM0 >= (orreg_t)PARAM1)
|
if((orreg_t)PARAM0 >= (orreg_t)PARAM1)
|
cpu_state.sprs[SPR_SR] |= SPR_SR_F;
|
cpu_state.sprs[SPR_SR] |= SPR_SR_F;
|
else
|
else
|
cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
|
cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
|
}
|
}
|
INSTRUCTION (l_sflts) {
|
INSTRUCTION (l_sflts) {
|
if((orreg_t)PARAM0 < (orreg_t)PARAM1)
|
if((orreg_t)PARAM0 < (orreg_t)PARAM1)
|
cpu_state.sprs[SPR_SR] |= SPR_SR_F;
|
cpu_state.sprs[SPR_SR] |= SPR_SR_F;
|
else
|
else
|
cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
|
cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
|
}
|
}
|
INSTRUCTION (l_sfles) {
|
INSTRUCTION (l_sfles) {
|
if((orreg_t)PARAM0 <= (orreg_t)PARAM1)
|
if((orreg_t)PARAM0 <= (orreg_t)PARAM1)
|
cpu_state.sprs[SPR_SR] |= SPR_SR_F;
|
cpu_state.sprs[SPR_SR] |= SPR_SR_F;
|
else
|
else
|
cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
|
cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
|
}
|
}
|
INSTRUCTION (l_sfgtu) {
|
INSTRUCTION (l_sfgtu) {
|
if(PARAM0 > PARAM1)
|
if(PARAM0 > PARAM1)
|
cpu_state.sprs[SPR_SR] |= SPR_SR_F;
|
cpu_state.sprs[SPR_SR] |= SPR_SR_F;
|
else
|
else
|
cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
|
cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
|
}
|
}
|
INSTRUCTION (l_sfgeu) {
|
INSTRUCTION (l_sfgeu) {
|
if(PARAM0 >= PARAM1)
|
if(PARAM0 >= PARAM1)
|
cpu_state.sprs[SPR_SR] |= SPR_SR_F;
|
cpu_state.sprs[SPR_SR] |= SPR_SR_F;
|
else
|
else
|
cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
|
cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
|
}
|
}
|
INSTRUCTION (l_sfltu) {
|
INSTRUCTION (l_sfltu) {
|
if(PARAM0 < PARAM1)
|
if(PARAM0 < PARAM1)
|
cpu_state.sprs[SPR_SR] |= SPR_SR_F;
|
cpu_state.sprs[SPR_SR] |= SPR_SR_F;
|
else
|
else
|
cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
|
cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
|
}
|
}
|
INSTRUCTION (l_sfleu) {
|
INSTRUCTION (l_sfleu) {
|
if(PARAM0 <= PARAM1)
|
if(PARAM0 <= PARAM1)
|
cpu_state.sprs[SPR_SR] |= SPR_SR_F;
|
cpu_state.sprs[SPR_SR] |= SPR_SR_F;
|
else
|
else
|
cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
|
cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
|
}
|
}
|
INSTRUCTION (l_extbs) {
|
INSTRUCTION (l_extbs) {
|
int8_t x;
|
int8_t x;
|
x = PARAM1;
|
x = PARAM1;
|
SET_PARAM0((orreg_t)x);
|
SET_PARAM0((orreg_t)x);
|
}
|
}
|
INSTRUCTION (l_extbz) {
|
INSTRUCTION (l_extbz) {
|
uint8_t x;
|
uint8_t x;
|
x = PARAM1;
|
x = PARAM1;
|
SET_PARAM0((uorreg_t)x);
|
SET_PARAM0((uorreg_t)x);
|
}
|
}
|
INSTRUCTION (l_exths) {
|
INSTRUCTION (l_exths) {
|
int16_t x;
|
int16_t x;
|
x = PARAM1;
|
x = PARAM1;
|
SET_PARAM0((orreg_t)x);
|
SET_PARAM0((orreg_t)x);
|
}
|
}
|
INSTRUCTION (l_exthz) {
|
INSTRUCTION (l_exthz) {
|
uint16_t x;
|
uint16_t x;
|
x = PARAM1;
|
x = PARAM1;
|
SET_PARAM0((uorreg_t)x);
|
SET_PARAM0((uorreg_t)x);
|
}
|
}
|
INSTRUCTION (l_extws) {
|
INSTRUCTION (l_extws) {
|
int32_t x;
|
int32_t x;
|
x = PARAM1;
|
x = PARAM1;
|
SET_PARAM0((orreg_t)x);
|
SET_PARAM0((orreg_t)x);
|
}
|
}
|
INSTRUCTION (l_extwz) {
|
INSTRUCTION (l_extwz) {
|
uint32_t x;
|
uint32_t x;
|
x = PARAM1;
|
x = PARAM1;
|
SET_PARAM0((uorreg_t)x);
|
SET_PARAM0((uorreg_t)x);
|
}
|
}
|
INSTRUCTION (l_mtspr) {
|
INSTRUCTION (l_mtspr) {
|
uint16_t regno = PARAM0 + PARAM2;
|
uint16_t regno = PARAM0 + PARAM2;
|
uorreg_t value = PARAM1;
|
uorreg_t value = PARAM1;
|
|
|
if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
|
if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
|
mtspr(regno, value);
|
mtspr(regno, value);
|
else {
|
else {
|
PRINTF("WARNING: trying to write SPR while SR[SUPV] is cleared.\n");
|
PRINTF("WARNING: trying to write SPR while SR[SUPV] is cleared.\n");
|
sim_done();
|
sim_done();
|
}
|
}
|
}
|
}
|
INSTRUCTION (l_mfspr) {
|
INSTRUCTION (l_mfspr) {
|
uint16_t regno = PARAM1 + PARAM2;
|
uint16_t regno = PARAM1 + PARAM2;
|
uorreg_t value = mfspr(regno);
|
uorreg_t value = mfspr(regno);
|
|
|
if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
|
if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
|
SET_PARAM0(value);
|
SET_PARAM0(value);
|
else {
|
else {
|
SET_PARAM0(0);
|
SET_PARAM0(0);
|
PRINTF("WARNING: trying to read SPR while SR[SUPV] is cleared.\n");
|
PRINTF("WARNING: trying to read SPR while SR[SUPV] is cleared.\n");
|
sim_done();
|
sim_done();
|
}
|
}
|
}
|
}
|
INSTRUCTION (l_sys) {
|
INSTRUCTION (l_sys) {
|
except_handle(EXCEPT_SYSCALL, cpu_state.sprs[SPR_EEAR_BASE]);
|
except_handle(EXCEPT_SYSCALL, cpu_state.sprs[SPR_EEAR_BASE]);
|
}
|
}
|
INSTRUCTION (l_trap) {
|
INSTRUCTION (l_trap) {
|
/* TODO: some SR related code here! */
|
/* TODO: some SR related code here! */
|
except_handle(EXCEPT_TRAP, cpu_state.sprs[SPR_EEAR_BASE]);
|
except_handle(EXCEPT_TRAP, cpu_state.sprs[SPR_EEAR_BASE]);
|
}
|
}
|
INSTRUCTION (l_mac) {
|
INSTRUCTION (l_mac) {
|
uorreg_t lo, hi;
|
uorreg_t lo, hi;
|
LONGEST l;
|
LONGEST l;
|
orreg_t x, y;
|
orreg_t x, y;
|
|
|
lo = cpu_state.sprs[SPR_MACLO];
|
lo = cpu_state.sprs[SPR_MACLO];
|
hi = cpu_state.sprs[SPR_MACHI];
|
hi = cpu_state.sprs[SPR_MACHI];
|
x = PARAM0;
|
x = PARAM0;
|
y = PARAM1;
|
y = PARAM1;
|
/* PRINTF ("[%"PRIxREG",%"PRIxREG"]\t", x, y); */
|
/* PRINTF ("[%"PRIxREG",%"PRIxREG"]\t", x, y); */
|
l = (ULONGEST)lo | ((LONGEST)hi << 32);
|
l = (ULONGEST)lo | ((LONGEST)hi << 32);
|
l += (LONGEST) x * (LONGEST) y;
|
l += (LONGEST) x * (LONGEST) y;
|
|
|
/* This implementation is very fast - it needs only one cycle for mac. */
|
/* This implementation is very fast - it needs only one cycle for mac. */
|
lo = ((ULONGEST)l) & 0xFFFFFFFF;
|
lo = ((ULONGEST)l) & 0xFFFFFFFF;
|
hi = ((LONGEST)l) >> 32;
|
hi = ((LONGEST)l) >> 32;
|
cpu_state.sprs[SPR_MACLO] = lo;
|
cpu_state.sprs[SPR_MACLO] = lo;
|
cpu_state.sprs[SPR_MACHI] = hi;
|
cpu_state.sprs[SPR_MACHI] = hi;
|
/* PRINTF ("(%"PRIxREG",%"PRIxREG"\n", hi, lo); */
|
/* PRINTF ("(%"PRIxREG",%"PRIxREG"\n", hi, lo); */
|
}
|
}
|
INSTRUCTION (l_msb) {
|
INSTRUCTION (l_msb) {
|
uorreg_t lo, hi;
|
uorreg_t lo, hi;
|
LONGEST l;
|
LONGEST l;
|
orreg_t x, y;
|
orreg_t x, y;
|
|
|
lo = cpu_state.sprs[SPR_MACLO];
|
lo = cpu_state.sprs[SPR_MACLO];
|
hi = cpu_state.sprs[SPR_MACHI];
|
hi = cpu_state.sprs[SPR_MACHI];
|
x = PARAM0;
|
x = PARAM0;
|
y = PARAM1;
|
y = PARAM1;
|
|
|
/* PRINTF ("[%"PRIxREG",%"PRIxREG"]\t", x, y); */
|
/* PRINTF ("[%"PRIxREG",%"PRIxREG"]\t", x, y); */
|
|
|
l = (ULONGEST)lo | ((LONGEST)hi << 32);
|
l = (ULONGEST)lo | ((LONGEST)hi << 32);
|
l -= x * y;
|
l -= x * y;
|
|
|
/* This implementation is very fast - it needs only one cycle for msb. */
|
/* This implementation is very fast - it needs only one cycle for msb. */
|
lo = ((ULONGEST)l) & 0xFFFFFFFF;
|
lo = ((ULONGEST)l) & 0xFFFFFFFF;
|
hi = ((LONGEST)l) >> 32;
|
hi = ((LONGEST)l) >> 32;
|
cpu_state.sprs[SPR_MACLO] = lo;
|
cpu_state.sprs[SPR_MACLO] = lo;
|
cpu_state.sprs[SPR_MACHI] = hi;
|
cpu_state.sprs[SPR_MACHI] = hi;
|
/* PRINTF ("(%"PRIxREG",%"PRIxREG")\n", hi, lo); */
|
/* PRINTF ("(%"PRIxREG",%"PRIxREG")\n", hi, lo); */
|
}
|
}
|
INSTRUCTION (l_macrc) {
|
INSTRUCTION (l_macrc) {
|
uorreg_t lo, hi;
|
uorreg_t lo, hi;
|
LONGEST l;
|
LONGEST l;
|
/* No need for synchronization here -- all MAC instructions are 1 cycle long. */
|
/* No need for synchronization here -- all MAC instructions are 1 cycle long. */
|
lo = cpu_state.sprs[SPR_MACLO];
|
lo = cpu_state.sprs[SPR_MACLO];
|
hi = cpu_state.sprs[SPR_MACHI];
|
hi = cpu_state.sprs[SPR_MACHI];
|
l = (ULONGEST) lo | ((LONGEST)hi << 32);
|
l = (ULONGEST) lo | ((LONGEST)hi << 32);
|
l >>= 28;
|
l >>= 28;
|
//PRINTF ("<%08x>\n", (unsigned long)l);
|
//PRINTF ("<%08x>\n", (unsigned long)l);
|
SET_PARAM0((orreg_t)l);
|
SET_PARAM0((orreg_t)l);
|
cpu_state.sprs[SPR_MACLO] = 0;
|
cpu_state.sprs[SPR_MACLO] = 0;
|
cpu_state.sprs[SPR_MACHI] = 0;
|
cpu_state.sprs[SPR_MACHI] = 0;
|
}
|
}
|
INSTRUCTION (l_cmov) {
|
INSTRUCTION (l_cmov) {
|
SET_PARAM0(cpu_state.sprs[SPR_SR] & SPR_SR_F ? PARAM1 : PARAM2);
|
SET_PARAM0(cpu_state.sprs[SPR_SR] & SPR_SR_F ? PARAM1 : PARAM2);
|
}
|
}
|
INSTRUCTION (l_ff1) {
|
INSTRUCTION (l_ff1) {
|
SET_PARAM0(ffs(PARAM1));
|
SET_PARAM0(ffs(PARAM1));
|
}
|
}
|
/******* Floating point instructions *******/
|
/******* Floating point instructions *******/
|
/* Single precision */
|
/* Single precision */
|
INSTRUCTION (lf_add_s) {
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INSTRUCTION (lf_add_s) {
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SET_PARAM0((float)PARAM1 + (float)PARAM2);
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if (config.cpu.hardfloat) {
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FLOAT param0, param1, param2;
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param1.hval = (uorreg_t)PARAM1;
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param2.hval = (uorreg_t)PARAM2;
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param0.fval = param1.fval + param2.fval;
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SET_PARAM0(param0.hval);
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} else l_invalid();
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}
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}
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INSTRUCTION (lf_div_s) {
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INSTRUCTION (lf_div_s) {
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SET_PARAM0((float)PARAM1 / (float)PARAM2);
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if (config.cpu.hardfloat) {
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FLOAT param0, param1, param2;
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param1.hval = (uorreg_t)PARAM1;
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param2.hval = (uorreg_t)PARAM2;
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param0.fval = param1.fval / param2.fval;
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SET_PARAM0(param0.hval);
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} else l_invalid();
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}
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}
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INSTRUCTION (lf_ftoi_s) {
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INSTRUCTION (lf_ftoi_s) {
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// set_operand32(0, freg[get_operand(1)], &breakpoint);
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if (config.cpu.hardfloat) {
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// no other way appeared to work --jb
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float tmp_f; memcpy((void*)&tmp_f, (void*)&PARAM1, sizeof(float));
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SET_PARAM0((int)tmp_f);
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} else l_invalid();
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}
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}
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INSTRUCTION (lf_itof_s) {
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INSTRUCTION (lf_itof_s) {
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// freg[get_operand(0)] = eval_operand32(1, &breakpoint);
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if (config.cpu.hardfloat) {
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FLOAT param0;
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param0.fval = (float)((int)PARAM1);
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SET_PARAM0(param0.hval);
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} else l_invalid();
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}
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}
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INSTRUCTION (lf_madd_s) {
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INSTRUCTION (lf_madd_s) {
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SET_PARAM0((float)PARAM0 + (float)PARAM1 * (float)PARAM2);
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if (config.cpu.hardfloat) {
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FLOAT param0,param1, param2;
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param0.hval = PARAM0;
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param1.hval = PARAM1;
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param2.hval = PARAM2;
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param0.fval += param1.fval * param2.fval;
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SET_PARAM0(param0.hval);
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} else l_invalid();
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}
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}
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INSTRUCTION (lf_mul_s) {
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INSTRUCTION (lf_mul_s) {
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SET_PARAM0((float)PARAM1 * (float)PARAM2);
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if (config.cpu.hardfloat) {
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FLOAT param0, param1, param2;
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param1.hval = (uorreg_t)PARAM1;
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param2.hval = (uorreg_t)PARAM2;
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param0.fval = param1.fval * param2.fval;
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SET_PARAM0(param0.hval);
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} else l_invalid();
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}
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}
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INSTRUCTION (lf_rem_s) {
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INSTRUCTION (lf_rem_s) {
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float temp = (float)PARAM1 / (float)PARAM2;
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if (config.cpu.hardfloat) {
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SET_PARAM0(temp - (uint32_t)temp);
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FLOAT param0, param1, param2;
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param1.hval = PARAM1;
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param2.hval = PARAM2;
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param0.fval = param1.fval / param2.fval;
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SET_PARAM0(param0.hval);
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} else l_invalid();
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}
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}
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INSTRUCTION (lf_sfeq_s) {
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INSTRUCTION (lf_sfeq_s) {
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if((float)PARAM0 == (float)PARAM1)
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if (config.cpu.hardfloat) {
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FLOAT param0, param1;
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param0.hval = PARAM0;
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param1.hval = PARAM1;
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if(param0.fval == param1.fval)
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cpu_state.sprs[SPR_SR] |= SPR_SR_F;
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cpu_state.sprs[SPR_SR] |= SPR_SR_F;
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else
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else
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cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
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cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
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} else l_invalid();
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}
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}
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INSTRUCTION (lf_sfge_s) {
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INSTRUCTION (lf_sfge_s) {
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if((float)PARAM0 >= (float)PARAM1)
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if (config.cpu.hardfloat) {
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FLOAT param0, param1;
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param0.hval = PARAM0;
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param1.hval = PARAM1;
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if(param0.fval >= param1.fval)
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cpu_state.sprs[SPR_SR] |= SPR_SR_F;
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cpu_state.sprs[SPR_SR] |= SPR_SR_F;
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else
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else
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cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
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cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
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} else l_invalid();
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}
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}
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INSTRUCTION (lf_sfgt_s) {
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INSTRUCTION (lf_sfgt_s) {
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if((float)PARAM0 > (float)PARAM1)
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if (config.cpu.hardfloat) {
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FLOAT param0, param1;
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param0.hval = PARAM0;
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param1.hval = PARAM1;
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if(param0.fval > param1.fval)
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cpu_state.sprs[SPR_SR] |= SPR_SR_F;
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cpu_state.sprs[SPR_SR] |= SPR_SR_F;
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else
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else
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cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
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cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
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} else l_invalid();
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}
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}
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INSTRUCTION (lf_sfle_s) {
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INSTRUCTION (lf_sfle_s) {
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if((float)PARAM0 <= (float)PARAM1)
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if (config.cpu.hardfloat) {
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FLOAT param0, param1;
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param0.hval = PARAM0;
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param1.hval = PARAM1;
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if(param0.fval <= param1.fval)
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cpu_state.sprs[SPR_SR] |= SPR_SR_F;
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cpu_state.sprs[SPR_SR] |= SPR_SR_F;
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else
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else
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cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
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cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
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} else l_invalid();
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}
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}
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INSTRUCTION (lf_sflt_s) {
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INSTRUCTION (lf_sflt_s) {
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if((float)PARAM0 < (float)PARAM1)
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if (config.cpu.hardfloat) {
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FLOAT param0, param1;
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param0.hval = PARAM0;
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param1.hval = PARAM1;
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if(param0.fval < param1.fval)
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cpu_state.sprs[SPR_SR] |= SPR_SR_F;
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cpu_state.sprs[SPR_SR] |= SPR_SR_F;
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else
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else
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cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
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cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
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} else l_invalid();
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}
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}
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INSTRUCTION (lf_sfne_s) {
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INSTRUCTION (lf_sfne_s) {
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if((float)PARAM0 != (float)PARAM1)
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if (config.cpu.hardfloat) {
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FLOAT param0, param1;
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param0.hval = PARAM0;
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param1.hval = PARAM1;
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if(param0.fval != param1.fval)
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cpu_state.sprs[SPR_SR] |= SPR_SR_F;
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cpu_state.sprs[SPR_SR] |= SPR_SR_F;
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else
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else
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cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
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cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
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} else l_invalid();
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}
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}
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INSTRUCTION (lf_sub_s) {
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INSTRUCTION (lf_sub_s) {
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SET_PARAM0((float)PARAM1 - (float)PARAM2);
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if (config.cpu.hardfloat) {
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FLOAT param0, param1, param2;
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param1.hval = PARAM1;
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param2.hval = PARAM2;
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param0.fval = param1.fval - param2.fval;
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SET_PARAM0(param0.hval);
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} else l_invalid();
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}
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}
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|
/******* Custom instructions *******/
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/******* Custom instructions *******/
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INSTRUCTION (l_cust1) {
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INSTRUCTION (l_cust1) {
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/*int destr = current->insn >> 21;
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/*int destr = current->insn >> 21;
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int src1r = current->insn >> 15;
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int src1r = current->insn >> 15;
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int src2r = current->insn >> 9;*/
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int src2r = current->insn >> 9;*/
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}
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}
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INSTRUCTION (l_cust2) {
|
INSTRUCTION (l_cust2) {
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}
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}
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INSTRUCTION (l_cust3) {
|
INSTRUCTION (l_cust3) {
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}
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}
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INSTRUCTION (l_cust4) {
|
INSTRUCTION (l_cust4) {
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}
|
}
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|
INSTRUCTION (lf_cust1) {
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}
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INSTRUCTION (lf_cust2) {
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}
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INSTRUCTION (lf_cust3) {
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|
}
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|
INSTRUCTION (lf_cust4) {
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}
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No newline at end of file
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No newline at end of file
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