/* Table of opcodes for the OpenRISC 1000 ISA.
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/* Table of opcodes for the OpenRISC 1000 ISA.
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Copyright 1990, 1991, 1992, 1993 Free Software Foundation, Inc.
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Copyright 1990, 1991, 1992, 1993 Free Software Foundation, Inc.
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Copyright (C) 2008 Embecosm Limited
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Copyright (C) 2008 Embecosm Limited
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Contributed by Damjan Lampret (lampret@opencores.org).
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Contributed by Damjan Lampret (lampret@opencores.org).
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
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This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
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This file is also part of gen_or1k_isa, GDB and GAS.
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This file is also part of gen_or1k_isa, GDB and GAS.
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This program is free software; you can redistribute it and/or modify it
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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more details.
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You should have received a copy of the GNU General Public License along
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You should have received a copy of the GNU General Public License along
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* This program is commented throughout in a fashion suitable for processing
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/* This program is commented throughout in a fashion suitable for processing
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with Doxygen. */
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with Doxygen. */
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/* Autoconf and/or portability configuration */
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/* Autoconf and/or portability configuration */
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#include "config.h"
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#include "config.h"
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#include "port.h"
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#include "port.h"
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/* System includes */
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/* System includes */
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#include <stdlib.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdio.h>
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/* Package includes */
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/* Package includes */
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#include "opcode/or32.h"
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#include "opcode/or32.h"
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/* We treat all letters the same in encode/decode routines so
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/* We treat all letters the same in encode/decode routines so
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we need to assign some characteristics to them like signess etc.*/
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we need to assign some characteristics to them like signess etc.*/
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CONST struct or32_letter or32_letters[] = {
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CONST struct or32_letter or32_letters[] = {
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{'A', NUM_UNSIGNED},
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{'A', NUM_UNSIGNED},
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{'B', NUM_UNSIGNED},
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{'B', NUM_UNSIGNED},
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{'D', NUM_UNSIGNED},
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{'D', NUM_UNSIGNED},
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{'I', NUM_SIGNED},
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{'I', NUM_SIGNED},
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{'K', NUM_UNSIGNED},
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{'K', NUM_UNSIGNED},
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{'L', NUM_UNSIGNED},
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{'L', NUM_UNSIGNED},
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{'N', NUM_SIGNED},
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{'N', NUM_SIGNED},
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{'0', NUM_UNSIGNED},
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{'0', NUM_UNSIGNED},
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{'\0', 0} /* dummy entry */
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{'\0', 0} /* dummy entry */
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};
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};
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/* Opcode encoding:
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/* Opcode encoding:
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machine[31:30]: first two bits of opcode
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machine[31:30]: first two bits of opcode
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00 - neither of source operands is GPR
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00 - neither of source operands is GPR
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01 - second source operand is GPR (rB)
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01 - second source operand is GPR (rB)
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10 - first source operand is GPR (rA)
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10 - first source operand is GPR (rA)
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11 - both source operands are GPRs (rA and rB)
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11 - both source operands are GPRs (rA and rB)
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machine[29:26]: next four bits of opcode
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machine[29:26]: next four bits of opcode
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machine[25:00]: instruction operands (specific to individual instruction)
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machine[25:00]: instruction operands (specific to individual instruction)
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Recommendation: irrelevant instruction bits should be set with a value of
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Recommendation: irrelevant instruction bits should be set with a value of
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bits in same positions of instruction preceding current instruction in the
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bits in same positions of instruction preceding current instruction in the
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code (when assembling).
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code (when assembling).
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*/
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*/
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#ifdef HAVE_EXECUTION
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#ifdef HAVE_EXECUTION
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# if SIMPLE_EXECUTION
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# if SIMPLE_EXECUTION
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# define EFN &l_none
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# define EFN &l_none
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# define EF(func) &(func)
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# define EF(func) &(func)
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# define EFI &l_invalid
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# define EFI &l_invalid
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# elif COMPLEX_EXECUTION
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# elif COMPLEX_EXECUTION
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# define EFN "l_none"
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# define EFN "l_none"
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# define EFI "l_invalid"
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# define EFI "l_invalid"
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# ifdef __GNUC__
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# ifdef __GNUC__
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# define EF(func) #func
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# define EF(func) #func
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# else
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# else
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# define EF(func) "func"
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# define EF(func) "func"
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# endif
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# endif
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# else /* DYNAMIC_EXECUTION */
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# else /* DYNAMIC_EXECUTION */
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# define EFN &l_none
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# define EFN &l_none
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# define EF(func) &(gen_ ##func)
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# define EF(func) &(gen_ ##func)
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# define EFI &gen_l_invalid
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# define EFI &gen_l_invalid
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# endif
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# endif
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#else /* HAVE_EXECUTION */
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#else /* HAVE_EXECUTION */
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# define EFN &l_none
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# define EFN &l_none
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# define EF(func) EFN
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# define EF(func) EFN
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# define EFI EFN
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# define EFI EFN
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#endif /* HAVE_EXECUTION */
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#endif /* HAVE_EXECUTION */
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CONST struct or32_opcode or32_opcodes[] = {
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CONST struct or32_opcode or32_opcodes[] = {
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{"l.j", "N", "00 0x0 NNNNN NNNNN NNNN NNNN NNNN NNNN",
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{"l.j", "N", "00 0x0 NNNNN NNNNN NNNN NNNN NNNN NNNN",
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EF (l_j), OR32_IF_DELAY, it_jump},
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EF (l_j), OR32_IF_DELAY, it_jump},
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{"l.jal", "N", "00 0x1 NNNNN NNNNN NNNN NNNN NNNN NNNN",
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{"l.jal", "N", "00 0x1 NNNNN NNNNN NNNN NNNN NNNN NNNN",
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EF (l_jal), OR32_IF_DELAY, it_jump},
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EF (l_jal), OR32_IF_DELAY, it_jump},
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{"l.bnf", "N", "00 0x3 NNNNN NNNNN NNNN NNNN NNNN NNNN",
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{"l.bnf", "N", "00 0x3 NNNNN NNNNN NNNN NNNN NNNN NNNN",
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EF (l_bnf), OR32_IF_DELAY | OR32_R_FLAG, it_branch},
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EF (l_bnf), OR32_IF_DELAY | OR32_R_FLAG, it_branch},
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{"l.bf", "N", "00 0x4 NNNNN NNNNN NNNN NNNN NNNN NNNN",
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{"l.bf", "N", "00 0x4 NNNNN NNNNN NNNN NNNN NNNN NNNN",
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EF (l_bf), OR32_IF_DELAY | OR32_R_FLAG, it_branch},
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EF (l_bf), OR32_IF_DELAY | OR32_R_FLAG, it_branch},
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{"l.nop", "K", "00 0x5 01--- ----- KKKK KKKK KKKK KKKK",
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{"l.nop", "K", "00 0x5 01--- ----- KKKK KKKK KKKK KKKK",
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EF (l_nop), 0, it_nop},
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EF (l_nop), 0, it_nop},
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{"l.movhi", "rD,K", "00 0x6 DDDDD ----0 KKKK KKKK KKKK KKKK",
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{"l.movhi", "rD,K", "00 0x6 DDDDD ----0 KKKK KKKK KKKK KKKK",
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EF (l_movhi), 0, it_movimm},
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EF (l_movhi), 0, it_movimm},
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{"l.macrc", "rD", "00 0x6 DDDDD ----1 0000 0000 0000 0000",
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{"l.macrc", "rD", "00 0x6 DDDDD ----1 0000 0000 0000 0000",
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EF (l_macrc), 0, it_mac},
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EF (l_macrc), 0, it_mac},
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{"l.sys", "K", "00 0x8 00000 00000 KKKK KKKK KKKK KKKK",
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{"l.sys", "K", "00 0x8 00000 00000 KKKK KKKK KKKK KKKK",
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EF (l_sys), 0, it_exception},
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EF (l_sys), 0, it_exception},
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{"l.trap", "K", "00 0x8 01000 00000 KKKK KKKK KKKK KKKK",
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{"l.trap", "K", "00 0x8 01000 00000 KKKK KKKK KKKK KKKK",
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EF (l_trap), 0, it_exception},
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EF (l_trap), 0, it_exception},
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{"l.msync", "", "00 0x8 10000 00000 0000 0000 0000 0000", EFN,
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{"l.msync", "", "00 0x8 10000 00000 0000 0000 0000 0000", EFN,
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0, it_unknown},
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0, it_unknown},
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{"l.psync", "", "00 0x8 10100 00000 0000 0000 0000 0000", EFN,
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{"l.psync", "", "00 0x8 10100 00000 0000 0000 0000 0000", EFN,
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0, it_unknown},
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0, it_unknown},
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{"l.csync", "", "00 0x8 11000 00000 0000 0000 0000 0000", EFN,
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{"l.csync", "", "00 0x8 11000 00000 0000 0000 0000 0000", EFN,
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0, it_unknown},
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0, it_unknown},
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{"l.rfe", "", "00 0x9 ----- ----- ---- ---- ---- ----",
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{"l.rfe", "", "00 0x9 ----- ----- ---- ---- ---- ----",
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EF (l_rfe), 0, it_exception},
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EF (l_rfe), 0, it_exception},
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{"lv.all_eq.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0,
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{"lv.all_eq.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0,
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it_unknown},
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it_unknown},
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{"lv.all_eq.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0,
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{"lv.all_eq.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0,
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it_unknown},
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it_unknown},
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{"lv.all_ge.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0,
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{"lv.all_ge.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0,
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it_unknown},
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it_unknown},
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{"lv.all_ge.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0,
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{"lv.all_ge.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0,
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it_unknown},
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it_unknown},
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{"lv.all_gt.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0,
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{"lv.all_gt.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x4", EFI, 0,
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it_unknown},
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it_unknown},
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{"lv.all_gt.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0,
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{"lv.all_gt.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x5", EFI, 0,
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it_unknown},
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it_unknown},
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{"lv.all_le.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0,
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{"lv.all_le.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0,
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it_unknown},
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it_unknown},
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{"lv.all_le.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0,
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{"lv.all_le.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0,
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it_unknown},
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it_unknown},
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{"lv.all_lt.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x8", EFI, 0,
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{"lv.all_lt.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x8", EFI, 0,
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it_unknown},
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it_unknown},
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{"lv.all_lt.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x9", EFI, 0,
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{"lv.all_lt.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0x9", EFI, 0,
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it_unknown},
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it_unknown},
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{"lv.all_ne.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0xA", EFI, 0,
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{"lv.all_ne.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0xA", EFI, 0,
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it_unknown},
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it_unknown},
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{"lv.all_ne.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0xB", EFI, 0,
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{"lv.all_ne.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x1 0xB", EFI, 0,
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it_unknown},
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it_unknown},
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{"lv.any_eq.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x0", EFI, 0,
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{"lv.any_eq.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x0", EFI, 0,
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it_unknown},
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it_unknown},
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{"lv.any_eq.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x1", EFI, 0,
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{"lv.any_eq.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x1", EFI, 0,
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it_unknown},
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it_unknown},
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{"lv.any_ge.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x2", EFI, 0,
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{"lv.any_ge.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x2", EFI, 0,
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it_unknown},
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it_unknown},
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{"lv.any_ge.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x3", EFI, 0,
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{"lv.any_ge.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x3", EFI, 0,
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it_unknown},
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it_unknown},
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{"lv.any_gt.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x4", EFI, 0,
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{"lv.any_gt.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x4", EFI, 0,
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it_unknown},
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it_unknown},
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{"lv.any_gt.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x5", EFI, 0,
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{"lv.any_gt.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x5", EFI, 0,
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it_unknown},
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it_unknown},
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{"lv.any_le.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x6", EFI, 0,
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{"lv.any_le.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x6", EFI, 0,
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it_unknown},
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it_unknown},
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{"lv.any_le.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x7", EFI, 0,
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{"lv.any_le.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x7", EFI, 0,
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it_unknown},
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it_unknown},
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{"lv.any_lt.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x8", EFI, 0,
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{"lv.any_lt.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x8", EFI, 0,
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it_unknown},
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it_unknown},
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{"lv.any_lt.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x9", EFI, 0,
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{"lv.any_lt.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0x9", EFI, 0,
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it_unknown},
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it_unknown},
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{"lv.any_ne.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0xA", EFI, 0,
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{"lv.any_ne.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0xA", EFI, 0,
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it_unknown},
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it_unknown},
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{"lv.any_ne.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0xB", EFI, 0,
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{"lv.any_ne.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x2 0xB", EFI, 0,
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it_unknown},
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it_unknown},
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{"lv.add.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x0", EFI, 0,
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{"lv.add.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x0", EFI, 0,
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it_unknown},
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it_unknown},
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{"lv.add.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x1", EFI, 0,
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{"lv.add.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x1", EFI, 0,
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it_unknown},
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it_unknown},
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{"lv.adds.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x2", EFI, 0,
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{"lv.adds.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x2", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.adds.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x3", EFI, 0,
|
{"lv.adds.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x3", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.addu.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x4", EFI, 0,
|
{"lv.addu.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x4", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.addu.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x5", EFI, 0,
|
{"lv.addu.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x5", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.addus.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x6", EFI, 0,
|
{"lv.addus.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x6", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.addus.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x7", EFI, 0,
|
{"lv.addus.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x7", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.and", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x8", EFI, 0,
|
{"lv.and", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x8", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.avg.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x9", EFI, 0,
|
{"lv.avg.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0x9", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.avg.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0xA", EFI, 0,
|
{"lv.avg.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x3 0xA", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.cmp_eq.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x0", EFI, 0,
|
{"lv.cmp_eq.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x0", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.cmp_eq.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x1", EFI, 0,
|
{"lv.cmp_eq.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x1", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.cmp_ge.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x2", EFI, 0,
|
{"lv.cmp_ge.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x2", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.cmp_ge.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x3", EFI, 0,
|
{"lv.cmp_ge.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x3", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.cmp_gt.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x4", EFI, 0,
|
{"lv.cmp_gt.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x4", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.cmp_gt.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x5", EFI, 0,
|
{"lv.cmp_gt.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x5", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.cmp_le.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x6", EFI, 0,
|
{"lv.cmp_le.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x6", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.cmp_le.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x7", EFI, 0,
|
{"lv.cmp_le.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x7", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.cmp_lt.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x8", EFI, 0,
|
{"lv.cmp_lt.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x8", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.cmp_lt.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x9", EFI, 0,
|
{"lv.cmp_lt.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0x9", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.cmp_ne.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0xA", EFI, 0,
|
{"lv.cmp_ne.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0xA", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.cmp_ne.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0xB", EFI, 0,
|
{"lv.cmp_ne.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x4 0xB", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.madds.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x4", EFI, 0,
|
{"lv.madds.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x4", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.max.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x5", EFI, 0,
|
{"lv.max.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x5", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.max.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x6", EFI, 0,
|
{"lv.max.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x6", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.merge.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x7", EFI, 0,
|
{"lv.merge.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x7", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.merge.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x8", EFI, 0,
|
{"lv.merge.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x8", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.min.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x9", EFI, 0,
|
{"lv.min.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0x9", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.min.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xA", EFI, 0,
|
{"lv.min.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xA", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.msubs.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xB", EFI, 0,
|
{"lv.msubs.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xB", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.muls.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xC", EFI, 0,
|
{"lv.muls.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xC", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.nand", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xD", EFI, 0,
|
{"lv.nand", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xD", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.nor", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xE", EFI, 0,
|
{"lv.nor", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xE", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.or", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xF", EFI, 0,
|
{"lv.or", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x5 0xF", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.pack.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x0", EFI, 0,
|
{"lv.pack.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x0", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.pack.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x1", EFI, 0,
|
{"lv.pack.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x1", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.packs.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x2", EFI, 0,
|
{"lv.packs.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x2", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.packs.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x3", EFI, 0,
|
{"lv.packs.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x3", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.packus.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x4", EFI, 0,
|
{"lv.packus.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x4", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.packus.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x5", EFI, 0,
|
{"lv.packus.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x5", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.perm.n", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x6", EFI, 0,
|
{"lv.perm.n", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x6", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.rl.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x7", EFI, 0,
|
{"lv.rl.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x7", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.rl.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x8", EFI, 0,
|
{"lv.rl.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x8", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.sll.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x9", EFI, 0,
|
{"lv.sll.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0x9", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.sll.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xA", EFI, 0,
|
{"lv.sll.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xA", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.sll", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xB", EFI, 0,
|
{"lv.sll", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xB", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.srl.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xC", EFI, 0,
|
{"lv.srl.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xC", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.srl.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xD", EFI, 0,
|
{"lv.srl.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xD", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.sra.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xE", EFI, 0,
|
{"lv.sra.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xE", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.sra.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xF", EFI, 0,
|
{"lv.sra.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x6 0xF", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.srl", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x0", EFI, 0,
|
{"lv.srl", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x0", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.sub.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x1", EFI, 0,
|
{"lv.sub.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x1", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.sub.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x2", EFI, 0,
|
{"lv.sub.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x2", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.subs.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x3", EFI, 0,
|
{"lv.subs.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x3", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.subs.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x4", EFI, 0,
|
{"lv.subs.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x4", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.subu.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x5", EFI, 0,
|
{"lv.subu.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x5", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.subu.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x6", EFI, 0,
|
{"lv.subu.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x6", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.subus.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x7", EFI, 0,
|
{"lv.subus.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x7", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.subus.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x8", EFI, 0,
|
{"lv.subus.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x8", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.unpack.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x9", EFI, 0,
|
{"lv.unpack.b", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0x9", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.unpack.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0xA", EFI, 0,
|
{"lv.unpack.h", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0xA", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.xor", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0xB", EFI, 0,
|
{"lv.xor", "rD,rA,rB", "00 0xA DDDDD AAAAA BBBB B--- 0x7 0xB", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.cust1", "", "00 0xA ----- ----- ---- ---- 0xC ----", EFI, 0,
|
{"lv.cust1", "", "00 0xA ----- ----- ---- ---- 0xC ----", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.cust2", "", "00 0xA ----- ----- ---- ---- 0xD ----", EFI, 0,
|
{"lv.cust2", "", "00 0xA ----- ----- ---- ---- 0xD ----", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.cust3", "", "00 0xA ----- ----- ---- ---- 0xE ----", EFI, 0,
|
{"lv.cust3", "", "00 0xA ----- ----- ---- ---- 0xE ----", EFI, 0,
|
it_unknown},
|
it_unknown},
|
{"lv.cust4", "", "00 0xA ----- ----- ---- ---- 0xF ----", EFI, 0,
|
{"lv.cust4", "", "00 0xA ----- ----- ---- ---- 0xF ----", EFI, 0,
|
it_unknown},
|
it_unknown},
|
|
|
{"l.jr", "rB", "01 0x1 ----- ----- BBBB B--- ---- ----",
|
{"l.jr", "rB", "01 0x1 ----- ----- BBBB B--- ---- ----",
|
EF (l_jr), OR32_IF_DELAY, it_jump},
|
EF (l_jr), OR32_IF_DELAY, it_jump},
|
{"l.jalr", "rB", "01 0x2 ----- ----- BBBB B--- ---- ----",
|
{"l.jalr", "rB", "01 0x2 ----- ----- BBBB B--- ---- ----",
|
EF (l_jalr), OR32_IF_DELAY, it_jump},
|
EF (l_jalr), OR32_IF_DELAY, it_jump},
|
{"l.maci", "rA,I", "01 0x3 ----- AAAAA IIII IIII IIII IIII",
|
{"l.maci", "rA,I", "01 0x3 ----- AAAAA IIII IIII IIII IIII",
|
EF (l_mac), 0, it_mac},
|
EF (l_mac), 0, it_mac},
|
{"l.cust1", "", "01 0xC ----- ----- ---- ---- ---- ----",
|
{"l.cust1", "", "01 0xC ----- ----- ---- ---- ---- ----",
|
EF (l_cust1), 0, it_unknown},
|
EF (l_cust1), 0, it_unknown},
|
{"l.cust2", "", "01 0xD ----- ----- ---- ---- ---- ----",
|
{"l.cust2", "", "01 0xD ----- ----- ---- ---- ---- ----",
|
EF (l_cust2), 0, it_unknown},
|
EF (l_cust2), 0, it_unknown},
|
{"l.cust3", "", "01 0xE ----- ----- ---- ---- ---- ----",
|
{"l.cust3", "", "01 0xE ----- ----- ---- ---- ---- ----",
|
EF (l_cust3), 0, it_unknown},
|
EF (l_cust3), 0, it_unknown},
|
{"l.cust4", "", "01 0xF ----- ----- ---- ---- ---- ----",
|
{"l.cust4", "", "01 0xF ----- ----- ---- ---- ---- ----",
|
EF (l_cust4), 0, it_unknown},
|
EF (l_cust4), 0, it_unknown},
|
|
|
{"l.ld", "rD,I(rA)", "10 0x0 DDDDD AAAAA IIII IIII IIII IIII", EFI,
|
{"l.ld", "rD,I(rA)", "10 0x0 DDDDD AAAAA IIII IIII IIII IIII", EFI,
|
0, it_load},
|
0, it_load},
|
{"l.lwz", "rD,I(rA)", "10 0x1 DDDDD AAAAA IIII IIII IIII IIII",
|
{"l.lwz", "rD,I(rA)", "10 0x1 DDDDD AAAAA IIII IIII IIII IIII",
|
EF (l_lwz), 0, it_load},
|
EF (l_lwz), 0, it_load},
|
{"l.lws", "rD,I(rA)", "10 0x2 DDDDD AAAAA IIII IIII IIII IIII",
|
{"l.lws", "rD,I(rA)", "10 0x2 DDDDD AAAAA IIII IIII IIII IIII",
|
EF (l_lws), 0, it_load},
|
EF (l_lws), 0, it_load},
|
{"l.lbz", "rD,I(rA)", "10 0x3 DDDDD AAAAA IIII IIII IIII IIII",
|
{"l.lbz", "rD,I(rA)", "10 0x3 DDDDD AAAAA IIII IIII IIII IIII",
|
EF (l_lbz), 0, it_load},
|
EF (l_lbz), 0, it_load},
|
{"l.lbs", "rD,I(rA)", "10 0x4 DDDDD AAAAA IIII IIII IIII IIII",
|
{"l.lbs", "rD,I(rA)", "10 0x4 DDDDD AAAAA IIII IIII IIII IIII",
|
EF (l_lbs), 0, it_load},
|
EF (l_lbs), 0, it_load},
|
{"l.lhz", "rD,I(rA)", "10 0x5 DDDDD AAAAA IIII IIII IIII IIII",
|
{"l.lhz", "rD,I(rA)", "10 0x5 DDDDD AAAAA IIII IIII IIII IIII",
|
EF (l_lhz), 0, it_load},
|
EF (l_lhz), 0, it_load},
|
{"l.lhs", "rD,I(rA)", "10 0x6 DDDDD AAAAA IIII IIII IIII IIII",
|
{"l.lhs", "rD,I(rA)", "10 0x6 DDDDD AAAAA IIII IIII IIII IIII",
|
EF (l_lhs), 0, it_load},
|
EF (l_lhs), 0, it_load},
|
|
|
{"l.addi", "rD,rA,I", "10 0x7 DDDDD AAAAA IIII IIII IIII IIII",
|
{"l.addi", "rD,rA,I", "10 0x7 DDDDD AAAAA IIII IIII IIII IIII",
|
EF (l_add), OR32_W_FLAG, it_arith},
|
EF (l_add), OR32_W_FLAG, it_arith},
|
{"l.addic", "rD,rA,I", "10 0x8 DDDDD AAAAA IIII IIII IIII IIII",
|
{"l.addic", "rD,rA,I", "10 0x8 DDDDD AAAAA IIII IIII IIII IIII",
|
EF (l_addc), OR32_W_FLAG, it_arith},
|
EF (l_addc), OR32_W_FLAG, it_arith},
|
{"l.andi", "rD,rA,K", "10 0x9 DDDDD AAAAA KKKK KKKK KKKK KKKK",
|
{"l.andi", "rD,rA,K", "10 0x9 DDDDD AAAAA KKKK KKKK KKKK KKKK",
|
EF (l_and), OR32_W_FLAG, it_arith},
|
EF (l_and), OR32_W_FLAG, it_arith},
|
{"l.ori", "rD,rA,K", "10 0xA DDDDD AAAAA KKKK KKKK KKKK KKKK",
|
{"l.ori", "rD,rA,K", "10 0xA DDDDD AAAAA KKKK KKKK KKKK KKKK",
|
EF (l_or), 0, it_arith},
|
EF (l_or), 0, it_arith},
|
|
#if HAVE_UNSIGNED_XORI
|
|
{"l.xori", "rD,rA,K", "10 0xB DDDDD AAAAA KKKK KKKK KKKK KKKK",
|
|
EF (l_xor), 0, it_arith},
|
|
#else
|
{"l.xori", "rD,rA,I", "10 0xB DDDDD AAAAA IIII IIII IIII IIII",
|
{"l.xori", "rD,rA,I", "10 0xB DDDDD AAAAA IIII IIII IIII IIII",
|
EF (l_xor), 0, it_arith},
|
EF (l_xor), 0, it_arith},
|
|
#endif
|
{"l.muli", "rD,rA,I", "10 0xC DDDDD AAAAA IIII IIII IIII IIII",
|
{"l.muli", "rD,rA,I", "10 0xC DDDDD AAAAA IIII IIII IIII IIII",
|
EF (l_mul), 0, it_arith},
|
EF (l_mul), 0, it_arith},
|
{"l.mfspr", "rD,rA,K", "10 0xD DDDDD AAAAA KKKK KKKK KKKK KKKK",
|
{"l.mfspr", "rD,rA,K", "10 0xD DDDDD AAAAA KKKK KKKK KKKK KKKK",
|
EF (l_mfspr), 0, it_move},
|
EF (l_mfspr), 0, it_move},
|
{"l.slli", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 00LL LLLL",
|
{"l.slli", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 00LL LLLL",
|
EF (l_sll), 0, it_shift},
|
EF (l_sll), 0, it_shift},
|
{"l.srli", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 01LL LLLL",
|
{"l.srli", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 01LL LLLL",
|
EF (l_srl), 0, it_shift},
|
EF (l_srl), 0, it_shift},
|
{"l.srai", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 10LL LLLL",
|
{"l.srai", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 10LL LLLL",
|
EF (l_sra), 0, it_shift},
|
EF (l_sra), 0, it_shift},
|
{"l.rori", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 11LL LLLL",
|
{"l.rori", "rD,rA,L", "10 0xE DDDDD AAAAA ---- ---- 11LL LLLL",
|
EF (l_ror), 0, it_shift},
|
EF (l_ror), 0, it_shift},
|
|
|
{"l.sfeqi", "rA,I", "10 0xF 00000 AAAAA IIII IIII IIII IIII",
|
{"l.sfeqi", "rA,I", "10 0xF 00000 AAAAA IIII IIII IIII IIII",
|
EF (l_sfeq), OR32_W_FLAG, it_compare},
|
EF (l_sfeq), OR32_W_FLAG, it_compare},
|
{"l.sfnei", "rA,I", "10 0xF 00001 AAAAA IIII IIII IIII IIII",
|
{"l.sfnei", "rA,I", "10 0xF 00001 AAAAA IIII IIII IIII IIII",
|
EF (l_sfne), OR32_W_FLAG, it_compare},
|
EF (l_sfne), OR32_W_FLAG, it_compare},
|
{"l.sfgtui", "rA,I", "10 0xF 00010 AAAAA IIII IIII IIII IIII",
|
{"l.sfgtui", "rA,I", "10 0xF 00010 AAAAA IIII IIII IIII IIII",
|
EF (l_sfgtu), OR32_W_FLAG, it_compare},
|
EF (l_sfgtu), OR32_W_FLAG, it_compare},
|
{"l.sfgeui", "rA,I", "10 0xF 00011 AAAAA IIII IIII IIII IIII",
|
{"l.sfgeui", "rA,I", "10 0xF 00011 AAAAA IIII IIII IIII IIII",
|
EF (l_sfgeu), OR32_W_FLAG, it_compare},
|
EF (l_sfgeu), OR32_W_FLAG, it_compare},
|
{"l.sfltui", "rA,I", "10 0xF 00100 AAAAA IIII IIII IIII IIII",
|
{"l.sfltui", "rA,I", "10 0xF 00100 AAAAA IIII IIII IIII IIII",
|
EF (l_sfltu), OR32_W_FLAG, it_compare},
|
EF (l_sfltu), OR32_W_FLAG, it_compare},
|
{"l.sfleui", "rA,I", "10 0xF 00101 AAAAA IIII IIII IIII IIII",
|
{"l.sfleui", "rA,I", "10 0xF 00101 AAAAA IIII IIII IIII IIII",
|
EF (l_sfleu), OR32_W_FLAG, it_compare},
|
EF (l_sfleu), OR32_W_FLAG, it_compare},
|
{"l.sfgtsi", "rA,I", "10 0xF 01010 AAAAA IIII IIII IIII IIII",
|
{"l.sfgtsi", "rA,I", "10 0xF 01010 AAAAA IIII IIII IIII IIII",
|
EF (l_sfgts), OR32_W_FLAG, it_compare},
|
EF (l_sfgts), OR32_W_FLAG, it_compare},
|
{"l.sfgesi", "rA,I", "10 0xF 01011 AAAAA IIII IIII IIII IIII",
|
{"l.sfgesi", "rA,I", "10 0xF 01011 AAAAA IIII IIII IIII IIII",
|
EF (l_sfges), OR32_W_FLAG, it_compare},
|
EF (l_sfges), OR32_W_FLAG, it_compare},
|
{"l.sfltsi", "rA,I", "10 0xF 01100 AAAAA IIII IIII IIII IIII",
|
{"l.sfltsi", "rA,I", "10 0xF 01100 AAAAA IIII IIII IIII IIII",
|
EF (l_sflts), OR32_W_FLAG, it_compare},
|
EF (l_sflts), OR32_W_FLAG, it_compare},
|
{"l.sflesi", "rA,I", "10 0xF 01101 AAAAA IIII IIII IIII IIII",
|
{"l.sflesi", "rA,I", "10 0xF 01101 AAAAA IIII IIII IIII IIII",
|
EF (l_sfles), OR32_W_FLAG, it_compare},
|
EF (l_sfles), OR32_W_FLAG, it_compare},
|
|
|
{"l.mtspr", "rA,rB,K", "11 0x0 KKKKK AAAAA BBBB BKKK KKKK KKKK",
|
{"l.mtspr", "rA,rB,K", "11 0x0 KKKKK AAAAA BBBB BKKK KKKK KKKK",
|
EF (l_mtspr), 0, it_move},
|
EF (l_mtspr), 0, it_move},
|
{"l.mac", "rA,rB", "11 0x1 ----- AAAAA BBBB B--- ---- 0x1",
|
{"l.mac", "rA,rB", "11 0x1 ----- AAAAA BBBB B--- ---- 0x1",
|
EF (l_mac), 0, it_mac},
|
EF (l_mac), 0, it_mac},
|
{"l.msb", "rA,rB", "11 0x1 ----- AAAAA BBBB B--- ---- 0x2",
|
{"l.msb", "rA,rB", "11 0x1 ----- AAAAA BBBB B--- ---- 0x2",
|
EF (l_msb), 0, it_mac},
|
EF (l_msb), 0, it_mac},
|
|
|
{"lf.add.s", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x0 0x0",
|
{"lf.add.s", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x0 0x0",
|
EF (lf_add_s), 0, it_float},
|
EF (lf_add_s), 0, it_float},
|
{"lf.sub.s", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x0 0x1",
|
{"lf.sub.s", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x0 0x1",
|
EF (lf_sub_s), 0, it_float},
|
EF (lf_sub_s), 0, it_float},
|
{"lf.mul.s", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x0 0x2",
|
{"lf.mul.s", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x0 0x2",
|
EF (lf_mul_s), 0, it_float},
|
EF (lf_mul_s), 0, it_float},
|
{"lf.div.s", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x0 0x3",
|
{"lf.div.s", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x0 0x3",
|
EF (lf_div_s), 0, it_float},
|
EF (lf_div_s), 0, it_float},
|
{"lf.itof.s", "rD,rA", "11 0x2 DDDDD AAAAA 0000 0--- 0x0 0x4",
|
{"lf.itof.s", "rD,rA", "11 0x2 DDDDD AAAAA 0000 0--- 0x0 0x4",
|
EF (lf_itof_s), 0, it_float},
|
EF (lf_itof_s), 0, it_float},
|
{"lf.ftoi.s", "rD,rA", "11 0x2 DDDDD AAAAA 0000 0--- 0x0 0x5",
|
{"lf.ftoi.s", "rD,rA", "11 0x2 DDDDD AAAAA 0000 0--- 0x0 0x5",
|
EF (lf_ftoi_s), 0, it_float},
|
EF (lf_ftoi_s), 0, it_float},
|
{"lf.rem.s", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x0 0x6",
|
{"lf.rem.s", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x0 0x6",
|
EF (lf_rem_s), 0, it_float},
|
EF (lf_rem_s), 0, it_float},
|
{"lf.madd.s", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x0 0x7",
|
{"lf.madd.s", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x0 0x7",
|
EF (lf_madd_s), 0, it_float},
|
EF (lf_madd_s), 0, it_float},
|
{"lf.sfeq.s", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x0 0x8",
|
{"lf.sfeq.s", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x0 0x8",
|
EF (lf_sfeq_s), 0, it_float},
|
EF (lf_sfeq_s), 0, it_float},
|
{"lf.sfne.s", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x0 0x9",
|
{"lf.sfne.s", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x0 0x9",
|
EF (lf_sfne_s), 0, it_float},
|
EF (lf_sfne_s), 0, it_float},
|
{"lf.sfgt.s", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x0 0xA",
|
{"lf.sfgt.s", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x0 0xA",
|
EF (lf_sfgt_s), 0, it_float},
|
EF (lf_sfgt_s), 0, it_float},
|
{"lf.sfge.s", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x0 0xB",
|
{"lf.sfge.s", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x0 0xB",
|
EF (lf_sfge_s), 0, it_float},
|
EF (lf_sfge_s), 0, it_float},
|
{"lf.sflt.s", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x0 0xC",
|
{"lf.sflt.s", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x0 0xC",
|
EF (lf_sflt_s), 0, it_float},
|
EF (lf_sflt_s), 0, it_float},
|
{"lf.sfle.s", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x0 0xD",
|
{"lf.sfle.s", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x0 0xD",
|
EF (lf_sfle_s), 0, it_float},
|
EF (lf_sfle_s), 0, it_float},
|
{"lf.cust1.s", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0xD ----", EFI,
|
{"lf.cust1.s", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0xD ----", EFI,
|
0, it_float},
|
0, it_float},
|
|
|
{"lf.add.d", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0,
|
{"lf.add.d", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x1 0x0", EFI, 0,
|
it_float},
|
it_float},
|
{"lf.sub.d", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0,
|
{"lf.sub.d", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x1 0x1", EFI, 0,
|
it_float},
|
it_float},
|
{"lf.mul.d", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0,
|
{"lf.mul.d", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x1 0x2", EFI, 0,
|
it_float},
|
it_float},
|
{"lf.div.d", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0,
|
{"lf.div.d", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x1 0x3", EFI, 0,
|
it_float},
|
it_float},
|
{"lf.itof.d", "rD,rA", "11 0x2 DDDDD AAAAA 0000 0--- 0x1 0x4", EFI, 0,
|
{"lf.itof.d", "rD,rA", "11 0x2 DDDDD AAAAA 0000 0--- 0x1 0x4", EFI, 0,
|
it_float},
|
it_float},
|
{"lf.ftoi.d", "rD,rA", "11 0x2 DDDDD AAAAA 0000 0--- 0x1 0x5", EFI, 0,
|
{"lf.ftoi.d", "rD,rA", "11 0x2 DDDDD AAAAA 0000 0--- 0x1 0x5", EFI, 0,
|
it_float},
|
it_float},
|
{"lf.rem.d", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0,
|
{"lf.rem.d", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x1 0x6", EFI, 0,
|
it_float},
|
it_float},
|
{"lf.madd.d", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0,
|
{"lf.madd.d", "rD,rA,rB", "11 0x2 DDDDD AAAAA BBBB B--- 0x1 0x7", EFI, 0,
|
it_float},
|
it_float},
|
{"lf.sfeq.d", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x1 0x8", EFI, 0,
|
{"lf.sfeq.d", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x1 0x8", EFI, 0,
|
it_float},
|
it_float},
|
{"lf.sfne.d", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x1 0x9", EFI, 0,
|
{"lf.sfne.d", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x1 0x9", EFI, 0,
|
it_float},
|
it_float},
|
{"lf.sfgt.d", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x1 0xA", EFI, 0,
|
{"lf.sfgt.d", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x1 0xA", EFI, 0,
|
it_float},
|
it_float},
|
{"lf.sfge.d", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x1 0xB", EFI, 0,
|
{"lf.sfge.d", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x1 0xB", EFI, 0,
|
it_float},
|
it_float},
|
{"lf.sflt.d", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x1 0xC", EFI, 0,
|
{"lf.sflt.d", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x1 0xC", EFI, 0,
|
it_float},
|
it_float},
|
{"lf.sfle.d", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x1 0xD", EFI, 0,
|
{"lf.sfle.d", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0x1 0xD", EFI, 0,
|
it_float},
|
it_float},
|
{"lf.cust1.d", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0xE ----", EFI, 0,
|
{"lf.cust1.d", "rA,rB", "11 0x2 ----- AAAAA BBBB B--- 0xE ----", EFI, 0,
|
it_float},
|
it_float},
|
|
|
{"l.sd", "I(rA),rB", "11 0x4 IIIII AAAAA BBBB BIII IIII IIII", EFI,
|
{"l.sd", "I(rA),rB", "11 0x4 IIIII AAAAA BBBB BIII IIII IIII", EFI,
|
0, it_store},
|
0, it_store},
|
{"l.sw", "I(rA),rB", "11 0x5 IIIII AAAAA BBBB BIII IIII IIII",
|
{"l.sw", "I(rA),rB", "11 0x5 IIIII AAAAA BBBB BIII IIII IIII",
|
EF (l_sw), 0, it_store},
|
EF (l_sw), 0, it_store},
|
{"l.sb", "I(rA),rB", "11 0x6 IIIII AAAAA BBBB BIII IIII IIII",
|
{"l.sb", "I(rA),rB", "11 0x6 IIIII AAAAA BBBB BIII IIII IIII",
|
EF (l_sb), 0, it_store},
|
EF (l_sb), 0, it_store},
|
{"l.sh", "I(rA),rB", "11 0x7 IIIII AAAAA BBBB BIII IIII IIII",
|
{"l.sh", "I(rA),rB", "11 0x7 IIIII AAAAA BBBB BIII IIII IIII",
|
EF (l_sh), 0, it_store},
|
EF (l_sh), 0, it_store},
|
|
|
{"l.add", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x0",
|
{"l.add", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x0",
|
EF (l_add), OR32_W_FLAG, it_arith},
|
EF (l_add), OR32_W_FLAG, it_arith},
|
{"l.addc", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x1",
|
{"l.addc", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x1",
|
EF (l_addc), OR32_W_FLAG, it_arith},
|
EF (l_addc), OR32_W_FLAG, it_arith},
|
{"l.sub", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x2",
|
{"l.sub", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x2",
|
EF (l_sub), 0, it_arith},
|
EF (l_sub), 0, it_arith},
|
{"l.and", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x3",
|
{"l.and", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x3",
|
EF (l_and), OR32_W_FLAG, it_arith},
|
EF (l_and), OR32_W_FLAG, it_arith},
|
{"l.or", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x4",
|
{"l.or", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x4",
|
EF (l_or), 0, it_arith},
|
EF (l_or), 0, it_arith},
|
{"l.xor", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x5",
|
{"l.xor", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0x5",
|
EF (l_xor), 0, it_arith},
|
EF (l_xor), 0, it_arith},
|
{"l.mul", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0x6",
|
{"l.mul", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0x6",
|
EF (l_mul), 0, it_arith},
|
EF (l_mul), 0, it_arith},
|
|
|
{"l.sll", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 00-- 0x8",
|
{"l.sll", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 00-- 0x8",
|
EF (l_sll), 0, it_shift},
|
EF (l_sll), 0, it_shift},
|
{"l.srl", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 01-- 0x8",
|
{"l.srl", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 01-- 0x8",
|
EF (l_srl), 0, it_shift},
|
EF (l_srl), 0, it_shift},
|
{"l.sra", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 10-- 0x8",
|
{"l.sra", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 10-- 0x8",
|
EF (l_sra), 0, it_shift},
|
EF (l_sra), 0, it_shift},
|
{"l.ror", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 11-- 0x8",
|
{"l.ror", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 11-- 0x8",
|
EF (l_ror), 0, it_shift},
|
EF (l_ror), 0, it_shift},
|
{"l.div", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0x9",
|
{"l.div", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0x9",
|
EF (l_div), 0, it_arith},
|
EF (l_div), 0, it_arith},
|
{"l.divu", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0xA",
|
{"l.divu", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0xA",
|
EF (l_divu), 0, it_arith},
|
EF (l_divu), 0, it_arith},
|
{"l.mulu", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0xB",
|
{"l.mulu", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-11 ---- 0xB",
|
EF (l_mulu), 0, it_arith},
|
EF (l_mulu), 0, it_arith},
|
{"l.extbs", "rD,rA", "11 0x8 DDDDD AAAAA ---- --00 01-- 0xC",
|
{"l.extbs", "rD,rA", "11 0x8 DDDDD AAAAA ---- --00 01-- 0xC",
|
EF (l_extbs), 0, it_move},
|
EF (l_extbs), 0, it_move},
|
{"l.exths", "rD,rA", "11 0x8 DDDDD AAAAA ---- --00 00-- 0xC",
|
{"l.exths", "rD,rA", "11 0x8 DDDDD AAAAA ---- --00 00-- 0xC",
|
EF (l_exths), 0, it_move},
|
EF (l_exths), 0, it_move},
|
{"l.extws", "rD,rA", "11 0x8 DDDDD AAAAA ---- --00 00-- 0xD",
|
{"l.extws", "rD,rA", "11 0x8 DDDDD AAAAA ---- --00 00-- 0xD",
|
EF (l_extws), 0, it_move},
|
EF (l_extws), 0, it_move},
|
{"l.extbz", "rD,rA", "11 0x8 DDDDD AAAAA ---- --00 11-- 0xC",
|
{"l.extbz", "rD,rA", "11 0x8 DDDDD AAAAA ---- --00 11-- 0xC",
|
EF (l_extbz), 0, it_move},
|
EF (l_extbz), 0, it_move},
|
{"l.exthz", "rD,rA", "11 0x8 DDDDD AAAAA ---- --00 10-- 0xC",
|
{"l.exthz", "rD,rA", "11 0x8 DDDDD AAAAA ---- --00 10-- 0xC",
|
EF (l_exthz), 0, it_move},
|
EF (l_exthz), 0, it_move},
|
{"l.extwz", "rD,rA", "11 0x8 DDDDD AAAAA ---- --00 01-- 0xD",
|
{"l.extwz", "rD,rA", "11 0x8 DDDDD AAAAA ---- --00 01-- 0xD",
|
EF (l_extwz), 0, it_move},
|
EF (l_extwz), 0, it_move},
|
{"l.cmov", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0xE",
|
{"l.cmov", "rD,rA,rB", "11 0x8 DDDDD AAAAA BBBB B-00 ---- 0xE",
|
EF (l_cmov), OR32_R_FLAG, it_move},
|
EF (l_cmov), OR32_R_FLAG, it_move},
|
{"l.ff1", "rD,rA", "11 0x8 DDDDD AAAAA ---- --00 ---- 0xF",
|
{"l.ff1", "rD,rA", "11 0x8 DDDDD AAAAA ---- --00 ---- 0xF",
|
EF (l_ff1), 0, it_arith},
|
EF (l_ff1), 0, it_arith},
|
{"l.fl1", "rD,rA", "11 0x8 DDDDD AAAAA ---- --01 ---- 0xF",
|
{"l.fl1", "rD,rA", "11 0x8 DDDDD AAAAA ---- --01 ---- 0xF",
|
EF (l_fl1), 0, it_arith},
|
EF (l_fl1), 0, it_arith},
|
|
|
{"l.sfeq", "rA,rB", "11 0x9 00000 AAAAA BBBB B--- ---- ----",
|
{"l.sfeq", "rA,rB", "11 0x9 00000 AAAAA BBBB B--- ---- ----",
|
EF (l_sfeq), OR32_W_FLAG, it_compare},
|
EF (l_sfeq), OR32_W_FLAG, it_compare},
|
{"l.sfne", "rA,rB", "11 0x9 00001 AAAAA BBBB B--- ---- ----",
|
{"l.sfne", "rA,rB", "11 0x9 00001 AAAAA BBBB B--- ---- ----",
|
EF (l_sfne), OR32_W_FLAG, it_compare},
|
EF (l_sfne), OR32_W_FLAG, it_compare},
|
{"l.sfgtu", "rA,rB", "11 0x9 00010 AAAAA BBBB B--- ---- ----",
|
{"l.sfgtu", "rA,rB", "11 0x9 00010 AAAAA BBBB B--- ---- ----",
|
EF (l_sfgtu), OR32_W_FLAG, it_compare},
|
EF (l_sfgtu), OR32_W_FLAG, it_compare},
|
{"l.sfgeu", "rA,rB", "11 0x9 00011 AAAAA BBBB B--- ---- ----",
|
{"l.sfgeu", "rA,rB", "11 0x9 00011 AAAAA BBBB B--- ---- ----",
|
EF (l_sfgeu), OR32_W_FLAG, it_compare},
|
EF (l_sfgeu), OR32_W_FLAG, it_compare},
|
{"l.sfltu", "rA,rB", "11 0x9 00100 AAAAA BBBB B--- ---- ----",
|
{"l.sfltu", "rA,rB", "11 0x9 00100 AAAAA BBBB B--- ---- ----",
|
EF (l_sfltu), OR32_W_FLAG, it_compare},
|
EF (l_sfltu), OR32_W_FLAG, it_compare},
|
{"l.sfleu", "rA,rB", "11 0x9 00101 AAAAA BBBB B--- ---- ----",
|
{"l.sfleu", "rA,rB", "11 0x9 00101 AAAAA BBBB B--- ---- ----",
|
EF (l_sfleu), OR32_W_FLAG, it_compare},
|
EF (l_sfleu), OR32_W_FLAG, it_compare},
|
{"l.sfgts", "rA,rB", "11 0x9 01010 AAAAA BBBB B--- ---- ----",
|
{"l.sfgts", "rA,rB", "11 0x9 01010 AAAAA BBBB B--- ---- ----",
|
EF (l_sfgts), OR32_W_FLAG, it_compare},
|
EF (l_sfgts), OR32_W_FLAG, it_compare},
|
{"l.sfges", "rA,rB", "11 0x9 01011 AAAAA BBBB B--- ---- ----",
|
{"l.sfges", "rA,rB", "11 0x9 01011 AAAAA BBBB B--- ---- ----",
|
EF (l_sfges), OR32_W_FLAG, it_compare},
|
EF (l_sfges), OR32_W_FLAG, it_compare},
|
{"l.sflts", "rA,rB", "11 0x9 01100 AAAAA BBBB B--- ---- ----",
|
{"l.sflts", "rA,rB", "11 0x9 01100 AAAAA BBBB B--- ---- ----",
|
EF (l_sflts), OR32_W_FLAG, it_compare},
|
EF (l_sflts), OR32_W_FLAG, it_compare},
|
{"l.sfles", "rA,rB", "11 0x9 01101 AAAAA BBBB B--- ---- ----",
|
{"l.sfles", "rA,rB", "11 0x9 01101 AAAAA BBBB B--- ---- ----",
|
EF (l_sfles), OR32_W_FLAG, it_compare},
|
EF (l_sfles), OR32_W_FLAG, it_compare},
|
|
|
{"l.cust5", "rD,rA,rB,L,K", "11 0xC DDDDD AAAAA BBBB BLLL LLLK KKKK", EFI,
|
{"l.cust5", "rD,rA,rB,L,K", "11 0xC DDDDD AAAAA BBBB BLLL LLLK KKKK", EFI,
|
0, it_unknown},
|
0, it_unknown},
|
{"l.cust6", "", "11 0xD ----- ----- ---- ---- ---- ----", EFI,
|
{"l.cust6", "", "11 0xD ----- ----- ---- ---- ---- ----", EFI,
|
0, it_unknown},
|
0, it_unknown},
|
{"l.cust7", "", "11 0xE ----- ----- ---- ---- ---- ----", EFI,
|
{"l.cust7", "", "11 0xE ----- ----- ---- ---- ---- ----", EFI,
|
0, it_unknown},
|
0, it_unknown},
|
{"l.cust8", "", "11 0xF ----- ----- ---- ---- ---- ----", EFI,
|
{"l.cust8", "", "11 0xF ----- ----- ---- ---- ---- ----", EFI,
|
0, it_unknown},
|
0, it_unknown},
|
|
|
/* This section should not be defined in or1ksim, since it contains duplicates,
|
/* This section should not be defined in or1ksim, since it contains duplicates,
|
which would cause machine builder to complain. */
|
which would cause machine builder to complain. */
|
#ifdef HAS_CUST
|
#ifdef HAS_CUST
|
{"l.cust5_1", "rD", "11 0xC DDDDD ----- ---- ---- ---- ----", EFI,
|
{"l.cust5_1", "rD", "11 0xC DDDDD ----- ---- ---- ---- ----", EFI,
|
0, it_unknown},
|
0, it_unknown},
|
{"l.cust5_2", "rD,rA", "11 0xC DDDDD AAAAA ---- ---- ---- ----", EFI,
|
{"l.cust5_2", "rD,rA", "11 0xC DDDDD AAAAA ---- ---- ---- ----", EFI,
|
0, it_unknown},
|
0, it_unknown},
|
{"l.cust5_3", "rD,rA,rB", "11 0xC DDDDD AAAAA BBBB B--- ---- ----", EFI,
|
{"l.cust5_3", "rD,rA,rB", "11 0xC DDDDD AAAAA BBBB B--- ---- ----", EFI,
|
0, it_unknown},
|
0, it_unknown},
|
|
|
{"l.cust6_1", "rD", "11 0xD DDDDD ----- ---- ---- ---- ----", EFI,
|
{"l.cust6_1", "rD", "11 0xD DDDDD ----- ---- ---- ---- ----", EFI,
|
0, it_unknown},
|
0, it_unknown},
|
{"l.cust6_2", "rD,rA", "11 0xD DDDDD AAAAA ---- ---- ---- ----", EFI,
|
{"l.cust6_2", "rD,rA", "11 0xD DDDDD AAAAA ---- ---- ---- ----", EFI,
|
0, it_unknown},
|
0, it_unknown},
|
{"l.cust6_3", "rD,rA,rB", "11 0xD DDDDD AAAAA BBBB B--- ---- ----", EFI,
|
{"l.cust6_3", "rD,rA,rB", "11 0xD DDDDD AAAAA BBBB B--- ---- ----", EFI,
|
0, it_unknown},
|
0, it_unknown},
|
|
|
{"l.cust7_1", "rD", "11 0xE DDDDD ----- ---- ---- ---- ----", EFI,
|
{"l.cust7_1", "rD", "11 0xE DDDDD ----- ---- ---- ---- ----", EFI,
|
0, it_unknown},
|
0, it_unknown},
|
{"l.cust7_2", "rD,rA", "11 0xE DDDDD AAAAA ---- ---- ---- ----", EFI,
|
{"l.cust7_2", "rD,rA", "11 0xE DDDDD AAAAA ---- ---- ---- ----", EFI,
|
0, it_unknown},
|
0, it_unknown},
|
{"l.cust7_3", "rD,rA,rB", "11 0xE DDDDD AAAAA BBBB B--- ---- ----", EFI,
|
{"l.cust7_3", "rD,rA,rB", "11 0xE DDDDD AAAAA BBBB B--- ---- ----", EFI,
|
0, it_unknown},
|
0, it_unknown},
|
|
|
{"l.cust8_1", "rD", "11 0xF DDDDD ----- ---- ---- ---- ----", EFI,
|
{"l.cust8_1", "rD", "11 0xF DDDDD ----- ---- ---- ---- ----", EFI,
|
0, it_unknown},
|
0, it_unknown},
|
{"l.cust8_2", "rD,rA", "11 0xF DDDDD AAAAA ---- ---- ---- ----", EFI,
|
{"l.cust8_2", "rD,rA", "11 0xF DDDDD AAAAA ---- ---- ---- ----", EFI,
|
0, it_unknown},
|
0, it_unknown},
|
{"l.cust8_3", "rD,rA,rB", "11 0xF DDDDD AAAAA BBBB B--- ---- ----", EFI,
|
{"l.cust8_3", "rD,rA,rB", "11 0xF DDDDD AAAAA BBBB B--- ---- ----", EFI,
|
0, it_unknown},
|
0, it_unknown},
|
#endif
|
#endif
|
|
|
{"", "", "", EFI, 0, 0} /* Dummy entry, not included in num_opcodes. This
|
{"", "", "", EFI, 0, 0} /* Dummy entry, not included in num_opcodes. This
|
* lets code examine entry i+1 without checking
|
* lets code examine entry i+1 without checking
|
* if we've run off the end of the table. */
|
* if we've run off the end of the table. */
|
};
|
};
|
|
|
#undef EFI
|
#undef EFI
|
#undef EFN
|
#undef EFN
|
#undef EF
|
#undef EF
|
|
|
CONST int num_opcodes =
|
CONST int num_opcodes =
|
((sizeof (or32_opcodes)) / (sizeof (struct or32_opcode))) - 1;
|
((sizeof (or32_opcodes)) / (sizeof (struct or32_opcode))) - 1;
|
|
|
/* Calculates instruction length in bytes. Always 4 for OR32. */
|
/* Calculates instruction length in bytes. Always 4 for OR32. */
|
int
|
int
|
insn_len (int insn_index)
|
insn_len (int insn_index)
|
{
|
{
|
insn_index = 0; /* Just to get rid that warning. */
|
insn_index = 0; /* Just to get rid that warning. */
|
return 4;
|
return 4;
|
}
|
}
|
|
|
/* Is individual insn's operand signed or unsigned? */
|
/* Is individual insn's operand signed or unsigned? */
|
int
|
int
|
letter_signed (char l)
|
letter_signed (char l)
|
{
|
{
|
CONST struct or32_letter *pletter;
|
CONST struct or32_letter *pletter;
|
|
|
for (pletter = or32_letters; pletter->letter != '\0'; pletter++)
|
for (pletter = or32_letters; pletter->letter != '\0'; pletter++)
|
if (pletter->letter == l)
|
if (pletter->letter == l)
|
return pletter->sign;
|
return pletter->sign;
|
|
|
printf ("letter_signed(%c): Unknown letter.\n", l);
|
printf ("letter_signed(%c): Unknown letter.\n", l);
|
return 0;
|
return 0;
|
}
|
}
|
|
|
/* Simple cache for letter ranges */
|
/* Simple cache for letter ranges */
|
static int range_cache[256] = { 0 };
|
static int range_cache[256] = { 0 };
|
|
|
/* Number of letters in the individual lettered operand. */
|
/* Number of letters in the individual lettered operand. */
|
int
|
int
|
letter_range (char l)
|
letter_range (char l)
|
{
|
{
|
CONST struct or32_opcode *pinsn;
|
CONST struct or32_opcode *pinsn;
|
char *enc;
|
char *enc;
|
int range = 0;
|
int range = 0;
|
|
|
/* Is value cached? */
|
/* Is value cached? */
|
if ((range = range_cache[(unsigned char) l]))
|
if ((range = range_cache[(unsigned char) l]))
|
return range;
|
return range;
|
|
|
for (pinsn = or32_opcodes; strlen (pinsn->name); pinsn++)
|
for (pinsn = or32_opcodes; strlen (pinsn->name); pinsn++)
|
{
|
{
|
if (strchr (pinsn->encoding, l))
|
if (strchr (pinsn->encoding, l))
|
{
|
{
|
for (enc = pinsn->encoding; *enc != '\0'; enc++)
|
for (enc = pinsn->encoding; *enc != '\0'; enc++)
|
if ((*enc == '0') && (*(enc + 1) == 'x'))
|
if ((*enc == '0') && (*(enc + 1) == 'x'))
|
enc += 2;
|
enc += 2;
|
else if (*enc == l)
|
else if (*enc == l)
|
range++;
|
range++;
|
return range_cache[(unsigned char) l] = range;
|
return range_cache[(unsigned char) l] = range;
|
}
|
}
|
}
|
}
|
|
|
printf ("\nABORT: letter_range(%c): Never used letter.\n", l);
|
printf ("\nABORT: letter_range(%c): Never used letter.\n", l);
|
exit (1);
|
exit (1);
|
}
|
}
|
|
|
/* MM: Returns index of given instruction name. */
|
/* MM: Returns index of given instruction name. */
|
int
|
int
|
insn_index (char *insn)
|
insn_index (char *insn)
|
{
|
{
|
int i, found = -1;
|
int i, found = -1;
|
for (i = 0; i < num_opcodes; i++)
|
for (i = 0; i < num_opcodes; i++)
|
if (!strcmp (or32_opcodes[i].name, insn))
|
if (!strcmp (or32_opcodes[i].name, insn))
|
{
|
{
|
found = i;
|
found = i;
|
break;
|
break;
|
}
|
}
|
return found;
|
return found;
|
}
|
}
|
|
|
/* Returns name of the specified instruction index */
|
/* Returns name of the specified instruction index */
|
CONST char *
|
CONST char *
|
insn_name (int index)
|
insn_name (int index)
|
{
|
{
|
if (index >= 0 && index < num_opcodes)
|
if (index >= 0 && index < num_opcodes)
|
return or32_opcodes[index].name;
|
return or32_opcodes[index].name;
|
else
|
else
|
return "???";
|
return "???";
|
}
|
}
|
|
|
#if defined(HAVE_EXECUTION) && SIMPLE_EXECUTION
|
#if defined(HAVE_EXECUTION) && SIMPLE_EXECUTION
|
void
|
void
|
l_none (struct iqueue_entry *current)
|
l_none (struct iqueue_entry *current)
|
{
|
{
|
}
|
}
|
#elif defined(HAVE_EXECUTION) && DYNAMIC_EXECUTION
|
#elif defined(HAVE_EXECUTION) && DYNAMIC_EXECUTION
|
void
|
void
|
l_none (struct op_queue *opq, int *param_t, int delay_slot)
|
l_none (struct op_queue *opq, int *param_t, int delay_slot)
|
{
|
{
|
}
|
}
|
#else
|
#else
|
void
|
void
|
l_none ()
|
l_none ()
|
{
|
{
|
}
|
}
|
#endif
|
#endif
|
|
|
/*** Finite automata for instruction decoding building code ***/
|
/*** Finite automata for instruction decoding building code ***/
|
|
|
/* Find symbols in encoding. */
|
/* Find symbols in encoding. */
|
unsigned long
|
unsigned long
|
insn_extract (param_ch, enc_initial)
|
insn_extract (param_ch, enc_initial)
|
char param_ch;
|
char param_ch;
|
char *enc_initial;
|
char *enc_initial;
|
{
|
{
|
char *enc;
|
char *enc;
|
unsigned long ret = 0;
|
unsigned long ret = 0;
|
unsigned opc_pos = 32;
|
unsigned opc_pos = 32;
|
for (enc = enc_initial; *enc != '\0';)
|
for (enc = enc_initial; *enc != '\0';)
|
if ((*enc == '0') && (*(enc + 1) == 'x'))
|
if ((*enc == '0') && (*(enc + 1) == 'x'))
|
{
|
{
|
unsigned long tmp = strtol (enc + 2, NULL, 16);
|
unsigned long tmp = strtol (enc + 2, NULL, 16);
|
opc_pos -= 4;
|
opc_pos -= 4;
|
if (param_ch == '0' || param_ch == '1')
|
if (param_ch == '0' || param_ch == '1')
|
{
|
{
|
if (param_ch == '0')
|
if (param_ch == '0')
|
tmp = 15 - tmp;
|
tmp = 15 - tmp;
|
ret |= tmp << opc_pos;
|
ret |= tmp << opc_pos;
|
}
|
}
|
enc += 3;
|
enc += 3;
|
}
|
}
|
else
|
else
|
{
|
{
|
if (*enc == '0' || *enc == '1' || *enc == '-' || isalpha (*enc))
|
if (*enc == '0' || *enc == '1' || *enc == '-' || isalpha (*enc))
|
{
|
{
|
opc_pos--;
|
opc_pos--;
|
if (param_ch == *enc)
|
if (param_ch == *enc)
|
ret |= 1 << opc_pos;
|
ret |= 1 << opc_pos;
|
}
|
}
|
enc++;
|
enc++;
|
}
|
}
|
return ret;
|
return ret;
|
}
|
}
|
|
|
#define MAX_AUTOMATA_SIZE (1200)
|
#define MAX_AUTOMATA_SIZE (1200)
|
#define MAX_OP_TABLE_SIZE (1200)
|
#define MAX_OP_TABLE_SIZE (1200)
|
#define MAX_LEN (8)
|
#define MAX_LEN (8)
|
|
|
#ifndef MIN
|
#ifndef MIN
|
# define MIN(x,y) ((x) < (y) ? (x) : (y))
|
# define MIN(x,y) ((x) < (y) ? (x) : (y))
|
#endif
|
#endif
|
|
|
unsigned long *automata;
|
unsigned long *automata;
|
int nuncovered;
|
int nuncovered;
|
int curpass = 0;
|
int curpass = 0;
|
|
|
/* MM: Struct that holds runtime build information about instructions. */
|
/* MM: Struct that holds runtime build information about instructions. */
|
struct temp_insn_struct *ti;
|
struct temp_insn_struct *ti;
|
|
|
struct insn_op_struct *op_data, **op_start;
|
struct insn_op_struct *op_data, **op_start;
|
|
|
static void
|
static void
|
or32_debug (int level, const char *format, ...)
|
or32_debug (int level, const char *format, ...)
|
{
|
{
|
#if DEBUG
|
#if DEBUG
|
char *p;
|
char *p;
|
va_list ap;
|
va_list ap;
|
|
|
if ((p = malloc (1000)) == NULL)
|
if ((p = malloc (1000)) == NULL)
|
return;
|
return;
|
va_start (ap, format);
|
va_start (ap, format);
|
(void) vsnprintf (p, 1000, format, ap);
|
(void) vsnprintf (p, 1000, format, ap);
|
va_end (ap);
|
va_end (ap);
|
printf ("%s\n", p);
|
printf ("%s\n", p);
|
fflush (stdout);
|
fflush (stdout);
|
free (p);
|
free (p);
|
#endif
|
#endif
|
}
|
}
|
|
|
/* Recursive utility function used to find best match and to build automata. */
|
/* Recursive utility function used to find best match and to build automata. */
|
static unsigned long *
|
static unsigned long *
|
cover_insn (unsigned long *cur, int pass, unsigned int mask)
|
cover_insn (unsigned long *cur, int pass, unsigned int mask)
|
{
|
{
|
int best_first = 0, best_len = 0, i, last_match = -1, ninstr = 0;
|
int best_first = 0, best_len = 0, i, last_match = -1, ninstr = 0;
|
unsigned long cur_mask = mask;
|
unsigned long cur_mask = mask;
|
unsigned long *next;
|
unsigned long *next;
|
|
|
for (i = 0; i < num_opcodes; i++)
|
for (i = 0; i < num_opcodes; i++)
|
if (ti[i].in_pass == pass)
|
if (ti[i].in_pass == pass)
|
{
|
{
|
cur_mask &= ti[i].insn_mask;
|
cur_mask &= ti[i].insn_mask;
|
ninstr++;
|
ninstr++;
|
last_match = i;
|
last_match = i;
|
}
|
}
|
|
|
or32_debug (8, "%08X %08lX\n", mask, cur_mask);
|
or32_debug (8, "%08X %08lX\n", mask, cur_mask);
|
if (ninstr == 0)
|
if (ninstr == 0)
|
return 0;
|
return 0;
|
if (ninstr == 1)
|
if (ninstr == 1)
|
{
|
{
|
/* Leaf holds instruction index. */
|
/* Leaf holds instruction index. */
|
or32_debug (8, "%i>I%i %s\n", cur - automata, last_match,
|
or32_debug (8, "%i>I%i %s\n", cur - automata, last_match,
|
or32_opcodes[last_match].name);
|
or32_opcodes[last_match].name);
|
*cur = LEAF_FLAG | last_match;
|
*cur = LEAF_FLAG | last_match;
|
cur++;
|
cur++;
|
nuncovered--;
|
nuncovered--;
|
}
|
}
|
else
|
else
|
{
|
{
|
/* Find longest match. */
|
/* Find longest match. */
|
for (i = 0; i < 32; i++)
|
for (i = 0; i < 32; i++)
|
{
|
{
|
int len;
|
int len;
|
for (len = best_len + 1; len < MIN (MAX_LEN, 33 - i); len++)
|
for (len = best_len + 1; len < MIN (MAX_LEN, 33 - i); len++)
|
{
|
{
|
unsigned long m = (1UL << ((unsigned long) len)) - 1;
|
unsigned long m = (1UL << ((unsigned long) len)) - 1;
|
or32_debug (9, " (%i(%08lX & %08lX>>%i = %08lX, %08lX)", len, m,
|
or32_debug (9, " (%i(%08lX & %08lX>>%i = %08lX, %08lX)", len, m,
|
cur_mask, i, (cur_mask >> (unsigned) i),
|
cur_mask, i, (cur_mask >> (unsigned) i),
|
(cur_mask >> (unsigned) i) & m);
|
(cur_mask >> (unsigned) i) & m);
|
if ((m & (cur_mask >> (unsigned) i)) == m)
|
if ((m & (cur_mask >> (unsigned) i)) == m)
|
{
|
{
|
best_len = len;
|
best_len = len;
|
best_first = i;
|
best_first = i;
|
or32_debug (9, "!");
|
or32_debug (9, "!");
|
}
|
}
|
else
|
else
|
break;
|
break;
|
}
|
}
|
}
|
}
|
or32_debug (9, "\n");
|
or32_debug (9, "\n");
|
if (!best_len)
|
if (!best_len)
|
{
|
{
|
fprintf (stderr, "%i instructions match mask 0x%08X:\n", ninstr,
|
fprintf (stderr, "%i instructions match mask 0x%08X:\n", ninstr,
|
mask);
|
mask);
|
for (i = 0; i < num_opcodes; i++)
|
for (i = 0; i < num_opcodes; i++)
|
if (ti[i].in_pass == pass)
|
if (ti[i].in_pass == pass)
|
fprintf (stderr, "%s ", or32_opcodes[i].name);
|
fprintf (stderr, "%s ", or32_opcodes[i].name);
|
|
|
fprintf (stderr, "\n");
|
fprintf (stderr, "\n");
|
exit (1);
|
exit (1);
|
}
|
}
|
or32_debug (8, "%i> #### %i << %i (%i) ####\n", cur - automata, best_len,
|
or32_debug (8, "%i> #### %i << %i (%i) ####\n", cur - automata, best_len,
|
best_first, ninstr);
|
best_first, ninstr);
|
*cur = best_first;
|
*cur = best_first;
|
cur++;
|
cur++;
|
*cur = (1 << best_len) - 1;
|
*cur = (1 << best_len) - 1;
|
cur++;
|
cur++;
|
next = cur;
|
next = cur;
|
/* Allocate space for pointers. */
|
/* Allocate space for pointers. */
|
cur += 1 << best_len;
|
cur += 1 << best_len;
|
cur_mask = (1 << (unsigned long) best_len) - 1;
|
cur_mask = (1 << (unsigned long) best_len) - 1;
|
|
|
for (i = 0; i < (1 << (unsigned long) best_len); i++)
|
for (i = 0; i < (1 << (unsigned long) best_len); i++)
|
{
|
{
|
int j;
|
int j;
|
unsigned long *c;
|
unsigned long *c;
|
curpass++;
|
curpass++;
|
for (j = 0; j < num_opcodes; j++)
|
for (j = 0; j < num_opcodes; j++)
|
if (ti[j].in_pass == pass
|
if (ti[j].in_pass == pass
|
&& ((ti[j].insn >> best_first) & cur_mask) ==
|
&& ((ti[j].insn >> best_first) & cur_mask) ==
|
(unsigned long) i
|
(unsigned long) i
|
&& ((ti[j].insn_mask >> best_first) & cur_mask) == cur_mask)
|
&& ((ti[j].insn_mask >> best_first) & cur_mask) == cur_mask)
|
ti[j].in_pass = curpass;
|
ti[j].in_pass = curpass;
|
|
|
or32_debug (9, "%08X %08lX %i\n", mask, cur_mask, best_first);
|
or32_debug (9, "%08X %08lX %i\n", mask, cur_mask, best_first);
|
c = cover_insn (cur, curpass, mask & (~(cur_mask << best_first)));
|
c = cover_insn (cur, curpass, mask & (~(cur_mask << best_first)));
|
if (c)
|
if (c)
|
{
|
{
|
or32_debug (8, "%i> #%X -> %u\n", next - automata, i,
|
or32_debug (8, "%i> #%X -> %u\n", next - automata, i,
|
cur - automata);
|
cur - automata);
|
*next = cur - automata;
|
*next = cur - automata;
|
cur = c;
|
cur = c;
|
}
|
}
|
else
|
else
|
{
|
{
|
or32_debug (8, "%i> N/A\n", next - automata);
|
or32_debug (8, "%i> N/A\n", next - automata);
|
*next = 0;
|
*next = 0;
|
}
|
}
|
next++;
|
next++;
|
}
|
}
|
}
|
}
|
return cur;
|
return cur;
|
}
|
}
|
|
|
/* Returns number of nonzero bits. */
|
/* Returns number of nonzero bits. */
|
static int
|
static int
|
num_ones (unsigned long value)
|
num_ones (unsigned long value)
|
{
|
{
|
int c = 0;
|
int c = 0;
|
while (value)
|
while (value)
|
{
|
{
|
if (value & 1)
|
if (value & 1)
|
c++;
|
c++;
|
value >>= 1;
|
value >>= 1;
|
}
|
}
|
return c;
|
return c;
|
}
|
}
|
|
|
/* Utility function, which converts parameters from or32_opcode format to more binary form.
|
/* Utility function, which converts parameters from or32_opcode format to more binary form.
|
Parameters are stored in ti struct. */
|
Parameters are stored in ti struct. */
|
|
|
static struct insn_op_struct *
|
static struct insn_op_struct *
|
parse_params (CONST struct or32_opcode *opcode, struct insn_op_struct *cur)
|
parse_params (CONST struct or32_opcode *opcode, struct insn_op_struct *cur)
|
{
|
{
|
char *args = opcode->args;
|
char *args = opcode->args;
|
int i, type;
|
int i, type;
|
int num_cur_op = 0;;
|
int num_cur_op = 0;;
|
|
|
i = 0;
|
i = 0;
|
type = 0;
|
type = 0;
|
/* In case we don't have any parameters, we add dummy read from r0. */
|
/* In case we don't have any parameters, we add dummy read from r0. */
|
if (!(*args))
|
if (!(*args))
|
{
|
{
|
cur->type = OPTYPE_REG | OPTYPE_OP | OPTYPE_LAST;
|
cur->type = OPTYPE_REG | OPTYPE_OP | OPTYPE_LAST;
|
cur->data = 0;
|
cur->data = 0;
|
or32_debug (9, "#%08lX %08lX\n", cur->type, cur->data);
|
or32_debug (9, "#%08lX %08lX\n", cur->type, cur->data);
|
cur++;
|
cur++;
|
return cur;
|
return cur;
|
}
|
}
|
|
|
while (*args != '\0')
|
while (*args != '\0')
|
{
|
{
|
if (*args == 'r')
|
if (*args == 'r')
|
{
|
{
|
args++;
|
args++;
|
type |= OPTYPE_REG;
|
type |= OPTYPE_REG;
|
if (*args == 'D')
|
if (*args == 'D')
|
type |= OPTYPE_DST;
|
type |= OPTYPE_DST;
|
}
|
}
|
else if (isalpha (*args))
|
else if (isalpha (*args))
|
{
|
{
|
unsigned long arg;
|
unsigned long arg;
|
arg = insn_extract (*args, opcode->encoding);
|
arg = insn_extract (*args, opcode->encoding);
|
or32_debug (9, "%s : %08lX ------\n", opcode->name, arg);
|
or32_debug (9, "%s : %08lX ------\n", opcode->name, arg);
|
if (letter_signed (*args))
|
if (letter_signed (*args))
|
{
|
{
|
type |= OPTYPE_SIG;
|
type |= OPTYPE_SIG;
|
type |= ((num_ones (arg) - 1) << OPTYPE_SBIT_SHR) & OPTYPE_SBIT;
|
type |= ((num_ones (arg) - 1) << OPTYPE_SBIT_SHR) & OPTYPE_SBIT;
|
}
|
}
|
|
|
num_cur_op = 0;
|
num_cur_op = 0;
|
/* Split argument to sequences of consecutive ones. */
|
/* Split argument to sequences of consecutive ones. */
|
while (arg)
|
while (arg)
|
{
|
{
|
int shr = 0;
|
int shr = 0;
|
unsigned long tmp = arg, mask = 0;
|
unsigned long tmp = arg, mask = 0;
|
while ((tmp & 1) == 0)
|
while ((tmp & 1) == 0)
|
{
|
{
|
shr++;
|
shr++;
|
tmp >>= 1;
|
tmp >>= 1;
|
}
|
}
|
while (tmp & 1)
|
while (tmp & 1)
|
{
|
{
|
mask++;
|
mask++;
|
tmp >>= 1;
|
tmp >>= 1;
|
}
|
}
|
cur->type = type | shr;
|
cur->type = type | shr;
|
cur->data = mask;
|
cur->data = mask;
|
arg &= ~(((1 << mask) - 1) << shr);
|
arg &= ~(((1 << mask) - 1) << shr);
|
or32_debug (6, "|%08lX %08lX\n", cur->type, cur->data);
|
or32_debug (6, "|%08lX %08lX\n", cur->type, cur->data);
|
cur++;
|
cur++;
|
num_cur_op++;
|
num_cur_op++;
|
}
|
}
|
args++;
|
args++;
|
}
|
}
|
else if (*args == '(')
|
else if (*args == '(')
|
{
|
{
|
/* Next param is displacement. Later we will treat them as one operand. */
|
/* Next param is displacement. Later we will treat them as one operand. */
|
/* Set the OPTYPE_DIS flag on all insn_op_structs that belong to this
|
/* Set the OPTYPE_DIS flag on all insn_op_structs that belong to this
|
* operand */
|
* operand */
|
while (num_cur_op > 0)
|
while (num_cur_op > 0)
|
{
|
{
|
cur[-num_cur_op].type |= type | OPTYPE_DIS;
|
cur[-num_cur_op].type |= type | OPTYPE_DIS;
|
num_cur_op--;
|
num_cur_op--;
|
}
|
}
|
cur[-1].type |= OPTYPE_OP;
|
cur[-1].type |= OPTYPE_OP;
|
or32_debug (9, ">%08lX %08lX\n", cur->type, cur->data);
|
or32_debug (9, ">%08lX %08lX\n", cur->type, cur->data);
|
type = 0;
|
type = 0;
|
i++;
|
i++;
|
args++;
|
args++;
|
}
|
}
|
else if (*args == OPERAND_DELIM)
|
else if (*args == OPERAND_DELIM)
|
{
|
{
|
cur--;
|
cur--;
|
cur->type = type | cur->type | OPTYPE_OP;
|
cur->type = type | cur->type | OPTYPE_OP;
|
or32_debug (9, ">%08lX %08lX\n", cur->type, cur->data);
|
or32_debug (9, ">%08lX %08lX\n", cur->type, cur->data);
|
cur++;
|
cur++;
|
type = 0;
|
type = 0;
|
i++;
|
i++;
|
args++;
|
args++;
|
}
|
}
|
else if (*args == '0')
|
else if (*args == '0')
|
{
|
{
|
cur->type = type;
|
cur->type = type;
|
cur->data = 0;
|
cur->data = 0;
|
or32_debug (9, ">%08lX %08lX\n", cur->type, cur->data);
|
or32_debug (9, ">%08lX %08lX\n", cur->type, cur->data);
|
cur++;
|
cur++;
|
type = 0;
|
type = 0;
|
i++;
|
i++;
|
args++;
|
args++;
|
}
|
}
|
else if (*args == ')')
|
else if (*args == ')')
|
args++;
|
args++;
|
else
|
else
|
{
|
{
|
fprintf (stderr, "%s : parse error in args.\n", opcode->name);
|
fprintf (stderr, "%s : parse error in args.\n", opcode->name);
|
exit (1);
|
exit (1);
|
}
|
}
|
}
|
}
|
cur--;
|
cur--;
|
cur->type = type | cur->type | OPTYPE_OP | OPTYPE_LAST;
|
cur->type = type | cur->type | OPTYPE_OP | OPTYPE_LAST;
|
or32_debug (9, "#%08lX %08lX\n", cur->type, cur->data);
|
or32_debug (9, "#%08lX %08lX\n", cur->type, cur->data);
|
cur++;
|
cur++;
|
return cur;
|
return cur;
|
}
|
}
|
|
|
/* Constructs new automata based on or32_opcodes array. */
|
/* Constructs new automata based on or32_opcodes array. */
|
|
|
void
|
void
|
build_automata ()
|
build_automata ()
|
{
|
{
|
int i;
|
int i;
|
unsigned long *end;
|
unsigned long *end;
|
struct insn_op_struct *cur;
|
struct insn_op_struct *cur;
|
|
|
automata =
|
automata =
|
(unsigned long *) malloc (MAX_AUTOMATA_SIZE * sizeof (unsigned long));
|
(unsigned long *) malloc (MAX_AUTOMATA_SIZE * sizeof (unsigned long));
|
ti =
|
ti =
|
(struct temp_insn_struct *) malloc (sizeof (struct temp_insn_struct) *
|
(struct temp_insn_struct *) malloc (sizeof (struct temp_insn_struct) *
|
num_opcodes);
|
num_opcodes);
|
|
|
nuncovered = num_opcodes;
|
nuncovered = num_opcodes;
|
|
|
#ifdef HAVE_EXECUTION
|
#ifdef HAVE_EXECUTION
|
printf ("Building automata... ");
|
printf ("Building automata... ");
|
#endif
|
#endif
|
|
|
/* Build temporary information about instructions. */
|
/* Build temporary information about instructions. */
|
for (i = 0; i < num_opcodes; i++)
|
for (i = 0; i < num_opcodes; i++)
|
{
|
{
|
unsigned long ones, zeros;
|
unsigned long ones, zeros;
|
char *encoding = or32_opcodes[i].encoding;
|
char *encoding = or32_opcodes[i].encoding;
|
ones = insn_extract ('1', encoding);
|
ones = insn_extract ('1', encoding);
|
zeros = insn_extract ('0', encoding);
|
zeros = insn_extract ('0', encoding);
|
ti[i].insn_mask = ones | zeros;
|
ti[i].insn_mask = ones | zeros;
|
ti[i].insn = ones;
|
ti[i].insn = ones;
|
ti[i].in_pass = curpass = 0;
|
ti[i].in_pass = curpass = 0;
|
/*debug(9, "%s: %s %08X %08X\n", or32_opcodes[i].name,
|
/*debug(9, "%s: %s %08X %08X\n", or32_opcodes[i].name,
|
or32_opcodes[i].encoding, ti[i].insn_mask, ti[i].insn); */
|
or32_opcodes[i].encoding, ti[i].insn_mask, ti[i].insn); */
|
}
|
}
|
|
|
/* Until all are covered search for best criteria to separate them. */
|
/* Until all are covered search for best criteria to separate them. */
|
end = cover_insn (automata, curpass, 0xFFFFFFFF);
|
end = cover_insn (automata, curpass, 0xFFFFFFFF);
|
if (end - automata > MAX_AUTOMATA_SIZE)
|
if (end - automata > MAX_AUTOMATA_SIZE)
|
{
|
{
|
fprintf (stderr, "Automata too large. Increase MAX_AUTOMATA_SIZE.");
|
fprintf (stderr, "Automata too large. Increase MAX_AUTOMATA_SIZE.");
|
exit (1);
|
exit (1);
|
}
|
}
|
#ifdef HAVE_EXECUTION
|
#ifdef HAVE_EXECUTION
|
printf ("done, num uncovered: %i/%i.\n", nuncovered, num_opcodes);
|
printf ("done, num uncovered: %i/%i.\n", nuncovered, num_opcodes);
|
#endif
|
#endif
|
|
|
#ifdef HAVE_EXECUTION
|
#ifdef HAVE_EXECUTION
|
printf ("Parsing operands data... ");
|
printf ("Parsing operands data... ");
|
#endif
|
#endif
|
op_data =
|
op_data =
|
(struct insn_op_struct *) malloc (MAX_OP_TABLE_SIZE *
|
(struct insn_op_struct *) malloc (MAX_OP_TABLE_SIZE *
|
sizeof (struct insn_op_struct));
|
sizeof (struct insn_op_struct));
|
op_start =
|
op_start =
|
(struct insn_op_struct **) malloc (num_opcodes *
|
(struct insn_op_struct **) malloc (num_opcodes *
|
sizeof (struct insn_op_struct *));
|
sizeof (struct insn_op_struct *));
|
cur = op_data;
|
cur = op_data;
|
for (i = 0; i < num_opcodes; i++)
|
for (i = 0; i < num_opcodes; i++)
|
{
|
{
|
op_start[i] = cur;
|
op_start[i] = cur;
|
cur = parse_params (&or32_opcodes[i], cur);
|
cur = parse_params (&or32_opcodes[i], cur);
|
if (cur - op_data > MAX_OP_TABLE_SIZE)
|
if (cur - op_data > MAX_OP_TABLE_SIZE)
|
{
|
{
|
fprintf (stderr,
|
fprintf (stderr,
|
"Operands table too small, increase MAX_OP_TABLE_SIZE.\n");
|
"Operands table too small, increase MAX_OP_TABLE_SIZE.\n");
|
exit (1);
|
exit (1);
|
}
|
}
|
}
|
}
|
#ifdef HAVE_EXECUTION
|
#ifdef HAVE_EXECUTION
|
printf ("done.\n");
|
printf ("done.\n");
|
#endif
|
#endif
|
}
|
}
|
|
|
void
|
void
|
destruct_automata ()
|
destruct_automata ()
|
{
|
{
|
free (ti);
|
free (ti);
|
free (automata);
|
free (automata);
|
free (op_data);
|
free (op_data);
|
free (op_start);
|
free (op_start);
|
}
|
}
|
|
|
/* Decodes instruction and returns instruction index. */
|
/* Decodes instruction and returns instruction index. */
|
int
|
int
|
insn_decode (unsigned int insn)
|
insn_decode (unsigned int insn)
|
{
|
{
|
unsigned long *a = automata;
|
unsigned long *a = automata;
|
int i;
|
int i;
|
while (!(*a & LEAF_FLAG))
|
while (!(*a & LEAF_FLAG))
|
{
|
{
|
unsigned int first = *a;
|
unsigned int first = *a;
|
//debug(9, "%i ", a - automata);
|
//debug(9, "%i ", a - automata);
|
a++;
|
a++;
|
i = (insn >> first) & *a;
|
i = (insn >> first) & *a;
|
a++;
|
a++;
|
if (!*(a + i))
|
if (!*(a + i))
|
{ /* Invalid instruction found? */
|
{ /* Invalid instruction found? */
|
//debug(9, "XXX\n", i);
|
//debug(9, "XXX\n", i);
|
return -1;
|
return -1;
|
}
|
}
|
a = automata + *(a + i);
|
a = automata + *(a + i);
|
}
|
}
|
i = *a & ~LEAF_FLAG;
|
i = *a & ~LEAF_FLAG;
|
//debug(9, "%i\n", i);
|
//debug(9, "%i\n", i);
|
/* Final check - do we have direct match?
|
/* Final check - do we have direct match?
|
(based on or32_opcodes this should be the only possibility,
|
(based on or32_opcodes this should be the only possibility,
|
but in case of invalid/missing instruction we must perform a check) */
|
but in case of invalid/missing instruction we must perform a check) */
|
if ((ti[i].insn_mask & insn) == ti[i].insn)
|
if ((ti[i].insn_mask & insn) == ti[i].insn)
|
return i;
|
return i;
|
else
|
else
|
return -1;
|
return -1;
|
}
|
}
|
|
|
static char disassembled_str[50];
|
static char disassembled_str[50];
|
char *disassembled = &disassembled_str[0];
|
char *disassembled = &disassembled_str[0];
|
|
|
/* Automagically does zero- or sign- extension and also finds correct
|
/* Automagically does zero- or sign- extension and also finds correct
|
sign bit position if sign extension is correct extension. Which extension
|
sign bit position if sign extension is correct extension. Which extension
|
is proper is figured out from letter description. */
|
is proper is figured out from letter description. */
|
|
|
unsigned long
|
unsigned long
|
extend_imm (unsigned long imm, char l)
|
extend_imm (unsigned long imm, char l)
|
{
|
{
|
unsigned long mask;
|
unsigned long mask;
|
int letter_bits;
|
int letter_bits;
|
|
|
/* First truncate all bits above valid range for this letter
|
/* First truncate all bits above valid range for this letter
|
in case it is zero extend. */
|
in case it is zero extend. */
|
letter_bits = letter_range (l);
|
letter_bits = letter_range (l);
|
mask = (1 << letter_bits) - 1;
|
mask = (1 << letter_bits) - 1;
|
imm &= mask;
|
imm &= mask;
|
|
|
/* Do sign extend if this is the right one. */
|
/* Do sign extend if this is the right one. */
|
if (letter_signed (l) && (imm >> (letter_bits - 1)))
|
if (letter_signed (l) && (imm >> (letter_bits - 1)))
|
imm |= (~mask);
|
imm |= (~mask);
|
|
|
return imm;
|
return imm;
|
}
|
}
|
|
|
unsigned long
|
unsigned long
|
or32_extract (param_ch, enc_initial, insn)
|
or32_extract (param_ch, enc_initial, insn)
|
char param_ch;
|
char param_ch;
|
char *enc_initial;
|
char *enc_initial;
|
unsigned long insn;
|
unsigned long insn;
|
{
|
{
|
char *enc;
|
char *enc;
|
unsigned long ret = 0;
|
unsigned long ret = 0;
|
int opc_pos = 0;
|
int opc_pos = 0;
|
int param_pos = 0;
|
int param_pos = 0;
|
|
|
for (enc = enc_initial; *enc != '\0'; enc++)
|
for (enc = enc_initial; *enc != '\0'; enc++)
|
if (*enc == param_ch)
|
if (*enc == param_ch)
|
{
|
{
|
if (enc - 2 >= enc_initial && (*(enc - 2) == '0')
|
if (enc - 2 >= enc_initial && (*(enc - 2) == '0')
|
&& (*(enc - 1) == 'x'))
|
&& (*(enc - 1) == 'x'))
|
continue;
|
continue;
|
else
|
else
|
param_pos++;
|
param_pos++;
|
}
|
}
|
|
|
#if DEBUG
|
#if DEBUG
|
printf ("or32_extract: %x ", param_pos);
|
printf ("or32_extract: %x ", param_pos);
|
#endif
|
#endif
|
opc_pos = 32;
|
opc_pos = 32;
|
for (enc = enc_initial; *enc != '\0';)
|
for (enc = enc_initial; *enc != '\0';)
|
if ((*enc == '0') && (*(enc + 1) == 'x'))
|
if ((*enc == '0') && (*(enc + 1) == 'x'))
|
{
|
{
|
opc_pos -= 4;
|
opc_pos -= 4;
|
if ((param_ch == '0') || (param_ch == '1'))
|
if ((param_ch == '0') || (param_ch == '1'))
|
{
|
{
|
unsigned long tmp = strtol (enc, NULL, 16);
|
unsigned long tmp = strtol (enc, NULL, 16);
|
#if DEBUG
|
#if DEBUG
|
printf (" enc=%s, tmp=%x ", enc, tmp);
|
printf (" enc=%s, tmp=%x ", enc, tmp);
|
#endif
|
#endif
|
if (param_ch == '0')
|
if (param_ch == '0')
|
tmp = 15 - tmp;
|
tmp = 15 - tmp;
|
ret |= tmp << opc_pos;
|
ret |= tmp << opc_pos;
|
}
|
}
|
enc += 3;
|
enc += 3;
|
}
|
}
|
else if ((*enc == '0') || (*enc == '1'))
|
else if ((*enc == '0') || (*enc == '1'))
|
{
|
{
|
opc_pos--;
|
opc_pos--;
|
if (param_ch == *enc)
|
if (param_ch == *enc)
|
ret |= 1 << opc_pos;
|
ret |= 1 << opc_pos;
|
enc++;
|
enc++;
|
}
|
}
|
else if (*enc == param_ch)
|
else if (*enc == param_ch)
|
{
|
{
|
opc_pos--;
|
opc_pos--;
|
param_pos--;
|
param_pos--;
|
#if DEBUG
|
#if DEBUG
|
printf ("\n ret=%x opc_pos=%x, param_pos=%x\n", ret, opc_pos,
|
printf ("\n ret=%x opc_pos=%x, param_pos=%x\n", ret, opc_pos,
|
param_pos);
|
param_pos);
|
#endif
|
#endif
|
if (islower (param_ch))
|
if (islower (param_ch))
|
ret -= ((insn >> opc_pos) & 0x1) << param_pos;
|
ret -= ((insn >> opc_pos) & 0x1) << param_pos;
|
else
|
else
|
ret += ((insn >> opc_pos) & 0x1) << param_pos;
|
ret += ((insn >> opc_pos) & 0x1) << param_pos;
|
enc++;
|
enc++;
|
}
|
}
|
else if (isalpha (*enc))
|
else if (isalpha (*enc))
|
{
|
{
|
opc_pos--;
|
opc_pos--;
|
enc++;
|
enc++;
|
}
|
}
|
else if (*enc == '-')
|
else if (*enc == '-')
|
{
|
{
|
opc_pos--;
|
opc_pos--;
|
enc++;
|
enc++;
|
}
|
}
|
else
|
else
|
enc++;
|
enc++;
|
|
|
#if DEBUG
|
#if DEBUG
|
printf ("ret=%x\n", ret);
|
printf ("ret=%x\n", ret);
|
#endif
|
#endif
|
return ret;
|
return ret;
|
}
|
}
|
|
|
/* Print register. Used only by print_insn. */
|
/* Print register. Used only by print_insn. */
|
|
|
static char *
|
static char *
|
or32_print_register (dest, param_ch, encoding, insn)
|
or32_print_register (dest, param_ch, encoding, insn)
|
char *dest;
|
char *dest;
|
char param_ch;
|
char param_ch;
|
char *encoding;
|
char *encoding;
|
unsigned long insn;
|
unsigned long insn;
|
{
|
{
|
int regnum = or32_extract (param_ch, encoding, insn);
|
int regnum = or32_extract (param_ch, encoding, insn);
|
|
|
sprintf (dest, "r%d", regnum);
|
sprintf (dest, "r%d", regnum);
|
while (*dest)
|
while (*dest)
|
dest++;
|
dest++;
|
return dest;
|
return dest;
|
}
|
}
|
|
|
/* Print immediate. Used only by print_insn. */
|
/* Print immediate. Used only by print_insn. */
|
|
|
static char *
|
static char *
|
or32_print_immediate (dest, param_ch, encoding, insn)
|
or32_print_immediate (dest, param_ch, encoding, insn)
|
char *dest;
|
char *dest;
|
char param_ch;
|
char param_ch;
|
char *encoding;
|
char *encoding;
|
unsigned long insn;
|
unsigned long insn;
|
{
|
{
|
int imm = or32_extract (param_ch, encoding, insn);
|
int imm = or32_extract (param_ch, encoding, insn);
|
|
|
imm = extend_imm (imm, param_ch);
|
imm = extend_imm (imm, param_ch);
|
|
|
if (letter_signed (param_ch))
|
if (letter_signed (param_ch))
|
{
|
{
|
if (imm < 0)
|
if (imm < 0)
|
sprintf (dest, "%d", imm);
|
sprintf (dest, "%d", imm);
|
else
|
else
|
sprintf (dest, "0x%x", imm);
|
sprintf (dest, "0x%x", imm);
|
}
|
}
|
else
|
else
|
sprintf (dest, "%#x", imm);
|
sprintf (dest, "%#x", imm);
|
while (*dest)
|
while (*dest)
|
dest++;
|
dest++;
|
return dest;
|
return dest;
|
}
|
}
|
|
|
/* Disassemble one instruction from insn to disassemble.
|
/* Disassemble one instruction from insn to disassemble.
|
Return the size of the instruction. */
|
Return the size of the instruction. */
|
|
|
int
|
int
|
disassemble_insn (insn)
|
disassemble_insn (insn)
|
unsigned long insn;
|
unsigned long insn;
|
{
|
{
|
return disassemble_index (insn, insn_decode (insn));
|
return disassemble_index (insn, insn_decode (insn));
|
}
|
}
|
|
|
/* Disassemble one instruction from insn index.
|
/* Disassemble one instruction from insn index.
|
Return the size of the instruction. */
|
Return the size of the instruction. */
|
|
|
int
|
int
|
disassemble_index (insn, index)
|
disassemble_index (insn, index)
|
unsigned long insn;
|
unsigned long insn;
|
int index;
|
int index;
|
{
|
{
|
char *dest = disassembled;
|
char *dest = disassembled;
|
if (index >= 0)
|
if (index >= 0)
|
{
|
{
|
struct or32_opcode const *opcode = &or32_opcodes[index];
|
struct or32_opcode const *opcode = &or32_opcodes[index];
|
char *s;
|
char *s;
|
|
|
strcpy (dest, opcode->name);
|
strcpy (dest, opcode->name);
|
while (*dest)
|
while (*dest)
|
dest++;
|
dest++;
|
*dest++ = ' ';
|
*dest++ = ' ';
|
*dest = 0;
|
*dest = 0;
|
|
|
for (s = opcode->args; *s != '\0'; ++s)
|
for (s = opcode->args; *s != '\0'; ++s)
|
{
|
{
|
switch (*s)
|
switch (*s)
|
{
|
{
|
case '\0':
|
case '\0':
|
return insn_len (insn);
|
return insn_len (insn);
|
|
|
case 'r':
|
case 'r':
|
dest = or32_print_register (dest, *++s, opcode->encoding, insn);
|
dest = or32_print_register (dest, *++s, opcode->encoding, insn);
|
break;
|
break;
|
|
|
default:
|
default:
|
if (strchr (opcode->encoding, *s))
|
if (strchr (opcode->encoding, *s))
|
dest =
|
dest =
|
or32_print_immediate (dest, *s, opcode->encoding, insn);
|
or32_print_immediate (dest, *s, opcode->encoding, insn);
|
else
|
else
|
{
|
{
|
*dest++ = *s;
|
*dest++ = *s;
|
*dest = 0;
|
*dest = 0;
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
else
|
else
|
{
|
{
|
/* This used to be %8x for binutils. */
|
/* This used to be %8x for binutils. */
|
sprintf (dest, ".word 0x%08lx", insn);
|
sprintf (dest, ".word 0x%08lx", insn);
|
while (*dest)
|
while (*dest)
|
dest++;
|
dest++;
|
}
|
}
|
return insn_len (insn);
|
return insn_len (insn);
|
}
|
}
|
|
|