/* libtoplevel.c -- Top level simulator library source file
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/* libtoplevel.c -- Top level simulator library source file
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 2008 Embecosm Limited
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Copyright (C) 2008 Embecosm Limited
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify it
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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more details.
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You should have received a copy of the GNU General Public License along
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You should have received a copy of the GNU General Public License along
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* This program is commented throughout in a fashion suitable for processing
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/* This program is commented throughout in a fashion suitable for processing
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with Doxygen. */
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with Doxygen. */
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/* Autoconf and/or portability configuration */
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/* Autoconf and/or portability configuration */
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#include "config.h"
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#include "config.h"
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/* System includes */
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/* System includes */
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#include <stdlib.h>
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#include <stdlib.h>
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#include <unistd.h>
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#include <unistd.h>
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#include <signal.h>
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#include <signal.h>
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/* Package includes */
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/* Package includes */
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#include "or1ksim.h"
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#include "or1ksim.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "toplevel-support.h"
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#include "toplevel-support.h"
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#include "sched.h"
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#include "sched.h"
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#include "execute.h"
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#include "execute.h"
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#include "pic.h"
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#include "pic.h"
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#include "jtag.h"
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#include "jtag.h"
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/* Indices of GDB registers that are not GPRs. Must match GDB settings! */
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#define MAX_GPRS 32 /*!< Maximum GPRs */
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#define PPC_REGNUM (MAX_GPRS + 0) /*!< Previous PC */
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#define NPC_REGNUM (MAX_GPRS + 1) /*!< Next PC */
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#define SR_REGNUM (MAX_GPRS + 2) /*!< Supervision Register */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/*!Initialize the simulator.
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/*!Initialize the simulator.
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Allows specification of an (optional) config file and an image file. Builds
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Allows specification of an (optional) config file and an image file. Builds
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up dummy argc/argv to pass to the existing argument parser.
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up dummy argc/argv to pass to the existing argument parser.
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@param[in] config_file Or1ksim configuration file name
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@param[in] config_file Or1ksim configuration file name
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@param[in] image_file The program image to execute
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@param[in] image_file The program image to execute
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@param[in] class_ptr Pointer to a C++ class instance (for use when
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@param[in] class_ptr Pointer to a C++ class instance (for use when
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called by C++)
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called by C++)
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@param[in] upr Upcall routine for reads
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@param[in] upr Upcall routine for reads
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@param[in] upw Upcall routine for writes
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@param[in] upw Upcall routine for writes
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@return 0 on success and an error code on failure */
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@return 0 on success and an error code on failure */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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int
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int
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or1ksim_init (const char *config_file,
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or1ksim_init (const char *config_file,
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const char *image_file,
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const char *image_file,
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void *class_ptr,
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void *class_ptr,
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int (*upr) (void *class_ptr,
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int (*upr) (void *class_ptr,
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unsigned long int addr,
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unsigned long int addr,
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unsigned char mask[],
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unsigned char mask[],
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unsigned char rdata[],
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unsigned char rdata[],
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int data_len),
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int data_len),
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int (*upw) (void *class_ptr,
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int (*upw) (void *class_ptr,
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unsigned long int addr,
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unsigned long int addr,
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unsigned char mask[],
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unsigned char mask[],
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unsigned char wdata[],
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unsigned char wdata[],
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int data_len))
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int data_len))
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{
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{
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int dummy_argc;
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int dummy_argc;
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char *dummy_argv[4];
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char *dummy_argv[4];
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/* Dummy argv array. Varies depending on whether an image file is
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/* Dummy argv array. Varies depending on whether an image file is
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specified. */
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specified. */
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dummy_argv[0] = "libsim";
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dummy_argv[0] = "libsim";
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dummy_argv[1] = "-f";
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dummy_argv[1] = "-f";
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dummy_argv[2] = (char *) ((NULL != config_file) ? config_file : "sim.cfg");
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dummy_argv[2] = (char *) ((NULL != config_file) ? config_file : "sim.cfg");
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dummy_argv[3] = (char *) image_file;
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dummy_argv[3] = (char *) image_file;
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dummy_argc = (NULL == image_file) ? 3 : 4;
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dummy_argc = (NULL == image_file) ? 3 : 4;
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/* Initialization copied from existing main() */
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/* Initialization copied from existing main() */
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srand (getpid ());
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srand (getpid ());
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init_defconfig ();
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init_defconfig ();
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reg_config_secs ();
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reg_config_secs ();
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if (parse_args (dummy_argc, dummy_argv))
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if (parse_args (dummy_argc, dummy_argv))
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{
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{
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return OR1KSIM_RC_BADINIT;
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return OR1KSIM_RC_BADINIT;
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}
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}
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config.sim.is_library = 1; /* Library operation */
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config.sim.profile = 0; /* No profiling */
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config.sim.profile = 0; /* No profiling */
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config.sim.mprofile = 0;
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config.sim.mprofile = 0;
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config.ext.class_ptr = class_ptr; /* SystemC linkage */
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config.ext.class_ptr = class_ptr; /* SystemC linkage */
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config.ext.read_up = upr;
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config.ext.read_up = upr;
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config.ext.write_up = upw;
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config.ext.write_up = upw;
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print_config (); /* Will go eventually */
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print_config (); /* Will go eventually */
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signal (SIGINT, ctrl_c); /* Not sure we want this really */
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signal (SIGINT, ctrl_c); /* Not sure we want this really */
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runtime.sim.hush = 1; /* Not sure if this is needed */
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runtime.sim.hush = 1; /* Not sure if this is needed */
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do_stats = config.cpu.superscalar ||
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do_stats = config.cpu.superscalar ||
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config.cpu.dependstats ||
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config.cpu.dependstats ||
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config.sim.history ||
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config.sim.history ||
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config.sim.exe_log;
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config.sim.exe_log;
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sim_init ();
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sim_init ();
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runtime.sim.ext_int_set = 0; /* No interrupts pending to be set */
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runtime.sim.ext_int_set = 0; /* No interrupts pending to be set */
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runtime.sim.ext_int_clr = 0; /* No interrupts pending to be cleared */
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runtime.sim.ext_int_clr = 0; /* No interrupts pending to be cleared */
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return OR1KSIM_RC_OK;
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return OR1KSIM_RC_OK;
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} /* or1ksim_init() */
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} /* or1ksim_init () */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/*!Run the simulator
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/*!Run the simulator
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The argument is a time in seconds, which is converted to a number of
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The argument is a time in seconds, which is converted to a number of
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cycles, if positive. A negative value means "run for ever".
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cycles, if positive. A negative value means "run for ever".
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With the JTAG interface, it is possible to stall the processor between
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With the JTAG interface, it is possible to stall the processor between
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calls of this function (but not during upcalls). In which case we return
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calls of this function (but not during upcalls). In which case we return
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immediately.
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immediately.
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@todo Is it possible (or desirable) to permit JTAG activity during upcalls,
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@todo Is it possible (or desirable) to permit JTAG activity during upcalls,
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in which case we could stall mid-run.
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in which case we could stall mid-run.
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@todo Should the JTAG functionality require enabling?
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@todo Should the JTAG functionality require enabling?
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The semantics are that the duration for which the run may occur may be
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The semantics are that the duration for which the run may occur may be
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changed mid-run by a call to or1ksim_reset_duration(). This is to allow for
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changed mid-run by a call to or1ksim_reset_duration(). This is to allow for
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the upcalls to generic components adding time, and reducing the time
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the upcalls to generic components adding time, and reducing the time
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permitted for ISS execution before synchronization of the parent SystemC
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permitted for ISS execution before synchronization of the parent SystemC
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wrapper.
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wrapper.
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This is over-ridden if the call was for a negative duration, which means
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This is over-ridden if the call was for a negative duration, which means
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run forever!
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run forever!
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Uses a simplified version of the old main program loop. Returns success if
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Uses a simplified version of the old main program loop. Returns success if
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the requested number of cycles were run and an error code otherwise.
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the requested number of cycles were run and an error code otherwise.
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@param[in] duration Time to execute for (seconds)
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@param[in] duration Time to execute for (seconds)
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@return OR1KSIM_RC_OK if we run to completion, OR1KSIM_RC_BRKPT if we hit
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@return OR1KSIM_RC_OK if we run to completion, OR1KSIM_RC_BRKPT if we hit
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a breakpoint (not clear how this can be set without CLI access) */
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a breakpoint (not clear how this can be set without CLI access) */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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int
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int
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or1ksim_run (double duration)
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or1ksim_run (double duration)
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{
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{
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const int num_ints = sizeof (runtime.sim.ext_int_set) * 8;
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const int num_ints = sizeof (runtime.sim.ext_int_set) * 8;
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/* If we are stalled we can't do anything. We treat this as hitting a
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/* If we are stalled we can't do anything. We treat this as hitting a
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breakpoint. */
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breakpoint or halting. */
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if(runtime.cpu.stalled)
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if(runtime.cpu.stalled)
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{
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{
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return OR1KSIM_RC_BRKPT;
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return runtime.cpu.halted ? OR1KSIM_RC_HALTED : OR1KSIM_RC_BRKPT;
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}
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}
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/* Reset the duration */
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/* Reset the duration */
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or1ksim_reset_duration (duration);
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or1ksim_reset_duration (duration);
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/* Loop until we have done enough cycles (or forever if we had a negative
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/* Loop until we have done enough cycles (or forever if we had a negative
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duration) */
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duration) */
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while (duration < 0.0 || (runtime.sim.cycles < runtime.sim.end_cycles))
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while (duration < 0.0 || (runtime.sim.cycles < runtime.sim.end_cycles))
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{
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{
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long long int time_start = runtime.sim.cycles;
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long long int time_start = runtime.sim.cycles;
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int i; /* Interrupt # */
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int i; /* Interrupt # */
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/* Each cycle has counter of mem_cycles; this value is joined with cycles
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/* Each cycle has counter of mem_cycles; this value is joined with cycles
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* at the end of the cycle; no sim originated memory accesses should be
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* at the end of the cycle; no sim originated memory accesses should be
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* performed in between. */
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* performed in between. */
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runtime.sim.mem_cycles = 0;
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runtime.sim.mem_cycles = 0;
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if (cpu_clock ())
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if (cpu_clock ())
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{
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{
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return OR1KSIM_RC_BRKPT; /* Hit a breakpoint */
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/* This is probably wrong. This is an Or1ksim breakpoint, not a GNU
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one. */
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return runtime.cpu.halted ? OR1KSIM_RC_HALTED : OR1KSIM_RC_BRKPT;
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}
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/* If we are stalled we can't do anything. We treat this as hitting a
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breakpoint or halting. */
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if(runtime.cpu.stalled)
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{
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return runtime.cpu.halted ? OR1KSIM_RC_HALTED : OR1KSIM_RC_BRKPT;
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}
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}
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runtime.sim.cycles += runtime.sim.mem_cycles;
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runtime.sim.cycles += runtime.sim.mem_cycles;
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/* Take any external interrupts. Outer test is for the common case for
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/* Take any external interrupts. Outer test is for the common case for
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efficiency. */
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efficiency. */
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if (0 != runtime.sim.ext_int_set)
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if (0 != runtime.sim.ext_int_set)
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{
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{
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for (i = 0; i < num_ints; i++)
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for (i = 0; i < num_ints; i++)
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{
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{
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if (0x1 == ((runtime.sim.ext_int_set >> i) & 0x1))
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if (0x1 == ((runtime.sim.ext_int_set >> i) & 0x1))
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{
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{
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report_interrupt (i);
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report_interrupt (i);
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runtime.sim.ext_int_set &= ~(1 << i); /* Clear req flag */
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runtime.sim.ext_int_set &= ~(1 << i); /* Clear req flag */
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}
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}
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}
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}
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}
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}
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/* Clear any interrupts as requested. For edge triggered interrupts this
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/* Clear any interrupts as requested. For edge triggered interrupts this
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will happen in the same cycle. For level triggered, it must be an
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will happen in the same cycle. For level triggered, it must be an
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explicit call. */
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explicit call. */
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if (0 != runtime.sim.ext_int_clr)
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if (0 != runtime.sim.ext_int_clr)
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{
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{
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for (i = 0; i < num_ints; i++)
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for (i = 0; i < num_ints; i++)
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{
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{
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/* Only clear interrupts that have been explicitly cleared */
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/* Only clear interrupts that have been explicitly cleared */
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if(0x1 == ((runtime.sim.ext_int_clr >> i) & 0x1))
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if(0x1 == ((runtime.sim.ext_int_clr >> i) & 0x1))
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{
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{
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clear_interrupt(i);
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clear_interrupt(i);
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runtime.sim.ext_int_clr &= ~(1 << i); /* Clear clr flag */
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runtime.sim.ext_int_clr &= ~(1 << i); /* Clear clr flag */
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}
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}
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}
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}
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}
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}
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/* Update the scheduler queue */
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/* Update the scheduler queue */
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scheduler.job_queue->time -= (runtime.sim.cycles - time_start);
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scheduler.job_queue->time -= (runtime.sim.cycles - time_start);
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if (scheduler.job_queue->time <= 0)
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if (scheduler.job_queue->time <= 0)
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{
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{
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do_scheduler ();
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do_scheduler ();
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}
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}
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}
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}
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return OR1KSIM_RC_OK;
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return OR1KSIM_RC_OK;
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} /* or1ksim_run() */
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} /* or1ksim_run () */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/*!Step the simulator
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This is just a wrapper for the run function, specifying a time
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corresponding to a single cycle. This will in fact mean that a single
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instruction is executed, even if takes more than one cycle to execute.
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@todo What happens if an event is triggered - that may mean multiple
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instructions.
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@return OR1KSIM_RC_OK if we step to completion, OR1KSIM_RC_BRKPT if we hit
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a breakpoint (not clear how this can be set without CLI access) */
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/*---------------------------------------------------------------------------*/
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int
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or1ksim_step ()
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{
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return or1ksim_run ((double) config.sim.clkcycle_ps / 1e12);
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} /* or1ksim_step () */
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/*---------------------------------------------------------------------------*/
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/*!Reset the run-time simulation end point
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/*!Reset the run-time simulation end point
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Reset the time for which the simulation should run to the specified duration
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Reset the time for which the simulation should run to the specified duration
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from NOW (i.e. NOT from when the run started).
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from NOW (i.e. NOT from when the run started).
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@param[in] duration Time to run for in seconds */
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@param[in] duration Time to run for in seconds */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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void
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void
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or1ksim_reset_duration (double duration)
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or1ksim_reset_duration (double duration)
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{
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{
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runtime.sim.end_cycles =
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runtime.sim.end_cycles =
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runtime.sim.cycles +
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runtime.sim.cycles +
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(long long int) (duration * 1.0e12 / (double) config.sim.clkcycle_ps);
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(long long int) (duration * 1.0e12 / (double) config.sim.clkcycle_ps);
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} /* or1ksim_reset_duration() */
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} /* or1ksim_reset_duration () */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/*!Return time executed so far
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/*!Return time executed so far
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Internal utility to return the time executed so far. Note that this is a
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Internal utility to return the time executed so far. Note that this is a
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re-entrant routine.
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re-entrant routine.
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@return Time executed so far in seconds */
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@return Time executed so far in seconds */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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static double
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static double
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internal_or1ksim_time ()
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internal_or1ksim_time ()
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{
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{
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return (double) runtime.sim.cycles * (double) config.sim.clkcycle_ps /
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return (double) runtime.sim.cycles * (double) config.sim.clkcycle_ps /
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1.0e12;
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1.0e12;
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} // or1ksim_cycle_count()
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} // or1ksim_cycle_count()
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/*!Mark a time point in the simulation
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/*!Mark a time point in the simulation
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Sets the internal parameter recording this point in the simulation */
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Sets the internal parameter recording this point in the simulation */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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void
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void
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or1ksim_set_time_point ()
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or1ksim_set_time_point ()
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{
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{
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runtime.sim.time_point = internal_or1ksim_time ();
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runtime.sim.time_point = internal_or1ksim_time ();
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|
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} /* or1ksim_set_time_point() */
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} /* or1ksim_set_time_point () */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/*!Return the time since the time point was set
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/*!Return the time since the time point was set
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|
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Get the value from the internal parameter */
|
Get the value from the internal parameter */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
|
double
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double
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or1ksim_get_time_period ()
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or1ksim_get_time_period ()
|
{
|
{
|
return internal_or1ksim_time () - runtime.sim.time_point;
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return internal_or1ksim_time () - runtime.sim.time_point;
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|
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} /* or1ksim_get_time_period() */
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} /* or1ksim_get_time_period () */
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|
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|
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/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
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/*!Return the endianism of the model
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/*!Return the endianism of the model
|
|
|
Note that this is a re-entrant routine.
|
Note that this is a re-entrant routine.
|
|
|
@return 1 if the model is little endian, 0 otherwise. */
|
@return 1 if the model is little endian, 0 otherwise. */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
int
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int
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or1ksim_is_le ()
|
or1ksim_is_le ()
|
{
|
{
|
#ifdef OR32_BIG_ENDIAN
|
#ifdef OR32_BIG_ENDIAN
|
return 0;
|
return 0;
|
#else
|
#else
|
return 1;
|
return 1;
|
#endif
|
#endif
|
|
|
} /* or1ksim_is_le() */
|
} /* or1ksim_is_le () */
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/*!Return the clock rate
|
/*!Return the clock rate
|
|
|
Value is part of the configuration
|
Value is part of the configuration
|
|
|
@return Clock rate in Hz. */
|
@return Clock rate in Hz. */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
unsigned long int
|
unsigned long int
|
or1ksim_clock_rate ()
|
or1ksim_clock_rate ()
|
{
|
{
|
return (unsigned long int) (1000000000000ULL /
|
return (unsigned long int) (1000000000000ULL /
|
(unsigned long long int) (config.sim.
|
(unsigned long long int) (config.sim.
|
clkcycle_ps));
|
clkcycle_ps));
|
} /* or1ksim_clock_rate() */
|
} /* or1ksim_clock_rate () */
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/*!Trigger an edge triggered interrupt
|
/*!Trigger an edge triggered interrupt
|
|
|
This function is appropriate for edge triggered interrupts, which are taken
|
This function is appropriate for edge triggered interrupts, which are taken
|
and then immediately cleared.
|
and then immediately cleared.
|
|
|
@note There is no check that the specified interrupt number is reasonable
|
@note There is no check that the specified interrupt number is reasonable
|
(i.e. <= 31).
|
(i.e. <= 31).
|
|
|
@param[in] i The interrupt number */
|
@param[in] i The interrupt number */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
void
|
void
|
or1ksim_interrupt (int i)
|
or1ksim_interrupt (int i)
|
{
|
{
|
if (!config.pic.edge_trigger)
|
if (!config.pic.edge_trigger)
|
{
|
{
|
fprintf (stderr, "Warning: or1ksim_interrupt should not be used for "
|
fprintf (stderr, "Warning: or1ksim_interrupt should not be used for "
|
"level triggered interrupts. Ignored\n");
|
"level triggered interrupts. Ignored\n");
|
}
|
}
|
else
|
else
|
{
|
{
|
runtime.sim.ext_int_set |= 1 << i; // Better not be > 31!
|
runtime.sim.ext_int_set |= 1 << i; // Better not be > 31!
|
runtime.sim.ext_int_clr |= 1 << i; // Better not be > 31!
|
runtime.sim.ext_int_clr |= 1 << i; // Better not be > 31!
|
}
|
}
|
} /* or1ksim_interrupt() */
|
} /* or1ksim_interrupt () */
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/*!Set a level triggered interrupt
|
/*!Set a level triggered interrupt
|
|
|
This function is appropriate for level triggered interrupts, which must be
|
This function is appropriate for level triggered interrupts, which must be
|
explicitly cleared in a separate call.
|
explicitly cleared in a separate call.
|
|
|
@note There is no check that the specified interrupt number is reasonable
|
@note There is no check that the specified interrupt number is reasonable
|
(i.e. <= 31).
|
(i.e. <= 31).
|
|
|
@param[in] i The interrupt number to set */
|
@param[in] i The interrupt number to set */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
void
|
void
|
or1ksim_interrupt_set (int i)
|
or1ksim_interrupt_set (int i)
|
{
|
{
|
if (config.pic.edge_trigger)
|
if (config.pic.edge_trigger)
|
{
|
{
|
fprintf (stderr, "Warning: or1ksim_interrupt_set should not be used for "
|
fprintf (stderr, "Warning: or1ksim_interrupt_set should not be used for "
|
"edge triggered interrupts. Ignored\n");
|
"edge triggered interrupts. Ignored\n");
|
}
|
}
|
else
|
else
|
{
|
{
|
runtime.sim.ext_int_set |= 1 << i; // Better not be > 31!
|
runtime.sim.ext_int_set |= 1 << i; // Better not be > 31!
|
}
|
}
|
} /* or1ksim_interrupt() */
|
} /* or1ksim_interrupt () */
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/*!Clear a level triggered interrupt
|
/*!Clear a level triggered interrupt
|
|
|
This function is appropriate for level triggered interrupts, which must be
|
This function is appropriate for level triggered interrupts, which must be
|
explicitly set first in a separate call.
|
explicitly set first in a separate call.
|
|
|
@note There is no check that the specified interrupt number is reasonable
|
@note There is no check that the specified interrupt number is reasonable
|
(i.e. <= 31).
|
(i.e. <= 31).
|
|
|
@param[in] i The interrupt number to clear */
|
@param[in] i The interrupt number to clear */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
void
|
void
|
or1ksim_interrupt_clear (int i)
|
or1ksim_interrupt_clear (int i)
|
{
|
{
|
if (config.pic.edge_trigger)
|
if (config.pic.edge_trigger)
|
{
|
{
|
fprintf (stderr, "Warning: or1ksim_interrupt_clear should not be used "
|
fprintf (stderr, "Warning: or1ksim_interrupt_clear should not be used "
|
"for edge triggered interrupts. Ignored\n");
|
"for edge triggered interrupts. Ignored\n");
|
}
|
}
|
else
|
else
|
{
|
{
|
runtime.sim.ext_int_clr |= 1 << i; // Better not be > 31!
|
runtime.sim.ext_int_clr |= 1 << i; // Better not be > 31!
|
}
|
}
|
} /* or1ksim_interrupt() */
|
} /* or1ksim_interrupt () */
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/*!Reset the JTAG interface
|
/*!Reset the JTAG interface
|
|
|
@note Like all the JTAG interface functions, this must not be called
|
@note Like all the JTAG interface functions, this must not be called
|
re-entrantly while a call to any other function (e.g. or1kim_run ())
|
re-entrantly while a call to any other function (e.g. or1kim_run ())
|
is in progress. It is the responsibility of the caller to ensure this
|
is in progress. It is the responsibility of the caller to ensure this
|
constraint is met, for example by use of a SystemC mutex.
|
constraint is met, for example by use of a SystemC mutex.
|
|
|
@return The time in seconds which the reset took. */
|
@return The time in seconds which the reset took. */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
double
|
double
|
or1ksim_jtag_reset ()
|
or1ksim_jtag_reset ()
|
{
|
{
|
/* Number of JTAG clock cycles a reset sequence takes */
|
/* Number of JTAG clock cycles a reset sequence takes */
|
const double JTAG_RESET_CYCLES = 5.0;
|
const double JTAG_RESET_CYCLES = 5.0;
|
|
|
jtag_reset ();
|
jtag_reset ();
|
|
|
return JTAG_RESET_CYCLES * (double) config.debug.jtagcycle_ps / 1.0e12;
|
return JTAG_RESET_CYCLES * (double) config.debug.jtagcycle_ps / 1.0e12;
|
|
|
} /* or1ksim_jtag_reset () */
|
} /* or1ksim_jtag_reset () */
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/*!Shift a JTAG instruction register
|
/*!Shift a JTAG instruction register
|
|
|
@note Like all the JTAG interface functions, this must not be called
|
@note Like all the JTAG interface functions, this must not be called
|
re-entrantly while a call to any other function (e.g. or1kim_run ())
|
re-entrantly while a call to any other function (e.g. or1kim_run ())
|
is in progress. It is the responsibility of the caller to ensure this
|
is in progress. It is the responsibility of the caller to ensure this
|
constraint is met, for example by use of a SystemC mutex.
|
constraint is met, for example by use of a SystemC mutex.
|
|
|
The register is represented as a vector of bytes, with the byte at offset
|
The register is represented as a vector of bytes, with the byte at offset
|
zero being shifted first, and the least significant bit in each byte being
|
zero being shifted first, and the least significant bit in each byte being
|
shifted first. Where the register will not fit in an exact number of bytes,
|
shifted first. Where the register will not fit in an exact number of bytes,
|
the odd bits are in the highest numbered byte, shifted to the low end.
|
the odd bits are in the highest numbered byte, shifted to the low end.
|
|
|
The only JTAG instruction for which we have any significant behavior in
|
The only JTAG instruction for which we have any significant behavior in
|
this model is DEBUG. For completeness the register is parsed and a warning
|
this model is DEBUG. For completeness the register is parsed and a warning
|
given if any register other than DEBUG is shifted.
|
given if any register other than DEBUG is shifted.
|
|
|
@param[in,out] jreg The register to shift in, and the register shifted
|
@param[in,out] jreg The register to shift in, and the register shifted
|
back out.
|
back out.
|
@param[in] num_bits The number of bits in the register. Just for
|
@param[in] num_bits The number of bits in the register. Just for
|
sanity check (it should always be 4).
|
sanity check (it should always be 4).
|
|
|
@return The time in seconds which the shift took. */
|
@return The time in seconds which the shift took. */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
double
|
double
|
or1ksim_jtag_shift_ir (unsigned char *jreg,
|
or1ksim_jtag_shift_ir (unsigned char *jreg,
|
int num_bits)
|
int num_bits)
|
{
|
{
|
jtag_shift_ir (jreg, num_bits);
|
jtag_shift_ir (jreg, num_bits);
|
|
|
return (double) num_bits * (double) config.debug.jtagcycle_ps / 1.0e12;
|
return (double) num_bits * (double) config.debug.jtagcycle_ps / 1.0e12;
|
|
|
} /* or1ksim_jtag_shift_ir () */
|
} /* or1ksim_jtag_shift_ir () */
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/*!Shift a JTAG data register
|
/*!Shift a JTAG data register
|
|
|
@note Like all the JTAG interface functions, this must not be called
|
@note Like all the JTAG interface functions, this must not be called
|
re-entrantly while a call to any other function (e.g. or1kim_run ())
|
re-entrantly while a call to any other function (e.g. or1kim_run ())
|
is in progress. It is the responsibility of the caller to ensure this
|
is in progress. It is the responsibility of the caller to ensure this
|
constraint is met, for example by use of a SystemC mutex.
|
constraint is met, for example by use of a SystemC mutex.
|
|
|
The register is represented as a vector of bytes, with the byte at offset
|
The register is represented as a vector of bytes, with the byte at offset
|
zero being shifted first, and the least significant bit in each byte being
|
zero being shifted first, and the least significant bit in each byte being
|
shifted first. Where the register will not fit in an exact number of bytes,
|
shifted first. Where the register will not fit in an exact number of bytes,
|
the odd bits are in the highest numbered byte, shifted to the low end.
|
the odd bits are in the highest numbered byte, shifted to the low end.
|
|
|
The register is parsed to determine which of the six possible register
|
The register is parsed to determine which of the six possible register
|
types it could be.
|
types it could be.
|
- MODULE_SELECT
|
- MODULE_SELECT
|
- WRITE_COMMNAND
|
- WRITE_COMMNAND
|
- READ_COMMAND
|
- READ_COMMAND
|
- GO_COMMAND
|
- GO_COMMAND
|
- WRITE_CONTROL
|
- WRITE_CONTROL
|
- READ_CONTROL
|
- READ_CONTROL
|
|
|
@note In practice READ_COMMAND is not used. However the functionality is
|
@note In practice READ_COMMAND is not used. However the functionality is
|
provided for future compatibility.
|
provided for future compatibility.
|
|
|
@param[in,out] jreg The register to shift in, and the register shifted
|
@param[in,out] jreg The register to shift in, and the register shifted
|
back out.
|
back out.
|
@param[in] num_bits The number of bits in the register. This is
|
@param[in] num_bits The number of bits in the register. This is
|
essential to prevent bugs where the size of
|
essential to prevent bugs where the size of
|
register supplied is incorrect.
|
register supplied is incorrect.
|
|
|
@return The time in seconds which the shift took. */
|
@return The time in seconds which the shift took. */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
double
|
double
|
or1ksim_jtag_shift_dr (unsigned char *jreg,
|
or1ksim_jtag_shift_dr (unsigned char *jreg,
|
int num_bits)
|
int num_bits)
|
{
|
{
|
jtag_shift_dr (jreg, num_bits);
|
jtag_shift_dr (jreg, num_bits);
|
|
|
return (double) num_bits * (double) config.debug.jtagcycle_ps / 1.0e12;
|
return (double) num_bits * (double) config.debug.jtagcycle_ps / 1.0e12;
|
|
|
} /* or1ksim_jtag_shift_dr () */
|
} /* or1ksim_jtag_shift_dr () */
|
|
|
No newline at end of file
|
No newline at end of file
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/*!Read a block of memory.
|
|
|
|
@param[out] buf Where to put the data.
|
|
@param[in] addr The address to read from.
|
|
@param[in] len The number of bytes to read.
|
|
|
|
@return Number of bytes read, or zero if error. */
|
|
/*---------------------------------------------------------------------------*/
|
|
int
|
|
or1ksim_read_mem (unsigned char *buf,
|
|
unsigned int addr,
|
|
int len)
|
|
{
|
|
int off; /* Offset into the memory */
|
|
|
|
/* Fill the buffer with data */
|
|
for (off = 0; off < len; off++)
|
|
{
|
|
/* Check memory area is valid */
|
|
if (NULL == verify_memoryarea (addr + off))
|
|
{
|
|
/* Fail silently - others can raise any error message. */
|
|
return 0;
|
|
}
|
|
else
|
|
{
|
|
/* Get the memory direct - no translation. */
|
|
buf[off] = eval_direct8 (addr + off, 0, 0);
|
|
}
|
|
}
|
|
|
|
return len;
|
|
|
|
} /* or1ksim_read_mem () */
|
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/*!Write a block of memory.
|
|
|
|
@param[in] buf Where to get the data from.
|
|
@param[in] addr The address to write to.
|
|
@param[in] len The number of bytes to write.
|
|
|
|
@return Number of bytes written, or zero if error. */
|
|
/*---------------------------------------------------------------------------*/
|
|
int
|
|
or1ksim_write_mem (unsigned char *buf,
|
|
unsigned int addr,
|
|
int len)
|
|
{
|
|
int off; /* Offset into the memory */
|
|
|
|
/* Write the bytes to memory */
|
|
for (off = 0; off < len; off++)
|
|
{
|
|
if (NULL == verify_memoryarea (addr + off))
|
|
{
|
|
/* Fail silently - others can raise any error message. */
|
|
return 0;
|
|
}
|
|
else
|
|
{
|
|
/* circumvent the read-only check usually done for mem accesses data
|
|
is in host order, because that's what set_direct32 needs */
|
|
set_program8 (addr + off, buf[off]);
|
|
}
|
|
}
|
|
|
|
return len;
|
|
|
|
} /* or1ksim_write_mem () */
|
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/*!Read a single register
|
|
|
|
The registers follow the GDB sequence for OR1K: GPR0 through GPR31, PC
|
|
(i.e. SPR NPC) and SR (i.e. SPR SR).
|
|
|
|
@param[out] buf Where to put the data.
|
|
@param[in] regnum The register to read.
|
|
@param[in] len Size of the register in bytes
|
|
|
|
@return Size of the register, or zero if error. */
|
|
/*---------------------------------------------------------------------------*/
|
|
int
|
|
or1ksim_read_reg (unsigned char *buf,
|
|
int regnum,
|
|
int len)
|
|
{
|
|
unsigned long int *regbuf = (unsigned long *) buf;
|
|
|
|
if (4 != len)
|
|
{
|
|
return 0; /* Not 32-bit reg */
|
|
}
|
|
|
|
/* Get the relevant register */
|
|
if (regnum < MAX_GPRS)
|
|
{
|
|
*regbuf = cpu_state.reg[regnum];
|
|
}
|
|
else if (PPC_REGNUM == regnum)
|
|
{
|
|
*regbuf = cpu_state.sprs[SPR_PPC];
|
|
}
|
|
else if (NPC_REGNUM == regnum)
|
|
{
|
|
*regbuf = cpu_state.pc;
|
|
}
|
|
else if (SR_REGNUM == regnum)
|
|
{
|
|
*regbuf = cpu_state.sprs[SPR_SR];
|
|
}
|
|
else
|
|
{
|
|
/* Silent error response if we don't know the register */
|
|
return 0;
|
|
}
|
|
|
|
return len;
|
|
|
|
} /* or1ksim_read_reg () */
|
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/*!Write a single register
|
|
|
|
The registers follow the GDB sequence for OR1K: GPR0 through GPR31, PC
|
|
(i.e. SPR NPC) and SR (i.e. SPR SR). The register is specified as a
|
|
sequence of bytes in target endian order.
|
|
|
|
Each byte is packed as a pair of hex digits.
|
|
|
|
@param[in] buf Where to get the data from.
|
|
@param[in] regnum The register to write.
|
|
@param[in] len Size of the register in bytes
|
|
|
|
@return Size of the register, or zero if error. */
|
|
/*---------------------------------------------------------------------------*/
|
|
int
|
|
or1ksim_write_reg (unsigned char *buf,
|
|
int regnum,
|
|
int len)
|
|
{
|
|
unsigned long int *regbuf = (unsigned long *) buf;
|
|
unsigned long int regval = *regbuf;
|
|
|
|
if (4 != len)
|
|
{
|
|
return 0; /* Not 32-bit reg */
|
|
}
|
|
|
|
/* Set the relevant register */
|
|
if (regnum < MAX_GPRS)
|
|
{
|
|
cpu_state.reg[regnum] =regval;
|
|
}
|
|
else if (PPC_REGNUM == regnum)
|
|
{
|
|
cpu_state.sprs[SPR_PPC] = regval;
|
|
}
|
|
else if (NPC_REGNUM == regnum)
|
|
{
|
|
if (cpu_state.pc != regval)
|
|
{
|
|
cpu_state.pc = regval;
|
|
cpu_state.delay_insn = 0;
|
|
pcnext = regval + 4;
|
|
}
|
|
}
|
|
else if (SR_REGNUM == regnum)
|
|
{
|
|
cpu_state.sprs[SPR_SR] = regval;
|
|
}
|
|
else
|
|
{
|
|
/* Silent error response if we don't know the register */
|
|
return 0;
|
|
}
|
|
|
|
return len;
|
|
|
|
} /* or1ksim_write_reg () */
|
|
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
