/* dmmu.c -- Data MMU simulation
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/* dmmu.c -- Data MMU simulation
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 2008 Embecosm Limited
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Copyright (C) 2008 Embecosm Limited
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
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This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify it
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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more details.
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You should have received a copy of the GNU General Public License along
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You should have received a copy of the GNU General Public License along
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* This program is commented throughout in a fashion suitable for processing
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/* This program is commented throughout in a fashion suitable for processing
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with Doxygen. */
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with Doxygen. */
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/* DMMU model, perfectly functional. */
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/* DMMU model, perfectly functional. */
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/* Autoconf and/or portability configuration */
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/* Autoconf and/or portability configuration */
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#include "config.h"
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#include "config.h"
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#include "port.h"
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#include "port.h"
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/* System includes */
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/* System includes */
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#include <stdlib.h>
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#include <stdlib.h>
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/* Package includes */
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/* Package includes */
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#include "dmmu.h"
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#include "dmmu.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "arch.h"
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#include "arch.h"
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#include "execute.h"
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#include "execute.h"
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#include "spr-defs.h"
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#include "spr-defs.h"
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#include "stats.h"
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#include "stats.h"
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#include "except.h"
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#include "except.h"
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#include "sprs.h"
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#include "sprs.h"
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#include "misc.h"
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#include "misc.h"
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#include "sim-cmd.h"
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#include "sim-cmd.h"
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#include "pcu.h"
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struct dmmu *dmmu_state;
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struct dmmu *dmmu_state;
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/* Data MMU */
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/* Data MMU */
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static uorreg_t *
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static uorreg_t *
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dmmu_find_tlbmr (oraddr_t virtaddr, uorreg_t ** dtlbmr_lru, struct dmmu *dmmu)
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dmmu_find_tlbmr (oraddr_t virtaddr, uorreg_t ** dtlbmr_lru, struct dmmu *dmmu)
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{
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{
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int set;
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int set;
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int i;
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int i;
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oraddr_t vpn;
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oraddr_t vpn;
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uorreg_t *dtlbmr;
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uorreg_t *dtlbmr;
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/* Which set to check out? */
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/* Which set to check out? */
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set = DADDR_PAGE (virtaddr) >> dmmu->pagesize_log2;
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set = DADDR_PAGE (virtaddr) >> dmmu->pagesize_log2;
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set &= dmmu->set_mask;
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set &= dmmu->set_mask;
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vpn = virtaddr & dmmu->vpn_mask;
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vpn = virtaddr & dmmu->vpn_mask;
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dtlbmr = &cpu_state.sprs[SPR_DTLBMR_BASE (0) + set];
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dtlbmr = &cpu_state.sprs[SPR_DTLBMR_BASE (0) + set];
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*dtlbmr_lru = dtlbmr;
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*dtlbmr_lru = dtlbmr;
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/* FIXME: Should this be reversed? */
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/* FIXME: Should this be reversed? */
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for (i = dmmu->nways; i; i--, dtlbmr += (128 * 2))
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for (i = dmmu->nways; i; i--, dtlbmr += (128 * 2))
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{
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{
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if (((*dtlbmr & dmmu->vpn_mask) == vpn) && (*dtlbmr & SPR_DTLBMR_V))
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if (((*dtlbmr & dmmu->vpn_mask) == vpn) && (*dtlbmr & SPR_DTLBMR_V))
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return dtlbmr;
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return dtlbmr;
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}
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}
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return NULL;
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return NULL;
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}
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}
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oraddr_t
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oraddr_t
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dmmu_translate (oraddr_t virtaddr, int write_access)
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dmmu_translate (oraddr_t virtaddr, int write_access)
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{
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{
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int i;
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int i;
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uorreg_t *dtlbmr;
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uorreg_t *dtlbmr;
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uorreg_t *dtlbtr;
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uorreg_t *dtlbtr;
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uorreg_t *dtlbmr_lru;
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uorreg_t *dtlbmr_lru;
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struct dmmu *dmmu = dmmu_state;
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struct dmmu *dmmu = dmmu_state;
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if (!(cpu_state.sprs[SPR_SR] & SPR_SR_DME) ||
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if (!(cpu_state.sprs[SPR_SR] & SPR_SR_DME) ||
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!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP))
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!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP))
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{
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{
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data_ci = (virtaddr >= 0x80000000);
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data_ci = (virtaddr >= 0x80000000);
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return virtaddr;
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return virtaddr;
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}
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}
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dtlbmr = dmmu_find_tlbmr (virtaddr, &dtlbmr_lru, dmmu);
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dtlbmr = dmmu_find_tlbmr (virtaddr, &dtlbmr_lru, dmmu);
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/* Did we find our tlb entry? */
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/* Did we find our tlb entry? */
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if (dtlbmr)
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if (dtlbmr)
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{ /* Yes, we did. */
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{ /* Yes, we did. */
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dmmu_stats.loads_tlbhit++;
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dmmu_stats.loads_tlbhit++;
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dtlbtr = dtlbmr + 128;
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dtlbtr = dtlbmr + 128;
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/* Set LRUs */
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/* Set LRUs */
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for (i = 0; i < dmmu->nways; i++, dtlbmr_lru += (128 * 2))
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for (i = 0; i < dmmu->nways; i++, dtlbmr_lru += (128 * 2))
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{
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{
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if (*dtlbmr_lru & SPR_DTLBMR_LRU)
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if (*dtlbmr_lru & SPR_DTLBMR_LRU)
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*dtlbmr_lru = (*dtlbmr_lru & ~SPR_DTLBMR_LRU) |
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*dtlbmr_lru = (*dtlbmr_lru & ~SPR_DTLBMR_LRU) |
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((*dtlbmr_lru & SPR_DTLBMR_LRU) - 0x40);
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((*dtlbmr_lru & SPR_DTLBMR_LRU) - 0x40);
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}
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}
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/* This is not necessary `*dtlbmr &= ~SPR_DTLBMR_LRU;' since SPR_DTLBMR_LRU
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/* This is not necessary `*dtlbmr &= ~SPR_DTLBMR_LRU;' since SPR_DTLBMR_LRU
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* is always decremented and the number of sets is always a power of two and
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* is always decremented and the number of sets is always a power of two and
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* as such lru_reload has all bits set that get touched during decrementing
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* as such lru_reload has all bits set that get touched during decrementing
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* SPR_DTLBMR_LRU */
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* SPR_DTLBMR_LRU */
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*dtlbmr |= dmmu->lru_reload;
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*dtlbmr |= dmmu->lru_reload;
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/* Check if page is cache inhibited */
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/* Check if page is cache inhibited */
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data_ci = *dtlbtr & SPR_DTLBTR_CI;
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data_ci = *dtlbtr & SPR_DTLBTR_CI;
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runtime.sim.mem_cycles += dmmu->hitdelay;
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runtime.sim.mem_cycles += dmmu->hitdelay;
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/* Test for page fault */
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/* Test for page fault */
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if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
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if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
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{
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{
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if ((write_access && !(*dtlbtr & SPR_DTLBTR_SWE))
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if ((write_access && !(*dtlbtr & SPR_DTLBTR_SWE))
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|| (!write_access && !(*dtlbtr & SPR_DTLBTR_SRE)))
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|| (!write_access && !(*dtlbtr & SPR_DTLBTR_SRE)))
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except_handle (EXCEPT_DPF, virtaddr);
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except_handle (EXCEPT_DPF, virtaddr);
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}
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}
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else
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else
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{
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{
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if ((write_access && !(*dtlbtr & SPR_DTLBTR_UWE))
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if ((write_access && !(*dtlbtr & SPR_DTLBTR_UWE))
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|| (!write_access && !(*dtlbtr & SPR_DTLBTR_URE)))
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|| (!write_access && !(*dtlbtr & SPR_DTLBTR_URE)))
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except_handle (EXCEPT_DPF, virtaddr);
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except_handle (EXCEPT_DPF, virtaddr);
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}
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}
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return (*dtlbtr & SPR_DTLBTR_PPN) | (virtaddr &
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return (*dtlbtr & SPR_DTLBTR_PPN) | (virtaddr &
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(dmmu->page_offset_mask));
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(dmmu->page_offset_mask));
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}
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}
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/* No, we didn't. */
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/* No, we didn't. */
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dmmu_stats.loads_tlbmiss++;
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dmmu_stats.loads_tlbmiss++;
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#if 0
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for (i = 0; i < dmmu->nways; i++)
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if (((cpu_state.sprs[SPR_DTLBMR_BASE (i) + set] & SPR_DTLBMR_LRU) >> 6) <
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minlru)
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minway = i;
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cpu_state.sprs[SPR_DTLBMR_BASE (minway) + set] &= ~SPR_DTLBMR_VPN;
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cpu_state.sprs[SPR_DTLBMR_BASE (minway) + set] |= vpn << 12;
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for (i = 0; i < dmmu->nways; i++)
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{
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uorreg_t lru = cpu_state.sprs[SPR_DTLBMR_BASE (i) + set];
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if (lru & SPR_DTLBMR_LRU)
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{
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lru = (lru & ~SPR_DTLBMR_LRU) | ((lru & SPR_DTLBMR_LRU) - 0x40);
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cpu_state.sprs[SPR_DTLBMR_BASE (i) + set] = lru;
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}
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}
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cpu_state.sprs[SPR_DTLBMR_BASE (way) + set] &= ~SPR_DTLBMR_LRU;
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cpu_state.sprs[SPR_DTLBMR_BASE (way) + set] |= (dmmu->nsets - 1) << 6;
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/* 1 to 1 mapping */
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cpu_state.sprs[SPR_DTLBTR_BASE (minway) + set] &= ~SPR_DTLBTR_PPN;
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cpu_state.sprs[SPR_DTLBTR_BASE (minway) + set] |= vpn << 12;
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cpu_state.sprs[SPR_DTLBMR_BASE (minway) + set] |= SPR_DTLBMR_V;
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#endif
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runtime.sim.mem_cycles += dmmu->missdelay;
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runtime.sim.mem_cycles += dmmu->missdelay;
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/* if tlb refill implemented in HW */
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/* if tlb refill implemented in HW */
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/* return ((cpu_state.sprs[SPR_DTLBTR_BASE(minway) + set] & SPR_DTLBTR_PPN) >> 12) * dmmu->pagesize + (virtaddr % dmmu->pagesize); */
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/* return ((cpu_state.sprs[SPR_DTLBTR_BASE(minway) + set] & SPR_DTLBTR_PPN) >> 12) * dmmu->pagesize + (virtaddr % dmmu->pagesize); */
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except_handle (EXCEPT_DTLBMISS, virtaddr);
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except_handle (EXCEPT_DTLBMISS, virtaddr);
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if (config.pcu.enabled)
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pcu_count_event(SPR_PCMR_DTLBM);
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return 0;
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return 0;
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}
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}
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/* DESC: try to find EA -> PA transaltion without changing
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/* DESC: try to find EA -> PA transaltion without changing
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* any of precessor states. if this is not passible gives up
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* any of precessor states. if this is not passible gives up
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* (without triggering exceptions)
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* (without triggering exceptions)
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*
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*
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* PRMS: virtaddr - EA for which to find translation
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* PRMS: virtaddr - EA for which to find translation
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*
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*
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* write_access - 0 ignore testing for write access
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* write_access - 0 ignore testing for write access
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* 1 test for write access, if fails
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* 1 test for write access, if fails
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* do not return translation
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* do not return translation
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*
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*
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* through_dc - 1 go through data cache
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* through_dc - 1 go through data cache
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* 0 ignore data cache
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* 0 ignore data cache
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*
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*
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* RTRN: 0 - no DMMU, DMMU disabled or ITLB miss
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* RTRN: 0 - no DMMU, DMMU disabled or ITLB miss
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* else - appropriate PA (note it DMMU is not present
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* else - appropriate PA (note it DMMU is not present
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* PA === EA)
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* PA === EA)
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*/
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*/
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oraddr_t
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oraddr_t
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peek_into_dtlb (oraddr_t virtaddr, int write_access, int through_dc)
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peek_into_dtlb (oraddr_t virtaddr, int write_access, int through_dc)
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{
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{
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uorreg_t *dtlbmr;
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uorreg_t *dtlbmr;
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uorreg_t *dtlbtr;
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uorreg_t *dtlbtr;
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uorreg_t *dtlbmr_lru;
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uorreg_t *dtlbmr_lru;
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struct dmmu *dmmu = dmmu_state;
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struct dmmu *dmmu = dmmu_state;
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if (!(cpu_state.sprs[SPR_SR] & SPR_SR_DME) ||
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if (!(cpu_state.sprs[SPR_SR] & SPR_SR_DME) ||
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!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP))
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!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP))
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{
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{
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if (through_dc)
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if (through_dc)
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data_ci = (virtaddr >= 0x80000000);
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data_ci = (virtaddr >= 0x80000000);
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return virtaddr;
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return virtaddr;
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}
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}
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dtlbmr = dmmu_find_tlbmr (virtaddr, &dtlbmr_lru, dmmu);
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dtlbmr = dmmu_find_tlbmr (virtaddr, &dtlbmr_lru, dmmu);
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/* Did we find our tlb entry? */
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/* Did we find our tlb entry? */
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if (dtlbmr)
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if (dtlbmr)
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{ /* Yes, we did. */
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{ /* Yes, we did. */
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dmmu_stats.loads_tlbhit++;
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dmmu_stats.loads_tlbhit++;
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dtlbtr = dtlbmr + 128;
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dtlbtr = dtlbmr + 128;
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/* Test for page fault */
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/* Test for page fault */
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if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
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if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
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{
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{
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if ((write_access && !(*dtlbtr & SPR_DTLBTR_SWE)) ||
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if ((write_access && !(*dtlbtr & SPR_DTLBTR_SWE)) ||
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(!write_access && !(*dtlbtr & SPR_DTLBTR_SRE)))
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(!write_access && !(*dtlbtr & SPR_DTLBTR_SRE)))
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/* otherwise exception DPF would be raised */
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/* otherwise exception DPF would be raised */
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return (0);
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return (0);
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}
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}
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else
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else
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{
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{
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if ((write_access && !(*dtlbtr & SPR_DTLBTR_UWE)) ||
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if ((write_access && !(*dtlbtr & SPR_DTLBTR_UWE)) ||
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(!write_access && !(*dtlbtr & SPR_DTLBTR_URE)))
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(!write_access && !(*dtlbtr & SPR_DTLBTR_URE)))
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/* otherwise exception DPF would be raised */
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/* otherwise exception DPF would be raised */
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return (0);
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return (0);
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}
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}
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if (through_dc)
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if (through_dc)
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{
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{
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/* Check if page is cache inhibited */
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/* Check if page is cache inhibited */
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data_ci = *dtlbtr & SPR_DTLBTR_CI;
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data_ci = *dtlbtr & SPR_DTLBTR_CI;
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}
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}
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return (*dtlbtr & SPR_DTLBTR_PPN) | (virtaddr &
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return (*dtlbtr & SPR_DTLBTR_PPN) | (virtaddr &
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(dmmu->page_offset_mask));
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(dmmu->page_offset_mask));
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}
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}
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return (0);
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return (0);
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}
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}
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/* FIXME: Is this comment valid? */
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/* FIXME: Is this comment valid? */
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/* First check if virtual address is covered by DTLB and if it is:
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/* First check if virtual address is covered by DTLB and if it is:
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- increment DTLB read hit stats,
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- increment DTLB read hit stats,
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- set 'lru' at this way to dmmu->ustates - 1 and
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- set 'lru' at this way to dmmu->ustates - 1 and
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decrement 'lru' of other ways unless they have reached 0,
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decrement 'lru' of other ways unless they have reached 0,
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- check page access attributes and invoke DMMU page fault exception
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- check page access attributes and invoke DMMU page fault exception
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handler if necessary
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handler if necessary
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and if not:
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and if not:
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- increment DTLB read miss stats
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- increment DTLB read miss stats
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- find lru way and entry and invoke DTLB miss exception handler
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- find lru way and entry and invoke DTLB miss exception handler
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- set 'lru' with dmmu->ustates - 1 and decrement 'lru' of other
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- set 'lru' with dmmu->ustates - 1 and decrement 'lru' of other
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ways unless they have reached 0
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ways unless they have reached 0
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*/
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*/
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static void
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static void
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dtlb_status (void *dat)
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dtlb_status (void *dat)
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{
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{
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struct dmmu *dmmu = dat;
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struct dmmu *dmmu = dat;
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int set;
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int set;
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int way;
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int way;
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int end_set = dmmu->nsets;
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int end_set = dmmu->nsets;
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|
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if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP))
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if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP))
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{
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{
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PRINTF ("DMMU not implemented. Set UPR[DMP].\n");
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PRINTF ("DMMU not implemented. Set UPR[DMP].\n");
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return;
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return;
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}
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}
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if (0 < end_set)
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if (0 < end_set)
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PRINTF ("\nDMMU: ");
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PRINTF ("\nDMMU: ");
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/* Scan set(s) and way(s). */
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/* Scan set(s) and way(s). */
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for (set = 0; set < end_set; set++)
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for (set = 0; set < end_set; set++)
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{
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{
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for (way = 0; way < dmmu->nways; way++)
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for (way = 0; way < dmmu->nways; way++)
|
{
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{
|
PRINTF ("%s\n", dump_spr (SPR_DTLBMR_BASE (way) + set,
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PRINTF ("%s\n", dump_spr (SPR_DTLBMR_BASE (way) + set,
|
cpu_state.sprs[SPR_DTLBMR_BASE (way) +
|
cpu_state.sprs[SPR_DTLBMR_BASE (way) +
|
set]));
|
set]));
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PRINTF ("%s\n",
|
PRINTF ("%s\n",
|
dump_spr (SPR_DTLBTR_BASE (way) + set,
|
dump_spr (SPR_DTLBTR_BASE (way) + set,
|
cpu_state.sprs[SPR_DTLBTR_BASE (way) + set]));
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cpu_state.sprs[SPR_DTLBTR_BASE (way) + set]));
|
}
|
}
|
}
|
}
|
if (0 < end_set)
|
if (0 < end_set)
|
PRINTF ("\n");
|
PRINTF ("\n");
|
}
|
}
|
|
|
/*---------------------------------------------------[ DMMU configuration ]---*/
|
/*---------------------------------------------------[ DMMU configuration ]---*/
|
|
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/*!Enable or disable the DMMU
|
/*!Enable or disable the DMMU
|
|
|
Set the corresponding field in the UPR
|
Set the corresponding field in the UPR
|
|
|
@param[in] val The value to use
|
@param[in] val The value to use
|
@param[in] dat The config data structure */
|
@param[in] dat The config data structure */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
static void
|
static void
|
dmmu_enabled (union param_val val, void *dat)
|
dmmu_enabled (union param_val val, void *dat)
|
{
|
{
|
struct dmmu *dmmu = dat;
|
struct dmmu *dmmu = dat;
|
|
|
if (val.int_val)
|
if (val.int_val)
|
{
|
{
|
cpu_state.sprs[SPR_UPR] |= SPR_UPR_DMP;
|
cpu_state.sprs[SPR_UPR] |= SPR_UPR_DMP;
|
}
|
}
|
else
|
else
|
{
|
{
|
cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_DMP;
|
cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_DMP;
|
}
|
}
|
|
|
dmmu->enabled = val.int_val;
|
dmmu->enabled = val.int_val;
|
|
|
} /* dmmu_enabled() */
|
} /* dmmu_enabled() */
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/*!Set the number of DMMU sets
|
/*!Set the number of DMMU sets
|
|
|
Value must be a power of 2 <= 256. Ignore any other values with a
|
Value must be a power of 2 <= 256. Ignore any other values with a
|
warning. Set the corresponding DMMU configuration flags.
|
warning. Set the corresponding DMMU configuration flags.
|
|
|
@param[in] val The value to use
|
@param[in] val The value to use
|
@param[in] dat The config data structure */
|
@param[in] dat The config data structure */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
static void
|
static void
|
dmmu_nsets (union param_val val,
|
dmmu_nsets (union param_val val,
|
void *dat)
|
void *dat)
|
{
|
{
|
struct dmmu *dmmu = dat;
|
struct dmmu *dmmu = dat;
|
|
|
if (is_power2 (val.int_val) && val.int_val <= 128)
|
if (is_power2 (val.int_val) && val.int_val <= 128)
|
{
|
{
|
int set_bits = log2_int (val.int_val);
|
int set_bits = log2_int (val.int_val);
|
|
|
dmmu->nsets = val.int_val;
|
dmmu->nsets = val.int_val;
|
|
|
cpu_state.sprs[SPR_DMMUCFGR] &= ~SPR_DMMUCFGR_NTS;
|
cpu_state.sprs[SPR_DMMUCFGR] &= ~SPR_DMMUCFGR_NTS;
|
cpu_state.sprs[SPR_DMMUCFGR] |= set_bits << SPR_DMMUCFGR_NTS_OFF;
|
cpu_state.sprs[SPR_DMMUCFGR] |= set_bits << SPR_DMMUCFGR_NTS_OFF;
|
}
|
}
|
else
|
else
|
{
|
{
|
fprintf (stderr, "Warning DMMU nsets not a power of 2 <= 128: ignored\n");
|
fprintf (stderr, "Warning DMMU nsets not a power of 2 <= 128: ignored\n");
|
}
|
}
|
} /* dmmu_nsets() */
|
} /* dmmu_nsets() */
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/*!Set the number of DMMU ways
|
/*!Set the number of DMMU ways
|
|
|
Value must be in the range 1-4. Ignore other values with a warning. Set the
|
Value must be in the range 1-4. Ignore other values with a warning. Set the
|
corresponding DMMU configuration flags.
|
corresponding DMMU configuration flags.
|
|
|
@param[in] val The value to use
|
@param[in] val The value to use
|
@param[in] dat The config data structure */
|
@param[in] dat The config data structure */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
static void
|
static void
|
dmmu_nways (union param_val val,
|
dmmu_nways (union param_val val,
|
void *dat)
|
void *dat)
|
{
|
{
|
struct dmmu *dmmu = dat;
|
struct dmmu *dmmu = dat;
|
|
|
if (val.int_val >= 1 && val.int_val <= 4)
|
if (val.int_val >= 1 && val.int_val <= 4)
|
{
|
{
|
int way_bits = val.int_val - 1;
|
int way_bits = val.int_val - 1;
|
|
|
dmmu->nways = val.int_val;
|
dmmu->nways = val.int_val;
|
|
|
cpu_state.sprs[SPR_DMMUCFGR] &= ~SPR_DMMUCFGR_NTW;
|
cpu_state.sprs[SPR_DMMUCFGR] &= ~SPR_DMMUCFGR_NTW;
|
cpu_state.sprs[SPR_DMMUCFGR] |= way_bits << SPR_DMMUCFGR_NTW_OFF;
|
cpu_state.sprs[SPR_DMMUCFGR] |= way_bits << SPR_DMMUCFGR_NTW_OFF;
|
}
|
}
|
else
|
else
|
{
|
{
|
fprintf (stderr, "Warning DMMU nways not in range 1-4: ignored\n");
|
fprintf (stderr, "Warning DMMU nways not in range 1-4: ignored\n");
|
}
|
}
|
} /* dmmu_nways() */
|
} /* dmmu_nways() */
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/*!Set the DMMU page size
|
/*!Set the DMMU page size
|
|
|
Value must be a power of 2. Ignore other values with a warning
|
Value must be a power of 2. Ignore other values with a warning
|
|
|
@param[in] val The value to use
|
@param[in] val The value to use
|
@param[in] dat The config data structure */
|
@param[in] dat The config data structure */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
static void
|
static void
|
dmmu_pagesize (union param_val val,
|
dmmu_pagesize (union param_val val,
|
void *dat)
|
void *dat)
|
{
|
{
|
struct dmmu *dmmu = dat;
|
struct dmmu *dmmu = dat;
|
|
|
if (is_power2 (val.int_val))
|
if (is_power2 (val.int_val))
|
{
|
{
|
dmmu->pagesize = val.int_val;
|
dmmu->pagesize = val.int_val;
|
}
|
}
|
else
|
else
|
{
|
{
|
fprintf (stderr, "Warning DMMU page size must be power of 2: ignored\n");
|
fprintf (stderr, "Warning DMMU page size must be power of 2: ignored\n");
|
}
|
}
|
} /* dmmu_pagesize() */
|
} /* dmmu_pagesize() */
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/*!Set the DMMU entry size
|
/*!Set the DMMU entry size
|
|
|
Value must be a power of 2. Ignore other values with a warning
|
Value must be a power of 2. Ignore other values with a warning
|
|
|
@param[in] val The value to use
|
@param[in] val The value to use
|
@param[in] dat The config data structure */
|
@param[in] dat The config data structure */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
static void
|
static void
|
dmmu_entrysize (union param_val val,
|
dmmu_entrysize (union param_val val,
|
void *dat)
|
void *dat)
|
{
|
{
|
struct dmmu *dmmu = dat;
|
struct dmmu *dmmu = dat;
|
|
|
if (is_power2 (val.int_val))
|
if (is_power2 (val.int_val))
|
{
|
{
|
dmmu->entrysize = val.int_val;
|
dmmu->entrysize = val.int_val;
|
}
|
}
|
else
|
else
|
{
|
{
|
fprintf (stderr, "Warning DMMU entry size must be power of 2: ignored\n");
|
fprintf (stderr, "Warning DMMU entry size must be power of 2: ignored\n");
|
}
|
}
|
} /* dmmu_entrysize() */
|
} /* dmmu_entrysize() */
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/*!Set the number of DMMU usage states
|
/*!Set the number of DMMU usage states
|
|
|
Value must be 2, 3 or 4. Ignore other values with a warning
|
Value must be 2, 3 or 4. Ignore other values with a warning
|
|
|
@param[in] val The value to use
|
@param[in] val The value to use
|
@param[in] dat The config data structure */
|
@param[in] dat The config data structure */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
static void
|
static void
|
dmmu_ustates (union param_val val,
|
dmmu_ustates (union param_val val,
|
void *dat)
|
void *dat)
|
{
|
{
|
struct dmmu *dmmu = dat;
|
struct dmmu *dmmu = dat;
|
|
|
if ((val.int_val >= 2) && (val.int_val <= 4))
|
if ((val.int_val >= 2) && (val.int_val <= 4))
|
{
|
{
|
dmmu->ustates = val.int_val;
|
dmmu->ustates = val.int_val;
|
}
|
}
|
else
|
else
|
{
|
{
|
fprintf (stderr, "Warning number of DMMU usage states must be 2, 3 or 4:"
|
fprintf (stderr, "Warning number of DMMU usage states must be 2, 3 or 4:"
|
"ignored\n");
|
"ignored\n");
|
}
|
}
|
} /* dmmu_ustates() */
|
} /* dmmu_ustates() */
|
|
|
|
|
static void
|
static void
|
dmmu_missdelay (union param_val val, void *dat)
|
dmmu_missdelay (union param_val val, void *dat)
|
{
|
{
|
struct dmmu *dmmu = dat;
|
struct dmmu *dmmu = dat;
|
|
|
dmmu->missdelay = val.int_val;
|
dmmu->missdelay = val.int_val;
|
}
|
}
|
|
|
static void
|
static void
|
dmmu_hitdelay (union param_val val, void *dat)
|
dmmu_hitdelay (union param_val val, void *dat)
|
{
|
{
|
struct dmmu *dmmu = dat;
|
struct dmmu *dmmu = dat;
|
|
|
dmmu->hitdelay = val.int_val;
|
dmmu->hitdelay = val.int_val;
|
}
|
}
|
|
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/*!Initialize a new DMMU configuration
|
/*!Initialize a new DMMU configuration
|
|
|
ALL parameters are set explicitly to default values. Corresponding SPR
|
ALL parameters are set explicitly to default values. Corresponding SPR
|
flags are set as appropriate.
|
flags are set as appropriate.
|
|
|
@return The new memory configuration data structure */
|
@return The new memory configuration data structure */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
static void *
|
static void *
|
dmmu_start_sec ()
|
dmmu_start_sec ()
|
{
|
{
|
struct dmmu *dmmu;
|
struct dmmu *dmmu;
|
int set_bits;
|
int set_bits;
|
int way_bits;
|
int way_bits;
|
|
|
if (NULL == (dmmu = malloc (sizeof (struct dmmu))))
|
if (NULL == (dmmu = malloc (sizeof (struct dmmu))))
|
{
|
{
|
fprintf (stderr, "OOM\n");
|
fprintf (stderr, "OOM\n");
|
exit (1);
|
exit (1);
|
}
|
}
|
|
|
dmmu->enabled = 0;
|
dmmu->enabled = 0;
|
dmmu->nsets = 1;
|
dmmu->nsets = 1;
|
dmmu->nways = 1;
|
dmmu->nways = 1;
|
dmmu->pagesize = 8192;
|
dmmu->pagesize = 8192;
|
dmmu->entrysize = 1; /* Not currently used */
|
dmmu->entrysize = 1; /* Not currently used */
|
dmmu->ustates = 2;
|
dmmu->ustates = 2;
|
dmmu->hitdelay = 1;
|
dmmu->hitdelay = 1;
|
dmmu->missdelay = 1;
|
dmmu->missdelay = 1;
|
|
|
if (dmmu->enabled)
|
if (dmmu->enabled)
|
{
|
{
|
cpu_state.sprs[SPR_UPR] |= SPR_UPR_DMP;
|
cpu_state.sprs[SPR_UPR] |= SPR_UPR_DMP;
|
}
|
}
|
else
|
else
|
{
|
{
|
cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_DMP;
|
cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_DMP;
|
}
|
}
|
|
|
set_bits = log2_int (dmmu->nsets);
|
set_bits = log2_int (dmmu->nsets);
|
cpu_state.sprs[SPR_DMMUCFGR] &= ~SPR_DMMUCFGR_NTS;
|
cpu_state.sprs[SPR_DMMUCFGR] &= ~SPR_DMMUCFGR_NTS;
|
cpu_state.sprs[SPR_DMMUCFGR] |= set_bits << SPR_DMMUCFGR_NTS_OFF;
|
cpu_state.sprs[SPR_DMMUCFGR] |= set_bits << SPR_DMMUCFGR_NTS_OFF;
|
|
|
way_bits = dmmu->nways - 1;
|
way_bits = dmmu->nways - 1;
|
cpu_state.sprs[SPR_DMMUCFGR] &= ~SPR_DMMUCFGR_NTW;
|
cpu_state.sprs[SPR_DMMUCFGR] &= ~SPR_DMMUCFGR_NTW;
|
cpu_state.sprs[SPR_DMMUCFGR] |= way_bits << SPR_DMMUCFGR_NTW_OFF;
|
cpu_state.sprs[SPR_DMMUCFGR] |= way_bits << SPR_DMMUCFGR_NTW_OFF;
|
|
|
dmmu_state = dmmu;
|
dmmu_state = dmmu;
|
return dmmu;
|
return dmmu;
|
|
|
} /* dmmu_start_sec() */
|
} /* dmmu_start_sec() */
|
|
|
|
|
static void
|
static void
|
dmmu_end_sec (void *dat)
|
dmmu_end_sec (void *dat)
|
{
|
{
|
struct dmmu *dmmu = dat;
|
struct dmmu *dmmu = dat;
|
|
|
/* Precalculate some values for use during address translation */
|
/* Precalculate some values for use during address translation */
|
dmmu->pagesize_log2 = log2_int (dmmu->pagesize);
|
dmmu->pagesize_log2 = log2_int (dmmu->pagesize);
|
dmmu->page_offset_mask = dmmu->pagesize - 1;
|
dmmu->page_offset_mask = dmmu->pagesize - 1;
|
dmmu->page_mask = ~dmmu->page_offset_mask;
|
dmmu->page_mask = ~dmmu->page_offset_mask;
|
dmmu->vpn_mask = ~((dmmu->pagesize * dmmu->nsets) - 1);
|
dmmu->vpn_mask = ~((dmmu->pagesize * dmmu->nsets) - 1);
|
dmmu->set_mask = dmmu->nsets - 1;
|
dmmu->set_mask = dmmu->nsets - 1;
|
dmmu->lru_reload = (dmmu->set_mask << 6) & SPR_DTLBMR_LRU;
|
dmmu->lru_reload = (dmmu->set_mask << 6) & SPR_DTLBMR_LRU;
|
|
|
if (dmmu->enabled)
|
if (dmmu->enabled)
|
{
|
{
|
PRINTF ("Data MMU %dKB: %d ways, %d sets, entry size %d bytes\n",
|
PRINTF ("Data MMU %dKB: %d ways, %d sets, entry size %d bytes\n",
|
dmmu->nsets * dmmu->entrysize * dmmu->nways / 1024, dmmu->nways,
|
dmmu->nsets * dmmu->entrysize * dmmu->nways / 1024, dmmu->nways,
|
dmmu->nsets, dmmu->entrysize);
|
dmmu->nsets, dmmu->entrysize);
|
reg_sim_stat (dtlb_status, dmmu);
|
reg_sim_stat (dtlb_status, dmmu);
|
}
|
}
|
}
|
}
|
|
|
void
|
void
|
reg_dmmu_sec (void)
|
reg_dmmu_sec (void)
|
{
|
{
|
struct config_section *sec = reg_config_sec ("dmmu", dmmu_start_sec,
|
struct config_section *sec = reg_config_sec ("dmmu", dmmu_start_sec,
|
dmmu_end_sec);
|
dmmu_end_sec);
|
|
|
reg_config_param (sec, "enabled", PARAMT_INT, dmmu_enabled);
|
reg_config_param (sec, "enabled", PARAMT_INT, dmmu_enabled);
|
reg_config_param (sec, "nsets", PARAMT_INT, dmmu_nsets);
|
reg_config_param (sec, "nsets", PARAMT_INT, dmmu_nsets);
|
reg_config_param (sec, "nways", PARAMT_INT, dmmu_nways);
|
reg_config_param (sec, "nways", PARAMT_INT, dmmu_nways);
|
reg_config_param (sec, "pagesize", PARAMT_INT, dmmu_pagesize);
|
reg_config_param (sec, "pagesize", PARAMT_INT, dmmu_pagesize);
|
reg_config_param (sec, "entrysize", PARAMT_INT, dmmu_entrysize);
|
reg_config_param (sec, "entrysize", PARAMT_INT, dmmu_entrysize);
|
reg_config_param (sec, "ustates", PARAMT_INT, dmmu_ustates);
|
reg_config_param (sec, "ustates", PARAMT_INT, dmmu_ustates);
|
reg_config_param (sec, "hitdelay", PARAMT_INT, dmmu_hitdelay);
|
reg_config_param (sec, "hitdelay", PARAMT_INT, dmmu_hitdelay);
|
reg_config_param (sec, "missdelay", PARAMT_INT, dmmu_missdelay);
|
reg_config_param (sec, "missdelay", PARAMT_INT, dmmu_missdelay);
|
}
|
}
|
|
|
