/* dma.c -- Simulation of DMA
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/* dma.c -- Simulation of DMA
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Copyright (C) 2001 by Erez Volk, erez@opencores.org
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Copyright (C) 2001 by Erez Volk, erez@opencores.org
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Copyright (C) 2008 Embecosm Limited
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Copyright (C) 2008 Embecosm Limited
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
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This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify it
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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more details.
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You should have received a copy of the GNU General Public License along
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You should have received a copy of the GNU General Public License along
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* This program is commented throughout in a fashion suitable for processing
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/* This program is commented throughout in a fashion suitable for processing
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with Doxygen. */
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with Doxygen. */
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/* This simulation of the DMA core is not meant to be full. It is written
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/* This simulation of the DMA core is not meant to be full. It is written
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only to allow simulating the Ethernet core. Of course, if anyone feels
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only to allow simulating the Ethernet core. Of course, if anyone feels
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like perfecting it, feel free... */
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like perfecting it, feel free... */
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/* Autoconf and/or portability configuration */
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/* Autoconf and/or portability configuration */
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#include "config.h"
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#include "config.h"
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#include "port.h"
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#include "port.h"
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/* System includes */
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/* System includes */
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#include <stdlib.h>
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#include <stdlib.h>
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/* Package includes */
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/* Package includes */
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#include "dma.h"
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#include "dma.h"
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#include "fields.h"
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#include "fields.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "sched.h"
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#include "sched.h"
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#include "pic.h"
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#include "pic.h"
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#include "toplevel-support.h"
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#include "toplevel-support.h"
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#include "sim-cmd.h"
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#include "sim-cmd.h"
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/* We keep a copy of all our controllers because we have to export an interface
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/* We keep a copy of all our controllers because we have to export an interface
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* to other peripherals eg. ethernet */
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* to other peripherals eg. ethernet */
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static struct dma_controller *dmas = NULL;
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static struct dma_controller *dmas = NULL;
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static unsigned long dma_read_ch_csr (struct dma_channel *channel);
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static unsigned long dma_read_ch_csr (struct dma_channel *channel);
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static void dma_write_ch_csr (struct dma_channel *channel,
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static void dma_write_ch_csr (struct dma_channel *channel,
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unsigned long value);
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unsigned long value);
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static void dma_load_descriptor (struct dma_channel *channel);
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static void dma_load_descriptor (struct dma_channel *channel);
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static void dma_init_transfer (struct dma_channel *channel);
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static void dma_init_transfer (struct dma_channel *channel);
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static void dma_channel_terminate_transfer (struct dma_channel *channel,
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static void dma_channel_terminate_transfer (struct dma_channel *channel,
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int generate_interrupt);
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int generate_interrupt);
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static void dma_channel_clock (void *dat);
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static void dma_channel_clock (void *dat);
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static void masked_increase (oraddr_t * value, unsigned long mask);
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static void masked_increase (oraddr_t * value, unsigned long mask);
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#define CHANNEL_ND_I(ch) (TEST_FLAG(ch->regs.csr,DMA_CH_CSR,MODE) && TEST_FLAG(ch->regs.csr,DMA_CH_CSR,USE_ED) && ch->dma_nd_i)
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#define CHANNEL_ND_I(ch) (TEST_FLAG(ch->regs.csr,DMA_CH_CSR,MODE) && TEST_FLAG(ch->regs.csr,DMA_CH_CSR,USE_ED) && ch->dma_nd_i)
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/* Reset. Initializes all registers to default and places devices in memory address space. */
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/* Reset. Initializes all registers to default and places devices in memory address space. */
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static void
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static void
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dma_reset (void *dat)
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dma_reset (void *dat)
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{
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{
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struct dma_controller *dma = dat;
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struct dma_controller *dma = dat;
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unsigned channel_number;
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unsigned channel_number;
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memset (dma->ch, 0, sizeof (dma->ch));
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memset (dma->ch, 0, sizeof (dma->ch));
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dma->regs.csr = 0;
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dma->regs.csr = 0;
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dma->regs.int_msk_a = 0;
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dma->regs.int_msk_a = 0;
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dma->regs.int_msk_b = 0;
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dma->regs.int_msk_b = 0;
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dma->regs.int_src_a = 0;
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dma->regs.int_src_a = 0;
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dma->regs.int_src_b = 0;
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dma->regs.int_src_b = 0;
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for (channel_number = 0; channel_number < DMA_NUM_CHANNELS;
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for (channel_number = 0; channel_number < DMA_NUM_CHANNELS;
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++channel_number)
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++channel_number)
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{
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{
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dma->ch[channel_number].controller = dma;
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dma->ch[channel_number].controller = dma;
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dma->ch[channel_number].channel_number = channel_number;
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dma->ch[channel_number].channel_number = channel_number;
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dma->ch[channel_number].channel_mask = 1LU << channel_number;
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dma->ch[channel_number].channel_mask = 1LU << channel_number;
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dma->ch[channel_number].regs.am0 = dma->ch[channel_number].regs.am1 =
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dma->ch[channel_number].regs.am0 = dma->ch[channel_number].regs.am1 =
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0xFFFFFFFC;
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0xFFFFFFFC;
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}
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}
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}
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}
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/* Print register values on stdout */
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/* Print register values on stdout */
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static void
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static void
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dma_status (void *dat)
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dma_status (void *dat)
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{
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{
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unsigned j;
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unsigned j;
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struct dma_controller *dma = dat;
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struct dma_controller *dma = dat;
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if (dma->baseaddr == 0)
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if (dma->baseaddr == 0)
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return;
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return;
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PRINTF ("\nDMA controller at 0x%" PRIxADDR ":\n", dma->baseaddr);
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PRINTF ("\nDMA controller at 0x%" PRIxADDR ":\n", dma->baseaddr);
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PRINTF ("CSR : 0x%08lX\n", dma->regs.csr);
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PRINTF ("CSR : 0x%08lX\n", dma->regs.csr);
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PRINTF ("INT_MSK_A : 0x%08lX\n", dma->regs.int_msk_a);
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PRINTF ("INT_MSK_A : 0x%08lX\n", dma->regs.int_msk_a);
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PRINTF ("INT_MSK_B : 0x%08lX\n", dma->regs.int_msk_b);
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PRINTF ("INT_MSK_B : 0x%08lX\n", dma->regs.int_msk_b);
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PRINTF ("INT_SRC_A : 0x%08lX\n", dma->regs.int_src_a);
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PRINTF ("INT_SRC_A : 0x%08lX\n", dma->regs.int_src_a);
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PRINTF ("INT_SRC_B : 0x%08lX\n", dma->regs.int_src_b);
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PRINTF ("INT_SRC_B : 0x%08lX\n", dma->regs.int_src_b);
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for (j = 0; j < DMA_NUM_CHANNELS; ++j)
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for (j = 0; j < DMA_NUM_CHANNELS; ++j)
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{
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{
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struct dma_channel *channel = &(dma->ch[j]);
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struct dma_channel *channel = &(dma->ch[j]);
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if (!channel->referenced)
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if (!channel->referenced)
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continue;
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continue;
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PRINTF ("CH%u_CSR : 0x%08lX\n", j, channel->regs.csr);
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PRINTF ("CH%u_CSR : 0x%08lX\n", j, channel->regs.csr);
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PRINTF ("CH%u_SZ : 0x%08lX\n", j, channel->regs.sz);
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PRINTF ("CH%u_SZ : 0x%08lX\n", j, channel->regs.sz);
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PRINTF ("CH%u_A0 : 0x%08lX\n", j, channel->regs.a0);
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PRINTF ("CH%u_A0 : 0x%08lX\n", j, channel->regs.a0);
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PRINTF ("CH%u_AM0 : 0x%08lX\n", j, channel->regs.am0);
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PRINTF ("CH%u_AM0 : 0x%08lX\n", j, channel->regs.am0);
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PRINTF ("CH%u_A1 : 0x%08lX\n", j, channel->regs.a1);
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PRINTF ("CH%u_A1 : 0x%08lX\n", j, channel->regs.a1);
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PRINTF ("CH%u_AM1 : 0x%08lX\n", j, channel->regs.am1);
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PRINTF ("CH%u_AM1 : 0x%08lX\n", j, channel->regs.am1);
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PRINTF ("CH%u_DESC : 0x%08lX\n", j, channel->regs.desc);
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PRINTF ("CH%u_DESC : 0x%08lX\n", j, channel->regs.desc);
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PRINTF ("CH%u_SWPTR : 0x%08lX\n", j, channel->regs.swptr);
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PRINTF ("CH%u_SWPTR : 0x%08lX\n", j, channel->regs.swptr);
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}
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}
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}
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}
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/* Read a register */
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/* Read a register */
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static uint32_t
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static uint32_t
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dma_read32 (oraddr_t addr, void *dat)
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dma_read32 (oraddr_t addr, void *dat)
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{
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{
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struct dma_controller *dma = dat;
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struct dma_controller *dma = dat;
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uint32_t ret;
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uint32_t ret;
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if (addr < DMA_CH_BASE)
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if (addr < DMA_CH_BASE)
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{
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{
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/* case of global (not per-channel) registers */
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/* case of global (not per-channel) registers */
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switch (addr)
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switch (addr)
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{
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{
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case DMA_CSR:
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case DMA_CSR:
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return dma->regs.csr;
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return dma->regs.csr;
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case DMA_INT_MSK_A:
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case DMA_INT_MSK_A:
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return dma->regs.int_msk_a;
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return dma->regs.int_msk_a;
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case DMA_INT_MSK_B:
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case DMA_INT_MSK_B:
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return dma->regs.int_msk_b;
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return dma->regs.int_msk_b;
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case DMA_INT_SRC_A:
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case DMA_INT_SRC_A:
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if (dma->regs.int_src_a)
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if (dma->regs.int_src_a)
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clear_interrupt (dma->irq);
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clear_interrupt (dma->irq);
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ret = dma->regs.int_src_a;
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ret = dma->regs.int_src_a;
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dma->regs.int_src_a = 0;
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dma->regs.int_src_a = 0;
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return ret;
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return ret;
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case DMA_INT_SRC_B:
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case DMA_INT_SRC_B:
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return dma->regs.int_src_b;
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return dma->regs.int_src_b;
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default:
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default:
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fprintf (stderr,
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fprintf (stderr,
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"dma_read32( 0x%" PRIxADDR " ): Illegal register\n",
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"dma_read32( 0x%" PRIxADDR " ): Illegal register\n",
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addr + dma->baseaddr);
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addr + dma->baseaddr);
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return 0;
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return 0;
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}
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}
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}
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}
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else
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else
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{
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{
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/* case of per-channel registers */
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/* case of per-channel registers */
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unsigned chno = (addr - DMA_CH_BASE) / DMA_CH_SIZE;
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unsigned chno = (addr - DMA_CH_BASE) / DMA_CH_SIZE;
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addr = (addr - DMA_CH_BASE) % DMA_CH_SIZE;
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addr = (addr - DMA_CH_BASE) % DMA_CH_SIZE;
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switch (addr)
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switch (addr)
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{
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{
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case DMA_CH_CSR:
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case DMA_CH_CSR:
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return dma_read_ch_csr (&(dma->ch[chno]));
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return dma_read_ch_csr (&(dma->ch[chno]));
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case DMA_CH_SZ:
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case DMA_CH_SZ:
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return dma->ch[chno].regs.sz;
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return dma->ch[chno].regs.sz;
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case DMA_CH_A0:
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case DMA_CH_A0:
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return dma->ch[chno].regs.a0;
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return dma->ch[chno].regs.a0;
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case DMA_CH_AM0:
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case DMA_CH_AM0:
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return dma->ch[chno].regs.am0;
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return dma->ch[chno].regs.am0;
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case DMA_CH_A1:
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case DMA_CH_A1:
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return dma->ch[chno].regs.a1;
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return dma->ch[chno].regs.a1;
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case DMA_CH_AM1:
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case DMA_CH_AM1:
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return dma->ch[chno].regs.am1;
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return dma->ch[chno].regs.am1;
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case DMA_CH_DESC:
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case DMA_CH_DESC:
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return dma->ch[chno].regs.desc;
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return dma->ch[chno].regs.desc;
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case DMA_CH_SWPTR:
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case DMA_CH_SWPTR:
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return dma->ch[chno].regs.swptr;
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return dma->ch[chno].regs.swptr;
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}
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}
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}
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}
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return 0;
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return 0;
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}
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}
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/* Handle read from a channel CSR */
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/* Handle read from a channel CSR */
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static unsigned long
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static unsigned long
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dma_read_ch_csr (struct dma_channel *channel)
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dma_read_ch_csr (struct dma_channel *channel)
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{
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{
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unsigned long result = channel->regs.csr;
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unsigned long result = channel->regs.csr;
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/* before returning, clear all relevant bits */
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/* before returning, clear all relevant bits */
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CLEAR_FLAG (channel->regs.csr, DMA_CH_CSR, INT_CHUNK_DONE);
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CLEAR_FLAG (channel->regs.csr, DMA_CH_CSR, INT_CHUNK_DONE);
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CLEAR_FLAG (channel->regs.csr, DMA_CH_CSR, INT_DONE);
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CLEAR_FLAG (channel->regs.csr, DMA_CH_CSR, INT_DONE);
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CLEAR_FLAG (channel->regs.csr, DMA_CH_CSR, INT_ERR);
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CLEAR_FLAG (channel->regs.csr, DMA_CH_CSR, INT_ERR);
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CLEAR_FLAG (channel->regs.csr, DMA_CH_CSR, ERR);
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CLEAR_FLAG (channel->regs.csr, DMA_CH_CSR, ERR);
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return result;
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return result;
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}
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}
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/* Write a register */
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/* Write a register */
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static void
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static void
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dma_write32 (oraddr_t addr, uint32_t value, void *dat)
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dma_write32 (oraddr_t addr, uint32_t value, void *dat)
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{
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{
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struct dma_controller *dma = dat;
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struct dma_controller *dma = dat;
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|
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/* case of global (not per-channel) registers */
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/* case of global (not per-channel) registers */
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if (addr < DMA_CH_BASE)
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if (addr < DMA_CH_BASE)
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{
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{
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switch (addr)
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switch (addr)
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{
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{
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case DMA_CSR:
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case DMA_CSR:
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if (TEST_FLAG (value, DMA_CSR, PAUSE))
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if (TEST_FLAG (value, DMA_CSR, PAUSE))
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fprintf (stderr, "dma: PAUSE not implemented\n");
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fprintf (stderr, "dma: PAUSE not implemented\n");
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break;
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break;
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case DMA_INT_MSK_A:
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case DMA_INT_MSK_A:
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dma->regs.int_msk_a = value;
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dma->regs.int_msk_a = value;
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break;
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break;
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case DMA_INT_MSK_B:
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case DMA_INT_MSK_B:
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dma->regs.int_msk_b = value;
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dma->regs.int_msk_b = value;
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break;
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break;
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case DMA_INT_SRC_A:
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case DMA_INT_SRC_A:
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dma->regs.int_src_a = value;
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dma->regs.int_src_a = value;
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break;
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break;
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case DMA_INT_SRC_B:
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case DMA_INT_SRC_B:
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dma->regs.int_src_b = value;
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dma->regs.int_src_b = value;
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break;
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break;
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default:
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default:
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fprintf (stderr,
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fprintf (stderr,
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"dma_write32( 0x%" PRIxADDR " ): Illegal register\n",
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"dma_write32( 0x%" PRIxADDR " ): Illegal register\n",
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addr + dma->baseaddr);
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addr + dma->baseaddr);
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return;
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return;
|
}
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}
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}
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}
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else
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else
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{
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{
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/* case of per-channel registers */
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/* case of per-channel registers */
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unsigned chno = (addr - DMA_CH_BASE) / DMA_CH_SIZE;
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unsigned chno = (addr - DMA_CH_BASE) / DMA_CH_SIZE;
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struct dma_channel *channel = &(dma->ch[chno]);
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struct dma_channel *channel = &(dma->ch[chno]);
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channel->referenced = 1;
|
channel->referenced = 1;
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addr = (addr - DMA_CH_BASE) % DMA_CH_SIZE;
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addr = (addr - DMA_CH_BASE) % DMA_CH_SIZE;
|
switch (addr)
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switch (addr)
|
{
|
{
|
case DMA_CSR:
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case DMA_CSR:
|
dma_write_ch_csr (&(dma->ch[chno]), value);
|
dma_write_ch_csr (&(dma->ch[chno]), value);
|
break;
|
break;
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case DMA_CH_SZ:
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case DMA_CH_SZ:
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channel->regs.sz = value;
|
channel->regs.sz = value;
|
break;
|
break;
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case DMA_CH_A0:
|
case DMA_CH_A0:
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channel->regs.a0 = value;
|
channel->regs.a0 = value;
|
break;
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break;
|
case DMA_CH_AM0:
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case DMA_CH_AM0:
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channel->regs.am0 = value;
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channel->regs.am0 = value;
|
break;
|
break;
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case DMA_CH_A1:
|
case DMA_CH_A1:
|
channel->regs.a1 = value;
|
channel->regs.a1 = value;
|
break;
|
break;
|
case DMA_CH_AM1:
|
case DMA_CH_AM1:
|
channel->regs.am1 = value;
|
channel->regs.am1 = value;
|
break;
|
break;
|
case DMA_CH_DESC:
|
case DMA_CH_DESC:
|
channel->regs.desc = value;
|
channel->regs.desc = value;
|
break;
|
break;
|
case DMA_CH_SWPTR:
|
case DMA_CH_SWPTR:
|
channel->regs.swptr = value;
|
channel->regs.swptr = value;
|
break;
|
break;
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
|
|
/* Write a channel CSR
|
/* Write a channel CSR
|
* This ensures only the writable bits are modified.
|
* This ensures only the writable bits are modified.
|
*/
|
*/
|
static void
|
static void
|
dma_write_ch_csr (struct dma_channel *channel, unsigned long value)
|
dma_write_ch_csr (struct dma_channel *channel, unsigned long value)
|
{
|
{
|
/* Check if we should *start* a transfer */
|
/* Check if we should *start* a transfer */
|
if (!TEST_FLAG (channel->regs.csr, DMA_CH_CSR, CH_EN) &&
|
if (!TEST_FLAG (channel->regs.csr, DMA_CH_CSR, CH_EN) &&
|
TEST_FLAG (value, DMA_CH_CSR, CH_EN))
|
TEST_FLAG (value, DMA_CH_CSR, CH_EN))
|
SCHED_ADD (dma_channel_clock, channel, 1);
|
SCHED_ADD (dma_channel_clock, channel, 1);
|
else if (!TEST_FLAG (value, DMA_CH_CSR, CH_EN))
|
else if (!TEST_FLAG (value, DMA_CH_CSR, CH_EN))
|
/* The CH_EN flag is clear, check if we have a transfer in progress and
|
/* The CH_EN flag is clear, check if we have a transfer in progress and
|
* clear it */
|
* clear it */
|
SCHED_FIND_REMOVE (dma_channel_clock, channel);
|
SCHED_FIND_REMOVE (dma_channel_clock, channel);
|
|
|
/* Copy the writable bits to the channel CSR */
|
/* Copy the writable bits to the channel CSR */
|
channel->regs.csr &= ~DMA_CH_CSR_WRITE_MASK;
|
channel->regs.csr &= ~DMA_CH_CSR_WRITE_MASK;
|
channel->regs.csr |= value & DMA_CH_CSR_WRITE_MASK;
|
channel->regs.csr |= value & DMA_CH_CSR_WRITE_MASK;
|
}
|
}
|
|
|
|
|
|
|
/* Clock tick for one channel on one DMA controller.
|
/* Clock tick for one channel on one DMA controller.
|
* This does the actual "DMA" operation.
|
* This does the actual "DMA" operation.
|
* One chunk is transferred per clock.
|
* One chunk is transferred per clock.
|
*/
|
*/
|
static void
|
static void
|
dma_channel_clock (void *dat)
|
dma_channel_clock (void *dat)
|
{
|
{
|
struct dma_channel *channel = dat;
|
struct dma_channel *channel = dat;
|
|
|
/* Do we need to abort? */
|
/* Do we need to abort? */
|
if (TEST_FLAG (channel->regs.csr, DMA_CH_CSR, STOP))
|
if (TEST_FLAG (channel->regs.csr, DMA_CH_CSR, STOP))
|
{
|
{
|
CLEAR_FLAG (channel->regs.csr, DMA_CH_CSR, CH_EN);
|
CLEAR_FLAG (channel->regs.csr, DMA_CH_CSR, CH_EN);
|
CLEAR_FLAG (channel->regs.csr, DMA_CH_CSR, BUSY);
|
CLEAR_FLAG (channel->regs.csr, DMA_CH_CSR, BUSY);
|
SET_FLAG (channel->regs.csr, DMA_CH_CSR, ERR);
|
SET_FLAG (channel->regs.csr, DMA_CH_CSR, ERR);
|
|
|
if (TEST_FLAG (channel->regs.csr, DMA_CH_CSR, INE_ERR) &&
|
if (TEST_FLAG (channel->regs.csr, DMA_CH_CSR, INE_ERR) &&
|
(channel->controller->regs.int_msk_a & channel->channel_mask))
|
(channel->controller->regs.int_msk_a & channel->channel_mask))
|
{
|
{
|
SET_FLAG (channel->regs.csr, DMA_CH_CSR, INT_ERR);
|
SET_FLAG (channel->regs.csr, DMA_CH_CSR, INT_ERR);
|
channel->controller->regs.int_src_a = channel->channel_mask;
|
channel->controller->regs.int_src_a = channel->channel_mask;
|
report_interrupt (channel->controller->irq);
|
report_interrupt (channel->controller->irq);
|
}
|
}
|
|
|
return;
|
return;
|
}
|
}
|
|
|
/* In HW Handshake mode, only work when dma_req_i asserted */
|
/* In HW Handshake mode, only work when dma_req_i asserted */
|
if (TEST_FLAG (channel->regs.csr, DMA_CH_CSR, MODE) && !channel->dma_req_i)
|
if (TEST_FLAG (channel->regs.csr, DMA_CH_CSR, MODE) && !channel->dma_req_i)
|
{
|
{
|
/* Reschedule */
|
/* Reschedule */
|
SCHED_ADD (dma_channel_clock, dat, 1);
|
SCHED_ADD (dma_channel_clock, dat, 1);
|
return;
|
return;
|
}
|
}
|
|
|
/* If this is the first cycle of the transfer, initialize our state */
|
/* If this is the first cycle of the transfer, initialize our state */
|
if (!TEST_FLAG (channel->regs.csr, DMA_CH_CSR, BUSY))
|
if (!TEST_FLAG (channel->regs.csr, DMA_CH_CSR, BUSY))
|
{
|
{
|
CLEAR_FLAG (channel->regs.csr, DMA_CH_CSR, DONE);
|
CLEAR_FLAG (channel->regs.csr, DMA_CH_CSR, DONE);
|
CLEAR_FLAG (channel->regs.csr, DMA_CH_CSR, ERR);
|
CLEAR_FLAG (channel->regs.csr, DMA_CH_CSR, ERR);
|
SET_FLAG (channel->regs.csr, DMA_CH_CSR, BUSY);
|
SET_FLAG (channel->regs.csr, DMA_CH_CSR, BUSY);
|
|
|
/* If using linked lists, copy the appropriate fields to our registers */
|
/* If using linked lists, copy the appropriate fields to our registers */
|
if (TEST_FLAG (channel->regs.csr, DMA_CH_CSR, USE_ED))
|
if (TEST_FLAG (channel->regs.csr, DMA_CH_CSR, USE_ED))
|
dma_load_descriptor (channel);
|
dma_load_descriptor (channel);
|
else
|
else
|
channel->load_next_descriptor_when_done = 0;
|
channel->load_next_descriptor_when_done = 0;
|
|
|
/* Set our internal status */
|
/* Set our internal status */
|
dma_init_transfer (channel);
|
dma_init_transfer (channel);
|
|
|
/* Might need to skip descriptor */
|
/* Might need to skip descriptor */
|
if (CHANNEL_ND_I (channel))
|
if (CHANNEL_ND_I (channel))
|
{
|
{
|
dma_channel_terminate_transfer (channel, 0);
|
dma_channel_terminate_transfer (channel, 0);
|
return;
|
return;
|
}
|
}
|
}
|
}
|
|
|
/* Transfer one word */
|
/* Transfer one word */
|
set_direct32 (channel->destination, eval_direct32 (channel->source, 0, 0),
|
set_direct32 (channel->destination, eval_direct32 (channel->source, 0, 0),
|
0, 0);
|
0, 0);
|
|
|
/* Advance the source and destionation pointers */
|
/* Advance the source and destionation pointers */
|
masked_increase (&(channel->source), channel->source_mask);
|
masked_increase (&(channel->source), channel->source_mask);
|
masked_increase (&(channel->destination), channel->destination_mask);
|
masked_increase (&(channel->destination), channel->destination_mask);
|
++channel->words_transferred;
|
++channel->words_transferred;
|
|
|
/* Have we finished a whole chunk? */
|
/* Have we finished a whole chunk? */
|
channel->dma_ack_o =
|
channel->dma_ack_o =
|
(channel->words_transferred % channel->chunk_size == 0);
|
(channel->words_transferred % channel->chunk_size == 0);
|
|
|
/* When done with a chunk, check for dma_nd_i */
|
/* When done with a chunk, check for dma_nd_i */
|
if (CHANNEL_ND_I (channel))
|
if (CHANNEL_ND_I (channel))
|
{
|
{
|
dma_channel_terminate_transfer (channel, 0);
|
dma_channel_terminate_transfer (channel, 0);
|
return;
|
return;
|
}
|
}
|
|
|
/* Are we done? */
|
/* Are we done? */
|
if (channel->words_transferred >= channel->total_size)
|
if (channel->words_transferred >= channel->total_size)
|
{
|
{
|
dma_channel_terminate_transfer (channel, 1);
|
dma_channel_terminate_transfer (channel, 1);
|
return;
|
return;
|
}
|
}
|
|
|
/* Reschedule to transfer the next chunk */
|
/* Reschedule to transfer the next chunk */
|
SCHED_ADD (dma_channel_clock, dat, 1);
|
SCHED_ADD (dma_channel_clock, dat, 1);
|
}
|
}
|
|
|
|
|
/* Copy relevant valued from linked list descriptor to channel registers */
|
/* Copy relevant valued from linked list descriptor to channel registers */
|
static void
|
static void
|
dma_load_descriptor (struct dma_channel *channel)
|
dma_load_descriptor (struct dma_channel *channel)
|
{
|
{
|
unsigned long desc_csr =
|
unsigned long desc_csr =
|
eval_direct32 (channel->regs.desc + DMA_DESC_CSR, 0, 0);
|
eval_direct32 (channel->regs.desc + DMA_DESC_CSR, 0, 0);
|
|
|
channel->load_next_descriptor_when_done =
|
channel->load_next_descriptor_when_done =
|
!TEST_FLAG (desc_csr, DMA_DESC_CSR, EOL);
|
!TEST_FLAG (desc_csr, DMA_DESC_CSR, EOL);
|
|
|
ASSIGN_FLAG (channel->regs.csr, DMA_CH_CSR, INC_SRC,
|
ASSIGN_FLAG (channel->regs.csr, DMA_CH_CSR, INC_SRC,
|
TEST_FLAG (desc_csr, DMA_DESC_CSR, INC_SRC));
|
TEST_FLAG (desc_csr, DMA_DESC_CSR, INC_SRC));
|
ASSIGN_FLAG (channel->regs.csr, DMA_CH_CSR, INC_DST,
|
ASSIGN_FLAG (channel->regs.csr, DMA_CH_CSR, INC_DST,
|
TEST_FLAG (desc_csr, DMA_DESC_CSR, INC_DST));
|
TEST_FLAG (desc_csr, DMA_DESC_CSR, INC_DST));
|
ASSIGN_FLAG (channel->regs.csr, DMA_CH_CSR, SRC_SEL,
|
ASSIGN_FLAG (channel->regs.csr, DMA_CH_CSR, SRC_SEL,
|
TEST_FLAG (desc_csr, DMA_DESC_CSR, SRC_SEL));
|
TEST_FLAG (desc_csr, DMA_DESC_CSR, SRC_SEL));
|
ASSIGN_FLAG (channel->regs.csr, DMA_CH_CSR, DST_SEL,
|
ASSIGN_FLAG (channel->regs.csr, DMA_CH_CSR, DST_SEL,
|
TEST_FLAG (desc_csr, DMA_DESC_CSR, DST_SEL));
|
TEST_FLAG (desc_csr, DMA_DESC_CSR, DST_SEL));
|
|
|
SET_FIELD (channel->regs.sz, DMA_CH_SZ, TOT_SZ,
|
SET_FIELD (channel->regs.sz, DMA_CH_SZ, TOT_SZ,
|
GET_FIELD (desc_csr, DMA_DESC_CSR, TOT_SZ));
|
GET_FIELD (desc_csr, DMA_DESC_CSR, TOT_SZ));
|
|
|
channel->regs.a0 = eval_direct32 (channel->regs.desc + DMA_DESC_ADR0, 0, 0);
|
channel->regs.a0 = eval_direct32 (channel->regs.desc + DMA_DESC_ADR0, 0, 0);
|
channel->regs.a1 = eval_direct32 (channel->regs.desc + DMA_DESC_ADR1, 0, 0);
|
channel->regs.a1 = eval_direct32 (channel->regs.desc + DMA_DESC_ADR1, 0, 0);
|
|
|
channel->current_descriptor = channel->regs.desc;
|
channel->current_descriptor = channel->regs.desc;
|
channel->regs.desc =
|
channel->regs.desc =
|
eval_direct32 (channel->regs.desc + DMA_DESC_NEXT, 0, 0);
|
eval_direct32 (channel->regs.desc + DMA_DESC_NEXT, 0, 0);
|
}
|
}
|
|
|
|
|
/* Initialize internal parameters used to implement transfers */
|
/* Initialize internal parameters used to implement transfers */
|
static void
|
static void
|
dma_init_transfer (struct dma_channel *channel)
|
dma_init_transfer (struct dma_channel *channel)
|
{
|
{
|
channel->source = channel->regs.a0;
|
channel->source = channel->regs.a0;
|
channel->destination = channel->regs.a1;
|
channel->destination = channel->regs.a1;
|
channel->source_mask =
|
channel->source_mask =
|
TEST_FLAG (channel->regs.csr, DMA_CH_CSR,
|
TEST_FLAG (channel->regs.csr, DMA_CH_CSR,
|
INC_SRC) ? channel->regs.am0 : 0;
|
INC_SRC) ? channel->regs.am0 : 0;
|
channel->destination_mask =
|
channel->destination_mask =
|
TEST_FLAG (channel->regs.csr, DMA_CH_CSR,
|
TEST_FLAG (channel->regs.csr, DMA_CH_CSR,
|
INC_DST) ? channel->regs.am1 : 0;
|
INC_DST) ? channel->regs.am1 : 0;
|
channel->total_size = GET_FIELD (channel->regs.sz, DMA_CH_SZ, TOT_SZ);
|
channel->total_size = GET_FIELD (channel->regs.sz, DMA_CH_SZ, TOT_SZ);
|
channel->chunk_size = GET_FIELD (channel->regs.sz, DMA_CH_SZ, CHK_SZ);
|
channel->chunk_size = GET_FIELD (channel->regs.sz, DMA_CH_SZ, CHK_SZ);
|
if (!channel->chunk_size || (channel->chunk_size > channel->total_size))
|
if (!channel->chunk_size || (channel->chunk_size > channel->total_size))
|
channel->chunk_size = channel->total_size;
|
channel->chunk_size = channel->total_size;
|
channel->words_transferred = 0;
|
channel->words_transferred = 0;
|
}
|
}
|
|
|
|
|
/* Take care of transfer termination */
|
/* Take care of transfer termination */
|
static void
|
static void
|
dma_channel_terminate_transfer (struct dma_channel *channel,
|
dma_channel_terminate_transfer (struct dma_channel *channel,
|
int generate_interrupt)
|
int generate_interrupt)
|
{
|
{
|
/* Might be working in a linked list */
|
/* Might be working in a linked list */
|
if (channel->load_next_descriptor_when_done)
|
if (channel->load_next_descriptor_when_done)
|
{
|
{
|
dma_load_descriptor (channel);
|
dma_load_descriptor (channel);
|
dma_init_transfer (channel);
|
dma_init_transfer (channel);
|
/* Reschedule */
|
/* Reschedule */
|
SCHED_ADD (dma_channel_clock, channel, 1);
|
SCHED_ADD (dma_channel_clock, channel, 1);
|
return;
|
return;
|
}
|
}
|
|
|
/* Might be in auto-restart mode */
|
/* Might be in auto-restart mode */
|
if (TEST_FLAG (channel->regs.csr, DMA_CH_CSR, ARS))
|
if (TEST_FLAG (channel->regs.csr, DMA_CH_CSR, ARS))
|
{
|
{
|
dma_init_transfer (channel);
|
dma_init_transfer (channel);
|
return;
|
return;
|
}
|
}
|
|
|
/* If needed, write amount of data transferred back to memory */
|
/* If needed, write amount of data transferred back to memory */
|
if (TEST_FLAG (channel->regs.csr, DMA_CH_CSR, SZ_WB) &&
|
if (TEST_FLAG (channel->regs.csr, DMA_CH_CSR, SZ_WB) &&
|
TEST_FLAG (channel->regs.csr, DMA_CH_CSR, USE_ED))
|
TEST_FLAG (channel->regs.csr, DMA_CH_CSR, USE_ED))
|
{
|
{
|
/* TODO: What should we write back? Doc says "total number of remaining bytes" !? */
|
/* TODO: What should we write back? Doc says "total number of remaining bytes" !? */
|
unsigned long remaining_words =
|
unsigned long remaining_words =
|
channel->total_size - channel->words_transferred;
|
channel->total_size - channel->words_transferred;
|
SET_FIELD (channel->regs.sz, DMA_DESC_CSR, TOT_SZ, remaining_words);
|
SET_FIELD (channel->regs.sz, DMA_DESC_CSR, TOT_SZ, remaining_words);
|
}
|
}
|
|
|
/* Mark end of transfer */
|
/* Mark end of transfer */
|
CLEAR_FLAG (channel->regs.csr, DMA_CH_CSR, CH_EN);
|
CLEAR_FLAG (channel->regs.csr, DMA_CH_CSR, CH_EN);
|
SET_FLAG (channel->regs.csr, DMA_CH_CSR, DONE);
|
SET_FLAG (channel->regs.csr, DMA_CH_CSR, DONE);
|
CLEAR_FLAG (channel->regs.csr, DMA_CH_CSR, ERR);
|
CLEAR_FLAG (channel->regs.csr, DMA_CH_CSR, ERR);
|
CLEAR_FLAG (channel->regs.csr, DMA_CH_CSR, BUSY);
|
CLEAR_FLAG (channel->regs.csr, DMA_CH_CSR, BUSY);
|
|
|
/* If needed, generate interrupt */
|
/* If needed, generate interrupt */
|
if (generate_interrupt)
|
if (generate_interrupt)
|
{
|
{
|
/* TODO: Which channel should we interrupt? */
|
/* TODO: Which channel should we interrupt? */
|
if (TEST_FLAG (channel->regs.csr, DMA_CH_CSR, INE_DONE) &&
|
if (TEST_FLAG (channel->regs.csr, DMA_CH_CSR, INE_DONE) &&
|
(channel->controller->regs.int_msk_a & channel->channel_mask))
|
(channel->controller->regs.int_msk_a & channel->channel_mask))
|
{
|
{
|
SET_FLAG (channel->regs.csr, DMA_CH_CSR, INT_DONE);
|
SET_FLAG (channel->regs.csr, DMA_CH_CSR, INT_DONE);
|
channel->controller->regs.int_src_a = channel->channel_mask;
|
channel->controller->regs.int_src_a = channel->channel_mask;
|
report_interrupt (channel->controller->irq);
|
report_interrupt (channel->controller->irq);
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
/* Utility function: Add 4 to a value with a mask */
|
/* Utility function: Add 4 to a value with a mask */
|
static void
|
static void
|
masked_increase (oraddr_t * value, unsigned long mask)
|
masked_increase (oraddr_t * value, unsigned long mask)
|
{
|
{
|
*value = (*value & ~mask) | ((*value + 4) & mask);
|
*value = (*value & ~mask) | ((*value + 4) & mask);
|
}
|
}
|
|
|
/*-------------------------------------------[ DMA<->Peripheral interface ]---*/
|
/*-------------------------------------------[ DMA<->Peripheral interface ]---*/
|
/*
|
/*
|
* Simulation of control signals
|
* Simulation of control signals
|
* To be used by simulations for other devices, e.g. ethernet
|
* To be used by simulations for other devices, e.g. ethernet
|
*/
|
*/
|
|
|
void
|
void
|
set_dma_req_i (struct dma_channel *channel)
|
set_dma_req_i (struct dma_channel *channel)
|
{
|
{
|
channel->dma_req_i = 1;
|
channel->dma_req_i = 1;
|
}
|
}
|
|
|
void
|
void
|
clear_dma_req_i (struct dma_channel *channel)
|
clear_dma_req_i (struct dma_channel *channel)
|
{
|
{
|
channel->dma_req_i = 0;
|
channel->dma_req_i = 0;
|
}
|
}
|
|
|
void
|
void
|
set_dma_nd_i (struct dma_channel *channel)
|
set_dma_nd_i (struct dma_channel *channel)
|
{
|
{
|
channel->dma_nd_i = 1;
|
channel->dma_nd_i = 1;
|
}
|
}
|
|
|
void
|
void
|
clear_dma_nd_i (struct dma_channel *channel)
|
clear_dma_nd_i (struct dma_channel *channel)
|
{
|
{
|
channel->dma_nd_i = 0;
|
channel->dma_nd_i = 0;
|
}
|
}
|
|
|
unsigned
|
unsigned
|
check_dma_ack_o (struct dma_channel *channel)
|
check_dma_ack_o (struct dma_channel *channel)
|
{
|
{
|
return channel->dma_ack_o;
|
return channel->dma_ack_o;
|
}
|
}
|
|
|
struct dma_channel *
|
struct dma_channel *
|
find_dma_controller_ch (unsigned controller, unsigned channel)
|
find_dma_controller_ch (unsigned controller, unsigned channel)
|
{
|
{
|
struct dma_controller *cur = dmas;
|
struct dma_controller *cur = dmas;
|
|
|
while (cur && controller)
|
while (cur && controller)
|
{
|
{
|
cur = cur->next;
|
cur = cur->next;
|
controller--;
|
controller--;
|
}
|
}
|
|
|
if (!cur)
|
if (!cur)
|
return NULL;
|
return NULL;
|
|
|
return &(cur->ch[channel]);
|
return &(cur->ch[channel]);
|
}
|
}
|
|
|
|
|
/*----------------------------------------------------[ DMA configuration ]---*/
|
/*----------------------------------------------------[ DMA configuration ]---*/
|
static void
|
static void
|
dma_baseaddr (union param_val val, void *dat)
|
dma_baseaddr (union param_val val, void *dat)
|
{
|
{
|
struct dma_controller *dma = dat;
|
struct dma_controller *dma = dat;
|
dma->baseaddr = val.addr_val;
|
dma->baseaddr = val.addr_val;
|
}
|
}
|
|
|
static void
|
static void
|
dma_irq (union param_val val, void *dat)
|
dma_irq (union param_val val, void *dat)
|
{
|
{
|
struct dma_controller *dma = dat;
|
struct dma_controller *dma = dat;
|
dma->irq = val.int_val;
|
dma->irq = val.int_val;
|
}
|
}
|
|
|
static void
|
static void
|
dma_vapi_id (union param_val val, void *dat)
|
dma_vapi_id (union param_val val, void *dat)
|
{
|
{
|
struct dma_controller *dma = dat;
|
struct dma_controller *dma = dat;
|
dma->vapi_id = val.int_val;
|
dma->vapi_id = val.int_val;
|
}
|
}
|
|
|
static void
|
static void
|
dma_enabled (union param_val val, void *dat)
|
dma_enabled (union param_val val, void *dat)
|
{
|
{
|
struct dma_controller *dma = dat;
|
struct dma_controller *dma = dat;
|
dma->enabled = val.int_val;
|
dma->enabled = val.int_val;
|
}
|
}
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/*!Initialize a new DMA configuration
|
/*!Initialize a new DMA configuration
|
|
|
ALL parameters are set explicitly to default values. */
|
ALL parameters are set explicitly to default values. */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
static void *
|
static void *
|
dma_sec_start ()
|
dma_sec_start ()
|
{
|
{
|
struct dma_controller *new = malloc (sizeof (struct dma_controller));
|
struct dma_controller *new = malloc (sizeof (struct dma_controller));
|
|
|
if (!new)
|
if (!new)
|
{
|
{
|
fprintf (stderr, "Peripheral DMA: Run out of memory\n");
|
fprintf (stderr, "Peripheral DMA: Run out of memory\n");
|
exit (-1);
|
exit (-1);
|
}
|
}
|
|
|
new->next = NULL;
|
new->next = NULL;
|
new->enabled = 1;
|
new->enabled = 1;
|
new->baseaddr = 0;
|
new->baseaddr = 0;
|
new->irq = 0;
|
new->irq = 0;
|
new->vapi_id = 0;
|
new->vapi_id = 0;
|
|
|
return new;
|
return new;
|
|
|
} /* dma_sec_start() */
|
} /* dma_sec_start() */
|
|
|
static void
|
static void
|
dma_sec_end (void *dat)
|
dma_sec_end (void *dat)
|
{
|
{
|
struct dma_controller *dma = dat;
|
struct dma_controller *dma = dat;
|
struct dma_controller *cur;
|
struct dma_controller *cur;
|
struct mem_ops ops;
|
struct mem_ops ops;
|
|
|
if (!dma->enabled)
|
if (!dma->enabled)
|
{
|
{
|
free (dat);
|
free (dat);
|
return;
|
return;
|
}
|
}
|
|
|
memset (&ops, 0, sizeof (struct mem_ops));
|
memset (&ops, 0, sizeof (struct mem_ops));
|
|
|
ops.readfunc32 = dma_read32;
|
ops.readfunc32 = dma_read32;
|
ops.writefunc32 = dma_write32;
|
ops.writefunc32 = dma_write32;
|
ops.read_dat32 = dat;
|
ops.read_dat32 = dat;
|
ops.write_dat32 = dat;
|
ops.write_dat32 = dat;
|
|
|
/* FIXME: Correct delay?? */
|
/* FIXME: Correct delay?? */
|
ops.delayr = 2;
|
ops.delayr = 2;
|
ops.delayw = 2;
|
ops.delayw = 2;
|
|
|
reg_mem_area (dma->baseaddr, DMA_ADDR_SPACE, 0, &ops);
|
reg_mem_area (dma->baseaddr, DMA_ADDR_SPACE, 0, &ops);
|
reg_sim_reset (dma_reset, dat);
|
reg_sim_reset (dma_reset, dat);
|
reg_sim_stat (dma_status, dat);
|
reg_sim_stat (dma_status, dat);
|
|
|
if (dmas)
|
if (dmas)
|
{
|
{
|
for (cur = dmas; cur->next; cur = cur->next);
|
for (cur = dmas; cur->next; cur = cur->next);
|
cur->next = dma;
|
cur->next = dma;
|
}
|
}
|
else
|
else
|
dmas = dma;
|
dmas = dma;
|
}
|
}
|
|
|
void
|
void
|
reg_dma_sec (void)
|
reg_dma_sec (void)
|
{
|
{
|
struct config_section *sec =
|
struct config_section *sec =
|
reg_config_sec ("dma", dma_sec_start, dma_sec_end);
|
reg_config_sec ("dma", dma_sec_start, dma_sec_end);
|
|
|
reg_config_param (sec, "enabled", paramt_int, dma_enabled);
|
reg_config_param (sec, "enabled", PARAMT_INT, dma_enabled);
|
reg_config_param (sec, "baseaddr", paramt_addr, dma_baseaddr);
|
reg_config_param (sec, "baseaddr", PARAMT_ADDR, dma_baseaddr);
|
reg_config_param (sec, "irq", paramt_int, dma_irq);
|
reg_config_param (sec, "irq", PARAMT_INT, dma_irq);
|
reg_config_param (sec, "vapi_id", paramt_addr, dma_vapi_id);
|
reg_config_param (sec, "vapi_id", PARAMT_ADDR, dma_vapi_id);
|
}
|
}
|
|
|
