/* ethernet.c -- Simulation of Ethernet MAC
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/* ethernet.c -- Simulation of Ethernet MAC
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Copyright (C) 2001 by Erez Volk, erez@opencores.org
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Copyright (C) 2001 by Erez Volk, erez@opencores.org
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Ivan Guzvinec, ivang@opencores.org
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Ivan Guzvinec, ivang@opencores.org
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Copyright (C) 2008 Embecosm Limited
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Copyright (C) 2008, 2001 Embecosm Limited
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Copyright (C) 2010 ORSoC
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Copyright (C) 2010 ORSoC
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
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Contributor Julius Baxter <julius@orsoc.se>
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Contributor Julius Baxter <julius@orsoc.se>
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This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
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This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify it
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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more details.
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You should have received a copy of the GNU General Public License along
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You should have received a copy of the GNU General Public License along
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* This program is commented throughout in a fashion suitable for processing
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/* This program is commented throughout in a fashion suitable for processing
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with Doxygen. */
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with Doxygen. */
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/* Autoconf and/or portability configuration */
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/* Autoconf and/or portability configuration */
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#include "config.h"
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#include "config.h"
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#include "port.h"
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#include "port.h"
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/* System includes */
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/* System includes */
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#include <stdlib.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdio.h>
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#include <sys/socket.h>
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#include <sys/socket.h>
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#include <sys/ioctl.h>
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#include <sys/ioctl.h>
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#include <sys/stat.h>
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#include <sys/stat.h>
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#include <sys/types.h>
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#include <sys/types.h>
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#include <fcntl.h>
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#include <fcntl.h>
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#include <sys/poll.h>
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#include <sys/poll.h>
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#include <unistd.h>
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#include <unistd.h>
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#include <errno.h>
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#include <errno.h>
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#include <linux/if.h>
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#include <linux/if.h>
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#include <linux/if_tun.h>
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#include <linux/if_tun.h>
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/* Package includes */
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/* Package includes */
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#include "arch.h"
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#include "arch.h"
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#include "config.h"
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#include "config.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "eth.h"
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#include "eth.h"
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#include "dma.h"
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#include "dma.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "fields.h"
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#include "fields.h"
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#include "crc32.h"
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#include "crc32.h"
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#include "vapi.h"
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#include "vapi.h"
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#include "pic.h"
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#include "pic.h"
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#include "sched.h"
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#include "sched.h"
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#include "toplevel-support.h"
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#include "toplevel-support.h"
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#include "sim-cmd.h"
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#include "sim-cmd.h"
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/* Control debug messages */
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#ifndef ETH_DEBUG
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# define ETH_DEBUG 1
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#endif
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/* -------------------------------------------------------------------------- */
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/*!Structure describing the Ethernet device */
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/* -------------------------------------------------------------------------- */
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struct eth_device
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struct eth_device
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{
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{
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/* Is peripheral enabled */
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/* Basic stuff about the device */
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int enabled;
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int enabled; /* Is peripheral enabled */
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oraddr_t baseaddr; /* Base address in memory */
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unsigned long int base_vapi_id; /* Start of VAPI ID block */
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/* Base address in memory */
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/* DMA controller this MAC is connected to, and associated channels */
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oraddr_t baseaddr;
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/* Which DMA controller is this MAC connected to */
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unsigned dma;
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unsigned dma;
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unsigned tx_channel;
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unsigned tx_channel;
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unsigned rx_channel;
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unsigned rx_channel;
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/* Our address */
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/* Details of the hardware */
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unsigned char mac_address[ETHER_ADDR_LEN];
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unsigned char mac_address[ETHER_ADDR_LEN]; /* Ext HW address */
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unsigned long int phy_addr; /* Int HW address */
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/* interrupt line number */
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unsigned long int mac_int; /* interrupt line number */
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unsigned long mac_int;
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int int_line_stat; /* interrupt line status */
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/* interrupt line status */
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/* External interface deatils */
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int int_line_stat;
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int rtx_type; /* Type of external i/f: FILE or TAP */
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/* VAPI ID */
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unsigned long base_vapi_id;
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/* Ethernet PHY address */
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unsigned long phy_addr;
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/* What sort of external I/F: FILE or TAP */
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int rtx_type;
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/* RX and TX file names and handles for FILE type connection. */
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/* RX and TX file names and handles for FILE type connection. */
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char *rxfile, *txfile;
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char *rxfile; /* Rx filename */
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int txfd;
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char *txfile; /* Tx filename */
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int rxfd;
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int txfd; /* Rx file handle */
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off_t loopback_offset;
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int rxfd; /* Tx file handle */
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off_t loopback_offset; /* Circular buffer offset */
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/* Info for TAP type connections */
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/* Info for TAP type connections */
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int rtx_fd;
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char *tap_dev; /* The TAP device */
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char *tap_dev;
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int rtx_fd; /* TAP device handle */
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/* Current TX state */
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/* Current TX state */
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struct
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struct
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{
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{
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unsigned long state;
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unsigned long int bd_index;
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unsigned long bd_index;
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unsigned long bd;
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unsigned long bd_addr;
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unsigned working, waiting_for_dma, error;
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long packet_length;
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unsigned minimum_length, maximum_length;
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unsigned add_crc;
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unsigned crc_dly;
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unsigned long crc_value;
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long bytes_left, bytes_sent;
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} tx;
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} tx;
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/* Current RX state */
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/* Current RX state */
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struct
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struct
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{
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{
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unsigned long state;
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enum {
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unsigned long bd_index;
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ETH_RXSTATE_IDLE, /* Was set to 0 */
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unsigned long bd;
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ETH_RXSTATE_WAIT4BD, /* Was set to 10 */
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unsigned long bd_addr;
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ETH_RXSTATE_RECV, /* Was set to 20 */
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ETH_RXSTATE_WRITEFIFO, /* Was set to 30 */
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} state;
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unsigned long int bd_index;
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unsigned long int bd;
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unsigned long int bd_addr;
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int fd;
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int fd;
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off_t *offset;
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off_t *offset;
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unsigned working, error, waiting_for_dma;
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unsigned int working;
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long packet_length, bytes_read, bytes_left;
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unsigned int waiting_for_dma;
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unsigned int error;
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long int packet_length;
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long int bytes_read;
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long int bytes_left;
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} rx;
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} rx;
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/* Visible registers */
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/* Visible registers */
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struct
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struct
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{
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{
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unsigned long moder;
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unsigned long int moder;
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unsigned long int_source;
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unsigned long int int_source;
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unsigned long int_mask;
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unsigned long int int_mask;
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unsigned long ipgt;
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unsigned long int ipgt;
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unsigned long ipgr1;
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unsigned long int ipgr1;
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unsigned long ipgr2;
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unsigned long int ipgr2;
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unsigned long packetlen;
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unsigned long int packetlen;
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unsigned long collconf;
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unsigned long int collconf;
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unsigned long tx_bd_num;
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unsigned long int tx_bd_num;
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unsigned long controlmoder;
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unsigned long int controlmoder;
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unsigned long miimoder;
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unsigned long int miimoder;
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unsigned long miicommand;
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unsigned long int miicommand;
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unsigned long miiaddress;
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unsigned long int miiaddress;
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unsigned long miitx_data;
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unsigned long int miitx_data;
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unsigned long miirx_data;
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unsigned long int miirx_data;
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unsigned long miistatus;
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unsigned long int miistatus;
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unsigned long hash0;
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unsigned long int hash0;
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unsigned long hash1;
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unsigned long int hash1;
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/* Buffer descriptors */
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/* Buffer descriptors */
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unsigned long bd_ram[ETH_BD_SPACE / 4];
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unsigned long int bd_ram[ETH_BD_SPACE / 4];
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} regs;
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} regs;
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unsigned char rx_buff[ETH_MAXPL];
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unsigned char rx_buff[ETH_MAXPL];
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unsigned char tx_buff[ETH_MAXPL];
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unsigned char tx_buff[ETH_MAXPL];
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unsigned char lo_buff[ETH_MAXPL];
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unsigned char lo_buff[ETH_MAXPL];
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};
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};
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/* simulator interface */
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static void eth_vapi_read (unsigned long id, unsigned long data, void *dat);
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/* register interface */
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static void eth_write32 (oraddr_t addr, uint32_t value, void *dat);
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static uint32_t eth_read32 (oraddr_t addr, void *dat);
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/* clock */
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static void eth_controller_tx_clock (void *);
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static void eth_controller_rx_clock (void *);
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/* utility functions */
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static ssize_t eth_read_rx_file (struct eth_device *, void *, size_t);
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static void eth_skip_rx_file (struct eth_device *, off_t);
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static void eth_rx_next_packet (struct eth_device *);
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static void eth_write_tx_bd_num (struct eth_device *, unsigned long value);
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static void eth_miim_trans (void *dat);
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#define ETH_DEBUG 0
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/* ========================================================================== */
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/* Dummy socket routines. These are the points where we spoof an Ethernet */
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/* network. */
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/* -------------------------------------------------------------------------- */
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/* -------------------------------------------------------------------------- */
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/*!Utility function to read from the ethernet RX file.
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Helper function when using file I/O.
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/* ========================================================================= */
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This function moves the file pointer to the current place in the packet
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/* TX LOGIC */
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before reading. The Ethernet device datastructure contains the file
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/*---------------------------------------------------------------------------*/
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descriptor and offset to use.
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@param[in] eth Ethernet device datastruture.
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@param[out] buf Buffer for read data.
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@param[in] count Number of bytes to read.
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@return Number of bytes read, or zero on end-of-file or -1 on error. */
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/* -------------------------------------------------------------------------- */
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static ssize_t
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eth_read_rx_file (struct eth_device *eth,
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void *buf,
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size_t count)
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{
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ssize_t result;
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if (eth->rx.fd <= 0)
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{
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return 0;
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}
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if (eth->rx.offset)
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{
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if (lseek (eth->rx.fd, *(eth->rx.offset), SEEK_SET) == (off_t) - 1)
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{
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return 0;
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}
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}
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result = read (eth->rx.fd, buf, count);
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if (eth->rx.offset && result >= 0)
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{
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*(eth->rx.offset) += result;
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}
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return result;
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} /* eth_read_rx_file () */
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/* -------------------------------------------------------------------------- */
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/*!Skip bytes in the RX file.
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Helper function when using file I/O.
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This just updates the offset pointer in the ethernet device datastructure.
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@param[in] eth Ethernet device datastruture.
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@param[in] count Number of bytes to skip. */
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/* -------------------------------------------------------------------------- */
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static void
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eth_skip_rx_file (struct eth_device *eth,
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off_t count)
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{
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eth->rx.offset += count;
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} /* eth_skip_rx_file () */
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/* -------------------------------------------------------------------------- */
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/* Move to next buffer descriptor in RX file.
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Helper function when using file I/O.
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Skip any remaining bytes in the Rx file for this transaction.
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@param[in] eth Ethernet device datastruture. */
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/* -------------------------------------------------------------------------- */
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static void
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eth_rx_next_packet (struct eth_device *eth)
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{
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/* Skip any possible leftovers */
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if (eth->rx.bytes_left)
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{
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eth_skip_rx_file (eth, eth->rx.bytes_left);
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}
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} /* eth_rx_next_packet () */
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/* -------------------------------------------------------------------------- */
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/*!Emulate MIIM transaction to ethernet PHY
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@param[in] eth Ethernet device datastruture. */
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/* -------------------------------------------------------------------------- */
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static void
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eth_miim_trans (struct eth_device *eth)
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{
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switch (eth->regs.miicommand)
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{
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case ((1 << ETH_MIICOMM_WCDATA_OFFSET)):
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/* Perhaps something to emulate here later, but for now do nothing */
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break;
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case ((1 << ETH_MIICOMM_RSTAT_OFFSET)):
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/*
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/*
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* TX clock
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printf("or1ksim: eth_miim_trans: phy %d\n",(int)
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* Responsible for starting and finishing TX
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((eth->regs.miiaddress >> ETH_MIIADDR_FIAD_OFFSET)&
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ETH_MIIADDR_FIAD_MASK));
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printf("or1ksim: eth_miim_trans: reg %d\n",(int)
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((eth->regs.miiaddress >> ETH_MIIADDR_RGAD_OFFSET)&
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ETH_MIIADDR_RGAD_MASK));
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*/
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*/
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/*First check if it's the correct PHY to address */
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if (((eth->regs.miiaddress >> ETH_MIIADDR_FIAD_OFFSET)&
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ETH_MIIADDR_FIAD_MASK) == eth->phy_addr)
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{
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/* Correct PHY - now switch based on the register address in the PHY*/
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switch ((eth->regs.miiaddress >> ETH_MIIADDR_RGAD_OFFSET)&
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ETH_MIIADDR_RGAD_MASK)
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{
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case MII_BMCR:
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eth->regs.miirx_data = BMCR_FULLDPLX;
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break;
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case MII_BMSR:
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eth->regs.miirx_data = BMSR_LSTATUS | BMSR_ANEGCOMPLETE |
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BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL;
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break;
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case MII_PHYSID1:
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eth->regs.miirx_data = 0x22; /* Micrel PHYID */
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break;
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case MII_PHYSID2:
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eth->regs.miirx_data = 0x1613; /* Micrel PHYID */
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break;
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case MII_ADVERTISE:
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eth->regs.miirx_data = ADVERTISE_FULL;
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break;
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case MII_LPA:
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eth->regs.miirx_data = LPA_DUPLEX | LPA_100;
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break;
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case MII_EXPANSION:
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eth->regs.miirx_data = 0;
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break;
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case MII_CTRL1000:
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eth->regs.miirx_data = 0;
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break;
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case MII_STAT1000:
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eth->regs.miirx_data = 0;
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break;
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case MII_ESTATUS:
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eth->regs.miirx_data = 0;
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break;
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case MII_DCOUNTER:
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eth->regs.miirx_data = 0;
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break;
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case MII_FCSCOUNTER:
|
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eth->regs.miirx_data = 0;
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break;
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case MII_NWAYTEST:
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eth->regs.miirx_data = 0;
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break;
|
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case MII_RERRCOUNTER:
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eth->regs.miirx_data = 0;
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break;
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case MII_SREVISION:
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eth->regs.miirx_data = 0;
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break;
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case MII_RESV1:
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eth->regs.miirx_data = 0;
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break;
|
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case MII_LBRERROR:
|
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eth->regs.miirx_data = 0;
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break;
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case MII_PHYADDR:
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eth->regs.miirx_data = eth->phy_addr;
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break;
|
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case MII_RESV2:
|
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eth->regs.miirx_data = 0;
|
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break;
|
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case MII_TPISTATUS:
|
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eth->regs.miirx_data = 0;
|
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break;
|
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case MII_NCONFIG:
|
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eth->regs.miirx_data = 0;
|
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break;
|
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default:
|
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eth->regs.miirx_data = 0xffff;
|
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break;
|
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}
|
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}
|
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else
|
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{
|
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eth->regs.miirx_data = 0xffff; /* PHY doesn't exist, read all 1's */
|
|
}
|
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|
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break;
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|
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case ((1 << ETH_MIICOMM_SCANS_OFFSET)):
|
|
/* From MAC's datasheet:
|
|
A host initiates the Scan Status Operation by asserting the SCANSTAT
|
|
signal. The MIIM performs a continuous read operation of the PHY
|
|
Status register. The PHY is selected by the FIAD[4:0] signals. The
|
|
link status LinkFail signal is asserted/deasserted by the MIIM module
|
|
and reflects the link status bit of the PHY Status register. The
|
|
signal NVALID is used for qualifying the validity of the LinkFail
|
|
signals and the status data PRSD[15:0]. These signals are invalid
|
|
until the first scan status operation ends. During the scan status
|
|
operation, the BUSY signal is asserted until the last read is
|
|
performed (the scan status operation is stopped).
|
|
|
|
So for now - do nothing, leave link status indicator as permanently
|
|
with link.
|
|
*/
|
|
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
} /* eth_miim_trans () */
|
|
|
|
|
|
/* -------------------------------------------------------------------------- */
|
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/*!Tx clock function.
|
|
|
|
The original version had 4 states, which allowed modeling the transfer of
|
|
data one byte per cycle.
|
|
|
|
For now we use only the one state for efficiency. When we find something in
|
|
a buffer descriptor, we transmit it. We should wake up for this every 10
|
|
cycles.
|
|
|
|
We also remove numerous calculations that are not needed here.
|
|
|
|
@todo We should eventually reinstate the one byte per cycle transfer.
|
|
|
|
Responsible for starting and completing any TX actions.
|
|
|
|
@param[in] dat The Ethernet data structure, passed as a void pointer. */
|
|
/* -------------------------------------------------------------------------- */
|
static void
|
static void
|
eth_controller_tx_clock (void *dat)
|
eth_controller_tx_clock (void *dat)
|
{
|
{
|
struct eth_device *eth = dat;
|
struct eth_device *eth = dat;
|
int bAdvance = 1;
|
|
long nwritten = 0;
|
|
unsigned long read_word;
|
|
|
|
switch (eth->tx.state)
|
/* First word of BD is flags and length, second is pointer to buffer */
|
{
|
unsigned long int bd_info = eth->regs.bd_ram[eth->tx.bd_index];
|
case ETH_TXSTATE_IDLE:
|
unsigned long int bd_addr = eth->regs.bd_ram[eth->tx.bd_index + 1];
|
eth->tx.state = ETH_TXSTATE_WAIT4BD;
|
|
break;
|
|
case ETH_TXSTATE_WAIT4BD:
|
|
/* Read buffer descriptor */
|
|
eth->tx.bd = eth->regs.bd_ram[eth->tx.bd_index];
|
|
eth->tx.bd_addr = eth->regs.bd_ram[eth->tx.bd_index + 1];
|
|
|
|
if (TEST_FLAG (eth->tx.bd, ETH_TX_BD, READY))
|
/* If we have a buffer ready, get it and transmit it. */
|
|
if (TEST_FLAG (bd_info, ETH_TX_BD, READY))
|
{
|
{
|
/*****************/
|
long int packet_length;
|
/* initialize TX */
|
long int bytes_sent;
|
eth->tx.bytes_left = eth->tx.packet_length =
|
long int nwritten = 0;
|
GET_FIELD (eth->tx.bd, ETH_TX_BD, LENGTH);
|
|
eth->tx.bytes_sent = 0;
|
|
|
|
/* Initialize error status bits */
|
|
CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, DEFER);
|
|
CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, COLLISION);
|
|
CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, RETRANSMIT);
|
|
CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, UNDERRUN);
|
|
CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, NO_CARRIER);
|
|
SET_FIELD (eth->tx.bd, ETH_TX_BD, RETRY, 0);
|
|
|
|
/* Find out minimum length */
|
|
if (TEST_FLAG (eth->tx.bd, ETH_TX_BD, PAD) ||
|
|
TEST_FLAG (eth->regs.moder, ETH_MODER, PAD))
|
|
eth->tx.minimum_length =
|
|
GET_FIELD (eth->regs.packetlen, ETH_PACKETLEN, MINFL);
|
|
else
|
|
eth->tx.minimum_length = eth->tx.packet_length;
|
|
|
|
/* Find out maximum length */
|
/* Get the packet length */
|
if (TEST_FLAG (eth->regs.moder, ETH_MODER, HUGEN))
|
packet_length = GET_FIELD (bd_info, ETH_TX_BD, LENGTH);
|
eth->tx.maximum_length = eth->tx.packet_length;
|
|
else
|
|
eth->tx.maximum_length =
|
|
GET_FIELD (eth->regs.packetlen, ETH_PACKETLEN, MAXFL);
|
|
|
|
/* Do we need CRC on this packet? */
|
/* Clear error status bits and retry count. */
|
if (TEST_FLAG (eth->regs.moder, ETH_MODER, CRCEN) ||
|
CLEAR_FLAG (bd_info, ETH_TX_BD, DEFER);
|
(TEST_FLAG (eth->tx.bd, ETH_TX_BD, CRC) &&
|
CLEAR_FLAG (bd_info, ETH_TX_BD, COLLISION);
|
TEST_FLAG (eth->tx.bd, ETH_TX_BD, LAST)))
|
CLEAR_FLAG (bd_info, ETH_TX_BD, RETRANSMIT);
|
eth->tx.add_crc = 1;
|
CLEAR_FLAG (bd_info, ETH_TX_BD, UNDERRUN);
|
else
|
CLEAR_FLAG (bd_info, ETH_TX_BD, NO_CARRIER);
|
eth->tx.add_crc = 0;
|
|
|
|
if (TEST_FLAG (eth->regs.moder, ETH_MODER, DLYCRCEN))
|
SET_FIELD (bd_info, ETH_TX_BD, RETRY, 0);
|
eth->tx.crc_dly = 1;
|
|
else
|
|
eth->tx.crc_dly = 0;
|
|
/* XXX - For now we skip CRC calculation */
|
|
|
|
if (eth->rtx_type == ETH_RTX_FILE)
|
/* Copy data from buffer descriptor address into our local tx_buff. */
|
|
for (bytes_sent = 0; bytes_sent < packet_length; bytes_sent +=4)
|
{
|
{
|
/* write packet length to file */
|
unsigned long int read_word =
|
nwritten =
|
eval_direct32 (bytes_sent + bd_addr, 0, 0);
|
write (eth->txfd, &(eth->tx.packet_length),
|
|
sizeof (eth->tx.packet_length));
|
eth->tx_buff[bytes_sent] = (unsigned char) (read_word >> 24);
|
|
eth->tx_buff[bytes_sent + 1] = (unsigned char) (read_word >> 16);
|
|
eth->tx_buff[bytes_sent + 2] = (unsigned char) (read_word >> 8);
|
|
eth->tx_buff[bytes_sent + 3] = (unsigned char) (read_word);
|
}
|
}
|
|
|
/************************************************/
|
/* Send packet according to interface type. */
|
/* start transmit with reading packet into FIFO */
|
|
eth->tx.state = ETH_TXSTATE_READFIFO;
|
|
}
|
|
|
|
/* stay in this state if (TXEN && !READY) */
|
|
break;
|
|
case ETH_TXSTATE_READFIFO:
|
|
//if (eth->tx.bytes_sent < eth->tx.packet_length)
|
|
while (eth->tx.bytes_sent < eth->tx.packet_length)
|
|
{
|
|
read_word =
|
|
eval_direct32 (eth->tx.bytes_sent + eth->tx.bd_addr, 0, 0);
|
|
eth->tx_buff[eth->tx.bytes_sent] =
|
|
(unsigned char) (read_word >> 24);
|
|
eth->tx_buff[eth->tx.bytes_sent + 1] =
|
|
(unsigned char) (read_word >> 16);
|
|
eth->tx_buff[eth->tx.bytes_sent + 2] =
|
|
(unsigned char) (read_word >> 8);
|
|
eth->tx_buff[eth->tx.bytes_sent + 3] = (unsigned char) (read_word);
|
|
eth->tx.bytes_sent += 4;
|
|
}
|
|
//else
|
|
// {
|
|
eth->tx.state = ETH_TXSTATE_TRANSMIT;
|
|
// }
|
|
break;
|
|
case ETH_TXSTATE_TRANSMIT:
|
|
/* send packet */
|
|
switch (eth->rtx_type)
|
switch (eth->rtx_type)
|
{
|
{
|
case ETH_RTX_FILE:
|
case ETH_RTX_FILE:
|
nwritten = write (eth->txfd, eth->tx_buff, eth->tx.packet_length);
|
/* write packet length to file */
|
|
nwritten =
|
|
write (eth->txfd, &(packet_length),
|
|
sizeof (packet_length));
|
|
/* write data to file */
|
|
nwritten = write (eth->txfd, eth->tx_buff, packet_length);
|
break;
|
break;
|
|
|
case ETH_RTX_TAP:
|
case ETH_RTX_TAP:
|
#if ETH_DEBUG
|
#if ETH_DEBUG
|
|
{
|
|
int j;
|
|
|
printf ("Writing TAP\n");
|
printf ("Writing TAP\n");
|
|
printf (" packet %d bytes:", (int) packet_length);
|
|
|
|
for (j = 0; j < packet_length; j++)
|
|
{
|
|
if (0 == (j % 16))
|
|
{
|
|
printf ("\n");
|
|
}
|
|
else if (0 == (j % 8))
|
|
{
|
|
printf (" ");
|
|
}
|
|
|
printf("packet %d bytes:",(int) eth->tx.packet_length );
|
|
int j; for (j=0;j<eth->tx.packet_length;j++)
|
|
{ if (j%16==0)printf("\n");
|
|
else if (j%8==0) printf(" ");
|
|
printf("%.2x ", eth->tx_buff[j]);
|
printf("%.2x ", eth->tx_buff[j]);
|
}
|
}
|
|
|
printf("\nend packet:\n");
|
printf("\nend packet:\n");
|
|
}
|
#endif
|
#endif
|
nwritten = write (eth->rtx_fd, eth->tx_buff, eth->tx.packet_length);
|
nwritten = write (eth->rtx_fd, eth->tx_buff, packet_length);
|
break;
|
break;
|
}
|
}
|
|
|
/* set BD status */
|
/* Set BD status. If we didn't write the whole packet, then we retry. */
|
if (nwritten == eth->tx.packet_length)
|
if (nwritten == packet_length)
|
{
|
{
|
CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, READY);
|
CLEAR_FLAG (bd_info, ETH_TX_BD, READY);
|
SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, TXB);
|
SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, TXB);
|
|
|
eth->tx.state = ETH_TXSTATE_WAIT4BD;
|
|
}
|
}
|
else
|
else
|
{
|
{
|
/* XXX - implement retry mechanism here! */
|
/* Does this retry mechanism really work? */
|
CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, READY);
|
CLEAR_FLAG (bd_info, ETH_TX_BD, READY);
|
CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, COLLISION);
|
CLEAR_FLAG (bd_info, ETH_TX_BD, COLLISION);
|
SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, TXE);
|
SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, TXE);
|
|
#if ETH_DEBUG
|
eth->tx.state = ETH_TXSTATE_WAIT4BD;
|
printf ("Transmit retry request.\n");
|
|
#endif
|
}
|
}
|
|
|
eth->regs.bd_ram[eth->tx.bd_index] = eth->tx.bd;
|
/* Update the flags in the buffer descriptor */
|
|
eth->regs.bd_ram[eth->tx.bd_index] = bd_info;
|
|
|
|
/* This looks erroneous. Surely it will conflict with the retry flag */
|
SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, TXB);
|
SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, TXB);
|
|
|
/* generate OK interrupt */
|
/* Generate interrupt to indicate transfer complete, under the
|
if (TEST_FLAG (eth->regs.int_mask, ETH_INT_MASK, TXE_M) ||
|
following criteria all being met:
|
TEST_FLAG (eth->regs.int_mask, ETH_INT_MASK, TXB_M))
|
- either INT_MASK flag for Tx (OK or error) is set
|
{
|
- the bugger descriptor has its IRQ flag set
|
if (TEST_FLAG (eth->tx.bd, ETH_TX_BD, IRQ) && !eth->int_line_stat)
|
- there is no interrupt in progress.
|
|
|
|
@todo We ought to warn if we get here and fail to set an IRQ. */
|
|
if ((TEST_FLAG (eth->regs.int_mask, ETH_INT_MASK, TXE_M) ||
|
|
TEST_FLAG (eth->regs.int_mask, ETH_INT_MASK, TXB_M)) &&
|
|
TEST_FLAG (bd_info, ETH_TX_BD, IRQ) &&
|
|
!eth->int_line_stat)
|
{
|
{
|
#if ETH_DEBUG
|
#if ETH_DEBUG
|
printf ("ETH_TXSTATE_TRANSMIT interrupt\n");
|
printf ("TRANSMIT interrupt\n");
|
#endif
|
#endif
|
report_interrupt (eth->mac_int);
|
report_interrupt (eth->mac_int);
|
eth->int_line_stat = 1;
|
eth->int_line_stat = 1;
|
}
|
}
|
|
else
|
|
{
|
|
#if ETH_DEBUG
|
|
printf ("Failed to send TRANSMIT interrupt\n");
|
|
#endif
|
}
|
}
|
|
|
/* advance to next BD */
|
/* Advance to next BD, wrapping around if appropriate. */
|
if (bAdvance)
|
if (TEST_FLAG (bd_info, ETH_TX_BD, WRAP) ||
|
{
|
|
if (TEST_FLAG (eth->tx.bd, ETH_TX_BD, WRAP) ||
|
|
eth->tx.bd_index >= ETH_BD_COUNT)
|
eth->tx.bd_index >= ETH_BD_COUNT)
|
|
{
|
eth->tx.bd_index = 0;
|
eth->tx.bd_index = 0;
|
|
}
|
else
|
else
|
|
{
|
eth->tx.bd_index += 2;
|
eth->tx.bd_index += 2;
|
}
|
}
|
|
|
break;
|
|
}
|
}
|
|
|
/* Reschedule */
|
/* Wake up again after 1 ticks (was 10, changed by Julius). */
|
SCHED_ADD (eth_controller_tx_clock, dat, 1);
|
SCHED_ADD (eth_controller_tx_clock, dat, 1);
|
}
|
|
|
} /* eth_controller_tx_clock () */
|
|
|
|
|
|
/* -------------------------------------------------------------------------- */
|
|
/*!Rx clock function.
|
|
|
|
NEEDS WRITING
|
|
|
|
The original version had 4 states, which allowed modeling the transfer of
|
|
data one byte per cycle.
|
|
|
|
For now we use only the one state for efficiency. When we find something in
|
|
a buffer descriptor, we transmit it. We should wake up for this every 10
|
|
cycles.
|
|
|
|
We also remove numerous calculations that are not needed here.
|
|
|
|
@todo We should eventually reinstate the one byte per cycle transfer.
|
|
|
|
Responsible for starting and completing any TX actions.
|
|
|
|
@param[in] dat The Ethernet data structure, passed as a void pointer. */
|
|
/* -------------------------------------------------------------------------- */
|
|
|
/* ========================================================================= */
|
/* ========================================================================= */
|
|
|
|
|
/* ========================================================================= */
|
/* ========================================================================= */
|
/* RX LOGIC */
|
/* RX LOGIC */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
|
|
/*
|
/*
|
* RX clock
|
* RX clock
|
* Responsible for starting and finishing RX
|
* Responsible for starting and finishing RX
|
*/
|
*/
|
static void
|
static void
|
eth_controller_rx_clock (void *dat)
|
eth_controller_rx_clock (void *dat)
|
{
|
{
|
struct eth_device *eth = dat;
|
struct eth_device *eth = dat;
|
long nread = 0;
|
long nread = 0;
|
unsigned long send_word;
|
unsigned long send_word;
|
struct pollfd fds[1];
|
struct pollfd fds[1];
|
int n;
|
int n;
|
|
|
|
|
switch (eth->rx.state)
|
switch (eth->rx.state)
|
{
|
{
|
case ETH_RXSTATE_IDLE:
|
case ETH_RXSTATE_IDLE:
|
eth->rx.state = ETH_RXSTATE_WAIT4BD;
|
eth->rx.state = ETH_RXSTATE_WAIT4BD;
|
break;
|
break;
|
|
|
case ETH_RXSTATE_WAIT4BD:
|
case ETH_RXSTATE_WAIT4BD:
|
|
|
eth->rx.bd = eth->regs.bd_ram[eth->rx.bd_index];
|
eth->rx.bd = eth->regs.bd_ram[eth->rx.bd_index];
|
eth->rx.bd_addr = eth->regs.bd_ram[eth->rx.bd_index + 1];
|
eth->rx.bd_addr = eth->regs.bd_ram[eth->rx.bd_index + 1];
|
|
|
if (TEST_FLAG (eth->rx.bd, ETH_RX_BD, READY))
|
if (TEST_FLAG (eth->rx.bd, ETH_RX_BD, READY))
|
{
|
{
|
/*****************/
|
/*****************/
|
/* Initialize RX */
|
/* Initialize RX */
|
CLEAR_FLAG (eth->rx.bd, ETH_RX_BD, MISS);
|
CLEAR_FLAG (eth->rx.bd, ETH_RX_BD, MISS);
|
CLEAR_FLAG (eth->rx.bd, ETH_RX_BD, INVALID);
|
CLEAR_FLAG (eth->rx.bd, ETH_RX_BD, INVALID);
|
CLEAR_FLAG (eth->rx.bd, ETH_RX_BD, DRIBBLE);
|
CLEAR_FLAG (eth->rx.bd, ETH_RX_BD, DRIBBLE);
|
CLEAR_FLAG (eth->rx.bd, ETH_RX_BD, UVERRUN);
|
CLEAR_FLAG (eth->rx.bd, ETH_RX_BD, UVERRUN);
|
CLEAR_FLAG (eth->rx.bd, ETH_RX_BD, COLLISION);
|
CLEAR_FLAG (eth->rx.bd, ETH_RX_BD, COLLISION);
|
CLEAR_FLAG (eth->rx.bd, ETH_RX_BD, TOOBIG);
|
CLEAR_FLAG (eth->rx.bd, ETH_RX_BD, TOOBIG);
|
CLEAR_FLAG (eth->rx.bd, ETH_RX_BD, TOOSHORT);
|
CLEAR_FLAG (eth->rx.bd, ETH_RX_BD, TOOSHORT);
|
|
|
/* Setup file to read from */
|
/* Setup file to read from */
|
if (TEST_FLAG (eth->regs.moder, ETH_MODER, LOOPBCK))
|
if (TEST_FLAG (eth->regs.moder, ETH_MODER, LOOPBCK))
|
{
|
{
|
eth->rx.fd = eth->txfd;
|
eth->rx.fd = eth->txfd;
|
eth->rx.offset = &(eth->loopback_offset);
|
eth->rx.offset = &(eth->loopback_offset);
|
}
|
}
|
else
|
else
|
{
|
{
|
eth->rx.fd = eth->rxfd;
|
eth->rx.fd = eth->rxfd;
|
eth->rx.offset = 0;
|
eth->rx.offset = 0;
|
}
|
}
|
eth->rx.state = ETH_RXSTATE_RECV;
|
eth->rx.state = ETH_RXSTATE_RECV;
|
|
|
}
|
}
|
else if (!TEST_FLAG (eth->regs.moder, ETH_MODER, RXEN))
|
else if (!TEST_FLAG (eth->regs.moder, ETH_MODER, RXEN))
|
{
|
{
|
eth->rx.state = ETH_RXSTATE_IDLE;
|
eth->rx.state = ETH_RXSTATE_IDLE;
|
}
|
}
|
else
|
else
|
{
|
{
|
/* Poll to see if there is data to read */
|
/* Poll to see if there is data to read */
|
struct pollfd fds[1];
|
struct pollfd fds[1];
|
int n;
|
int n;
|
|
|
fds[0].fd = eth->rtx_fd;
|
fds[0].fd = eth->rtx_fd;
|
fds[0].events = POLLIN;
|
fds[0].events = POLLIN;
|
|
|
n = poll (fds, 1, 0);
|
n = poll (fds, 1, 0);
|
if (n < 0)
|
if (n < 0)
|
{
|
{
|
fprintf (stderr, "Warning: Poll of WAIT4BD failed %s: ignored.\n",
|
fprintf (stderr, "Warning: Poll of WAIT4BD failed %s: ignored.\n",
|
strerror (errno));
|
strerror (errno));
|
}
|
}
|
else if ((n > 0) && ((fds[0].revents & POLLIN) == POLLIN))
|
else if ((n > 0) && ((fds[0].revents & POLLIN) == POLLIN))
|
{
|
{
|
printf ("Reading TAP and all BDs full = BUSY\n");
|
printf ("Reading TAP and all BDs full = BUSY\n");
|
nread = read (eth->rtx_fd, eth->rx_buff, ETH_MAXPL);
|
nread = read (eth->rtx_fd, eth->rx_buff, ETH_MAXPL);
|
|
|
if (nread < 0)
|
if (nread < 0)
|
{
|
{
|
fprintf (stderr,
|
fprintf (stderr,
|
"Warning: Read of WAIT4BD failed %s: ignored\n",
|
"Warning: Read of WAIT4BD failed %s: ignored\n",
|
strerror (errno));
|
strerror (errno));
|
}
|
}
|
else if (nread > 0)
|
else if (nread > 0)
|
{
|
{
|
SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, BUSY);
|
SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, BUSY);
|
|
|
if (TEST_FLAG (eth->regs.int_mask, ETH_INT_MASK, BUSY_M) &&
|
if (TEST_FLAG (eth->regs.int_mask, ETH_INT_MASK, BUSY_M) &&
|
!eth->int_line_stat)
|
!eth->int_line_stat)
|
{
|
{
|
printf ("ETH_RXSTATE_WAIT4BD BUSY interrupt\n");
|
printf ("ETH_RXSTATE_WAIT4BD BUSY interrupt\n");
|
report_interrupt (eth->mac_int);
|
report_interrupt (eth->mac_int);
|
eth->int_line_stat = 1;
|
eth->int_line_stat = 1;
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
break;
|
break;
|
|
|
case ETH_RXSTATE_RECV:
|
case ETH_RXSTATE_RECV:
|
|
|
switch (eth->rtx_type)
|
switch (eth->rtx_type)
|
{
|
{
|
case ETH_RTX_FILE:
|
case ETH_RTX_FILE:
|
/* Read packet length */
|
/* Read packet length */
|
if (eth_read_rx_file
|
if (eth_read_rx_file
|
(eth, &(eth->rx.packet_length),
|
(eth, &(eth->rx.packet_length),
|
sizeof (eth->rx.packet_length)) <
|
sizeof (eth->rx.packet_length)) <
|
sizeof (eth->rx.packet_length))
|
sizeof (eth->rx.packet_length))
|
{
|
{
|
/* TODO: just do what real ethernet would do (some kind of error
|
/* TODO: just do what real ethernet would do (some kind of error
|
state) */
|
state) */
|
sim_done ();
|
sim_done ();
|
break;
|
break;
|
}
|
}
|
|
|
/* Packet must be big enough to hold a header */
|
/* Packet must be big enough to hold a header */
|
if (eth->rx.packet_length < ETHER_HDR_LEN)
|
if (eth->rx.packet_length < ETHER_HDR_LEN)
|
{
|
{
|
eth_rx_next_packet (eth);
|
eth_rx_next_packet (eth);
|
|
|
eth->rx.state = ETH_RXSTATE_WAIT4BD;
|
eth->rx.state = ETH_RXSTATE_WAIT4BD;
|
break;
|
break;
|
}
|
}
|
|
|
eth->rx.bytes_read = 0;
|
eth->rx.bytes_read = 0;
|
eth->rx.bytes_left = eth->rx.packet_length;
|
eth->rx.bytes_left = eth->rx.packet_length;
|
|
|
/* for now Read entire packet into memory */
|
/* for now Read entire packet into memory */
|
nread = eth_read_rx_file (eth, eth->rx_buff, eth->rx.bytes_left);
|
nread = eth_read_rx_file (eth, eth->rx_buff, eth->rx.bytes_left);
|
if (nread < eth->rx.bytes_left)
|
if (nread < eth->rx.bytes_left)
|
{
|
{
|
eth->rx.error = 1;
|
eth->rx.error = 1;
|
break;
|
break;
|
}
|
}
|
|
|
eth->rx.packet_length = nread;
|
eth->rx.packet_length = nread;
|
eth->rx.bytes_left = nread;
|
eth->rx.bytes_left = nread;
|
eth->rx.bytes_read = 0;
|
eth->rx.bytes_read = 0;
|
|
|
eth->rx.state = ETH_RXSTATE_WRITEFIFO;
|
eth->rx.state = ETH_RXSTATE_WRITEFIFO;
|
|
|
break;
|
break;
|
|
|
case ETH_RTX_TAP:
|
case ETH_RTX_TAP:
|
/* Poll to see if there is data to read */
|
/* Poll to see if there is data to read */
|
fds[0].fd = eth->rtx_fd;
|
fds[0].fd = eth->rtx_fd;
|
fds[0].events = POLLIN;
|
fds[0].events = POLLIN;
|
|
|
n = poll (fds, 1, 0);
|
n = poll (fds, 1, 0);
|
if (n < 0)
|
if (n < 0)
|
{
|
{
|
fprintf (stderr,
|
fprintf (stderr,
|
"Warning: Poll of RXTATE_RECV failed %s: ignored.\n",
|
"Warning: Poll of RXTATE_RECV failed %s: ignored.\n",
|
strerror (errno));
|
strerror (errno));
|
}
|
}
|
else if ((n > 0) && ((fds[0].revents & POLLIN) == POLLIN))
|
else if ((n > 0) && ((fds[0].revents & POLLIN) == POLLIN))
|
{
|
{
|
#if ETH_DEBUG
|
#if ETH_DEBUG
|
printf ("Reading TAP. ");
|
printf ("Reading TAP. ");
|
#endif
|
#endif
|
nread = read (eth->rtx_fd, eth->rx_buff, ETH_MAXPL);
|
nread = read (eth->rtx_fd, eth->rx_buff, ETH_MAXPL);
|
#if ETH_DEBUG
|
#if ETH_DEBUG
|
printf ("%d bytes read.\n",(int) nread);
|
printf ("%d bytes read.\n",(int) nread);
|
#endif
|
#endif
|
if (nread < 0)
|
if (nread < 0)
|
{
|
{
|
fprintf (stderr,
|
fprintf (stderr,
|
"Warning: Read of RXTATE_RECV failed %s: ignored\n",
|
"Warning: Read of RXTATE_RECV failed %s: ignored\n",
|
strerror (errno));
|
strerror (errno));
|
|
|
SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, RXE);
|
SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, RXE);
|
|
|
if (TEST_FLAG (eth->regs.int_mask, ETH_INT_MASK, RXE_M) &&
|
if (TEST_FLAG (eth->regs.int_mask, ETH_INT_MASK, RXE_M) &&
|
!eth->int_line_stat)
|
!eth->int_line_stat)
|
{
|
{
|
printf ("ETH_RXTATE_RECV RXE interrupt\n");
|
printf ("ETH_RXTATE_RECV RXE interrupt\n");
|
report_interrupt (eth->mac_int);
|
report_interrupt (eth->mac_int);
|
eth->int_line_stat = 1;
|
eth->int_line_stat = 1;
|
}
|
}
|
}
|
}
|
|
|
}
|
}
|
|
|
/* If not promiscouos mode, check the destination address */
|
/* If not promiscouos mode, check the destination address */
|
if (!TEST_FLAG (eth->regs.moder, ETH_MODER, PRO) && nread)
|
if (!TEST_FLAG (eth->regs.moder, ETH_MODER, PRO) && nread)
|
{
|
{
|
if (TEST_FLAG (eth->regs.moder, ETH_MODER, IAM)
|
if (TEST_FLAG (eth->regs.moder, ETH_MODER, IAM)
|
&& (eth->rx_buff[0] & 1))
|
&& (eth->rx_buff[0] & 1))
|
{
|
{
|
/* Nothing for now */
|
/* Nothing for now */
|
}
|
}
|
|
|
|
|
if (((eth->mac_address[5] != eth->rx_buff[0]) &&
|
if (((eth->mac_address[5] != eth->rx_buff[0]) &&
|
(eth->rx_buff[5] != 0xff) ) ||
|
(eth->rx_buff[5] != 0xff) ) ||
|
((eth->mac_address[4] != eth->rx_buff[1]) &&
|
((eth->mac_address[4] != eth->rx_buff[1]) &&
|
(eth->rx_buff[4] != 0xff) ) ||
|
(eth->rx_buff[4] != 0xff) ) ||
|
((eth->mac_address[3] != eth->rx_buff[2]) &&
|
((eth->mac_address[3] != eth->rx_buff[2]) &&
|
(eth->rx_buff[3] != 0xff) ) ||
|
(eth->rx_buff[3] != 0xff) ) ||
|
((eth->mac_address[2] != eth->rx_buff[3]) &&
|
((eth->mac_address[2] != eth->rx_buff[3]) &&
|
(eth->rx_buff[2] != 0xff) ) ||
|
(eth->rx_buff[2] != 0xff) ) ||
|
((eth->mac_address[1] != eth->rx_buff[4]) &&
|
((eth->mac_address[1] != eth->rx_buff[4]) &&
|
(eth->rx_buff[1] != 0xff) ) ||
|
(eth->rx_buff[1] != 0xff) ) ||
|
((eth->mac_address[0] != eth->rx_buff[5]) &&
|
((eth->mac_address[0] != eth->rx_buff[5]) &&
|
(eth->rx_buff[0] != 0xff)))
|
(eth->rx_buff[0] != 0xff)))
|
|
|
{
|
{
|
#if ETH_DEBUG
|
#if ETH_DEBUG
|
printf("ETH_RXSTATE dropping packet for %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n",
|
printf("ETH_RXSTATE dropping packet for %.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n",
|
eth->rx_buff[0],
|
eth->rx_buff[0],
|
eth->rx_buff[1],
|
eth->rx_buff[1],
|
eth->rx_buff[2],
|
eth->rx_buff[2],
|
eth->rx_buff[3],
|
eth->rx_buff[3],
|
eth->rx_buff[4],
|
eth->rx_buff[4],
|
eth->rx_buff[5]);
|
eth->rx_buff[5]);
|
#endif
|
#endif
|
break;
|
break;
|
}
|
}
|
}
|
}
|
|
|
eth->rx.packet_length = nread;
|
eth->rx.packet_length = nread;
|
eth->rx.bytes_left = nread;
|
eth->rx.bytes_left = nread;
|
eth->rx.bytes_read = 0;
|
eth->rx.bytes_read = 0;
|
|
|
if (nread)
|
if (nread)
|
eth->rx.state = ETH_RXSTATE_WRITEFIFO;
|
eth->rx.state = ETH_RXSTATE_WRITEFIFO;
|
|
|
break;
|
break;
|
case ETH_RTX_VAPI:
|
case ETH_RTX_VAPI:
|
break;
|
break;
|
}
|
}
|
break;
|
break;
|
|
|
case ETH_RXSTATE_WRITEFIFO:
|
case ETH_RXSTATE_WRITEFIFO:
|
#if ETH_DEBUG
|
#if ETH_DEBUG
|
printf("ETH_RXSTATE_WRITEFIFO: writing to RXBD%d: %d bytes @ 0x%.8x\n",
|
printf("ETH_RXSTATE_WRITEFIFO: writing to RXBD%d: %d bytes @ 0x%.8x\n",
|
(int) eth->rx.bd_index/2, (int)eth->rx.bytes_left,
|
(int) eth->rx.bd_index/2, (int)eth->rx.bytes_left,
|
(unsigned int)eth->rx.bd_addr);
|
(unsigned int)eth->rx.bd_addr);
|
#endif
|
#endif
|
if (eth->rx.bytes_left > 0){
|
if (eth->rx.bytes_left > 0){
|
while((int) eth->rx.bytes_left){
|
while((int) eth->rx.bytes_left){
|
send_word = ((unsigned long) eth->rx_buff[eth->rx.bytes_read] << 24) |
|
send_word = ((unsigned long) eth->rx_buff[eth->rx.bytes_read] << 24) |
|
((unsigned long) eth->rx_buff[eth->rx.bytes_read + 1] << 16) |
|
((unsigned long) eth->rx_buff[eth->rx.bytes_read + 1] << 16) |
|
((unsigned long) eth->rx_buff[eth->rx.bytes_read + 2] << 8) |
|
((unsigned long) eth->rx_buff[eth->rx.bytes_read + 2] << 8) |
|
((unsigned long) eth->rx_buff[eth->rx.bytes_read + 3]);
|
((unsigned long) eth->rx_buff[eth->rx.bytes_read + 3]);
|
set_direct32 (eth->rx.bd_addr + eth->rx.bytes_read, send_word, 0, 0);
|
set_direct32 (eth->rx.bd_addr + eth->rx.bytes_read, send_word, 0, 0);
|
/* update counters */
|
/* update counters */
|
if (eth->rx.bytes_left >= 4)
|
if (eth->rx.bytes_left >= 4)
|
{
|
{
|
eth->rx.bytes_left -= 4;
|
eth->rx.bytes_left -= 4;
|
eth->rx.bytes_read += 4;
|
eth->rx.bytes_read += 4;
|
}
|
}
|
else
|
else
|
{
|
{
|
eth->rx.bytes_read += eth->rx.bytes_left;
|
eth->rx.bytes_read += eth->rx.bytes_left;
|
eth->rx.bytes_left = 0;
|
eth->rx.bytes_left = 0;
|
}
|
}
|
}
|
}
|
|
|
}
|
}
|
#if ETH_DEBUG
|
#if ETH_DEBUG
|
printf("ETH_RXSTATE_WRITEFIFO: bytes read: 0x%.8x\n",
|
printf("ETH_RXSTATE_WRITEFIFO: bytes read: 0x%.8x\n",
|
(unsigned int)eth->rx.bytes_read);
|
(unsigned int)eth->rx.bytes_read);
|
#endif
|
#endif
|
if (eth->rx.bytes_left <= 0)
|
if (eth->rx.bytes_left <= 0)
|
{
|
{
|
/* Write result to bd */
|
/* Write result to bd */
|
SET_FIELD (eth->rx.bd, ETH_RX_BD, LENGTH, eth->rx.packet_length + 4);
|
SET_FIELD (eth->rx.bd, ETH_RX_BD, LENGTH, eth->rx.packet_length + 4);
|
CLEAR_FLAG (eth->rx.bd, ETH_RX_BD, READY);
|
CLEAR_FLAG (eth->rx.bd, ETH_RX_BD, READY);
|
SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, RXB);
|
SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, RXB);
|
/*
|
/*
|
if (eth->rx.packet_length <
|
if (eth->rx.packet_length <
|
(GET_FIELD (eth->regs.packetlen, ETH_PACKETLEN, MINFL) - 4))
|
(GET_FIELD (eth->regs.packetlen, ETH_PACKETLEN, MINFL) - 4))
|
SET_FLAG (eth->rx.bd, ETH_RX_BD, TOOSHORT);
|
SET_FLAG (eth->rx.bd, ETH_RX_BD, TOOSHORT);
|
if (eth->rx.packet_length >
|
if (eth->rx.packet_length >
|
GET_FIELD (eth->regs.packetlen, ETH_PACKETLEN, MAXFL))
|
GET_FIELD (eth->regs.packetlen, ETH_PACKETLEN, MAXFL))
|
SET_FLAG (eth->rx.bd, ETH_RX_BD, TOOBIG);
|
SET_FLAG (eth->rx.bd, ETH_RX_BD, TOOBIG);
|
*/
|
*/
|
eth->regs.bd_ram[eth->rx.bd_index] = eth->rx.bd;
|
eth->regs.bd_ram[eth->rx.bd_index] = eth->rx.bd;
|
|
|
/* advance to next BD */
|
/* advance to next BD */
|
if (TEST_FLAG (eth->rx.bd, ETH_RX_BD, WRAP)
|
if (TEST_FLAG (eth->rx.bd, ETH_RX_BD, WRAP)
|
|| eth->rx.bd_index >= ETH_BD_COUNT)
|
|| eth->rx.bd_index >= ETH_BD_COUNT)
|
eth->rx.bd_index = eth->regs.tx_bd_num << 1;
|
eth->rx.bd_index = eth->regs.tx_bd_num << 1;
|
else
|
else
|
eth->rx.bd_index += 2;
|
eth->rx.bd_index += 2;
|
|
|
SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, RXB);
|
SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, RXB);
|
|
|
if ((TEST_FLAG (eth->regs.int_mask, ETH_INT_MASK, RXB_M)) &&
|
if ((TEST_FLAG (eth->regs.int_mask, ETH_INT_MASK, RXB_M)) &&
|
(TEST_FLAG (eth->rx.bd, ETH_RX_BD, IRQ)) &&
|
(TEST_FLAG (eth->rx.bd, ETH_RX_BD, IRQ)) &&
|
!eth->int_line_stat)
|
!eth->int_line_stat)
|
{
|
{
|
#if ETH_DEBUG
|
#if ETH_DEBUG
|
printf ("ETH_RXSTATE_WRITEFIFO interrupt\n");
|
printf ("ETH_RXSTATE_WRITEFIFO interrupt\n");
|
#endif
|
#endif
|
report_interrupt (eth->mac_int);
|
report_interrupt (eth->mac_int);
|
eth->int_line_stat = 1;
|
eth->int_line_stat = 1;
|
}
|
}
|
|
|
/* ready to receive next packet */
|
/* ready to receive next packet */
|
eth->rx.state = ETH_RXSTATE_IDLE;
|
eth->rx.state = ETH_RXSTATE_IDLE;
|
}
|
}
|
break;
|
break;
|
}
|
}
|
|
|
/* Reschedule */
|
/* Reschedule. Was 10 ticks when waiting (ETH_RXSTATE_RECV). Now always 1
|
|
tick. */
|
SCHED_ADD (eth_controller_rx_clock, dat, 1);
|
SCHED_ADD (eth_controller_rx_clock, dat, 1);
|
}
|
}
|
|
|
/* ========================================================================= */
|
/* ========================================================================= */
|
/* Move to next RX BD */
|
|
static void
|
|
eth_rx_next_packet (struct eth_device *eth)
|
|
{
|
|
/* Skip any possible leftovers */
|
|
if (eth->rx.bytes_left)
|
|
eth_skip_rx_file (eth, eth->rx.bytes_left);
|
|
}
|
|
|
|
/* "Skip" bytes in RX file */
|
/* ========================================================================= */
|
static void
|
|
eth_skip_rx_file (struct eth_device *eth, off_t count)
|
|
{
|
|
eth->rx.offset += count;
|
|
}
|
|
|
|
/*
|
/*
|
* Utility function to read from the ethernet RX file
|
* VAPI connection to outside
|
* This function moves the file pointer to the current place in the packet before reading
|
|
*/
|
*/
|
static ssize_t
|
static void
|
eth_read_rx_file (struct eth_device *eth, void *buf, size_t count)
|
eth_vapi_read (unsigned long id, unsigned long data, void *dat)
|
{
|
{
|
ssize_t result;
|
unsigned long which;
|
|
struct eth_device *eth = dat;
|
|
|
if (eth->rx.fd <= 0)
|
which = id - eth->base_vapi_id;
|
|
|
|
if (!eth)
|
{
|
{
|
return 0;
|
return;
|
}
|
}
|
|
|
if (eth->rx.offset)
|
switch (which)
|
if (lseek (eth->rx.fd, *(eth->rx.offset), SEEK_SET) == (off_t) - 1)
|
|
{
|
{
|
return 0;
|
case ETH_VAPI_DATA:
|
|
break;
|
|
case ETH_VAPI_CTRL:
|
|
break;
|
}
|
}
|
|
|
result = read (eth->rx.fd, buf, count);
|
|
if (eth->rx.offset && result >= 0)
|
|
*(eth->rx.offset) += result;
|
|
|
|
return result;
|
|
}
|
}
|
|
|
/* ========================================================================= */
|
|
|
|
|
|
/* -------------------------------------------------------------------------- */
|
/* -------------------------------------------------------------------------- */
|
/*!Reset the Ethernet.
|
/*!Reset the Ethernet.
|
|
|
Open the correct type of simulation interface to the outside world.
|
Open the correct type of simulation interface to the outside world.
|
|
|
Initialize all registers to default and places devices in memory address
|
Initialize all registers to default and places devices in memory address
|
space.
|
space.
|
|
|
@param[in] dat The Ethernet interface data structure. */
|
@param[in] dat The Ethernet interface data structure. */
|
/* -------------------------------------------------------------------------- */
|
/* -------------------------------------------------------------------------- */
|
static void
|
static void
|
eth_reset (void *dat)
|
eth_reset (void *dat)
|
{
|
{
|
struct eth_device *eth = dat;
|
struct eth_device *eth = dat;
|
struct ifreq ifr;
|
struct ifreq ifr;
|
|
|
#if ETH_DEBUG
|
#if ETH_DEBUG
|
printf ("Resetting Ethernet\n");
|
printf ("Resetting Ethernet\n");
|
#endif
|
#endif
|
/* Nothing to do if we do not have a base address set.
|
/* Nothing to do if we do not have a base address set.
|
|
|
TODO: Surely this should test for being enabled? */
|
TODO: Surely this should test for being enabled? */
|
if (0 == eth->baseaddr)
|
if (0 == eth->baseaddr)
|
{
|
{
|
return;
|
return;
|
}
|
}
|
|
|
switch (eth->rtx_type)
|
switch (eth->rtx_type)
|
{
|
{
|
case ETH_RTX_FILE:
|
case ETH_RTX_FILE:
|
|
|
/* (Re-)open TX/RX files */
|
/* (Re-)open TX/RX files */
|
if (eth->rxfd >= 0)
|
if (eth->rxfd >= 0)
|
{
|
{
|
close (eth->rxfd);
|
close (eth->rxfd);
|
}
|
}
|
|
|
if (eth->txfd >= 0)
|
if (eth->txfd >= 0)
|
{
|
{
|
close (eth->txfd);
|
close (eth->txfd);
|
}
|
}
|
|
|
eth->rxfd = -1;
|
eth->rxfd = -1;
|
eth->txfd = -1;
|
eth->txfd = -1;
|
|
|
eth->rxfd = open (eth->rxfile, O_RDONLY);
|
eth->rxfd = open (eth->rxfile, O_RDONLY);
|
if (eth->rxfd < 0)
|
if (eth->rxfd < 0)
|
{
|
{
|
fprintf (stderr, "Warning: Cannot open Ethernet RX file \"%s\": %s\n",
|
fprintf (stderr, "Warning: Cannot open Ethernet RX file \"%s\": %s\n",
|
eth->rxfile, strerror (errno));
|
eth->rxfile, strerror (errno));
|
}
|
}
|
|
|
eth->txfd = open (eth->txfile,
|
eth->txfd = open (eth->txfile,
|
#if defined(O_SYNC) /* BSD/MacOS X doesn't know about O_SYNC */
|
#if defined(O_SYNC) /* BSD/MacOS X doesn't know about O_SYNC */
|
O_SYNC |
|
O_SYNC |
|
#endif
|
#endif
|
O_RDWR | O_CREAT | O_APPEND,
|
O_RDWR | O_CREAT | O_APPEND,
|
S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH);
|
S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH);
|
if (eth->txfd < 0)
|
if (eth->txfd < 0)
|
{
|
{
|
fprintf (stderr, "Warning: Cannot open Ethernet TX file \"%s\": %s\n",
|
fprintf (stderr, "Warning: Cannot open Ethernet TX file \"%s\": %s\n",
|
eth->txfile, strerror (errno));
|
eth->txfile, strerror (errno));
|
}
|
}
|
|
|
eth->loopback_offset = lseek (eth->txfd, 0, SEEK_END);
|
eth->loopback_offset = lseek (eth->txfd, 0, SEEK_END);
|
break;
|
break;
|
|
|
case ETH_RTX_TAP:
|
case ETH_RTX_TAP:
|
|
|
/* (Re-)open TAP interface if necessary */
|
/* (Re-)open TAP interface if necessary */
|
if (eth->rtx_fd != 0)
|
if (eth->rtx_fd != 0)
|
{
|
{
|
break;
|
break;
|
}
|
}
|
|
|
/* Open the TUN/TAP device */
|
/* Open the TUN/TAP device */
|
eth->rtx_fd = open ("/dev/net/tun", O_RDWR);
|
eth->rtx_fd = open ("/dev/net/tun", O_RDWR);
|
if( eth->rtx_fd < 0 )
|
if( eth->rtx_fd < 0 )
|
{
|
{
|
fprintf (stderr, "Warning: Failed to open TUN/TAP device: %s\n",
|
fprintf (stderr, "Warning: Failed to open TUN/TAP device: %s\n",
|
strerror (errno));
|
strerror (errno));
|
eth->rtx_fd = 0;
|
eth->rtx_fd = 0;
|
return;
|
return;
|
}
|
}
|
|
|
/* Turn it into a specific TAP device. If we haven't specified a
|
/* Turn it into a specific TAP device. If we haven't specified a
|
specific (persistent) device, one will be created, but that requires
|
specific (persistent) device, one will be created, but that requires
|
superuser, or at least CAP_NET_ADMIN capabilities. */
|
superuser, or at least CAP_NET_ADMIN capabilities. */
|
memset (&ifr, 0, sizeof(ifr));
|
memset (&ifr, 0, sizeof(ifr));
|
ifr.ifr_flags = IFF_TAP | IFF_NO_PI;
|
ifr.ifr_flags = IFF_TAP | IFF_NO_PI;
|
strncpy (ifr.ifr_name, eth->tap_dev, IFNAMSIZ);
|
strncpy (ifr.ifr_name, eth->tap_dev, IFNAMSIZ);
|
|
|
if (ioctl (eth->rtx_fd, TUNSETIFF, (void *) &ifr) < 0)
|
if (ioctl (eth->rtx_fd, TUNSETIFF, (void *) &ifr) < 0)
|
{
|
{
|
fprintf (stderr, "Warning: Failed to set TAP device: %s\n",
|
fprintf (stderr, "Warning: Failed to set TAP device: %s\n",
|
strerror (errno));
|
strerror (errno));
|
close (eth->rtx_fd);
|
close (eth->rtx_fd);
|
eth->rtx_fd = 0;
|
eth->rtx_fd = 0;
|
return;
|
return;
|
}
|
}
|
#if ETH_DEBUG
|
#if ETH_DEBUG
|
PRINTF ("Opened TAP %s\n", ifr.ifr_name);
|
PRINTF ("Opened TAP %s\n", ifr.ifr_name);
|
#endif
|
#endif
|
/* Do we need to flush any packets? */
|
/* Do we need to flush any packets? */
|
break;
|
break;
|
}
|
}
|
|
|
/* Set registers to default values */
|
/* Set registers to default values */
|
memset (&(eth->regs), 0, sizeof (eth->regs));
|
memset (&(eth->regs), 0, sizeof (eth->regs));
|
|
|
eth->regs.moder = 0x0000A000;
|
eth->regs.moder = 0x0000A000;
|
eth->regs.ipgt = 0x00000012;
|
eth->regs.ipgt = 0x00000012;
|
eth->regs.ipgr1 = 0x0000000C;
|
eth->regs.ipgr1 = 0x0000000C;
|
eth->regs.ipgr2 = 0x00000012;
|
eth->regs.ipgr2 = 0x00000012;
|
eth->regs.packetlen = 0x003C0600;
|
eth->regs.packetlen = 0x003C0600;
|
eth->regs.collconf = 0x000F003F;
|
eth->regs.collconf = 0x000F003F;
|
eth->regs.miimoder = 0x00000064;
|
eth->regs.miimoder = 0x00000064;
|
eth->regs.tx_bd_num = 0x00000040;
|
eth->regs.tx_bd_num = 0x00000040;
|
|
|
/* Clear TX/RX status and initialize buffer descriptor index. */
|
/* Clear TX/RX status and initialize buffer descriptor index. */
|
memset (&(eth->tx), 0, sizeof (eth->tx));
|
memset (&(eth->tx), 0, sizeof (eth->tx));
|
memset (&(eth->rx), 0, sizeof (eth->rx));
|
memset (&(eth->rx), 0, sizeof (eth->rx));
|
|
|
/* Reset TX/RX BD indexes */
|
/* Reset TX/RX BD indexes */
|
eth->tx.bd_index = 0;
|
eth->tx.bd_index = 0;
|
eth->rx.bd_index = eth->regs.tx_bd_num << 1;
|
eth->rx.bd_index = eth->regs.tx_bd_num << 1;
|
|
|
/* Reset IRQ line status */
|
/* Reset IRQ line status */
|
eth->int_line_stat = 0;
|
eth->int_line_stat = 0;
|
|
|
/* Initialize VAPI */
|
/* Initialize VAPI */
|
if (eth->base_vapi_id)
|
if (eth->base_vapi_id)
|
{
|
{
|
vapi_install_multi_handler (eth->base_vapi_id, ETH_NUM_VAPI_IDS,
|
vapi_install_multi_handler (eth->base_vapi_id, ETH_NUM_VAPI_IDS,
|
eth_vapi_read, dat);
|
eth_vapi_read, dat);
|
}
|
}
|
} /* eth_reset () */
|
} /* eth_reset () */
|
|
|
|
|
/*
|
/*
|
Print register values on stdout
|
Print register values on stdout
|
*/
|
*/
|
static void
|
static void
|
eth_status (void *dat)
|
eth_status (void *dat)
|
{
|
{
|
struct eth_device *eth = dat;
|
struct eth_device *eth = dat;
|
|
|
PRINTF ("\nEthernet MAC at 0x%" PRIxADDR ":\n", eth->baseaddr);
|
PRINTF ("\nEthernet MAC at 0x%" PRIxADDR ":\n", eth->baseaddr);
|
PRINTF ("MODER : 0x%08lX\n", eth->regs.moder);
|
PRINTF ("MODER : 0x%08lX\n", eth->regs.moder);
|
PRINTF ("INT_SOURCE : 0x%08lX\n", eth->regs.int_source);
|
PRINTF ("INT_SOURCE : 0x%08lX\n", eth->regs.int_source);
|
PRINTF ("INT_MASK : 0x%08lX\n", eth->regs.int_mask);
|
PRINTF ("INT_MASK : 0x%08lX\n", eth->regs.int_mask);
|
PRINTF ("IPGT : 0x%08lX\n", eth->regs.ipgt);
|
PRINTF ("IPGT : 0x%08lX\n", eth->regs.ipgt);
|
PRINTF ("IPGR1 : 0x%08lX\n", eth->regs.ipgr1);
|
PRINTF ("IPGR1 : 0x%08lX\n", eth->regs.ipgr1);
|
PRINTF ("IPGR2 : 0x%08lX\n", eth->regs.ipgr2);
|
PRINTF ("IPGR2 : 0x%08lX\n", eth->regs.ipgr2);
|
PRINTF ("PACKETLEN : 0x%08lX\n", eth->regs.packetlen);
|
PRINTF ("PACKETLEN : 0x%08lX\n", eth->regs.packetlen);
|
PRINTF ("COLLCONF : 0x%08lX\n", eth->regs.collconf);
|
PRINTF ("COLLCONF : 0x%08lX\n", eth->regs.collconf);
|
PRINTF ("TX_BD_NUM : 0x%08lX\n", eth->regs.tx_bd_num);
|
PRINTF ("TX_BD_NUM : 0x%08lX\n", eth->regs.tx_bd_num);
|
PRINTF ("CTRLMODER : 0x%08lX\n", eth->regs.controlmoder);
|
PRINTF ("CTRLMODER : 0x%08lX\n", eth->regs.controlmoder);
|
PRINTF ("MIIMODER : 0x%08lX\n", eth->regs.miimoder);
|
PRINTF ("MIIMODER : 0x%08lX\n", eth->regs.miimoder);
|
PRINTF ("MIICOMMAND : 0x%08lX\n", eth->regs.miicommand);
|
PRINTF ("MIICOMMAND : 0x%08lX\n", eth->regs.miicommand);
|
PRINTF ("MIIADDRESS : 0x%08lX\n", eth->regs.miiaddress);
|
PRINTF ("MIIADDRESS : 0x%08lX\n", eth->regs.miiaddress);
|
PRINTF ("MIITX_DATA : 0x%08lX\n", eth->regs.miitx_data);
|
PRINTF ("MIITX_DATA : 0x%08lX\n", eth->regs.miitx_data);
|
PRINTF ("MIIRX_DATA : 0x%08lX\n", eth->regs.miirx_data);
|
PRINTF ("MIIRX_DATA : 0x%08lX\n", eth->regs.miirx_data);
|
PRINTF ("MIISTATUS : 0x%08lX\n", eth->regs.miistatus);
|
PRINTF ("MIISTATUS : 0x%08lX\n", eth->regs.miistatus);
|
PRINTF ("MAC Address : %02X:%02X:%02X:%02X:%02X:%02X\n",
|
PRINTF ("MAC Address : %02X:%02X:%02X:%02X:%02X:%02X\n",
|
eth->mac_address[0], eth->mac_address[1], eth->mac_address[2],
|
eth->mac_address[0], eth->mac_address[1], eth->mac_address[2],
|
eth->mac_address[3], eth->mac_address[4], eth->mac_address[5]);
|
eth->mac_address[3], eth->mac_address[4], eth->mac_address[5]);
|
PRINTF ("HASH0 : 0x%08lX\n", eth->regs.hash0);
|
PRINTF ("HASH0 : 0x%08lX\n", eth->regs.hash0);
|
PRINTF ("HASH1 : 0x%08lX\n", eth->regs.hash1);
|
PRINTF ("HASH1 : 0x%08lX\n", eth->regs.hash1);
|
}
|
}
|
|
|
/* ========================================================================= */
|
/* ========================================================================= */
|
|
|
|
|
/*
|
/*
|
Read a register
|
Read a register
|
*/
|
*/
|
static uint32_t
|
static uint32_t
|
eth_read32 (oraddr_t addr, void *dat)
|
eth_read32 (oraddr_t addr, void *dat)
|
{
|
{
|
struct eth_device *eth = dat;
|
struct eth_device *eth = dat;
|
|
|
switch (addr)
|
switch (addr)
|
{
|
{
|
case ETH_MODER:
|
case ETH_MODER:
|
return eth->regs.moder;
|
return eth->regs.moder;
|
case ETH_INT_SOURCE:
|
case ETH_INT_SOURCE:
|
return eth->regs.int_source;
|
return eth->regs.int_source;
|
case ETH_INT_MASK:
|
case ETH_INT_MASK:
|
return eth->regs.int_mask;
|
return eth->regs.int_mask;
|
case ETH_IPGT:
|
case ETH_IPGT:
|
return eth->regs.ipgt;
|
return eth->regs.ipgt;
|
case ETH_IPGR1:
|
case ETH_IPGR1:
|
return eth->regs.ipgr1;
|
return eth->regs.ipgr1;
|
case ETH_IPGR2:
|
case ETH_IPGR2:
|
return eth->regs.ipgr2;
|
return eth->regs.ipgr2;
|
case ETH_PACKETLEN:
|
case ETH_PACKETLEN:
|
return eth->regs.packetlen;
|
return eth->regs.packetlen;
|
case ETH_COLLCONF:
|
case ETH_COLLCONF:
|
return eth->regs.collconf;
|
return eth->regs.collconf;
|
case ETH_TX_BD_NUM:
|
case ETH_TX_BD_NUM:
|
return eth->regs.tx_bd_num;
|
return eth->regs.tx_bd_num;
|
case ETH_CTRLMODER:
|
case ETH_CTRLMODER:
|
return eth->regs.controlmoder;
|
return eth->regs.controlmoder;
|
case ETH_MIIMODER:
|
case ETH_MIIMODER:
|
return eth->regs.miimoder;
|
return eth->regs.miimoder;
|
case ETH_MIICOMMAND:
|
case ETH_MIICOMMAND:
|
return eth->regs.miicommand;
|
return eth->regs.miicommand;
|
case ETH_MIIADDRESS:
|
case ETH_MIIADDRESS:
|
return eth->regs.miiaddress;
|
return eth->regs.miiaddress;
|
case ETH_MIITX_DATA:
|
case ETH_MIITX_DATA:
|
return eth->regs.miitx_data;
|
return eth->regs.miitx_data;
|
case ETH_MIIRX_DATA:
|
case ETH_MIIRX_DATA:
|
/*printf("or1ksim: read MIIM RX: 0x%x\n",(int)eth->regs.miirx_data);*/
|
/*printf("or1ksim: read MIIM RX: 0x%x\n",(int)eth->regs.miirx_data);*/
|
return eth->regs.miirx_data;
|
return eth->regs.miirx_data;
|
case ETH_MIISTATUS:
|
case ETH_MIISTATUS:
|
return eth->regs.miistatus;
|
return eth->regs.miistatus;
|
case ETH_MAC_ADDR0:
|
case ETH_MAC_ADDR0:
|
return (((unsigned long) eth->mac_address[3]) << 24) |
|
return (((unsigned long) eth->mac_address[3]) << 24) |
|
(((unsigned long) eth->mac_address[2]) << 16) |
|
(((unsigned long) eth->mac_address[2]) << 16) |
|
(((unsigned long) eth->mac_address[1]) << 8) |
|
(((unsigned long) eth->mac_address[1]) << 8) |
|
(unsigned long) eth->mac_address[0];
|
(unsigned long) eth->mac_address[0];
|
case ETH_MAC_ADDR1:
|
case ETH_MAC_ADDR1:
|
return (((unsigned long) eth->mac_address[5]) << 8) |
|
return (((unsigned long) eth->mac_address[5]) << 8) |
|
(unsigned long) eth->mac_address[4];
|
(unsigned long) eth->mac_address[4];
|
case ETH_HASH0:
|
case ETH_HASH0:
|
return eth->regs.hash0;
|
return eth->regs.hash0;
|
case ETH_HASH1:
|
case ETH_HASH1:
|
return eth->regs.hash1;
|
return eth->regs.hash1;
|
/*case ETH_DMA_RX_TX: return eth_rx( eth ); */
|
/*case ETH_DMA_RX_TX: return eth_rx( eth ); */
|
}
|
}
|
|
|
if ((addr >= ETH_BD_BASE) && (addr < ETH_BD_BASE + ETH_BD_SPACE))
|
if ((addr >= ETH_BD_BASE) && (addr < ETH_BD_BASE + ETH_BD_SPACE))
|
return eth->regs.bd_ram[(addr - ETH_BD_BASE) / 4];
|
return eth->regs.bd_ram[(addr - ETH_BD_BASE) / 4];
|
|
|
PRINTF ("eth_read32( 0x%" PRIxADDR " ): Illegal address\n",
|
PRINTF ("eth_read32( 0x%" PRIxADDR " ): Illegal address\n",
|
addr + eth->baseaddr);
|
addr + eth->baseaddr);
|
return 0;
|
return 0;
|
}
|
}
|
|
|
/* ========================================================================= */
|
/* ========================================================================= */
|
|
|
|
|
/*
|
/*
|
Write a register
|
Write a register
|
*/
|
*/
|
static void
|
static void
|
eth_write32 (oraddr_t addr, uint32_t value, void *dat)
|
eth_write32 (oraddr_t addr, uint32_t value, void *dat)
|
{
|
{
|
struct eth_device *eth = dat;
|
struct eth_device *eth = dat;
|
|
|
switch (addr)
|
switch (addr)
|
{
|
{
|
case ETH_MODER:
|
case ETH_MODER:
|
#if ETH_DEBUG
|
#if ETH_DEBUG
|
printf("eth_write32: MODER 0x%x\n",value);
|
printf("eth_write32: MODER 0x%x\n",value);
|
#endif
|
#endif
|
if (!TEST_FLAG (eth->regs.moder, ETH_MODER, RXEN) &&
|
if (!TEST_FLAG (eth->regs.moder, ETH_MODER, RXEN) &&
|
TEST_FLAG (value, ETH_MODER, RXEN))
|
TEST_FLAG (value, ETH_MODER, RXEN))
|
{
|
{
|
// Reset RX BD index
|
// Reset RX BD index
|
eth->rx.bd_index = eth->regs.tx_bd_num << 1;
|
eth->rx.bd_index = eth->regs.tx_bd_num << 1;
|
|
|
// Clear TAP
|
// Clear TAP
|
{
|
{
|
/* Poll to see if there is data to read */
|
/* Poll to see if there is data to read */
|
struct pollfd fds[1];
|
struct pollfd fds[1];
|
int n;
|
int n;
|
int nread;
|
int nread;
|
|
|
fds[0].fd = eth->rtx_fd;
|
fds[0].fd = eth->rtx_fd;
|
fds[0].events = POLLIN;
|
fds[0].events = POLLIN;
|
|
|
do {
|
do {
|
n = poll (fds, 1, 0);
|
n = poll (fds, 1, 0);
|
if (n < 0)
|
if (n < 0)
|
{
|
{
|
fprintf (stderr, "Warning: Poll in while emptying TAP: %s: ignored.\n",
|
fprintf (stderr, "Warning: Poll in while emptying TAP: %s: ignored.\n",
|
strerror (errno));
|
strerror (errno));
|
}
|
}
|
else if ((n > 0) && ((fds[0].revents & POLLIN) == POLLIN))
|
else if ((n > 0) && ((fds[0].revents & POLLIN) == POLLIN))
|
{
|
{
|
nread = read (eth->rtx_fd, eth->rx_buff, ETH_MAXPL);
|
nread = read (eth->rtx_fd, eth->rx_buff, ETH_MAXPL);
|
|
|
if (nread < 0)
|
if (nread < 0)
|
{
|
{
|
fprintf (stderr,
|
fprintf (stderr,
|
"Warning: Read failed %s: ignored\n",
|
"Warning: Read failed %s: ignored\n",
|
strerror (errno));
|
strerror (errno));
|
}
|
}
|
}
|
}
|
} while (n > 0);
|
} while (n > 0);
|
}
|
}
|
|
|
SCHED_ADD (eth_controller_rx_clock, dat, 1);
|
SCHED_ADD (eth_controller_rx_clock, dat, 1);
|
}
|
}
|
else if (!TEST_FLAG (value, ETH_MODER, RXEN) &&
|
else if (!TEST_FLAG (value, ETH_MODER, RXEN) &&
|
TEST_FLAG (eth->regs.moder, ETH_MODER, RXEN))
|
TEST_FLAG (eth->regs.moder, ETH_MODER, RXEN))
|
SCHED_FIND_REMOVE (eth_controller_rx_clock, dat);
|
SCHED_FIND_REMOVE (eth_controller_rx_clock, dat);
|
|
|
if (!TEST_FLAG (eth->regs.moder, ETH_MODER, TXEN) &&
|
if (!TEST_FLAG (eth->regs.moder, ETH_MODER, TXEN) &&
|
TEST_FLAG (value, ETH_MODER, TXEN))
|
TEST_FLAG (value, ETH_MODER, TXEN))
|
{
|
{
|
eth->tx.bd_index = 0;
|
eth->tx.bd_index = 0;
|
SCHED_ADD (eth_controller_tx_clock, dat, 1);
|
SCHED_ADD (eth_controller_tx_clock, dat, 1);
|
}
|
}
|
else if (!TEST_FLAG (value, ETH_MODER, TXEN) &&
|
else if (!TEST_FLAG (value, ETH_MODER, TXEN) &&
|
TEST_FLAG (eth->regs.moder, ETH_MODER, TXEN))
|
TEST_FLAG (eth->regs.moder, ETH_MODER, TXEN))
|
SCHED_FIND_REMOVE (eth_controller_tx_clock, dat);
|
SCHED_FIND_REMOVE (eth_controller_tx_clock, dat);
|
|
|
eth->regs.moder = value;
|
eth->regs.moder = value;
|
|
|
if (TEST_FLAG (value, ETH_MODER, RST))
|
if (TEST_FLAG (value, ETH_MODER, RST))
|
eth_reset (dat);
|
eth_reset (dat);
|
return;
|
return;
|
case ETH_INT_SOURCE:
|
case ETH_INT_SOURCE:
|
#if ETH_DEBUG
|
#if ETH_DEBUG
|
printf("eth_write32: INT_SOURCE 0x%x\n",value);
|
printf("eth_write32: INT_SOURCE 0x%x\n",value);
|
#endif
|
#endif
|
eth->regs.int_source &= ~value;
|
eth->regs.int_source &= ~value;
|
|
|
// Clear IRQ line if all interrupt sources have been dealt with
|
// Clear IRQ line if all interrupt sources have been dealt with
|
if (!(eth->regs.int_source & eth->regs.int_mask) && eth->int_line_stat)
|
if (!(eth->regs.int_source & eth->regs.int_mask) && eth->int_line_stat)
|
{
|
{
|
clear_interrupt (eth->mac_int);
|
clear_interrupt (eth->mac_int);
|
eth->int_line_stat = 0;
|
eth->int_line_stat = 0;
|
}
|
}
|
|
|
return;
|
return;
|
case ETH_INT_MASK:
|
case ETH_INT_MASK:
|
#if ETH_DEBUG
|
#if ETH_DEBUG
|
printf("eth_write32: INT_MASK 0x%x\n",value);
|
printf("eth_write32: INT_MASK 0x%x\n",value);
|
#endif
|
#endif
|
eth->regs.int_mask = value;
|
eth->regs.int_mask = value;
|
if ((eth->regs.int_source & eth->regs.int_mask) && !eth->int_line_stat)
|
if ((eth->regs.int_source & eth->regs.int_mask) && !eth->int_line_stat)
|
report_interrupt (eth->mac_int);
|
report_interrupt (eth->mac_int);
|
else
|
else
|
if (eth->int_line_stat)
|
if (eth->int_line_stat)
|
{
|
{
|
clear_interrupt (eth->mac_int);
|
clear_interrupt (eth->mac_int);
|
eth->int_line_stat = 0;
|
eth->int_line_stat = 0;
|
}
|
}
|
return;
|
return;
|
case ETH_IPGT:
|
case ETH_IPGT:
|
eth->regs.ipgt = value;
|
eth->regs.ipgt = value;
|
return;
|
return;
|
case ETH_IPGR1:
|
case ETH_IPGR1:
|
eth->regs.ipgr1 = value;
|
eth->regs.ipgr1 = value;
|
return;
|
return;
|
case ETH_IPGR2:
|
case ETH_IPGR2:
|
eth->regs.ipgr2 = value;
|
eth->regs.ipgr2 = value;
|
return;
|
return;
|
case ETH_PACKETLEN:
|
case ETH_PACKETLEN:
|
eth->regs.packetlen = value;
|
eth->regs.packetlen = value;
|
return;
|
return;
|
case ETH_COLLCONF:
|
case ETH_COLLCONF:
|
eth->regs.collconf = value;
|
eth->regs.collconf = value;
|
return;
|
return;
|
case ETH_TX_BD_NUM:
|
case ETH_TX_BD_NUM:
|
eth_write_tx_bd_num (eth, value);
|
/* When TX_BD_NUM is written, also reset current RX BD index */
|
|
eth->regs.tx_bd_num = value & 0xFF;
|
|
eth->rx.bd_index = eth->regs.tx_bd_num << 1;
|
return;
|
return;
|
case ETH_CTRLMODER:
|
case ETH_CTRLMODER:
|
eth->regs.controlmoder = value;
|
eth->regs.controlmoder = value;
|
return;
|
return;
|
case ETH_MIIMODER:
|
case ETH_MIIMODER:
|
eth->regs.miimoder = value;
|
eth->regs.miimoder = value;
|
return;
|
return;
|
case ETH_MIICOMMAND:
|
case ETH_MIICOMMAND:
|
eth->regs.miicommand = value;
|
eth->regs.miicommand = value;
|
/* Perform MIIM transaction, if required */
|
/* Perform MIIM transaction, if required */
|
eth_miim_trans(dat);
|
eth_miim_trans (eth);
|
return;
|
return;
|
case ETH_MIIADDRESS:
|
case ETH_MIIADDRESS:
|
eth->regs.miiaddress = value;
|
eth->regs.miiaddress = value;
|
return;
|
return;
|
case ETH_MIITX_DATA:
|
case ETH_MIITX_DATA:
|
eth->regs.miitx_data = value;
|
eth->regs.miitx_data = value;
|
return;
|
return;
|
case ETH_MIIRX_DATA:
|
case ETH_MIIRX_DATA:
|
/* Register is R/O
|
/* Register is R/O
|
eth->regs.miirx_data = value;
|
eth->regs.miirx_data = value;
|
*/
|
*/
|
return;
|
return;
|
case ETH_MIISTATUS:
|
case ETH_MIISTATUS:
|
/* Register is R/O
|
/* Register is R/O
|
eth->regs.miistatus = value;
|
eth->regs.miistatus = value;
|
*/
|
*/
|
return;
|
return;
|
|
|
case ETH_MAC_ADDR0:
|
case ETH_MAC_ADDR0:
|
eth->mac_address[0] = value & 0xFF;
|
eth->mac_address[0] = value & 0xFF;
|
eth->mac_address[1] = (value >> 8) & 0xFF;
|
eth->mac_address[1] = (value >> 8) & 0xFF;
|
eth->mac_address[2] = (value >> 16) & 0xFF;
|
eth->mac_address[2] = (value >> 16) & 0xFF;
|
eth->mac_address[3] = (value >> 24) & 0xFF;
|
eth->mac_address[3] = (value >> 24) & 0xFF;
|
return;
|
return;
|
case ETH_MAC_ADDR1:
|
case ETH_MAC_ADDR1:
|
eth->mac_address[4] = value & 0xFF;
|
eth->mac_address[4] = value & 0xFF;
|
eth->mac_address[5] = (value >> 8) & 0xFF;
|
eth->mac_address[5] = (value >> 8) & 0xFF;
|
return;
|
return;
|
case ETH_HASH0:
|
case ETH_HASH0:
|
eth->regs.hash0 = value;
|
eth->regs.hash0 = value;
|
return;
|
return;
|
case ETH_HASH1:
|
case ETH_HASH1:
|
eth->regs.hash1 = value;
|
eth->regs.hash1 = value;
|
return;
|
return;
|
|
|
/*case ETH_DMA_RX_TX: eth_tx( eth, value ); return; */
|
/*case ETH_DMA_RX_TX: eth_tx( eth, value ); return; */
|
}
|
}
|
|
|
if ((addr >= ETH_BD_BASE) && (addr < ETH_BD_BASE + ETH_BD_SPACE))
|
if ((addr >= ETH_BD_BASE) && (addr < ETH_BD_BASE + ETH_BD_SPACE))
|
{
|
{
|
eth->regs.bd_ram[(addr - ETH_BD_BASE) / 4] = value;
|
eth->regs.bd_ram[(addr - ETH_BD_BASE) / 4] = value;
|
return;
|
return;
|
}
|
}
|
|
|
PRINTF ("eth_write32( 0x%" PRIxADDR " ): Illegal address\n",
|
PRINTF ("eth_write32( 0x%" PRIxADDR " ): Illegal address\n",
|
addr + eth->baseaddr);
|
addr + eth->baseaddr);
|
return;
|
return;
|
}
|
}
|
|
|
/* ========================================================================= */
|
/* ========================================================================= */
|
|
|
|
|
/*
|
|
* VAPI connection to outside
|
|
*/
|
|
static void
|
|
eth_vapi_read (unsigned long id, unsigned long data, void *dat)
|
|
{
|
|
unsigned long which;
|
|
struct eth_device *eth = dat;
|
|
|
|
which = id - eth->base_vapi_id;
|
|
|
|
if (!eth)
|
|
{
|
|
return;
|
|
}
|
|
|
|
switch (which)
|
|
{
|
|
case ETH_VAPI_DATA:
|
|
break;
|
|
case ETH_VAPI_CTRL:
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* ========================================================================= */
|
/* ========================================================================= */
|
|
|
|
|
/* When TX_BD_NUM is written, also reset current RX BD index */
|
|
static void
|
|
eth_write_tx_bd_num (struct eth_device *eth, unsigned long value)
|
|
{
|
|
eth->regs.tx_bd_num = value & 0xFF;
|
|
eth->rx.bd_index = eth->regs.tx_bd_num << 1;
|
|
}
|
|
|
|
/* ========================================================================= */
|
/* ========================================================================= */
|
|
|
/*-----------------------------------------------[ Ethernet configuration ]---*/
|
/*-----------------------------------------------[ Ethernet configuration ]---*/
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/*!Enable or disable the Ethernet interface
|
/*!Enable or disable the Ethernet interface
|
|
|
@param[in] val The value to use
|
@param[in] val The value to use
|
@param[in] dat The config data structure */
|
@param[in] dat The config data structure */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
static void
|
static void
|
eth_enabled (union param_val val,
|
eth_enabled (union param_val val,
|
void *dat)
|
void *dat)
|
{
|
{
|
struct eth_device *eth = dat;
|
struct eth_device *eth = dat;
|
|
|
eth->enabled = val.int_val;
|
eth->enabled = val.int_val;
|
|
|
} /* eth_enabled() */
|
} /* eth_enabled() */
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/*!Set the Ethernet interface base address
|
/*!Set the Ethernet interface base address
|
|
|
@param[in] val The value to use
|
@param[in] val The value to use
|
@param[in] dat The config data structure */
|
@param[in] dat The config data structure */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
static void
|
static void
|
eth_baseaddr (union param_val val,
|
eth_baseaddr (union param_val val,
|
void *dat)
|
void *dat)
|
{
|
{
|
struct eth_device *eth = dat;
|
struct eth_device *eth = dat;
|
|
|
eth->baseaddr = val.addr_val;
|
eth->baseaddr = val.addr_val;
|
|
|
} /* eth_baseaddr() */
|
} /* eth_baseaddr() */
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/*!Set the Ethernet DMA port
|
/*!Set the Ethernet DMA port
|
|
|
This is not currently supported, so a warning message is printed.
|
This is not currently supported, so a warning message is printed.
|
|
|
@param[in] val The value to use
|
@param[in] val The value to use
|
@param[in] dat The config data structure */
|
@param[in] dat The config data structure */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
static void
|
static void
|
eth_dma (union param_val val,
|
eth_dma (union param_val val,
|
void *dat)
|
void *dat)
|
{
|
{
|
struct eth_device *eth = dat;
|
struct eth_device *eth = dat;
|
|
|
fprintf (stderr, "Warning: External Ethernet DMA not currently supported\n");
|
fprintf (stderr, "Warning: External Ethernet DMA not currently supported\n");
|
eth->dma = val.addr_val;
|
eth->dma = val.addr_val;
|
|
|
} /* eth_dma() */
|
} /* eth_dma() */
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/*!Set the Ethernet IRQ
|
/*!Set the Ethernet IRQ
|
|
|
@param[in] val The value to use
|
@param[in] val The value to use
|
@param[in] dat The config data structure */
|
@param[in] dat The config data structure */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
static void
|
static void
|
eth_irq (union param_val val,
|
eth_irq (union param_val val,
|
void *dat)
|
void *dat)
|
{
|
{
|
struct eth_device *eth = dat;
|
struct eth_device *eth = dat;
|
|
|
eth->mac_int = val.int_val;
|
eth->mac_int = val.int_val;
|
|
|
} /* eth_irq() */
|
} /* eth_irq() */
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/*!Set the Ethernet interface type
|
/*!Set the Ethernet interface type
|
|
|
Currently two types are supported, file and tap.
|
Currently two types are supported, file and tap.
|
|
|
@param[in] val The value to use. Currently "file" and "tap" are supported.
|
@param[in] val The value to use. Currently "file" and "tap" are supported.
|
@param[in] dat The config data structure */
|
@param[in] dat The config data structure */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
static void
|
static void
|
eth_rtx_type (union param_val val,
|
eth_rtx_type (union param_val val,
|
void *dat)
|
void *dat)
|
{
|
{
|
struct eth_device *eth = dat;
|
struct eth_device *eth = dat;
|
|
|
if (0 == strcasecmp ("file", val.str_val))
|
if (0 == strcasecmp ("file", val.str_val))
|
{
|
{
|
printf ("Ethernet FILE type\n");
|
printf ("Ethernet FILE type\n");
|
eth->rtx_type = ETH_RTX_FILE;
|
eth->rtx_type = ETH_RTX_FILE;
|
}
|
}
|
else if (0 == strcasecmp ("tap", val.str_val))
|
else if (0 == strcasecmp ("tap", val.str_val))
|
{
|
{
|
printf ("Ethernet TAP type\n");
|
printf ("Ethernet TAP type\n");
|
eth->rtx_type = ETH_RTX_TAP;
|
eth->rtx_type = ETH_RTX_TAP;
|
}
|
}
|
else
|
else
|
{
|
{
|
fprintf (stderr, "Warning: Unknown Ethernet type: file assumed.\n");
|
fprintf (stderr, "Warning: Unknown Ethernet type: file assumed.\n");
|
eth->rtx_type = ETH_RTX_FILE;
|
eth->rtx_type = ETH_RTX_FILE;
|
}
|
}
|
} /* eth_rtx_type() */
|
} /* eth_rtx_type() */
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/*!Set the Ethernet DMA Rx channel
|
/*!Set the Ethernet DMA Rx channel
|
|
|
External DMA is not currently supported, so a warning message is printed.
|
External DMA is not currently supported, so a warning message is printed.
|
|
|
@param[in] val The value to use
|
@param[in] val The value to use
|
@param[in] dat The config data structure */
|
@param[in] dat The config data structure */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
static void
|
static void
|
eth_rx_channel (union param_val val,
|
eth_rx_channel (union param_val val,
|
void *dat)
|
void *dat)
|
{
|
{
|
struct eth_device *eth = dat;
|
struct eth_device *eth = dat;
|
|
|
fprintf (stderr, "Warning: External Ethernet DMA not currently supported: "
|
fprintf (stderr, "Warning: External Ethernet DMA not currently supported: "
|
"Rx channel ignored\n");
|
"Rx channel ignored\n");
|
eth->rx_channel = val.int_val;
|
eth->rx_channel = val.int_val;
|
|
|
} /* eth_rx_channel() */
|
} /* eth_rx_channel() */
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/*!Set the Ethernet DMA Tx channel
|
/*!Set the Ethernet DMA Tx channel
|
|
|
External DMA is not currently supported, so a warning message is printed.
|
External DMA is not currently supported, so a warning message is printed.
|
|
|
@param[in] val The value to use
|
@param[in] val The value to use
|
@param[in] dat The config data structure */
|
@param[in] dat The config data structure */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
static void
|
static void
|
eth_tx_channel (union param_val val,
|
eth_tx_channel (union param_val val,
|
void *dat)
|
void *dat)
|
{
|
{
|
struct eth_device *eth = dat;
|
struct eth_device *eth = dat;
|
|
|
fprintf (stderr, "Warning: External Ethernet DMA not currently supported: "
|
fprintf (stderr, "Warning: External Ethernet DMA not currently supported: "
|
"Tx channel ignored\n");
|
"Tx channel ignored\n");
|
eth->tx_channel = val.int_val;
|
eth->tx_channel = val.int_val;
|
|
|
} /* eth_tx_channel() */
|
} /* eth_tx_channel() */
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/*!Set the Ethernet DMA Rx file
|
/*!Set the Ethernet DMA Rx file
|
|
|
Free any previously allocated value.
|
Free any previously allocated value.
|
|
|
@param[in] val The value to use
|
@param[in] val The value to use
|
@param[in] dat The config data structure */
|
@param[in] dat The config data structure */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
static void
|
static void
|
eth_rxfile (union param_val val,
|
eth_rxfile (union param_val val,
|
void *dat)
|
void *dat)
|
{
|
{
|
struct eth_device *eth = dat;
|
struct eth_device *eth = dat;
|
|
|
if (NULL != eth->rxfile)
|
if (NULL != eth->rxfile)
|
{
|
{
|
free (eth->rxfile);
|
free (eth->rxfile);
|
eth->rxfile = NULL;
|
eth->rxfile = NULL;
|
}
|
}
|
|
|
if (!(eth->rxfile = strdup (val.str_val)))
|
if (!(eth->rxfile = strdup (val.str_val)))
|
{
|
{
|
fprintf (stderr, "Peripheral Ethernet: Run out of memory\n");
|
fprintf (stderr, "Peripheral Ethernet: Run out of memory\n");
|
exit (-1);
|
exit (-1);
|
}
|
}
|
} /* eth_rxfile() */
|
} /* eth_rxfile() */
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/*!Set the Ethernet DMA Tx file
|
/*!Set the Ethernet DMA Tx file
|
|
|
Free any previously allocated value.
|
Free any previously allocated value.
|
|
|
@param[in] val The value to use
|
@param[in] val The value to use
|
@param[in] dat The config data structure */
|
@param[in] dat The config data structure */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
static void
|
static void
|
eth_txfile (union param_val val,
|
eth_txfile (union param_val val,
|
void *dat)
|
void *dat)
|
{
|
{
|
struct eth_device *eth = dat;
|
struct eth_device *eth = dat;
|
|
|
if (NULL != eth->txfile)
|
if (NULL != eth->txfile)
|
{
|
{
|
free (eth->txfile);
|
free (eth->txfile);
|
eth->txfile = NULL;
|
eth->txfile = NULL;
|
}
|
}
|
|
|
if (!(eth->txfile = strdup (val.str_val)))
|
if (!(eth->txfile = strdup (val.str_val)))
|
{
|
{
|
fprintf (stderr, "Peripheral Ethernet: Run out of memory\n");
|
fprintf (stderr, "Peripheral Ethernet: Run out of memory\n");
|
exit (-1);
|
exit (-1);
|
}
|
}
|
} /* eth_txfile() */
|
} /* eth_txfile() */
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/*!Set the Ethernet TAP device.
|
/*!Set the Ethernet TAP device.
|
|
|
If we are not superuser (or do not have CAP_NET_ADMIN priviledges), then we
|
If we are not superuser (or do not have CAP_NET_ADMIN priviledges), then we
|
must work with a persistent TAP device that is already set up. This option
|
must work with a persistent TAP device that is already set up. This option
|
specifies the device to user.
|
specifies the device to user.
|
|
|
@param[in] val The value to use.
|
@param[in] val The value to use.
|
@param[in] dat The config data structure */
|
@param[in] dat The config data structure */
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
static void
|
static void
|
eth_tap_dev (union param_val val,
|
eth_tap_dev (union param_val val,
|
void *dat)
|
void *dat)
|
{
|
{
|
struct eth_device *eth = dat;
|
struct eth_device *eth = dat;
|
|
|
if (NULL != eth->tap_dev)
|
if (NULL != eth->tap_dev)
|
{
|
{
|
free (eth->tap_dev);
|
free (eth->tap_dev);
|
eth->tap_dev = NULL;
|
eth->tap_dev = NULL;
|
}
|
}
|
|
|
eth->tap_dev = strdup (val.str_val);
|
eth->tap_dev = strdup (val.str_val);
|
|
|
if (NULL == eth->tap_dev)
|
if (NULL == eth->tap_dev)
|
{
|
{
|
fprintf (stderr, "ERROR: Peripheral Ethernet: Run out of memory\n");
|
fprintf (stderr, "ERROR: Peripheral Ethernet: Run out of memory\n");
|
exit (-1);
|
exit (-1);
|
}
|
}
|
} /* eth_tap_dev() */
|
} /* eth_tap_dev() */
|
|
|
|
|
static void
|
static void
|
eth_vapi_id (union param_val val,
|
eth_vapi_id (union param_val val,
|
void *dat)
|
void *dat)
|
{
|
{
|
struct eth_device *eth = dat;
|
struct eth_device *eth = dat;
|
eth->base_vapi_id = val.int_val;
|
eth->base_vapi_id = val.int_val;
|
}
|
}
|
|
|
|
|
static void
|
static void
|
eth_phy_addr (union param_val val,
|
eth_phy_addr (union param_val val,
|
void *dat)
|
void *dat)
|
{
|
{
|
struct eth_device *eth = dat;
|
struct eth_device *eth = dat;
|
eth->phy_addr = val.int_val & ETH_MIIADDR_FIAD_MASK;
|
eth->phy_addr = val.int_val & ETH_MIIADDR_FIAD_MASK;
|
}
|
}
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/*!Emulate MIIM transaction to ethernet PHY
|
|
|
|
@param[in] dat The config data structure */
|
|
/*---------------------------------------------------------------------------*/
|
|
static void
|
|
eth_miim_trans (void *dat)
|
|
{
|
|
struct eth_device *eth = dat;
|
|
switch (eth->regs.miicommand)
|
|
{
|
|
case ((1 << ETH_MIICOMM_WCDATA_OFFSET)):
|
|
/* Perhaps something to emulate here later, but for now do nothing */
|
|
break;
|
|
|
|
case ((1 << ETH_MIICOMM_RSTAT_OFFSET)):
|
|
/*
|
|
printf("or1ksim: eth_miim_trans: phy %d\n",(int)
|
|
((eth->regs.miiaddress >> ETH_MIIADDR_FIAD_OFFSET)&
|
|
ETH_MIIADDR_FIAD_MASK));
|
|
printf("or1ksim: eth_miim_trans: reg %d\n",(int)
|
|
((eth->regs.miiaddress >> ETH_MIIADDR_RGAD_OFFSET)&
|
|
ETH_MIIADDR_RGAD_MASK));
|
|
*/
|
|
/*First check if it's the correct PHY to address */
|
|
if (((eth->regs.miiaddress >> ETH_MIIADDR_FIAD_OFFSET)&
|
|
ETH_MIIADDR_FIAD_MASK) == eth->phy_addr)
|
|
{
|
|
/* Correct PHY - now switch based on the register address in the PHY*/
|
|
switch ((eth->regs.miiaddress >> ETH_MIIADDR_RGAD_OFFSET)&
|
|
ETH_MIIADDR_RGAD_MASK)
|
|
{
|
|
case MII_BMCR:
|
|
eth->regs.miirx_data = BMCR_FULLDPLX;
|
|
break;
|
|
case MII_BMSR:
|
|
eth->regs.miirx_data = BMSR_LSTATUS | BMSR_ANEGCOMPLETE |
|
|
BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL;
|
|
break;
|
|
case MII_PHYSID1:
|
|
eth->regs.miirx_data = 0x22; /* Micrel PHYID */
|
|
break;
|
|
case MII_PHYSID2:
|
|
eth->regs.miirx_data = 0x1613; /* Micrel PHYID */
|
|
break;
|
|
case MII_ADVERTISE:
|
|
eth->regs.miirx_data = ADVERTISE_FULL;
|
|
break;
|
|
case MII_LPA:
|
|
eth->regs.miirx_data = LPA_DUPLEX | LPA_100;
|
|
break;
|
|
case MII_EXPANSION:
|
|
eth->regs.miirx_data = 0;
|
|
break;
|
|
case MII_CTRL1000:
|
|
eth->regs.miirx_data = 0;
|
|
break;
|
|
case MII_STAT1000:
|
|
eth->regs.miirx_data = 0;
|
|
break;
|
|
case MII_ESTATUS:
|
|
eth->regs.miirx_data = 0;
|
|
break;
|
|
case MII_DCOUNTER:
|
|
eth->regs.miirx_data = 0;
|
|
break;
|
|
case MII_FCSCOUNTER:
|
|
eth->regs.miirx_data = 0;
|
|
break;
|
|
case MII_NWAYTEST:
|
|
eth->regs.miirx_data = 0;
|
|
break;
|
|
case MII_RERRCOUNTER:
|
|
eth->regs.miirx_data = 0;
|
|
break;
|
|
case MII_SREVISION:
|
|
eth->regs.miirx_data = 0;
|
|
break;
|
|
case MII_RESV1:
|
|
eth->regs.miirx_data = 0;
|
|
break;
|
|
case MII_LBRERROR:
|
|
eth->regs.miirx_data = 0;
|
|
break;
|
|
case MII_PHYADDR:
|
|
eth->regs.miirx_data = eth->phy_addr;
|
|
break;
|
|
case MII_RESV2:
|
|
eth->regs.miirx_data = 0;
|
|
break;
|
|
case MII_TPISTATUS:
|
|
eth->regs.miirx_data = 0;
|
|
break;
|
|
case MII_NCONFIG:
|
|
eth->regs.miirx_data = 0;
|
|
break;
|
|
default:
|
|
eth->regs.miirx_data = 0xffff;
|
|
break;
|
|
}
|
|
}
|
|
else
|
|
eth->regs.miirx_data = 0xffff; /* PHY doesn't exist, read all 1's */
|
|
break;
|
|
|
|
case ((1 << ETH_MIICOMM_SCANS_OFFSET)):
|
|
/* From MAC's datasheet:
|
|
A host initiates the Scan Status Operation by asserting the SCANSTAT
|
|
signal. The MIIM performs a continuous read operation of the PHY
|
|
Status register. The PHY is selected by the FIAD[4:0] signals. The
|
|
link status LinkFail signal is asserted/deasserted by the MIIM module
|
|
and reflects the link status bit of the PHY Status register. The
|
|
signal NVALID is used for qualifying the validity of the LinkFail
|
|
signals and the status data PRSD[15:0]. These signals are invalid
|
|
until the first scan status operation ends. During the scan status
|
|
operation, the BUSY signal is asserted until the last read is
|
|
performed (the scan status operation is stopped).
|
|
|
|
So for now - do nothing, leave link status indicator as permanently
|
|
with link.
|
|
*/
|
|
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
/*---------------------------------------------------------------------------*/
|
/*!Initialize a new Ethernet configuration
|
/*!Initialize a new Ethernet configuration
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ALL parameters are set explicitly to default values. */
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ALL parameters are set explicitly to default values. */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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static void *
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static void *
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eth_sec_start (void)
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eth_sec_start (void)
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{
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{
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struct eth_device *new = malloc (sizeof (struct eth_device));
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struct eth_device *new = malloc (sizeof (struct eth_device));
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if (!new)
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if (!new)
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{
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{
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fprintf (stderr, "Peripheral Eth: Run out of memory\n");
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fprintf (stderr, "Peripheral Eth: Run out of memory\n");
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exit (-1);
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exit (-1);
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}
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}
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memset (new, 0, sizeof (struct eth_device));
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memset (new, 0, sizeof (struct eth_device));
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new->enabled = 1;
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new->enabled = 1;
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new->baseaddr = 0;
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new->baseaddr = 0;
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new->dma = 0;
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new->dma = 0;
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new->mac_int = 0;
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new->mac_int = 0;
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new->int_line_stat= 0;
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new->int_line_stat= 0;
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new->rtx_type = ETH_RTX_FILE;
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new->rtx_type = ETH_RTX_FILE;
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new->rx_channel = 0;
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new->rx_channel = 0;
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new->tx_channel = 0;
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new->tx_channel = 0;
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new->rtx_fd = 0;
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new->rtx_fd = 0;
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new->rxfile = strdup ("eth_rx");
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new->rxfile = strdup ("eth_rx");
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new->txfile = strdup ("eth_tx");
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new->txfile = strdup ("eth_tx");
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new->tap_dev = strdup ("");
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new->tap_dev = strdup ("");
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new->base_vapi_id = 0;
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new->base_vapi_id = 0;
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new->phy_addr = 0;
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new->phy_addr = 0;
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return new;
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return new;
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}
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}
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static void
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static void
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eth_sec_end (void *dat)
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eth_sec_end (void *dat)
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{
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{
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struct eth_device *eth = dat;
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struct eth_device *eth = dat;
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struct mem_ops ops;
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struct mem_ops ops;
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if (!eth->enabled)
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if (!eth->enabled)
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{
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{
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free (eth->rxfile);
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free (eth->rxfile);
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free (eth->txfile);
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free (eth->txfile);
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free (eth->tap_dev);
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free (eth->tap_dev);
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free (eth);
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free (eth);
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return;
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return;
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}
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}
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memset (&ops, 0, sizeof (struct mem_ops));
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memset (&ops, 0, sizeof (struct mem_ops));
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ops.readfunc32 = eth_read32;
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ops.readfunc32 = eth_read32;
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ops.writefunc32 = eth_write32;
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ops.writefunc32 = eth_write32;
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ops.read_dat32 = dat;
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ops.read_dat32 = dat;
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ops.write_dat32 = dat;
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ops.write_dat32 = dat;
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/* FIXME: Correct delay? */
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/* FIXME: Correct delay? */
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ops.delayr = 2;
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ops.delayr = 2;
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ops.delayw = 2;
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ops.delayw = 2;
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reg_mem_area (eth->baseaddr, ETH_ADDR_SPACE, 0, &ops);
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reg_mem_area (eth->baseaddr, ETH_ADDR_SPACE, 0, &ops);
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reg_sim_stat (eth_status, dat);
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reg_sim_stat (eth_status, dat);
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reg_sim_reset (eth_reset, dat);
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reg_sim_reset (eth_reset, dat);
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}
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}
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/*!Register a new Ethernet configuration */
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/*!Register a new Ethernet configuration */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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void
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void
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reg_ethernet_sec ()
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reg_ethernet_sec ()
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{
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{
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struct config_section *sec =
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struct config_section *sec =
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reg_config_sec ("ethernet", eth_sec_start, eth_sec_end);
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reg_config_sec ("ethernet", eth_sec_start, eth_sec_end);
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reg_config_param (sec, "enabled", PARAMT_INT, eth_enabled);
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reg_config_param (sec, "enabled", PARAMT_INT, eth_enabled);
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reg_config_param (sec, "baseaddr", PARAMT_ADDR, eth_baseaddr);
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reg_config_param (sec, "baseaddr", PARAMT_ADDR, eth_baseaddr);
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reg_config_param (sec, "dma", PARAMT_INT, eth_dma);
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reg_config_param (sec, "dma", PARAMT_INT, eth_dma);
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reg_config_param (sec, "irq", PARAMT_INT, eth_irq);
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reg_config_param (sec, "irq", PARAMT_INT, eth_irq);
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reg_config_param (sec, "rtx_type", PARAMT_STR, eth_rtx_type);
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reg_config_param (sec, "rtx_type", PARAMT_STR, eth_rtx_type);
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reg_config_param (sec, "rx_channel", PARAMT_INT, eth_rx_channel);
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reg_config_param (sec, "rx_channel", PARAMT_INT, eth_rx_channel);
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reg_config_param (sec, "tx_channel", PARAMT_INT, eth_tx_channel);
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reg_config_param (sec, "tx_channel", PARAMT_INT, eth_tx_channel);
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reg_config_param (sec, "rxfile", PARAMT_STR, eth_rxfile);
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reg_config_param (sec, "rxfile", PARAMT_STR, eth_rxfile);
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reg_config_param (sec, "txfile", PARAMT_STR, eth_txfile);
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reg_config_param (sec, "txfile", PARAMT_STR, eth_txfile);
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reg_config_param (sec, "tap_dev", PARAMT_STR, eth_tap_dev);
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reg_config_param (sec, "tap_dev", PARAMT_STR, eth_tap_dev);
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reg_config_param (sec, "vapi_id", PARAMT_INT, eth_vapi_id);
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reg_config_param (sec, "vapi_id", PARAMT_INT, eth_vapi_id);
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reg_config_param (sec, "phy_addr", PARAMT_INT, eth_phy_addr);
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reg_config_param (sec, "phy_addr", PARAMT_INT, eth_phy_addr);
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} /* reg_ethernet_sec() */
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} /* reg_ethernet_sec() */
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